---------- Begin Simulation Statistics ----------
-sim_seconds 1.896442 # Number of seconds simulated
-sim_ticks 1896441913500 # Number of ticks simulated
-final_tick 1896441913500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.903702 # Number of seconds simulated
+sim_ticks 1903702212500 # Number of ticks simulated
+final_tick 1903702212500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 132187 # Simulator instruction rate (inst/s)
-host_op_rate 132187 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4418345683 # Simulator tick rate (ticks/s)
-host_mem_usage 311512 # Number of bytes of host memory used
-host_seconds 429.22 # Real time elapsed on the host
-sim_insts 56737124 # Number of instructions simulated
-sim_ops 56737124 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 937984 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24915648 # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 2650688 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 39872 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 337088 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28881280 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 937984 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 39872 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 977856 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7850944 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7850944 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 14656 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 389307 # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 41417 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 623 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 5267 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 451270 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 122671 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 122671 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 494602 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 13138102 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1397716 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 21025 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 177748 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15229193 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 494602 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 21025 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 515627 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4139828 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4139828 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4139828 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 494602 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 13138102 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1397716 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 21025 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 177748 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19369021 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 451270 # Total number of read requests seen
-system.physmem.writeReqs 122671 # Total number of write requests seen
-system.physmem.cpureqs 578881 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 28881280 # Total number of bytes read from memory
-system.physmem.bytesWritten 7850944 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 28881280 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7850944 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 67 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4936 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 28286 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 28331 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 28232 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 28037 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 28769 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 28511 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 28476 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 28312 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 28256 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 28154 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 28207 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 27864 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 27902 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 28010 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 27813 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 28043 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 7715 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7756 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 7743 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 7541 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 8184 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 7906 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7897 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 7828 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 7761 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7702 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7706 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 7342 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 7423 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 7442 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 7221 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 7504 # Track writes on a per bank basis
+host_inst_rate 94355 # Simulator instruction rate (inst/s)
+host_op_rate 94355 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3162860632 # Simulator tick rate (ticks/s)
+host_mem_usage 314400 # Number of bytes of host memory used
+host_seconds 601.89 # Real time elapsed on the host
+sim_insts 56791782 # Number of instructions simulated
+sim_ops 56791782 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 898816 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24768192 # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 78528 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 430592 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28825728 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 898816 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 78528 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 977344 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7790720 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7790720 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 14044 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 387003 # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 1227 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 6728 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 450402 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 121730 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 121730 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 472141 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 13010539 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1391814 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 41250 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 226187 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15141931 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 472141 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 41250 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 513391 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4092405 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4092405 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4092405 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 472141 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 13010539 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1391814 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 41250 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 226187 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19234336 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 450402 # Total number of read requests seen
+system.physmem.writeReqs 121730 # Total number of write requests seen
+system.physmem.cpureqs 577215 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 28825728 # Total number of bytes read from memory
+system.physmem.bytesWritten 7790720 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 28825728 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7790720 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 61 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 5081 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 28459 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 28431 # Track reads on a per bank basis
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+system.physmem.perBankRdReqs::15 28620 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 8184 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 4 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1896440622000 # Total gap between requests
+system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1903701167000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 451270 # Categorize read packet sizes
+system.physmem.readPktSize::6 450402 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 122671 # Categorize write packet sizes
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 3224 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see
-system.physmem.totQLat 7836942250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 15642141000 # Sum of mem lat for all requests
-system.physmem.totBusLat 2256015000 # Total cycles spent in databus access
-system.physmem.totBankLat 5549183750 # Total cycles spent in bank access
-system.physmem.avgQLat 17368.99 # Average queueing delay per request
-system.physmem.avgBankLat 12298.64 # Average bank access latency per request
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+system.physmem.wrQLenPdf::24 1379 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 316 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 40212 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 910.430717 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 224.153261 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 2362.806871 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-67 14303 35.57% 35.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-131 6082 15.12% 50.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-195 3751 9.33% 60.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-259 2511 6.24% 66.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-323 1745 4.34% 70.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-387 1426 3.55% 74.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-451 1071 2.66% 76.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-515 838 2.08% 78.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-579 669 1.66% 80.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-643 518 1.29% 81.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-707 558 1.39% 83.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-771 522 1.30% 84.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-835 270 0.67% 85.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-899 231 0.57% 85.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-963 190 0.47% 86.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1027 283 0.70% 86.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1091 119 0.30% 87.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1155 115 0.29% 87.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1219 106 0.26% 87.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1283 202 0.50% 88.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1347 170 0.42% 88.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1411 105 0.26% 88.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1475 478 1.19% 90.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1539 629 1.56% 91.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1603 105 0.26% 92.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1667 36 0.09% 92.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1731 35 0.09% 92.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1795 97 0.24% 92.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1859 29 0.07% 92.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1923 7 0.02% 92.51% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::total 40212 # Bytes accessed per row activation
+system.physmem.totQLat 6402871500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 13861687750 # Sum of mem lat for all requests
+system.physmem.totBusLat 2251705000 # Total cycles spent in databus access
+system.physmem.totBankLat 5207111250 # Total cycles spent in bank access
+system.physmem.avgQLat 14217.83 # Average queueing delay per request
+system.physmem.avgBankLat 11562.60 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 34667.64 # Average memory access latency
-system.physmem.avgRdBW 15.23 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 4.14 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 15.23 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 4.14 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 30780.43 # Average memory access latency
+system.physmem.avgRdBW 15.14 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 4.09 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 15.14 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 4.09 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.15 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 10.84 # Average write queue length over time
-system.physmem.readRowHits 423356 # Number of row buffer hits during reads
-system.physmem.writeRowHits 94009 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 93.83 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 76.64 # Row buffer hit rate for writes
-system.physmem.avgGap 3304243.16 # Average gap between requests
-system.l2c.replacements 344349 # number of replacements
-system.l2c.tagsinuse 65273.956353 # Cycle average of tags in use
-system.l2c.total_refs 2577923 # Total number of references to valid blocks.
-system.l2c.sampled_refs 409542 # Sample count of references to valid blocks.
-system.l2c.avg_refs 6.294649 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 5466319751 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 53748.349121 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 5295.726441 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 5975.264441 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 194.705269 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 59.911080 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.820135 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.080806 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.091175 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.002971 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.000914 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.996002 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst 875549 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 736473 # number of ReadReq hits
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-system.l2c.ReadReq_hits::cpu1.data 65181 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1879558 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 819599 # number of Writeback hits
-system.l2c.Writeback_hits::total 819599 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 179 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 274 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 453 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 44 # number of SCUpgradeReq hits
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-system.l2c.SCUpgradeReq_hits::total 67 # number of SCUpgradeReq hits
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-system.l2c.ReadExReq_hits::total 179039 # number of ReadExReq hits
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-system.l2c.demand_hits::cpu0.data 891834 # number of demand (read+write) hits
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-system.l2c.overall_hits::cpu1.data 88859 # number of overall hits
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-system.l2c.overall_miss_latency::cpu1.data 530132500 # number of overall miss cycles
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-system.l2c.ReadReq_accesses::cpu0.data 1010148 # number of ReadReq accesses(hits+misses)
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-system.l2c.ReadReq_accesses::cpu1.data 65488 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2168838 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 819599 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 819599 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 2870 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 1329 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 4199 # number of UpgradeReq accesses(hits+misses)
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+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10005.115226 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.849735 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68696.865849 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 97466.194672 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 70212.348628 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73909.060520 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55816.241053 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77712.510187 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 95828.745615 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 57164.832242 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73909.060520 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55816.241053 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77712.510187 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 95828.745615 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 57164.832242 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 41694 # number of replacements
-system.iocache.tagsinuse 0.474409 # Cycle average of tags in use
+system.iocache.replacements 41695 # number of replacements
+system.iocache.tagsinuse 0.492474 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 41710 # Sample count of references to valid blocks.
+system.iocache.sampled_refs 41711 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 1705455708000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide 0.474409 # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide 0.029651 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.029651 # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
+system.iocache.warmup_cycle 1710349466000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide 0.492474 # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide 0.030780 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.030780 # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
-system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
-system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
-system.iocache.overall_misses::total 41726 # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide 21041998 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 21041998 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 10633425431 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10633425431 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 10654467429 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10654467429 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 10654467429 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10654467429 # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses
+system.iocache.demand_misses::total 41727 # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses
+system.iocache.overall_misses::total 41727 # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide 21568883 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 21568883 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 10518241771 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 10518241771 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 10539810654 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 10539810654 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 10539810654 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 10539810654 # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120931.022989 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 120931.022989 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255906.464936 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 255906.464936 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 255343.608997 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 255343.608997 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 255343.608997 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 255343.608997 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 285994 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123250.760000 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 123250.760000 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 253134.428451 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 253134.428451 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 252589.705802 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 252589.705802 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 252589.705802 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 252589.705802 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 276539 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 27316 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 27281 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 10.469835 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 10.136689 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 41520 # number of writebacks
system.iocache.writebacks::total 41520 # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11993249 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 11993249 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8471449424 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 8471449424 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 8483442673 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 8483442673 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 8483442673 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 8483442673 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::tsunami.ide 41727 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 41727 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide 41727 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 41727 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12468133 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 12468133 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8356835276 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 8356835276 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 8369303409 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 8369303409 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 8369303409 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 8369303409 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68926.718391 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 68926.718391 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203875.852522 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 203875.852522 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203313.106289 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 203313.106289 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203313.106289 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 203313.106289 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71246.474286 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 71246.474286 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 201117.522045 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 201117.522045 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 200572.852326 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 200572.852326 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 200572.852326 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 200572.852326 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 12584062 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 10588139 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 341886 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 8301483 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 5323497 # Number of BTB hits
+system.cpu0.branchPred.lookups 12372167 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 10430268 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 327512 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 8051050 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 5251093 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 64.127060 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 804999 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 33376 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 65.222462 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 787082 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 28165 # Number of incorrect RAS predictions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 8950032 # DTB read hits
-system.cpu0.dtb.read_misses 34820 # DTB read misses
-system.cpu0.dtb.read_acv 539 # DTB read access violations
-system.cpu0.dtb.read_accesses 674081 # DTB read accesses
-system.cpu0.dtb.write_hits 5877992 # DTB write hits
-system.cpu0.dtb.write_misses 8366 # DTB write misses
-system.cpu0.dtb.write_acv 348 # DTB write access violations
-system.cpu0.dtb.write_accesses 235610 # DTB write accesses
-system.cpu0.dtb.data_hits 14828024 # DTB hits
-system.cpu0.dtb.data_misses 43186 # DTB misses
-system.cpu0.dtb.data_acv 887 # DTB access violations
-system.cpu0.dtb.data_accesses 909691 # DTB accesses
-system.cpu0.itb.fetch_hits 1040487 # ITB hits
-system.cpu0.itb.fetch_misses 31672 # ITB misses
-system.cpu0.itb.fetch_acv 1020 # ITB acv
-system.cpu0.itb.fetch_accesses 1072159 # ITB accesses
+system.cpu0.dtb.read_hits 8811099 # DTB read hits
+system.cpu0.dtb.read_misses 30390 # DTB read misses
+system.cpu0.dtb.read_acv 555 # DTB read access violations
+system.cpu0.dtb.read_accesses 626499 # DTB read accesses
+system.cpu0.dtb.write_hits 5759352 # DTB write hits
+system.cpu0.dtb.write_misses 7345 # DTB write misses
+system.cpu0.dtb.write_acv 331 # DTB write access violations
+system.cpu0.dtb.write_accesses 208988 # DTB write accesses
+system.cpu0.dtb.data_hits 14570451 # DTB hits
+system.cpu0.dtb.data_misses 37735 # DTB misses
+system.cpu0.dtb.data_acv 886 # DTB access violations
+system.cpu0.dtb.data_accesses 835487 # DTB accesses
+system.cpu0.itb.fetch_hits 988720 # ITB hits
+system.cpu0.itb.fetch_misses 28459 # ITB misses
+system.cpu0.itb.fetch_acv 940 # ITB acv
+system.cpu0.itb.fetch_accesses 1017179 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 103751291 # number of cpu cycles simulated
+system.cpu0.numCycles 113576100 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 25592047 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 64430414 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 12584062 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 6128496 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 12114182 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1732019 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles 37108557 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 31932 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 208707 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 355709 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 408 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 7808396 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 232068 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples 76528583 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.841913 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.179850 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 24795587 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 63494847 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 12372167 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 6038175 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 11937811 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1694344 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles 37245698 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 31806 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 195246 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 359396 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 7671411 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 221670 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples 75653727 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.839282 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.177028 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 64414401 84.17% 84.17% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 777905 1.02% 85.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 1574114 2.06% 87.24% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 716339 0.94% 88.18% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 2604704 3.40% 91.58% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 529326 0.69% 92.28% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 586322 0.77% 93.04% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 831890 1.09% 94.13% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 4493582 5.87% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 63715916 84.22% 84.22% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 763032 1.01% 85.23% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 1559362 2.06% 87.29% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 696709 0.92% 88.21% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 2577784 3.41% 91.62% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 516509 0.68% 92.30% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 573501 0.76% 93.06% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 819035 1.08% 94.14% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4431879 5.86% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 76528583 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.121291 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.621008 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 26850978 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 36641611 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 11018000 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 937421 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1080572 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 523116 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 36832 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 63252649 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 110299 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1080572 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 27872767 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 14726920 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 18377517 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 10342666 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 4128139 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 59880890 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 6989 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 638699 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1446922 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands 40104744 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 72926681 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 72541237 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 385444 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 35232895 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 4871841 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 1468873 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 214348 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 11259122 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 9368607 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 6150188 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1144221 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 763596 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 53152910 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1825418 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 51980474 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 87912 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 5962808 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 3052808 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 1237037 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 76528583 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.679230 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.328773 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 75653727 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.108933 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.559051 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 26076145 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 36746783 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 10850479 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 927296 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1053023 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 507905 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 35356 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 62314637 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 105308 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1053023 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 27090322 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 15013520 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 18214120 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 10165522 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 4117218 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 58954969 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 7221 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 636497 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 1465868 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands 39489312 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 71817747 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 71438623 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 379124 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 34689683 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 4799621 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 1442009 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 210125 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 11209509 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 9215492 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 6028586 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1140138 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 729797 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 52283270 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1794569 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 51124724 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 87475 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 5854476 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 3047065 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 53422858 69.81% 69.81% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 10519380 13.75% 83.55% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 4737419 6.19% 89.74% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 3110993 4.07% 93.81% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2482363 3.24% 97.05% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1230781 1.61% 98.66% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 656198 0.86% 99.52% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 315996 0.41% 99.93% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 52595 0.07% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 52928215 69.96% 69.96% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 10364815 13.70% 83.66% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 4648030 6.14% 89.81% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 3048990 4.03% 93.84% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2439160 3.22% 97.06% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1210231 1.60% 98.66% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 645067 0.85% 99.51% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 315070 0.42% 99.93% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 54149 0.07% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 76528583 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 75653727 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 81649 11.89% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 11.89% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 319979 46.59% 58.47% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 285231 41.53% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 82277 12.13% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.13% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 315255 46.46% 58.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 280962 41.41% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 3782 0.01% 0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 35814992 68.90% 68.91% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 57898 0.11% 69.02% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.02% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 15714 0.03% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.05% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 9315059 17.92% 86.97% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5946213 11.44% 98.41% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess 824933 1.59% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 3785 0.01% 0.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 35245093 68.94% 68.95% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 56186 0.11% 69.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 15594 0.03% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 1879 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 9165347 17.93% 87.02% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5826893 11.40% 98.42% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess 809947 1.58% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 51980474 # Type of FU issued
-system.cpu0.iq.rate 0.501010 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 686859 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.013214 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 180712322 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 60686814 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 50945996 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 551979 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 267326 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 260492 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 52374713 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 288838 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 545458 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 51124724 # Type of FU issued
+system.cpu0.iq.rate 0.450136 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 678494 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.013271 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 178124739 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 59681238 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 50082929 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 544404 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 263662 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 256861 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 51514533 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 284900 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 542155 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1121947 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2762 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 13266 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 454260 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1111126 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 3856 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 12844 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 447697 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 18544 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 124618 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 18437 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 153340 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1080572 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 10513662 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 794213 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 58228726 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 618999 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 9368607 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 6150188 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 1608738 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 580049 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 5099 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 13266 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 168319 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 356582 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 524901 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 51585627 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 9008604 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 394846 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1053023 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 10729289 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 792549 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 57283617 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 622169 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 9215492 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 6028586 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 1581349 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 577410 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 6280 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 12844 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 162347 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 348099 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 510446 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 50735914 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 8864635 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 388809 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 3250398 # number of nop insts executed
-system.cpu0.iew.exec_refs 14908735 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 8218209 # Number of branches executed
-system.cpu0.iew.exec_stores 5900131 # Number of stores executed
-system.cpu0.iew.exec_rate 0.497205 # Inst execution rate
-system.cpu0.iew.wb_sent 51301062 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 51206488 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 25493361 # num instructions producing a value
-system.cpu0.iew.wb_consumers 34352042 # num instructions consuming a value
+system.cpu0.iew.exec_nop 3205778 # number of nop insts executed
+system.cpu0.iew.exec_refs 14644864 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 8078425 # Number of branches executed
+system.cpu0.iew.exec_stores 5780229 # Number of stores executed
+system.cpu0.iew.exec_rate 0.446713 # Inst execution rate
+system.cpu0.iew.wb_sent 50428595 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 50339790 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 25084021 # num instructions producing a value
+system.cpu0.iew.wb_consumers 33790368 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.493550 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.742121 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.443225 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.742342 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 6443785 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 588381 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 491234 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 75448011 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.685042 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.601476 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 6311482 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 579303 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 475138 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 74600704 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.681919 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.596319 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 56013876 74.24% 74.24% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 8117892 10.76% 85.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 4422865 5.86% 90.86% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 2392310 3.17% 94.03% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 1343441 1.78% 95.81% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 564278 0.75% 96.56% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 477580 0.63% 97.20% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 442296 0.59% 97.78% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1673473 2.22% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 55419889 74.29% 74.29% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 8033545 10.77% 85.06% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 4371447 5.86% 90.92% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 2356278 3.16% 94.08% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 1324268 1.78% 95.85% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 555518 0.74% 96.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 469565 0.63% 97.22% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 427219 0.57% 97.80% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1642975 2.20% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 75448011 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 51685042 # Number of instructions committed
-system.cpu0.commit.committedOps 51685042 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 74600704 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 50871658 # Number of instructions committed
+system.cpu0.commit.committedOps 50871658 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 13942588 # Number of memory references committed
-system.cpu0.commit.loads 8246660 # Number of loads committed
-system.cpu0.commit.membars 199926 # Number of memory barriers committed
-system.cpu0.commit.branches 7810095 # Number of branches committed
-system.cpu0.commit.fp_insts 258326 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 47876421 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 664533 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 1673473 # number cycles where commit BW limit reached
+system.cpu0.commit.refs 13685255 # Number of memory references committed
+system.cpu0.commit.loads 8104366 # Number of loads committed
+system.cpu0.commit.membars 196950 # Number of memory barriers committed
+system.cpu0.commit.branches 7686240 # Number of branches committed
+system.cpu0.commit.fp_insts 254806 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 47114322 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 650737 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 1642975 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 131700376 # The number of ROB reads
-system.cpu0.rob.rob_writes 117338865 # The number of ROB writes
-system.cpu0.timesIdled 1069961 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 27222708 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 3689125904 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 48725185 # Number of Instructions Simulated
-system.cpu0.committedOps 48725185 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 48725185 # Number of Instructions Simulated
-system.cpu0.cpi 2.129315 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.129315 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.469634 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.469634 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 67898060 # number of integer regfile reads
-system.cpu0.int_regfile_writes 37063784 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 127956 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 129360 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 1719000 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 824833 # number of misc regfile writes
+system.cpu0.rob.rob_reads 129943858 # The number of ROB reads
+system.cpu0.rob.rob_writes 115419344 # The number of ROB writes
+system.cpu0.timesIdled 1091777 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 37922373 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 3693821721 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 47948786 # Number of Instructions Simulated
+system.cpu0.committedOps 47948786 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 47948786 # Number of Instructions Simulated
+system.cpu0.cpi 2.368696 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.368696 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.422173 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.422173 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 66777793 # number of integer regfile reads
+system.cpu0.int_regfile_writes 36448823 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 126128 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 127569 # number of floating regfile writes
+system.cpu0.misc_regfile_reads 1693303 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 810480 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu0.icache.replacements 889638 # number of replacements
-system.cpu0.icache.tagsinuse 510.303457 # Cycle average of tags in use
-system.cpu0.icache.total_refs 6872883 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 890147 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 7.721065 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 20517812000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 510.303457 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.996686 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.996686 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 6872883 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 6872883 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 6872883 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 6872883 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 6872883 # number of overall hits
-system.cpu0.icache.overall_hits::total 6872883 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 935512 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 935512 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 935512 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 935512 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 935512 # number of overall misses
-system.cpu0.icache.overall_misses::total 935512 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13284271991 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 13284271991 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 13284271991 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 13284271991 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 13284271991 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 13284271991 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 7808395 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 7808395 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 7808395 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 7808395 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 7808395 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 7808395 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.119808 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.119808 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.119808 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.119808 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.119808 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.119808 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14200.001701 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14200.001701 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14200.001701 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14200.001701 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14200.001701 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14200.001701 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 5547 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 2537 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 3 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 34.240741 # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets 845.666667 # average number of cycles each access was blocked
+system.toL2Bus.throughput 111431458 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 2199741 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2199647 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 13135 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 13135 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 819443 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 10566 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 6236 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 16802 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 343057 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 301508 # Transaction distribution
+system.toL2Bus.trans_dist::BadAddressError 77 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1737096 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3343563 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 452207 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 314296 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count 5847162 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 55584064 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 129094452 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 14469760 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 11514982 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size 210663258 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 210652954 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 1479360 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 4959879460 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 3910967404 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 5778463419 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 1017961113 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 540290711 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.throughput 1437243 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 7369 # Transaction distribution
+system.iobus.trans_dist::ReadResp 7369 # Transaction distribution
+system.iobus.trans_dist::WriteReq 54687 # Transaction distribution
+system.iobus.trans_dist::WriteResp 54687 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 12062 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 40658 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.cchip.pio 12062 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 124112 # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 48248 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 74458 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.tsunami.cchip.pio 48248 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 2736082 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 2736082 # Total data (bytes)
+system.iobus.reqLayer0.occupancy 11417000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
+system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer29.occupancy 378279654 # Layer occupancy (ticks)
+system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 27523000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer1.occupancy 42014000 # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu0.icache.replacements 867916 # number of replacements
+system.cpu0.icache.tagsinuse 509.785268 # Cycle average of tags in use
+system.cpu0.icache.total_refs 6758563 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 868427 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 7.782534 # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 25769681000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst 509.785268 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.995674 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.995674 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 6758564 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 6758564 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 6758564 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 6758564 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 6758564 # number of overall hits
+system.cpu0.icache.overall_hits::total 6758564 # number of overall hits
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+system.cpu0.icache.ReadReq_misses::total 912847 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 912847 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 912847 # number of demand (read+write) misses
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+system.cpu0.icache.overall_misses::total 912847 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13149310993 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 13149310993 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 13149310993 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 13149310993 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 13149310993 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 13149310993 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 7671411 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 7671411 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 7671411 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 7671411 # number of demand (read+write) accesses
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+system.cpu0.icache.overall_accesses::total 7671411 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118993 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.118993 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118993 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.118993 # miss rate for demand accesses
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+system.cpu0.icache.overall_miss_rate::total 0.118993 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14404.726086 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14404.726086 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14404.726086 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14404.726086 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14404.726086 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14404.726086 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 3418 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 152 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.486842 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45203 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 45203 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst 45203 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 45203 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst 45203 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 45203 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 890309 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 890309 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 890309 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 890309 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 890309 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 890309 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10926647992 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 10926647992 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10926647992 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 10926647992 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10926647992 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 10926647992 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.114019 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.114019 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.114019 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.114019 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.114019 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.114019 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12272.871545 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12272.871545 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12272.871545 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12272.871545 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12272.871545 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12272.871545 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 44252 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 44252 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst 44252 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 44252 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst 44252 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 44252 # number of overall MSHR hits
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+system.cpu0.icache.ReadReq_mshr_misses::total 868595 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 868595 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 868595 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 868595 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 868595 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10814937089 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 10814937089 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10814937089 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 10814937089 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10814937089 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 10814937089 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.113225 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.113225 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.113225 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.113225 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.113225 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.113225 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12451.069934 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12451.069934 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12451.069934 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12451.069934 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12451.069934 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12451.069934 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 1284134 # number of replacements
-system.cpu0.dcache.tagsinuse 505.722211 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 10611019 # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs 1284646 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 8.259878 # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 22124000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 505.722211 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data 0.987739 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total 0.987739 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 6528989 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 6528989 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 3717707 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 3717707 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164546 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 164546 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 188999 # number of StoreCondReq hits
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system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu0.dcache.writebacks::total 757117 # number of writebacks
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+system.cpu0.dcache.overall_mshr_hits::total 2041072 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 998425 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 998425 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 272155 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 272155 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15584 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15584 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3020 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 3020 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 1270580 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 1270580 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 1270580 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 1270580 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 26454916051 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 26454916051 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11388682739 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11388682739 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 172348003 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 172348003 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 16164000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 16164000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 37843598790 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 37843598790 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 37843598790 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 37843598790 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1459347502 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1459347502 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2156087498 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2156087498 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3615435000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3615435000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125326 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125326 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050610 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050610 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085876 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.085876 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016010 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016010 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.095216 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.095216 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.095216 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.095216 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26496.648272 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26496.648272 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41846.310885 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41846.310885 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11059.291774 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11059.291774 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5352.317881 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5352.317881 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29784.506910 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29784.506910 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29784.506910 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29784.506910 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 2374472 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 1973565 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 63683 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 1357670 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 789569 # Number of BTB hits
+system.cpu1.branchPred.lookups 2604526 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 2153409 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 75247 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 1513707 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 876072 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 58.156179 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 159848 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 6979 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 57.875930 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 179167 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 7740 # Number of incorrect RAS predictions.
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 1755569 # DTB read hits
-system.cpu1.dtb.read_misses 9259 # DTB read misses
-system.cpu1.dtb.read_acv 6 # DTB read access violations
-system.cpu1.dtb.read_accesses 277737 # DTB read accesses
-system.cpu1.dtb.write_hits 1124169 # DTB write hits
-system.cpu1.dtb.write_misses 1775 # DTB write misses
-system.cpu1.dtb.write_acv 38 # DTB write access violations
-system.cpu1.dtb.write_accesses 104346 # DTB write accesses
-system.cpu1.dtb.data_hits 2879738 # DTB hits
-system.cpu1.dtb.data_misses 11034 # DTB misses
-system.cpu1.dtb.data_acv 44 # DTB access violations
-system.cpu1.dtb.data_accesses 382083 # DTB accesses
-system.cpu1.itb.fetch_hits 378886 # ITB hits
-system.cpu1.itb.fetch_misses 5643 # ITB misses
-system.cpu1.itb.fetch_acv 144 # ITB acv
-system.cpu1.itb.fetch_accesses 384529 # ITB accesses
+system.cpu1.dtb.read_hits 1932131 # DTB read hits
+system.cpu1.dtb.read_misses 10237 # DTB read misses
+system.cpu1.dtb.read_acv 25 # DTB read access violations
+system.cpu1.dtb.read_accesses 320506 # DTB read accesses
+system.cpu1.dtb.write_hits 1251341 # DTB write hits
+system.cpu1.dtb.write_misses 1962 # DTB write misses
+system.cpu1.dtb.write_acv 65 # DTB write access violations
+system.cpu1.dtb.write_accesses 130037 # DTB write accesses
+system.cpu1.dtb.data_hits 3183472 # DTB hits
+system.cpu1.dtb.data_misses 12199 # DTB misses
+system.cpu1.dtb.data_acv 90 # DTB access violations
+system.cpu1.dtb.data_accesses 450543 # DTB accesses
+system.cpu1.itb.fetch_hits 430844 # ITB hits
+system.cpu1.itb.fetch_misses 6753 # ITB misses
+system.cpu1.itb.fetch_acv 212 # ITB acv
+system.cpu1.itb.fetch_accesses 437597 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 14403389 # number of cpu cycles simulated
+system.cpu1.numCycles 15794943 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 5507969 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 11118541 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 2374472 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 949417 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 1985955 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 349018 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles 5777579 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 25749 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 54503 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 55745 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 7 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 1323443 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 42238 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 13629786 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.815753 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.191288 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 6044274 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 12313553 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 2604526 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 1055239 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 2204838 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 395965 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles 6209579 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 26246 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 62195 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 53260 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 20 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 1481011 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 50405 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 14852690 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.829045 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.204427 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 11643831 85.43% 85.43% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 125140 0.92% 86.35% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 217081 1.59% 87.94% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 155934 1.14% 89.08% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 266080 1.95% 91.04% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 106134 0.78% 91.82% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 117650 0.86% 92.68% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 192941 1.42% 94.09% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 804995 5.91% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 12647852 85.16% 85.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 141564 0.95% 86.11% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 235652 1.59% 87.70% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 175889 1.18% 88.88% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 303768 2.05% 90.92% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 119285 0.80% 91.73% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 129403 0.87% 92.60% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 209113 1.41% 94.01% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 890164 5.99% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 13629786 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.164855 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.771939 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 5440584 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 6013692 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 1859543 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 99467 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 216499 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 99353 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 5852 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 10916304 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 17556 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 216499 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 5632614 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 346968 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 5076489 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 1765081 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 592133 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 10097386 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 38 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 55596 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 134498 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands 6632848 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 12019300 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 11877082 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 142218 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 5717715 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 915133 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 422143 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 38586 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 1845577 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 1850340 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 1191384 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 164933 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 85198 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 8855097 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 461396 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 8635428 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 27588 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 1251794 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 621930 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 331901 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 13629786 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.633570 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.306468 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 14852690 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.164896 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.779588 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 5971093 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 6462269 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 2062064 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 112088 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 245175 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 113398 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 7205 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 12081319 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 21458 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 245175 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 6179272 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 425366 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 5395094 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 1962879 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 644902 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 11197795 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 87 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 57093 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 157527 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands 7361429 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 13363056 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 13213666 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 149390 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 6300177 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 1061252 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 451071 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 42573 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 1993362 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 2041709 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 1326014 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 180090 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 100258 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 9822573 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 491625 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 9565946 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 29815 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 1410113 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 705464 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 352077 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 14852690 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.644055 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.318534 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 9807862 71.96% 71.96% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 1774840 13.02% 84.98% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 743934 5.46% 90.44% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 492954 3.62% 94.06% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 425816 3.12% 97.18% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 193635 1.42% 98.60% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 119802 0.88% 99.48% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 63937 0.47% 99.95% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 7006 0.05% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 10648951 71.70% 71.70% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 1930050 12.99% 84.69% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 818337 5.51% 90.20% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 551122 3.71% 93.91% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 476075 3.21% 97.12% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 213789 1.44% 98.56% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 136394 0.92% 99.48% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 69529 0.47% 99.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 8443 0.06% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 13629786 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 14852690 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 2819 1.60% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 95112 53.88% 55.48% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 78586 44.52% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 3207 1.63% 1.63% # attempts to use FU when none available
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+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.63% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 106178 53.97% 55.60% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 87357 44.40% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 5368636 62.17% 62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 14579 0.17% 62.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 10813 0.13% 62.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.50% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 1836056 21.26% 83.79% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 1146030 13.27% 97.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess 254037 2.94% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 3526 0.04% 0.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 5966011 62.37% 62.40% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 16243 0.17% 62.57% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.57% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 10971 0.11% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.69% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 2021702 21.13% 83.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 1274955 13.33% 97.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess 270775 2.83% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 8635428 # Type of FU issued
-system.cpu1.iq.rate 0.599541 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 176517 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.020441 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 30899211 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 10469267 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 8392820 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 205536 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 100351 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 97198 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 8701253 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 107174 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 85247 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 9565946 # Type of FU issued
+system.cpu1.iq.rate 0.605633 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 196742 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.020567 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 33995446 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 11620704 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 9288457 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 215693 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 105258 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 101999 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 9646700 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 112462 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 92569 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 244767 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 715 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 1400 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 111607 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 282729 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 1535 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 1711 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 123624 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 264 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 8613 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 323 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 14236 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 216499 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 208020 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 39541 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 9780313 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 131211 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 1850340 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 1191384 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 418145 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 33976 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 1692 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 1400 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 28557 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 89287 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 117844 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 8559872 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 1771461 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 75556 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 245175 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 256542 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 43339 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 10829040 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 147658 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 2041709 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 1326014 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 444647 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 36382 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 1620 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 1711 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 33953 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 99696 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 133649 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 9473535 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 1949759 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 92411 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 463820 # number of nop insts executed
-system.cpu1.iew.exec_refs 2903123 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 1270722 # Number of branches executed
-system.cpu1.iew.exec_stores 1131662 # Number of stores executed
-system.cpu1.iew.exec_rate 0.594296 # Inst execution rate
-system.cpu1.iew.wb_sent 8515413 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 8490018 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 3998147 # num instructions producing a value
-system.cpu1.iew.wb_consumers 5641896 # num instructions consuming a value
+system.cpu1.iew.exec_nop 514842 # number of nop insts executed
+system.cpu1.iew.exec_refs 3209162 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 1413585 # Number of branches executed
+system.cpu1.iew.exec_stores 1259403 # Number of stores executed
+system.cpu1.iew.exec_rate 0.599783 # Inst execution rate
+system.cpu1.iew.wb_sent 9417236 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 9390456 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 4401006 # num instructions producing a value
+system.cpu1.iew.wb_consumers 6190652 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.589446 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.708653 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.594523 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.710912 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 1285480 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 129495 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 111745 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 13413287 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.628190 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.573982 # Number of insts commited each cycle
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system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 10261662 76.50% 76.50% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 1478959 11.03% 87.53% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 542849 4.05% 91.58% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 333012 2.48% 94.06% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 234215 1.75% 95.81% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 91771 0.68% 96.49% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 99946 0.75% 97.24% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 99972 0.75% 97.98% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 270901 2.02% 100.00% # Number of insts commited each cycle
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+system.cpu1.commit.committed_per_cycle::1 1625013 11.12% 87.29% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 604004 4.13% 91.43% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 371910 2.55% 93.98% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 263907 1.81% 95.78% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 102565 0.70% 96.48% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 109537 0.75% 97.23% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 110097 0.75% 97.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 293995 2.01% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 13413287 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 8426096 # Number of instructions committed
-system.cpu1.commit.committedOps 8426096 # Number of ops (including micro ops) committed
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system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
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-system.cpu1.commit.branches 1197085 # Number of branches committed
-system.cpu1.commit.fp_insts 95994 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 7795496 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 132738 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 270901 # number cycles where commit BW limit reached
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system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu1.idleCycles 773603 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 3777797828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 8011939 # Number of Instructions Simulated
-system.cpu1.committedOps 8011939 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 8011939 # Number of Instructions Simulated
-system.cpu1.cpi 1.797741 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.797741 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.556254 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.556254 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 11010177 # number of integer regfile reads
-system.cpu1.int_regfile_writes 6039470 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 53089 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 52904 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 494875 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 202385 # number of misc regfile writes
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-system.cpu1.icache.sampled_refs 202955 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 5.487788 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 1886714019000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 470.727745 # Average occupied blocks per requestor
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-system.cpu1.icache.occ_percent::total 0.919390 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 1113774 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 1113774 # number of ReadReq hits
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-system.cpu1.icache.overall_hits::total 1113774 # number of overall hits
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-system.cpu1.icache.ReadReq_misses::total 209669 # number of ReadReq misses
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-system.cpu1.icache.demand_misses::total 209669 # number of demand (read+write) misses
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-system.cpu1.icache.ReadReq_avg_miss_latency::total 13413.797462 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13413.797462 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13413.797462 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13413.797462 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13413.797462 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 72 # number of cycles access was blocked
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+system.cpu1.committedInsts 8842996 # Number of Instructions Simulated
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+system.cpu1.committedInsts_total 8842996 # Number of Instructions Simulated
+system.cpu1.cpi 1.786153 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 1.786153 # CPI: Total CPI of All Threads
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+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13505.800464 # average overall miss latency
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system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 9 # number of cycles access was blocked
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system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
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-system.cpu1.icache.demand_mshr_hits::total 6654 # number of demand (read+write) MSHR hits
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-system.cpu1.icache.ReadReq_mshr_misses::total 203015 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 203015 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 203015 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 203015 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 203015 # number of overall MSHR misses
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-system.cpu1.icache.ReadReq_mshr_miss_latency::total 2347033500 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2347033500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 2347033500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2347033500 # number of overall MSHR miss cycles
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-system.cpu1.icache.demand_mshr_miss_rate::total 0.153399 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.153399 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.153399 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11560.887127 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11560.887127 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11560.887127 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11560.887127 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11560.887127 # average overall mshr miss latency
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+system.cpu1.icache.demand_mshr_misses::cpu1.inst 226117 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 226117 # number of demand (read+write) MSHR misses
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+system.cpu1.icache.demand_mshr_miss_rate::total 0.152677 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.152677 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.152677 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11622.719154 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11622.719154 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11622.719154 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11622.719154 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11622.719154 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11622.719154 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.replacements 95898 # number of replacements
-system.cpu1.dcache.tagsinuse 491.044785 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 2359205 # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs 96213 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 24.520647 # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 39003208000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data 491.044785 # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data 0.959072 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total 0.959072 # Average percentage of cache occupancy
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-system.cpu1.dcache.ReadReq_hits::total 1444297 # number of ReadReq hits
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system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu1.dcache.writebacks::total 62482 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 119560 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 119560 # number of ReadReq MSHR hits
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-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25170.304162 # average WriteReq mshr miss latency
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-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16050.740032 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16050.740032 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16050.740032 # average overall mshr miss latency
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+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 594 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 308982 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 308982 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 308982 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 308982 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 79474 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 79474 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 39167 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 39167 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4916 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4916 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3216 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 3216 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 118641 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 118641 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 118641 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 118641 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 893939249 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 893939249 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1081571527 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1081571527 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 37210004 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 37210004 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 16953500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 16953500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1975510776 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 1975510776 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1975510776 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 1975510776 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 23615501 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 23615501 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 628297501 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 628297501 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 651913002 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 651913002 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044232 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044232 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033717 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033717 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.129066 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.129066 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092480 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092480 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040103 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.040103 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040103 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.040103 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11248.197511 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11248.197511 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27614.357163 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27614.357163 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7569.162734 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7569.162734 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5271.610697 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5271.610697 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16651.164235 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16651.164235 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16651.164235 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16651.164235 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6633 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 185817 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 65566 40.59% 40.59% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 131 0.08% 40.67% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1923 1.19% 41.86% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 201 0.12% 41.99% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 93709 58.01% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 161530 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 64589 49.22% 49.22% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1923 1.47% 50.78% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 201 0.15% 50.94% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 64388 49.06% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 131232 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1860847795500 98.12% 98.12% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 64543000 0.00% 98.13% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 567978500 0.03% 98.16% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 98193500 0.01% 98.16% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 34862560000 1.84% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1896441070500 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.985099 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce 6605 # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei 182638 # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0 64421 40.50% 40.50% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21 131 0.08% 40.58% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22 1925 1.21% 41.79% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30 210 0.13% 41.93% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 92368 58.07% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 159055 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 63463 49.20% 49.20% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22 1925 1.49% 50.80% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30 210 0.16% 50.96% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31 63253 49.04% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total 128982 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0 1863089530500 97.87% 97.87% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 64074500 0.00% 97.87% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 567937500 0.03% 97.90% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30 100797000 0.01% 97.91% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 39879064000 2.09% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1903701403500 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.985129 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.687106 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.812431 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed
-system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed
-system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed
-system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed
-system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed
-system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed
-system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed
-system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed
-system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed
-system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed
-system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed
-system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed
-system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed
-system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed
-system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed
-system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed
-system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed
-system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed
-system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed
-system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed
-system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed
-system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed
-system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed
-system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed
-system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed
-system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed
-system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed
-system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed
-system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total 234 # number of syscalls executed
+system.cpu0.kern.ipl_used::31 0.684793 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total 0.810927 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2 7 3.32% 3.32% # number of syscalls executed
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+system.cpu0.kern.syscall::4 4 1.90% 13.27% # number of syscalls executed
+system.cpu0.kern.syscall::6 29 13.74% 27.01% # number of syscalls executed
+system.cpu0.kern.syscall::12 1 0.47% 27.49% # number of syscalls executed
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+system.cpu0.kern.syscall::19 7 3.32% 35.55% # number of syscalls executed
+system.cpu0.kern.syscall::20 4 1.90% 37.44% # number of syscalls executed
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+system.cpu0.kern.syscall::24 3 1.42% 39.34% # number of syscalls executed
+system.cpu0.kern.syscall::33 8 3.79% 43.13% # number of syscalls executed
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+system.cpu0.kern.syscall::45 37 17.54% 61.61% # number of syscalls executed
+system.cpu0.kern.syscall::47 3 1.42% 63.03% # number of syscalls executed
+system.cpu0.kern.syscall::48 8 3.79% 66.82% # number of syscalls executed
+system.cpu0.kern.syscall::54 9 4.27% 71.09% # number of syscalls executed
+system.cpu0.kern.syscall::58 1 0.47% 71.56% # number of syscalls executed
+system.cpu0.kern.syscall::59 5 2.37% 73.93% # number of syscalls executed
+system.cpu0.kern.syscall::71 27 12.80% 86.73% # number of syscalls executed
+system.cpu0.kern.syscall::73 3 1.42% 88.15% # number of syscalls executed
+system.cpu0.kern.syscall::74 7 3.32% 91.47% # number of syscalls executed
+system.cpu0.kern.syscall::87 1 0.47% 91.94% # number of syscalls executed
+system.cpu0.kern.syscall::90 2 0.95% 92.89% # number of syscalls executed
+system.cpu0.kern.syscall::92 7 3.32% 96.21% # number of syscalls executed
+system.cpu0.kern.syscall::97 2 0.95% 97.16% # number of syscalls executed
+system.cpu0.kern.syscall::98 2 0.95% 98.10% # number of syscalls executed
+system.cpu0.kern.syscall::132 1 0.47% 98.58% # number of syscalls executed
+system.cpu0.kern.syscall::144 1 0.47% 99.05% # number of syscalls executed
+system.cpu0.kern.syscall::147 2 0.95% 100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total 211 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir 284 0.17% 0.17% # number of callpals executed
-system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed
-system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 3552 2.08% 2.25% # number of callpals executed
-system.cpu0.kern.callpal::tbi 51 0.03% 2.28% # number of callpals executed
+system.cpu0.kern.callpal::wripir 302 0.18% 0.18% # number of callpals executed
+system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed
+system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed
+system.cpu0.kern.callpal::swpctx 3478 2.07% 2.26% # number of callpals executed
+system.cpu0.kern.callpal::tbi 48 0.03% 2.29% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.29% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 154681 90.79% 93.08% # number of callpals executed
-system.cpu0.kern.callpal::rdps 6653 3.90% 96.98% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp 1 0.00% 96.98% # number of callpals executed
-system.cpu0.kern.callpal::wrusp 4 0.00% 96.98% # number of callpals executed
-system.cpu0.kern.callpal::rdusp 9 0.01% 96.99% # number of callpals executed
-system.cpu0.kern.callpal::whami 2 0.00% 96.99% # number of callpals executed
-system.cpu0.kern.callpal::rti 4593 2.70% 99.69% # number of callpals executed
-system.cpu0.kern.callpal::callsys 394 0.23% 99.92% # number of callpals executed
-system.cpu0.kern.callpal::imb 139 0.08% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 170374 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 7193 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches
+system.cpu0.kern.callpal::swpipl 152288 90.83% 93.12% # number of callpals executed
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+system.cpu0.kern.callpal::wrkgp 1 0.00% 97.02% # number of callpals executed
+system.cpu0.kern.callpal::wrusp 4 0.00% 97.02% # number of callpals executed
+system.cpu0.kern.callpal::rdusp 8 0.00% 97.03% # number of callpals executed
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+system.cpu0.kern.callpal::rti 4500 2.68% 99.71% # number of callpals executed
+system.cpu0.kern.callpal::callsys 345 0.21% 99.92% # number of callpals executed
+system.cpu0.kern.callpal::imb 137 0.08% 100.00% # number of callpals executed
+system.cpu0.kern.callpal::total 167660 # number of callpals executed
+system.cpu0.kern.mode_switch::kernel 7044 # number of protection mode switches
+system.cpu0.kern.mode_switch::user 1286 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1369
-system.cpu0.kern.mode_good::user 1370
+system.cpu0.kern.mode_good::kernel 1285
+system.cpu0.kern.mode_good::user 1286
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.190324 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.182425 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.319865 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1894375479500 99.89% 99.89% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 2065583000 0.11% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total 0.308643 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 1901692288000 99.89% 99.89% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 2009107500 0.11% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3553 # number of times the context was actually changed
+system.cpu0.kern.swap_context 3479 # number of times the context was actually changed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2383 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 53842 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 16791 36.23% 36.23% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1921 4.14% 40.37% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 284 0.61% 40.99% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 27352 59.01% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 46348 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 16391 47.23% 47.23% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1921 5.54% 52.77% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 284 0.82% 53.59% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 16107 46.41% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 34703 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1871184919000 98.69% 98.69% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 531151500 0.03% 98.71% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 127549500 0.01% 98.72% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 24258165000 1.28% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1896101785000 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.976178 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce 2459 # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei 57331 # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0 18009 36.73% 36.73% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22 1924 3.92% 40.65% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30 302 0.62% 41.27% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31 28797 58.73% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total 49032 # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0 17590 47.41% 47.41% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22 1924 5.19% 52.59% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30 302 0.81% 53.41% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31 17288 46.59% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total 37104 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0 1873168497000 98.41% 98.41% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 531845000 0.03% 98.44% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 136792000 0.01% 98.45% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 29552054000 1.55% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1903389188000 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0 0.976734 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.588878 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total 0.748749 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed
-system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed
-system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed
-system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed
-system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed
-system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed
-system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed
-system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed
-system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed
-system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed
-system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed
-system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed
-system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total 92 # number of syscalls executed
+system.cpu1.kern.ipl_used::31 0.600340 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total 0.756730 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::2 1 0.87% 0.87% # number of syscalls executed
+system.cpu1.kern.syscall::3 13 11.30% 12.17% # number of syscalls executed
+system.cpu1.kern.syscall::6 13 11.30% 23.48% # number of syscalls executed
+system.cpu1.kern.syscall::15 1 0.87% 24.35% # number of syscalls executed
+system.cpu1.kern.syscall::17 5 4.35% 28.70% # number of syscalls executed
+system.cpu1.kern.syscall::19 3 2.61% 31.30% # number of syscalls executed
+system.cpu1.kern.syscall::20 2 1.74% 33.04% # number of syscalls executed
+system.cpu1.kern.syscall::23 3 2.61% 35.65% # number of syscalls executed
+system.cpu1.kern.syscall::24 3 2.61% 38.26% # number of syscalls executed
+system.cpu1.kern.syscall::33 3 2.61% 40.87% # number of syscalls executed
+system.cpu1.kern.syscall::45 17 14.78% 55.65% # number of syscalls executed
+system.cpu1.kern.syscall::47 3 2.61% 58.26% # number of syscalls executed
+system.cpu1.kern.syscall::48 2 1.74% 60.00% # number of syscalls executed
+system.cpu1.kern.syscall::54 1 0.87% 60.87% # number of syscalls executed
+system.cpu1.kern.syscall::59 2 1.74% 62.61% # number of syscalls executed
+system.cpu1.kern.syscall::71 27 23.48% 86.09% # number of syscalls executed
+system.cpu1.kern.syscall::74 9 7.83% 93.91% # number of syscalls executed
+system.cpu1.kern.syscall::90 1 0.87% 94.78% # number of syscalls executed
+system.cpu1.kern.syscall::92 2 1.74% 96.52% # number of syscalls executed
+system.cpu1.kern.syscall::132 3 2.61% 99.13% # number of syscalls executed
+system.cpu1.kern.syscall::144 1 0.87% 100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total 115 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir 201 0.42% 0.42% # number of callpals executed
-system.cpu1.kern.callpal::wrmces 1 0.00% 0.43% # number of callpals executed
-system.cpu1.kern.callpal::wrfen 1 0.00% 0.43% # number of callpals executed
-system.cpu1.kern.callpal::swpctx 1067 2.24% 2.67% # number of callpals executed
-system.cpu1.kern.callpal::tbi 3 0.01% 2.67% # number of callpals executed
-system.cpu1.kern.callpal::wrent 7 0.01% 2.69% # number of callpals executed
-system.cpu1.kern.callpal::swpipl 41171 86.33% 89.01% # number of callpals executed
-system.cpu1.kern.callpal::rdps 2098 4.40% 93.41% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp 1 0.00% 93.41% # number of callpals executed
-system.cpu1.kern.callpal::wrusp 3 0.01% 93.42% # number of callpals executed
-system.cpu1.kern.callpal::whami 3 0.01% 93.43% # number of callpals executed
-system.cpu1.kern.callpal::rti 2971 6.23% 99.66% # number of callpals executed
-system.cpu1.kern.callpal::callsys 121 0.25% 99.91% # number of callpals executed
-system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir 210 0.41% 0.42% # number of callpals executed
+system.cpu1.kern.callpal::wrmces 1 0.00% 0.42% # number of callpals executed
+system.cpu1.kern.callpal::wrfen 1 0.00% 0.42% # number of callpals executed
+system.cpu1.kern.callpal::swpctx 1165 2.30% 2.72% # number of callpals executed
+system.cpu1.kern.callpal::tbi 6 0.01% 2.73% # number of callpals executed
+system.cpu1.kern.callpal::wrent 7 0.01% 2.75% # number of callpals executed
+system.cpu1.kern.callpal::swpipl 43701 86.29% 89.04% # number of callpals executed
+system.cpu1.kern.callpal::rdps 2223 4.39% 93.43% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp 1 0.00% 93.43% # number of callpals executed
+system.cpu1.kern.callpal::wrusp 3 0.01% 93.44% # number of callpals executed
+system.cpu1.kern.callpal::rdusp 1 0.00% 93.44% # number of callpals executed
+system.cpu1.kern.callpal::whami 3 0.01% 93.44% # number of callpals executed
+system.cpu1.kern.callpal::rti 3104 6.13% 99.57% # number of callpals executed
+system.cpu1.kern.callpal::callsys 172 0.34% 99.91% # number of callpals executed
+system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 47692 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 1242 # number of protection mode switches
-system.cpu1.kern.mode_switch::user 368 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2406 # number of protection mode switches
-system.cpu1.kern.mode_good::kernel 576
-system.cpu1.kern.mode_good::user 368
-system.cpu1.kern.mode_good::idle 208
-system.cpu1.kern.mode_switch_good::kernel 0.463768 # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total 50643 # number of callpals executed
+system.cpu1.kern.mode_switch::kernel 1414 # number of protection mode switches
+system.cpu1.kern.mode_switch::user 459 # number of protection mode switches
+system.cpu1.kern.mode_switch::idle 2447 # number of protection mode switches
+system.cpu1.kern.mode_good::kernel 685
+system.cpu1.kern.mode_good::user 459
+system.cpu1.kern.mode_good::idle 226
+system.cpu1.kern.mode_switch_good::kernel 0.484441 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle 0.086451 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total 0.286853 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 4070064000 0.21% 0.21% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 689483000 0.04% 0.25% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1891020032000 99.75% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 1068 # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle 0.092358 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total 0.317130 # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel 4654463000 0.24% 0.24% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user 807268500 0.04% 0.29% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle 1897916233000 99.71% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context 1166 # number of times the context was actually changed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 1.854316 # Number of seconds simulated
-sim_ticks 1854315535000 # Number of ticks simulated
-final_tick 1854315535000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.859220 # Number of seconds simulated
+sim_ticks 1859219766000 # Number of ticks simulated
+final_tick 1859219766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 136218 # Simulator instruction rate (inst/s)
-host_op_rate 136218 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4770234092 # Simulator tick rate (ticks/s)
-host_mem_usage 308432 # Number of bytes of host memory used
-host_seconds 388.73 # Real time elapsed on the host
-sim_insts 52951550 # Number of instructions simulated
-sim_ops 52951550 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 963520 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24877248 # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28493120 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 963520 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 963520 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7502080 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7502080 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 15055 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 388707 # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 445205 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 117220 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 117220 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 519610 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 13415866 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1430367 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15365842 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 519610 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 519610 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4045741 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4045741 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4045741 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 519610 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 13415866 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1430367 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19411583 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 445205 # Total number of read requests seen
-system.physmem.writeReqs 117220 # Total number of write requests seen
-system.physmem.cpureqs 562608 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 28493120 # Total number of bytes read from memory
-system.physmem.bytesWritten 7502080 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 28493120 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7502080 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 56 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 28016 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 27755 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 27572 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 27335 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 27903 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 27978 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 27988 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 27793 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 28085 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 27815 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 27957 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 27734 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 27759 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 27962 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 27777 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 27720 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 7553 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7293 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 7144 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 6986 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7373 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 7381 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7449 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 7333 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 7646 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7356 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7497 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 7211 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 7256 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 7369 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 7178 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 7195 # Track writes on a per bank basis
+host_inst_rate 91264 # Simulator instruction rate (inst/s)
+host_op_rate 91264 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3202546943 # Simulator tick rate (ticks/s)
+host_mem_usage 310256 # Number of bytes of host memory used
+host_seconds 580.54 # Real time elapsed on the host
+sim_insts 52982774 # Number of instructions simulated
+sim_ops 52982774 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24879168 # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28495424 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 963968 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 963968 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7515392 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7515392 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 15062 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 388737 # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 445241 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 117428 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 117428 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 518480 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 13381510 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1426560 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15326550 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 518480 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 518480 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4042229 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4042229 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4042229 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 518480 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 13381510 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1426560 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19368779 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 445241 # Total number of read requests seen
+system.physmem.writeReqs 117428 # Total number of write requests seen
+system.physmem.cpureqs 562841 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 28495424 # Total number of bytes read from memory
+system.physmem.bytesWritten 7515392 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 28495424 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7515392 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 171 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 28229 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 27975 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 28436 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 28026 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 27802 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 27225 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 27248 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 27297 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 27658 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 27398 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 27928 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 27536 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 27551 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 28226 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 28326 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 28320 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7932 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7499 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 7946 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 7517 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7344 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 6679 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 6762 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 6683 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7096 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 6802 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7320 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 6981 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7118 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 7875 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 8048 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7826 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1854310136000 # Total gap between requests
+system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1859214351000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 445205 # Categorize read packet sizes
+system.physmem.readPktSize::6 445241 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 117220 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 323472 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 64407 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 19558 # What read queue length does an incoming req see
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+system.physmem.totQLat 6065400750 # Total cycles spent in queuing delays
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 34133.05 # Average memory access latency
-system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 4.05 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 30167.56 # Average memory access latency
+system.physmem.avgRdBW 15.33 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 15.33 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 4.04 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.15 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 7.57 # Average write queue length over time
-system.physmem.readRowHits 417721 # Number of row buffer hits during reads
-system.physmem.writeRowHits 91342 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 93.84 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 77.92 # Row buffer hit rate for writes
-system.physmem.avgGap 3296990.95 # Average gap between requests
+system.physmem.avgWrQLen 11.93 # Average write queue length over time
+system.physmem.readRowHits 430163 # Number of row buffer hits during reads
+system.physmem.writeRowHits 94965 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 96.63 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 80.87 # Row buffer hit rate for writes
+system.physmem.avgGap 3304277.21 # Average gap between requests
+system.membus.throughput 19411663 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 296022 # Transaction distribution
+system.membus.trans_dist::ReadResp 295937 # Transaction distribution
+system.membus.trans_dist::WriteReq 9598 # Transaction distribution
+system.membus.trans_dist::WriteResp 9598 # Transaction distribution
+system.membus.trans_dist::Writeback 117428 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 173 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 174 # Transaction distribution
+system.membus.trans_dist::ReadExReq 156790 # Transaction distribution
+system.membus.trans_dist::ReadExResp 156790 # Transaction distribution
+system.membus.trans_dist::BadAddressError 85 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884132 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917358 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.bridge.slave 33056 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port 1008811 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.membus.badaddr_responder.pio 170 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1042037 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30701760 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30745908 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.physmem.port 36010816 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 36054964 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 36054964 # Total data (bytes)
+system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 29876000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 1541728249 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 108500 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 3763624798 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.membus.respLayer2.occupancy 376221741 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.iocache.replacements 41685 # number of replacements
-system.iocache.tagsinuse 1.265062 # Cycle average of tags in use
+system.iocache.tagsinuse 1.261712 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 1704476481000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide 1.265062 # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide 0.079066 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.079066 # Average percentage of cache occupancy
+system.iocache.warmup_cycle 1709369770000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide 1.261712 # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide 0.078857 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.078857 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses
system.iocache.overall_misses::total 41725 # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 10641558911 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10641558911 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 10662486909 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10662486909 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 10662486909 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10662486909 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::tsunami.ide 21342883 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 21342883 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 10471007269 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 10471007269 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 10492350152 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 10492350152 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 10492350152 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 10492350152 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256102.207138 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 256102.207138 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 255541.927118 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 255541.927118 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 255541.927118 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 255541.927118 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 285704 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123369.265896 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 123369.265896 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 251997.672049 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 251997.672049 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 251464.353553 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 251464.353553 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 251464.353553 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 251464.353553 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 273612 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 27220 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 27136 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 10.496106 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 10.082989 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8479547437 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 8479547437 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 8491478686 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 8491478686 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 8491478686 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 8491478686 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12346133 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 12346133 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8309607278 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 8309607278 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 8321953411 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 8321953411 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 8321953411 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 8321953411 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204070.741168 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 204070.741168 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203510.573661 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 203510.573661 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203510.573661 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 203510.573661 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71364.930636 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 71364.930636 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199980.922170 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 199980.922170 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199447.655147 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 199447.655147 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199447.655147 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 199447.655147 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 13835452 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11604498 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 397875 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9360236 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 5805061 # Number of BTB hits
+system.cpu.branchPred.lookups 13839600 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11609173 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 399191 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9510547 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 5805743 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 62.018319 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 907052 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 38979 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 61.045311 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 906368 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 39168 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 9913942 # DTB read hits
-system.cpu.dtb.read_misses 41971 # DTB read misses
-system.cpu.dtb.read_acv 559 # DTB read access violations
-system.cpu.dtb.read_accesses 941163 # DTB read accesses
-system.cpu.dtb.write_hits 6591840 # DTB write hits
-system.cpu.dtb.write_misses 10659 # DTB write misses
+system.cpu.dtb.read_hits 9923550 # DTB read hits
+system.cpu.dtb.read_misses 41274 # DTB read misses
+system.cpu.dtb.read_acv 543 # DTB read access violations
+system.cpu.dtb.read_accesses 941562 # DTB read accesses
+system.cpu.dtb.write_hits 6598688 # DTB write hits
+system.cpu.dtb.write_misses 10641 # DTB write misses
system.cpu.dtb.write_acv 411 # DTB write access violations
-system.cpu.dtb.write_accesses 337869 # DTB write accesses
-system.cpu.dtb.data_hits 16505782 # DTB hits
-system.cpu.dtb.data_misses 52630 # DTB misses
-system.cpu.dtb.data_acv 970 # DTB access violations
-system.cpu.dtb.data_accesses 1279032 # DTB accesses
-system.cpu.itb.fetch_hits 1304387 # ITB hits
-system.cpu.itb.fetch_misses 38101 # ITB misses
-system.cpu.itb.fetch_acv 1094 # ITB acv
-system.cpu.itb.fetch_accesses 1342488 # ITB accesses
+system.cpu.dtb.write_accesses 338433 # DTB write accesses
+system.cpu.dtb.data_hits 16522238 # DTB hits
+system.cpu.dtb.data_misses 51915 # DTB misses
+system.cpu.dtb.data_acv 954 # DTB access violations
+system.cpu.dtb.data_accesses 1279995 # DTB accesses
+system.cpu.itb.fetch_hits 1308614 # ITB hits
+system.cpu.itb.fetch_misses 36742 # ITB misses
+system.cpu.itb.fetch_acv 1058 # ITB acv
+system.cpu.itb.fetch_accesses 1345356 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 108709176 # number of cpu cycles simulated
+system.cpu.numCycles 120145786 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 28075681 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 70625770 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 13835452 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 6712113 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 13231336 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1982002 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 37359508 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 32821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 254255 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 361301 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 440 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 8540739 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 263307 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 80598838 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.876263 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.220111 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 28059248 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 70722559 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 13839600 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 6712111 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 13258692 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1994060 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 38168658 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 32286 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 254324 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 364483 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 291 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 8570347 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 266679 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 81425482 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.868556 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.211321 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 67367502 83.58% 83.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 852306 1.06% 84.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1694888 2.10% 86.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 821828 1.02% 87.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2746821 3.41% 91.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 564765 0.70% 91.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 643702 0.80% 92.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1011325 1.25% 93.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 4895701 6.07% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 68166790 83.72% 83.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 854823 1.05% 84.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1706158 2.10% 86.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 819634 1.01% 87.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2757548 3.39% 91.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 561946 0.69% 91.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 649151 0.80% 92.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1013766 1.25% 93.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 4895666 6.01% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 80598838 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.127270 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.649676 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 29246161 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 37051175 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 12098296 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 961855 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1241350 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 583461 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 42570 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 69332672 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 129212 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1241350 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 30366961 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 13601503 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 19800886 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 11334089 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 4254047 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 65583694 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 7011 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 505967 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 1480663 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 43793573 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 79610392 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 79131107 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 479285 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 38157493 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 5636072 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1682036 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 239674 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12118674 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 10434139 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 6898397 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1310169 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 877649 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 58153519 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2049469 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 56771792 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 109314 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 6892902 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 3544978 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1388546 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 80598838 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.704375 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.365163 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 81425482 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.115190 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.588640 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 29284437 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 37811275 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 12102091 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 982484 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1245194 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 583690 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 42726 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 69419384 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 129751 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1245194 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 30419678 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 14066203 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 19996824 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 11337239 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 4360342 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 65632842 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 7067 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 503743 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 1590486 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 43821413 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 79676034 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 79196502 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 479532 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 38182467 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 5638938 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1682867 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 239802 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12252220 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 10440672 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 6902467 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1316833 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 861587 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 58171642 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2051698 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 56802904 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 100593 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 6885118 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 3554028 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1390714 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 81425482 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.697606 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.359574 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 55952160 69.42% 69.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 10819456 13.42% 82.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 5161521 6.40% 89.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 3379007 4.19% 93.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 2642777 3.28% 96.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 1459621 1.81% 98.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 760708 0.94% 99.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 329892 0.41% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 93696 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 56719527 69.66% 69.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 10865996 13.34% 83.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 5212450 6.40% 89.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 3349939 4.11% 93.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 2634366 3.24% 96.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 1460723 1.79% 98.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 752656 0.92% 99.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 333424 0.41% 99.88% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 80598838 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 81425482 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 91294 11.60% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 373063 47.40% 59.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 322658 41.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 93250 11.76% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 372953 47.03% 58.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 326761 41.21% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 38708062 68.18% 68.19% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 61690 0.11% 68.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 10346391 18.22% 86.58% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 6670119 11.75% 98.33% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 949001 1.67% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 38720727 68.17% 68.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 61725 0.11% 68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 10357561 18.23% 86.57% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 6677285 11.76% 98.33% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess 949077 1.67% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 56771792 # Type of FU issued
-system.cpu.iq.rate 0.522236 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 787015 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.013863 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 194345553 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 66772978 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 55538078 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 693197 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 336730 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 327888 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 57189578 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 361943 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 597316 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 56802904 # Type of FU issued
+system.cpu.iq.rate 0.472783 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 792964 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.013960 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 195231977 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 66785301 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 55558093 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 692869 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 336906 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 327947 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 57227049 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 361533 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 597916 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1346178 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 3275 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14144 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 522891 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1347952 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 3269 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 14100 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 524235 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 17954 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 174426 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 17914 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 199705 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1241350 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 9930800 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 684897 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 63726259 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 676325 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 10434139 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 6898397 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1805166 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 512910 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 18627 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 14144 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 201347 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 411340 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 612687 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 56305820 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 9984116 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 465971 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1245194 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 10207267 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 699182 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 63757422 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 685568 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 10440672 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 6902467 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1806514 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 512114 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 18348 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 14100 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 200766 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 410779 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 611545 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 56334870 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 9992999 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 468033 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 3523271 # number of nop insts executed
-system.cpu.iew.exec_refs 16601850 # number of memory reference insts executed
-system.cpu.iew.exec_branches 8919814 # Number of branches executed
-system.cpu.iew.exec_stores 6617734 # Number of stores executed
-system.cpu.iew.exec_rate 0.517949 # Inst execution rate
-system.cpu.iew.wb_sent 55981553 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 55865966 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 27748179 # num instructions producing a value
-system.cpu.iew.wb_consumers 37603022 # num instructions consuming a value
+system.cpu.iew.exec_nop 3534082 # number of nop insts executed
+system.cpu.iew.exec_refs 16617553 # number of memory reference insts executed
+system.cpu.iew.exec_branches 8923539 # Number of branches executed
+system.cpu.iew.exec_stores 6624554 # Number of stores executed
+system.cpu.iew.exec_rate 0.468888 # Inst execution rate
+system.cpu.iew.wb_sent 55999832 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 55886040 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 27701007 # num instructions producing a value
+system.cpu.iew.wb_consumers 37529982 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.513903 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.737924 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.465152 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.738103 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 7467988 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 660923 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 566730 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 79357488 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.707446 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.635929 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 7465540 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 660984 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 567902 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 80180288 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.700591 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.629829 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 58581738 73.82% 73.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 8607533 10.85% 84.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4610804 5.81% 90.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2534837 3.19% 93.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1515398 1.91% 95.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 609514 0.77% 96.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 522093 0.66% 97.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 538800 0.68% 97.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 1836771 2.31% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 59372363 74.05% 74.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 8630775 10.76% 84.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4656269 5.81% 90.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2498281 3.12% 93.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1510890 1.88% 95.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 609736 0.76% 96.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 522635 0.65% 97.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 527296 0.66% 97.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 1852043 2.31% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 79357488 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 56141140 # Number of instructions committed
-system.cpu.commit.committedOps 56141140 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 80180288 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 56173622 # Number of instructions committed
+system.cpu.commit.committedOps 56173622 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 15463467 # Number of memory references committed
-system.cpu.commit.loads 9087961 # Number of loads committed
-system.cpu.commit.membars 226334 # Number of memory barriers committed
-system.cpu.commit.branches 8436593 # Number of branches committed
+system.cpu.commit.refs 15470952 # Number of memory references committed
+system.cpu.commit.loads 9092720 # Number of loads committed
+system.cpu.commit.membars 226359 # Number of memory barriers committed
+system.cpu.commit.branches 8440448 # Number of branches committed
system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 51992006 # Number of committed integer instructions.
-system.cpu.commit.function_calls 740231 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 1836771 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 52023156 # Number of committed integer instructions.
+system.cpu.commit.function_calls 740622 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 1852043 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 140880188 # The number of ROB reads
-system.cpu.rob.rob_writes 128461324 # The number of ROB writes
-system.cpu.timesIdled 1178621 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 28110338 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 3599915455 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 52951550 # Number of Instructions Simulated
-system.cpu.committedOps 52951550 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 52951550 # Number of Instructions Simulated
-system.cpu.cpi 2.052993 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.052993 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.487094 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.487094 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 73826909 # number of integer regfile reads
-system.cpu.int_regfile_writes 40289801 # number of integer regfile writes
-system.cpu.fp_regfile_reads 166028 # number of floating regfile reads
-system.cpu.fp_regfile_writes 167439 # number of floating regfile writes
-system.cpu.misc_regfile_reads 1985478 # number of misc regfile reads
-system.cpu.misc_regfile_writes 938924 # number of misc regfile writes
+system.cpu.rob.rob_reads 141717845 # The number of ROB reads
+system.cpu.rob.rob_writes 128525319 # The number of ROB writes
+system.cpu.timesIdled 1192872 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 38720304 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 3598287306 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 52982774 # Number of Instructions Simulated
+system.cpu.committedOps 52982774 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 52982774 # Number of Instructions Simulated
+system.cpu.cpi 2.267639 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.267639 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.440987 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.440987 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 73877727 # number of integer regfile reads
+system.cpu.int_regfile_writes 40299404 # number of integer regfile writes
+system.cpu.fp_regfile_reads 166073 # number of floating regfile reads
+system.cpu.fp_regfile_writes 167447 # number of floating regfile writes
+system.cpu.misc_regfile_reads 1985193 # number of misc regfile reads
+system.cpu.misc_regfile_writes 938984 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu.icache.replacements 1007426 # number of replacements
-system.cpu.icache.tagsinuse 510.288426 # Cycle average of tags in use
-system.cpu.icache.total_refs 7476565 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 1007934 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 7.417713 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 20275724000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 510.288426 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.996657 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.996657 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 7476566 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 7476566 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 7476566 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 7476566 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 7476566 # number of overall hits
-system.cpu.icache.overall_hits::total 7476566 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1064170 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1064170 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1064170 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1064170 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1064170 # number of overall misses
-system.cpu.icache.overall_misses::total 1064170 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 14673680991 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 14673680991 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 14673680991 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 14673680991 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 14673680991 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 14673680991 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 8540736 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 8540736 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 8540736 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 8540736 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 8540736 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 8540736 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124599 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.124599 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.124599 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.124599 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.124599 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.124599 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13788.850457 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13788.850457 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13788.850457 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13788.850457 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13788.850457 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13788.850457 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 6348 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 862 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 199 # number of cycles access was blocked
+system.iobus.throughput 1455318 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
+system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
+system.iobus.trans_dist::WriteReq 51150 # Transaction distribution
+system.iobus.trans_dist::WriteResp 51150 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38119.936673 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.LoadLockedReq_mshr_misses::total 17463 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1383340 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1383340 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1383340 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1383340 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21322279500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 21322279500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9864847262 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 9864847262 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 200761000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 200761000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 66500 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 66500 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31187126762 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 31187126762 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31187126762 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 31187126762 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423835500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423835500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997377498 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997377498 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421212998 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421212998 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120266 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120266 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048856 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048856 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083684 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083684 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000023 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091302 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.091302 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091302 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.091302 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19686.271586 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19686.271586 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32856.976718 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32856.976718 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11496.363740 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11496.363740 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13300 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13300 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22544.802263 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22544.802263 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22544.802263 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22544.802263 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 840976 # number of writebacks
+system.cpu.dcache.writebacks::total 840976 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 719736 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 719736 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643409 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1643409 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5171 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 5171 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 2363145 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 2363145 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2363145 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 2363145 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084321 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1084321 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300378 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 300378 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17577 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 17577 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1384699 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1384699 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1384699 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1384699 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26518641540 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 26518641540 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11550001786 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 11550001786 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 202636005 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 202636005 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 57000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 57000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38068643326 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 38068643326 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38068643326 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 38068643326 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424047000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424047000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997793498 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997793498 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421840498 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421840498 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120414 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120414 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048858 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048858 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084224 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084224 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000019 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091382 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.091382 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091382 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.091382 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24456.449280 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24456.449280 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38451.556992 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38451.556992 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11528.474996 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11528.474996 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14250 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14250 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27492.359947 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 27492.359947 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27492.359947 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 27492.359947 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei 211001 # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0 74662 40.97% 40.97% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei 211017 # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0 74665 40.97% 40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31 105560 57.93% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total 182232 # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0 73295 49.32% 49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31 105572 57.93% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total 182248 # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0 73298 49.32% 49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31 73295 49.32% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total 148600 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1818327594000 98.06% 98.06% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 63775000 0.00% 98.06% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 558444000 0.03% 98.09% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 35364889500 1.91% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1854314702500 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31 73298 49.32% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total 148607 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0 1817988566000 97.78% 97.78% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21 64092000 0.00% 97.79% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22 554660500 0.03% 97.82% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 40611610500 2.18% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1859218929000 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0 0.981692 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31 0.694344 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total 0.815444 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31 0.694294 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total 0.815411 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl 175117 91.23% 93.43% # number of callpals executed
+system.cpu.kern.callpal::swpipl 175131 91.23% 93.43% # number of callpals executed
system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed
-system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed
+system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 191961 # number of callpals executed
-system.cpu.kern.mode_switch::kernel 5849 # number of protection mode switches
-system.cpu.kern.mode_switch::user 1739 # number of protection mode switches
-system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
-system.cpu.kern.mode_good::kernel 1909
-system.cpu.kern.mode_good::user 1739
+system.cpu.kern.callpal::total 191976 # number of callpals executed
+system.cpu.kern.mode_switch::kernel 5853 # number of protection mode switches
+system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
+system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches
+system.cpu.kern.mode_good::kernel 1910
+system.cpu.kern.mode_good::user 1740
system.cpu.kern.mode_good::idle 170
-system.cpu.kern.mode_switch_good::kernel 0.326381 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel 0.326328 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total 0.394218 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 29464996000 1.59% 1.59% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 2711269000 0.15% 1.74% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1822138429500 98.26% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total 0.394343 # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel 29661883000 1.60% 1.60% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user 2771562000 0.15% 1.74% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle 1826785476000 98.26% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 1.841721 # Number of seconds simulated
-sim_ticks 1841721066000 # Number of ticks simulated
-final_tick 1841721066000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.842698 # Number of seconds simulated
+sim_ticks 1842697801000 # Number of ticks simulated
+final_tick 1842697801000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 314597 # Simulator instruction rate (inst/s)
-host_op_rate 314597 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 8282501609 # Simulator tick rate (ticks/s)
-host_mem_usage 307380 # Number of bytes of host memory used
-host_seconds 222.36 # Real time elapsed on the host
-sim_insts 69954713 # Number of instructions simulated
-sim_ops 69954713 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 472704 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 19360768 # Number of bytes read from this memory
+host_inst_rate 215096 # Simulator instruction rate (inst/s)
+host_op_rate 215096 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5452418287 # Simulator tick rate (ticks/s)
+host_mem_usage 309280 # Number of bytes of host memory used
+host_seconds 337.96 # Real time elapsed on the host
+sim_insts 72693799 # Number of instructions simulated
+sim_ops 72693799 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 487424 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 20019264 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 152256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 2811776 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 294016 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 2696640 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28440512 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 472704 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 152256 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 294016 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 918976 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7466048 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7466048 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 7386 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 302512 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu1.inst 147904 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 2316480 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 282624 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 2529216 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28435264 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 487424 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 147904 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 282624 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 917952 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7459584 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7459584 # Number of bytes written to this memory
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+system.physmem.num_reads::cpu0.data 312801 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2379 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 43934 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 4594 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 42135 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 444383 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 116657 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 116657 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 256664 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 10512324 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1440149 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 82670 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1526711 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 159642 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 1464196 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15442356 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 256664 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 82670 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 159642 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 498977 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4053843 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4053843 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4053843 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 256664 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 10512324 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1440149 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 82670 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 1526711 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 159642 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 1464196 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19496199 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 109805 # Total number of read requests seen
-system.physmem.writeReqs 45348 # Total number of write requests seen
-system.physmem.cpureqs 155202 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 7027520 # Total number of bytes read from memory
-system.physmem.bytesWritten 2902272 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 7027520 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 2902272 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 5 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 42 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 6903 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 6718 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 6604 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 6507 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 6918 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 6911 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 6891 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 6873 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 7028 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 6837 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 7200 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 6974 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 6884 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 6958 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 6841 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 6753 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 2939 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 2758 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 2643 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 2556 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 2819 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 2749 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 2776 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 2848 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 3031 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 2909 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 3192 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 2889 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 2835 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 2902 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 2803 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 2699 # Track writes on a per bank basis
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+system.physmem.num_reads::cpu1.data 36195 # Number of read requests responded to by this memory
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+system.physmem.num_writes::total 116556 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 264517 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 10864106 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_read::cpu1.inst 80265 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 1257113 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 153375 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 1372561 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15431322 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 264517 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 80265 # Instruction read bandwidth from this memory (bytes/s)
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+system.physmem.bw_inst_read::total 498157 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4048186 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4048186 # Write bandwidth from this memory (bytes/s)
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+system.physmem.bw_total::cpu0.inst 264517 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::cpu1.inst 80265 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::cpu2.data 1372561 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19479509 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 99716 # Total number of read requests seen
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+system.physmem.cpureqs 144680 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 6381824 # Total number of bytes read from memory
+system.physmem.bytesWritten 2874880 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 6381824 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 2874880 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 44 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 6258 # Track reads on a per bank basis
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+system.physmem.perBankRdReqs::5 6396 # Track reads on a per bank basis
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+system.physmem.perBankRdReqs::14 6370 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 6146 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 2882 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::4 2624 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::12 2472 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 2709 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 2853 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 2760 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1840708761500 # Total gap between requests
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1841685476500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 109805 # Categorize read packet sizes
+system.physmem.readPktSize::6 99716 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 45348 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 80824 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 9409 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 5385 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::5 1199 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1092 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 1088 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 1066 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1043 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::11 590 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::13 554 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 550 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::17 614 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 376 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 44920 # Categorize write packet sizes
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+system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1413 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1617 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1638 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1833 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1972 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1971 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1969 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1965 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1972 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1970 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1968 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1965 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1964 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1962 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1960 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 1959 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 1957 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 1954 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 1953 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 1953 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 1951 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 1950 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 781 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 589 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 373 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 350 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 152 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 13 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see
-system.physmem.totQLat 2404806500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 4407346500 # Sum of mem lat for all requests
-system.physmem.totBusLat 549000000 # Total cycles spent in databus access
-system.physmem.totBankLat 1453540000 # Total cycles spent in bank access
-system.physmem.avgQLat 21901.70 # Average queueing delay per request
-system.physmem.avgBankLat 13238.07 # Average bank access latency per request
+system.physmem.wrQLenPdf::0 1388 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 1426 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 1839 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 1967 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 1966 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 1963 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 1963 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 1958 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::12 1948 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::19 1938 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 1934 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 15781 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 586.280717 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 172.240853 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 1929.214074 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-67 6626 41.99% 41.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-131 2550 16.16% 58.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-195 1431 9.07% 67.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-259 896 5.68% 72.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-323 638 4.04% 76.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-387 562 3.56% 80.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-451 391 2.48% 82.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-515 301 1.91% 84.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-579 260 1.65% 86.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-643 205 1.30% 87.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-707 214 1.36% 89.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-771 213 1.35% 90.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-835 77 0.49% 91.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-899 70 0.44% 91.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-963 80 0.51% 91.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1027 90 0.57% 92.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1091 36 0.23% 92.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1155 39 0.25% 93.02% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1344-1347 48 0.30% 93.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1411 35 0.22% 94.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1475 177 1.12% 95.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1539 87 0.55% 95.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1603 34 0.22% 96.00% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1792-1795 18 0.11% 96.24% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1920-1923 8 0.05% 96.38% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::2880-2883 3 0.02% 96.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3011 1 0.01% 96.57% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::3776-3779 1 0.01% 96.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840-3843 1 0.01% 96.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904-3907 1 0.01% 96.65% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::total 15781 # Bytes accessed per row activation
+system.physmem.totQLat 1934459750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 3605914750 # Sum of mem lat for all requests
+system.physmem.totBusLat 498525000 # Total cycles spent in databus access
+system.physmem.totBankLat 1172930000 # Total cycles spent in bank access
+system.physmem.avgQLat 19401.83 # Average queueing delay per request
+system.physmem.avgBankLat 11764.00 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 40139.77 # Average memory access latency
-system.physmem.avgRdBW 3.82 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 3.82 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 1.58 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 36165.84 # Average memory access latency
+system.physmem.avgRdBW 3.46 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 3.46 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.17 # Average write queue length over time
-system.physmem.readRowHits 99784 # Number of row buffer hits during reads
-system.physmem.writeRowHits 34161 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 90.88 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 75.33 # Row buffer hit rate for writes
-system.physmem.avgGap 11863829.65 # Average gap between requests
-system.l2c.replacements 337457 # number of replacements
-system.l2c.tagsinuse 65420.293999 # Cycle average of tags in use
-system.l2c.total_refs 2475568 # Total number of references to valid blocks.
-system.l2c.sampled_refs 402619 # Sample count of references to valid blocks.
-system.l2c.avg_refs 6.148662 # Average number of references to valid blocks.
+system.physmem.readRowHits 93388 # Number of row buffer hits during reads
+system.physmem.writeRowHits 35434 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 93.66 # Row buffer hit rate for reads
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+system.membus.snoop_data_through_bus 10048 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 12475000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 520545500 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
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+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 777595953 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 156419750 # Layer occupancy (ticks)
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system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 54855.924450 # Average occupied blocks per requestor
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-system.iocache.WriteReq_mshr_misses::tsunami.ide 16768 # number of WriteReq MSHR misses
-system.iocache.WriteReq_mshr_misses::total 16768 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide 16837 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 16837 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide 16837 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 16837 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5589249 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 5589249 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3458522887 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 3458522887 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 3464112136 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 3464112136 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 3464112136 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 3464112136 # number of overall MSHR miss cycles
+system.iocache.WriteReq_mshr_misses::tsunami.ide 17280 # number of WriteReq MSHR misses
+system.iocache.WriteReq_mshr_misses::total 17280 # number of WriteReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide 17349 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 17349 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide 17349 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 17349 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5924213 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 5924213 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3445287507 # number of WriteReq MSHR miss cycles
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+system.iocache.demand_mshr_miss_latency::tsunami.ide 3451211720 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 3451211720 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 3451211720 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 3451211720 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.398844 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.398844 # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.403543 # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total 0.403543 # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::tsunami.ide 0.403523 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 0.403523 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::tsunami.ide 0.403523 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 0.403523 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 81003.608696 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 81003.608696 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 206257.328662 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 206257.328662 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 205744.024232 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 205744.024232 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 205744.024232 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 205744.024232 # average overall mshr miss latency
+system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::tsunami.ide 0.415794 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 0.415794 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::tsunami.ide 0.415794 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 0.415794 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 85858.159420 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 85858.159420 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 199380.064062 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 199380.064062 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 198928.567641 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 198928.567641 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 198928.567641 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 198928.567641 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 4882934 # DTB read hits
-system.cpu0.dtb.read_misses 6016 # DTB read misses
-system.cpu0.dtb.read_acv 120 # DTB read access violations
-system.cpu0.dtb.read_accesses 427387 # DTB read accesses
-system.cpu0.dtb.write_hits 3510109 # DTB write hits
-system.cpu0.dtb.write_misses 663 # DTB write misses
-system.cpu0.dtb.write_acv 82 # DTB write access violations
-system.cpu0.dtb.write_accesses 162920 # DTB write accesses
-system.cpu0.dtb.data_hits 8393043 # DTB hits
-system.cpu0.dtb.data_misses 6679 # DTB misses
-system.cpu0.dtb.data_acv 202 # DTB access violations
-system.cpu0.dtb.data_accesses 590307 # DTB accesses
-system.cpu0.itb.fetch_hits 2747668 # ITB hits
-system.cpu0.itb.fetch_misses 3002 # ITB misses
-system.cpu0.itb.fetch_acv 100 # ITB acv
-system.cpu0.itb.fetch_accesses 2750670 # ITB accesses
+system.cpu0.dtb.read_hits 4916475 # DTB read hits
+system.cpu0.dtb.read_misses 6063 # DTB read misses
+system.cpu0.dtb.read_acv 126 # DTB read access violations
+system.cpu0.dtb.read_accesses 427415 # DTB read accesses
+system.cpu0.dtb.write_hits 3510632 # DTB write hits
+system.cpu0.dtb.write_misses 668 # DTB write misses
+system.cpu0.dtb.write_acv 84 # DTB write access violations
+system.cpu0.dtb.write_accesses 162993 # DTB write accesses
+system.cpu0.dtb.data_hits 8427107 # DTB hits
+system.cpu0.dtb.data_misses 6731 # DTB misses
+system.cpu0.dtb.data_acv 210 # DTB access violations
+system.cpu0.dtb.data_accesses 590408 # DTB accesses
+system.cpu0.itb.fetch_hits 2754785 # ITB hits
+system.cpu0.itb.fetch_misses 3015 # ITB misses
+system.cpu0.itb.fetch_acv 104 # ITB acv
+system.cpu0.itb.fetch_accesses 2757800 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 928534019 # number of cpu cycles simulated
+system.cpu0.numCycles 928378822 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 33030135 # Number of instructions committed
-system.cpu0.committedOps 33030135 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 30904296 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 168660 # Number of float alu accesses
-system.cpu0.num_func_calls 809909 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4463035 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 30904296 # number of integer instructions
-system.cpu0.num_fp_insts 168660 # number of float instructions
-system.cpu0.num_int_register_reads 43221651 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 22562663 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 87082 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 88661 # number of times the floating registers were written
-system.cpu0.num_mem_refs 8422848 # number of memory refs
-system.cpu0.num_load_insts 4904051 # Number of load instructions
-system.cpu0.num_store_insts 3518797 # Number of store instructions
-system.cpu0.num_idle_cycles 214028158129.505707 # Number of idle cycles
-system.cpu0.num_busy_cycles -213099624110.505707 # Number of busy cycles
-system.cpu0.not_idle_fraction -229.501149 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 230.501149 # Percentage of idle cycles
+system.cpu0.committedInsts 33851772 # Number of instructions committed
+system.cpu0.committedOps 33851772 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 31712153 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 169925 # Number of float alu accesses
+system.cpu0.num_func_calls 812668 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 4695347 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 31712153 # number of integer instructions
+system.cpu0.num_fp_insts 169925 # number of float instructions
+system.cpu0.num_int_register_reads 44553309 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 23136473 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 87700 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 89305 # number of times the floating registers were written
+system.cpu0.num_mem_refs 8457205 # number of memory refs
+system.cpu0.num_load_insts 4937806 # Number of load instructions
+system.cpu0.num_store_insts 3519399 # Number of store instructions
+system.cpu0.num_idle_cycles 213007832176.448029 # Number of idle cycles
+system.cpu0.num_busy_cycles -212079453354.448029 # Number of busy cycles
+system.cpu0.not_idle_fraction -228.440641 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 229.440641 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 211352 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl
+system.cpu0.kern.inst.quiesce 6420 # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei 211383 # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0 74805 40.97% 40.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 105677 57.89% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 182552 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 105697 57.89% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 182584 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 73438 49.30% 49.30% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1818574542500 98.74% 98.74% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 39495500 0.00% 98.75% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 364949500 0.02% 98.77% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 22741309000 1.23% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1841720296500 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31 73438 49.30% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total 148958 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0 1819523663000 98.74% 98.74% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 39251000 0.00% 98.74% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 365640000 0.02% 98.76% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 22768477500 1.24% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1842697031500 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.981726 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.694825 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.815850 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31 0.694797 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total 0.815833 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed
system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 175295 91.20% 93.41% # number of callpals executed
-system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed
+system.cpu0.kern.callpal::swpipl 175325 91.20% 93.41% # number of callpals executed
+system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed
-system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed
+system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed
system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 192206 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 5921 # number of protection mode switches
+system.cpu0.kern.callpal::total 192238 # number of callpals executed
+system.cpu0.kern.mode_switch::kernel 5923 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches
-system.cpu0.kern.mode_switch::idle 2094 # number of protection mode switches
+system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches
system.cpu0.kern.mode_good::kernel 1907
system.cpu0.kern.mode_good::user 1738
system.cpu0.kern.mode_good::idle 169
-system.cpu0.kern.mode_switch_good::kernel 0.322074 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.321965 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.391059 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 29798472500 1.62% 1.62% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 2570740000 0.14% 1.76% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::idle 1809351079500 98.24% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::total 0.391019 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 29806042000 1.62% 1.62% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 2607375500 0.14% 1.76% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::idle 1810283609500 98.24% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 4175 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu0.icache.replacements 953317 # number of replacements
-system.cpu0.icache.tagsinuse 511.202573 # Cycle average of tags in use
-system.cpu0.icache.total_refs 42520473 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 953828 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 44.578764 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 10247489000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 251.172377 # Average occupied blocks per requestor
-system.cpu0.icache.occ_blocks::cpu1.inst 83.809654 # Average occupied blocks per requestor
-system.cpu0.icache.occ_blocks::cpu2.inst 176.220543 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.490571 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::cpu1.inst 0.163691 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::cpu2.inst 0.344181 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.998443 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 32512787 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 7733014 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst 2274672 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 42520473 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 32512787 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 7733014 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst 2274672 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 42520473 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 32512787 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 7733014 # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst 2274672 # number of overall hits
-system.cpu0.icache.overall_hits::total 42520473 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 524229 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst 129219 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst 317357 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 970805 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 524229 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst 129219 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst 317357 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 970805 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 524229 # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst 129219 # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst 317357 # number of overall misses
-system.cpu0.icache.overall_misses::total 970805 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1820764500 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4451463485 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 6272227985 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 1820764500 # number of demand (read+write) miss cycles
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.072520 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071857 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.033094 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.072520 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071857 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.033094 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18847.946095 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16439.918892 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17128.636129 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26831.748695 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25295.057091 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25853.870875 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11175.134892 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12798.145117 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12330.765247 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21367.416443 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18602.861652 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19450.669612 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21367.416443 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18602.861652 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19450.669612 # average overall mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069824 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.070926 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.032237 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069824 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.070926 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.032237 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 20733.659013 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16820.503202 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17924.719500 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33878.310396 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 29355.224833 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30885.816310 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11213.324048 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12230.925919 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11941.258359 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 23000 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23000 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24838.195910 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20063.089461 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21484.251509 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24838.195910 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20063.089461 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21484.251509 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 1221065 # DTB read hits
-system.cpu1.dtb.read_misses 1489 # DTB read misses
-system.cpu1.dtb.read_acv 40 # DTB read access violations
-system.cpu1.dtb.read_accesses 143781 # DTB read accesses
-system.cpu1.dtb.write_hits 929390 # DTB write hits
-system.cpu1.dtb.write_misses 202 # DTB write misses
-system.cpu1.dtb.write_acv 24 # DTB write access violations
-system.cpu1.dtb.write_accesses 59266 # DTB write accesses
-system.cpu1.dtb.data_hits 2150455 # DTB hits
-system.cpu1.dtb.data_misses 1691 # DTB misses
-system.cpu1.dtb.data_acv 64 # DTB access violations
-system.cpu1.dtb.data_accesses 203047 # DTB accesses
-system.cpu1.itb.fetch_hits 872017 # ITB hits
-system.cpu1.itb.fetch_misses 756 # ITB misses
-system.cpu1.itb.fetch_acv 43 # ITB acv
-system.cpu1.itb.fetch_accesses 872773 # ITB accesses
+system.cpu1.dtb.read_hits 1206143 # DTB read hits
+system.cpu1.dtb.read_misses 1395 # DTB read misses
+system.cpu1.dtb.read_acv 35 # DTB read access violations
+system.cpu1.dtb.read_accesses 142828 # DTB read accesses
+system.cpu1.dtb.write_hits 904590 # DTB write hits
+system.cpu1.dtb.write_misses 190 # DTB write misses
+system.cpu1.dtb.write_acv 23 # DTB write access violations
+system.cpu1.dtb.write_accesses 58592 # DTB write accesses
+system.cpu1.dtb.data_hits 2110733 # DTB hits
+system.cpu1.dtb.data_misses 1585 # DTB misses
+system.cpu1.dtb.data_acv 58 # DTB access violations
+system.cpu1.dtb.data_accesses 201420 # DTB accesses
+system.cpu1.itb.fetch_hits 862559 # ITB hits
+system.cpu1.itb.fetch_misses 707 # ITB misses
+system.cpu1.itb.fetch_acv 34 # ITB acv
+system.cpu1.itb.fetch_accesses 863266 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 953614996 # number of cpu cycles simulated
+system.cpu1.numCycles 953614983 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 7860477 # Number of instructions committed
-system.cpu1.committedOps 7860477 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 7311992 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 45303 # Number of float alu accesses
-system.cpu1.num_func_calls 212165 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 960179 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 7311992 # number of integer instructions
-system.cpu1.num_fp_insts 45303 # number of float instructions
-system.cpu1.num_int_register_reads 10165443 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 5319467 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 24490 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 24717 # number of times the floating registers were written
-system.cpu1.num_mem_refs 2158115 # number of memory refs
-system.cpu1.num_load_insts 1226297 # Number of load instructions
-system.cpu1.num_store_insts 931818 # Number of store instructions
-system.cpu1.num_idle_cycles -703122010.262243 # Number of idle cycles
-system.cpu1.num_busy_cycles 1656737006.262243 # Number of busy cycles
-system.cpu1.not_idle_fraction 1.737323 # Percentage of non-idle cycles
-system.cpu1.idle_fraction -0.737323 # Percentage of idle cycles
+system.cpu1.committedInsts 7923216 # Number of instructions committed
+system.cpu1.committedOps 7923216 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 7378774 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 44696 # Number of float alu accesses
+system.cpu1.num_func_calls 212761 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 1003934 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 7378774 # number of integer instructions
+system.cpu1.num_fp_insts 44696 # number of float instructions
+system.cpu1.num_int_register_reads 10322317 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 5366754 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 24140 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 24473 # number of times the floating registers were written
+system.cpu1.num_mem_refs 2118035 # number of memory refs
+system.cpu1.num_load_insts 1211092 # Number of load instructions
+system.cpu1.num_store_insts 906943 # Number of store instructions
+system.cpu1.num_idle_cycles -710985323.015638 # Number of idle cycles
+system.cpu1.num_busy_cycles 1664600306.015638 # Number of busy cycles
+system.cpu1.not_idle_fraction 1.745569 # Percentage of non-idle cycles
+system.cpu1.idle_fraction -0.745569 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed
system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu1.kern.swap_context 0 # number of times the context was actually changed
-system.cpu2.branchPred.lookups 8370437 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 7682240 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 128031 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 6854257 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 5743720 # Number of BTB hits
+system.cpu2.branchPred.lookups 8997247 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 8318296 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 124435 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 7453298 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 6389224 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 83.797850 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 284899 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 14987 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct 85.723448 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 282371 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 13443 # Number of incorrect RAS predictions.
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
-system.cpu2.dtb.read_hits 3211638 # DTB read hits
-system.cpu2.dtb.read_misses 11756 # DTB read misses
-system.cpu2.dtb.read_acv 123 # DTB read access violations
-system.cpu2.dtb.read_accesses 216825 # DTB read accesses
-system.cpu2.dtb.write_hits 1985602 # DTB write hits
-system.cpu2.dtb.write_misses 2511 # DTB write misses
-system.cpu2.dtb.write_acv 137 # DTB write access violations
-system.cpu2.dtb.write_accesses 81903 # DTB write accesses
-system.cpu2.dtb.data_hits 5197240 # DTB hits
-system.cpu2.dtb.data_misses 14267 # DTB misses
-system.cpu2.dtb.data_acv 260 # DTB access violations
-system.cpu2.dtb.data_accesses 298728 # DTB accesses
-system.cpu2.itb.fetch_hits 370869 # ITB hits
-system.cpu2.itb.fetch_misses 5705 # ITB misses
-system.cpu2.itb.fetch_acv 274 # ITB acv
-system.cpu2.itb.fetch_accesses 376574 # ITB accesses
+system.cpu2.dtb.read_hits 3184667 # DTB read hits
+system.cpu2.dtb.read_misses 11563 # DTB read misses
+system.cpu2.dtb.read_acv 122 # DTB read access violations
+system.cpu2.dtb.read_accesses 218108 # DTB read accesses
+system.cpu2.dtb.write_hits 2003168 # DTB write hits
+system.cpu2.dtb.write_misses 2582 # DTB write misses
+system.cpu2.dtb.write_acv 105 # DTB write access violations
+system.cpu2.dtb.write_accesses 82984 # DTB write accesses
+system.cpu2.dtb.data_hits 5187835 # DTB hits
+system.cpu2.dtb.data_misses 14145 # DTB misses
+system.cpu2.dtb.data_acv 227 # DTB access violations
+system.cpu2.dtb.data_accesses 301092 # DTB accesses
+system.cpu2.itb.fetch_hits 370432 # ITB hits
+system.cpu2.itb.fetch_misses 5697 # ITB misses
+system.cpu2.itb.fetch_acv 245 # ITB acv
+system.cpu2.itb.fetch_accesses 376129 # ITB accesses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.read_acv 0 # DTB read access violations
system.cpu2.itb.data_misses 0 # DTB misses
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
-system.cpu2.numCycles 30454355 # number of cpu cycles simulated
+system.cpu2.numCycles 31194709 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 8502723 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 34791371 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 8370437 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 6028619 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 8097928 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 618452 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles 9649671 # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles 10614 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 1974 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 63437 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 88147 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 485 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 2592037 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 89025 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples 26817742 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.297327 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.307851 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles 8336463 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 36595534 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 8997247 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 6671595 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 8714180 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 607609 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.BlockedCycles 9678498 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles 11323 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 1980 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 64467 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 86613 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 511 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 2554168 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 86055 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples 27288913 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.341040 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.295561 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 18719814 69.80% 69.80% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 271918 1.01% 70.82% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 439106 1.64% 72.46% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 4240914 15.81% 88.27% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 731900 2.73% 91.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 166811 0.62% 91.62% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 194731 0.73% 92.35% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 431926 1.61% 93.96% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 1620622 6.04% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 18574733 68.07% 68.07% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 269160 0.99% 69.05% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 428961 1.57% 70.63% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 4866915 17.83% 88.46% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 754326 2.76% 91.22% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 165422 0.61% 91.83% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 191254 0.70% 92.53% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 429367 1.57% 94.10% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 1608775 5.90% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 26817742 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.274852 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 1.142410 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 8640997 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 9744638 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 7501940 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 293665 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 390587 # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved 167981 # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred 12867 # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts 34389263 # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts 40403 # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles 390587 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 8994385 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 2850333 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 5733998 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 7360278 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 1242256 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 33240737 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 2380 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 234906 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents 409580 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands 22320164 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 41423386 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 41259446 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 163940 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 20500425 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 1819739 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 502711 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 59638 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 3682174 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 3369954 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 2075842 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 372990 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 254270 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 30724821 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 626542 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 30272457 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 30970 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 2165066 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 1087715 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 442386 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 26817742 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.128822 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.564509 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 27288913 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.288422 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 1.173133 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 8484758 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 9763089 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 8105885 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 306526 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 382761 # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved 165822 # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred 12764 # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts 36197990 # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts 39851 # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles 382761 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 8844170 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 2798398 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 5770090 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 7975185 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 1272419 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 35047656 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 2444 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 232046 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents 447152 # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenamedOperands 23489226 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 43822690 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 43659490 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 163200 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 21694214 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 1795012 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 501276 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 59320 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 3724979 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 3343402 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 2093050 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 368261 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 257932 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 32557394 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 620599 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 32107794 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 34091 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 2143269 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 1080696 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 438167 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 27288913 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.176588 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.573888 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 15272797 56.95% 56.95% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 3099841 11.56% 68.51% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 1551477 5.79% 74.29% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 5057037 18.86% 93.15% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 907037 3.38% 96.53% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 485633 1.81% 98.34% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 283575 1.06% 99.40% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 141972 0.53% 99.93% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 18373 0.07% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 15150790 55.52% 55.52% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 3070151 11.25% 66.77% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 1548988 5.68% 72.45% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 5689584 20.85% 93.30% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 903005 3.31% 96.61% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 480338 1.76% 98.37% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 283929 1.04% 99.41% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 143393 0.53% 99.93% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 18735 0.07% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 26817742 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 27288913 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 34129 13.74% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.74% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 111357 44.84% 58.58% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 102854 41.42% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 33803 13.75% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 13.75% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 111727 45.45% 59.20% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 100297 40.80% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 2448 0.01% 0.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 24602631 81.27% 81.28% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 20294 0.07% 81.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 8465 0.03% 81.37% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.37% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.37% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.37% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 81.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.38% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 3340354 11.03% 92.41% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 2007868 6.63% 99.04% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess 289173 0.96% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 26449669 82.38% 82.39% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 20147 0.06% 82.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 82.45% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 8446 0.03% 82.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 82.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 82.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 82.47% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 1224 0.00% 82.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 82.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 82.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 82.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 82.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 82.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 82.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 82.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 82.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 82.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 82.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 82.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 82.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 3312033 10.32% 92.79% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 2025467 6.31% 99.10% # Type of FU issued
+system.cpu2.iq.FU_type_0::IprAccess 288360 0.90% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 30272457 # Type of FU issued
-system.cpu2.iq.rate 0.994027 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 248340 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.008203 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 87406741 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 33405587 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 29873950 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 235225 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 114899 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 111509 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 30395868 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 122481 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 188565 # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total 32107794 # Type of FU issued
+system.cpu2.iq.rate 1.029271 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 245827 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.007656 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 91550157 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 35210267 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 31710626 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 234262 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 114809 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses 110859 # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses 32229265 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 121908 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 186278 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 411297 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 939 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 4131 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 160227 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 409987 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 1098 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 3916 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 156672 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 4708 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 24260 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 4171 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 28368 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 390587 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 2070216 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 210596 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 32630441 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 224813 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 3369954 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 2075842 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 556425 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 148713 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 2116 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 4131 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 65748 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 128933 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 194681 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 30112166 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 3231643 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 160291 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 382761 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 2017515 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 205037 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 34446466 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 224960 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 3343402 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 2093050 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 551127 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 142834 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 2166 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 3916 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 63764 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 127616 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 191380 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 31948816 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 3204490 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 158978 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 1279078 # number of nop insts executed
-system.cpu2.iew.exec_refs 5224243 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 6789433 # Number of branches executed
-system.cpu2.iew.exec_stores 1992600 # Number of stores executed
-system.cpu2.iew.exec_rate 0.988764 # Inst execution rate
-system.cpu2.iew.wb_sent 30017965 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 29985459 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 17323993 # num instructions producing a value
-system.cpu2.iew.wb_consumers 20546016 # num instructions consuming a value
+system.cpu2.iew.exec_nop 1268473 # number of nop insts executed
+system.cpu2.iew.exec_refs 5214665 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 7427208 # Number of branches executed
+system.cpu2.iew.exec_stores 2010175 # Number of stores executed
+system.cpu2.iew.exec_rate 1.024174 # Inst execution rate
+system.cpu2.iew.wb_sent 31853816 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 31821485 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 18500784 # num instructions producing a value
+system.cpu2.iew.wb_consumers 21694431 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 0.984603 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.843180 # average fanout of values written-back
+system.cpu2.iew.wb_rate 1.020092 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.852790 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 2350466 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 184156 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 180720 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 26427155 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.144119 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.849310 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 2318994 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 182432 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 176935 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 26906152 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.192355 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 1.846387 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 16325181 61.77% 61.77% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 2317842 8.77% 70.54% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1215370 4.60% 75.14% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 4792789 18.14% 93.28% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 500443 1.89% 95.17% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 186108 0.70% 95.88% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 178909 0.68% 96.55% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 180996 0.68% 97.24% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 729517 2.76% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 16157542 60.05% 60.05% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 2331595 8.67% 68.72% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1218913 4.53% 73.25% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 5433463 20.19% 93.44% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 503772 1.87% 95.31% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 185469 0.69% 96.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 177448 0.66% 96.66% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 178843 0.66% 97.33% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 719107 2.67% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 26427155 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 30235823 # Number of instructions committed
-system.cpu2.commit.committedOps 30235823 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 26906152 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 32081688 # Number of instructions committed
+system.cpu2.commit.committedOps 32081688 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 4874272 # Number of memory references committed
-system.cpu2.commit.loads 2958657 # Number of loads committed
-system.cpu2.commit.membars 64665 # Number of memory barriers committed
-system.cpu2.commit.branches 6641301 # Number of branches committed
-system.cpu2.commit.fp_insts 110294 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 28781664 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 230734 # Number of function calls committed.
-system.cpu2.commit.bw_lim_events 729517 # number cycles where commit BW limit reached
+system.cpu2.commit.refs 4869793 # Number of memory references committed
+system.cpu2.commit.loads 2933415 # Number of loads committed
+system.cpu2.commit.membars 63859 # Number of memory barriers committed
+system.cpu2.commit.branches 7280639 # Number of branches committed
+system.cpu2.commit.fp_insts 109636 # Number of committed floating point instructions.
+system.cpu2.commit.int_insts 30638732 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 228563 # Number of function calls committed.
+system.cpu2.commit.bw_lim_events 719107 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 58211181 # The number of ROB reads
-system.cpu2.rob.rob_writes 65562875 # The number of ROB writes
-system.cpu2.timesIdled 242498 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 3636613 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 1745370399 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 29064101 # Number of Instructions Simulated
-system.cpu2.committedOps 29064101 # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total 29064101 # Number of Instructions Simulated
-system.cpu2.cpi 1.047834 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 1.047834 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.954350 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.954350 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 39595533 # number of integer regfile reads
-system.cpu2.int_regfile_writes 21195830 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 68078 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 68404 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 4592506 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 258747 # number of misc regfile writes
+system.cpu2.rob.rob_reads 60513787 # The number of ROB reads
+system.cpu2.rob.rob_writes 69183653 # The number of ROB writes
+system.cpu2.timesIdled 245794 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 3905796 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 1746583104 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 30918811 # Number of Instructions Simulated
+system.cpu2.committedOps 30918811 # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total 30918811 # Number of Instructions Simulated
+system.cpu2.cpi 1.008923 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 1.008923 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.991156 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.991156 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 42017360 # number of integer regfile reads
+system.cpu2.int_regfile_writes 22376128 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 67819 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 67985 # number of floating regfile writes
+system.cpu2.misc_regfile_reads 5215792 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 257331 # number of misc regfile writes
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed
---------- Begin Simulation Statistics ----------
-sim_seconds 2.533116 # Number of seconds simulated
-sim_ticks 2533115780500 # Number of ticks simulated
-final_tick 2533115780500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.534279 # Number of seconds simulated
+sim_ticks 2534279149500 # Number of ticks simulated
+final_tick 2534279149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 55678 # Simulator instruction rate (inst/s)
-host_op_rate 71642 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2338649550 # Simulator tick rate (ticks/s)
-host_mem_usage 398880 # Number of bytes of host memory used
-host_seconds 1083.15 # Real time elapsed on the host
-sim_insts 60307726 # Number of instructions simulated
-sim_ops 77599286 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory
+host_inst_rate 43780 # Simulator instruction rate (inst/s)
+host_op_rate 56332 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1839722930 # Simulator tick rate (ticks/s)
+host_mem_usage 400528 # Number of bytes of host memory used
+host_seconds 1377.53 # Real time elapsed on the host
+sim_insts 60307893 # Number of instructions simulated
+sim_ops 77599512 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd 119547392 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 796160 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9093200 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129429776 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 796160 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 796160 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3781760 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9094160 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129441552 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3783360 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6797832 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 6799432 # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd 14943424 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12440 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142115 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096806 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59090 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142130 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15098054 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59115 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813108 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47189972 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 813133 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47172148 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1136 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 314301 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3589729 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51095089 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 314301 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 314301 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1492928 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1190657 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2683585 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1492928 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47189972 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 314485 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3588460 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51076280 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 314485 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 314485 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1492874 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1190110 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2682985 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1492874 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47172148 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1136 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 314301 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4780386 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53778674 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15096806 # Total number of read requests seen
-system.physmem.writeReqs 813108 # Total number of write requests seen
-system.physmem.cpureqs 218339 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 966195584 # Total number of bytes read from memory
-system.physmem.bytesWritten 52038912 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 129429776 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6797832 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 312 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 943937 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 943392 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 944197 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 943973 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 943153 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 943272 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 943794 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 943286 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 943217 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 943610 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 943691 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 942979 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 943602 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50406 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50439 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51150 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 50184 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50277 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 50865 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51361 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 50798 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51185 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51244 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 50627 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51225 # Track writes on a per bank basis
+system.physmem.bw_total::cpu.inst 314485 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4778571 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53759265 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15098054 # Total number of read requests seen
+system.physmem.writeReqs 813133 # Total number of write requests seen
+system.physmem.cpureqs 218381 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 966275456 # Total number of bytes read from memory
+system.physmem.bytesWritten 52040512 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 129441552 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6799432 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 339 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4672 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 944601 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 943433 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 943409 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 943592 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 943465 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 943701 # Track reads on a per bank basis
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+system.physmem.perBankRdReqs::7 943240 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 943648 # Track reads on a per bank basis
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+system.physmem.perBankRdReqs::11 942809 # Track reads on a per bank basis
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+system.physmem.perBankRdReqs::14 943779 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 943691 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 49135 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 48909 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 50973 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 51086 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 51003 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 51258 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 51261 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::9 51095 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 50750 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::15 51120 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 32506 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2533114676500 # Total gap between requests
+system.physmem.numWrRetry 32444 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2534279100000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 36 # Categorize read packet sizes
-system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154562 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 754018 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 59090 # Categorize write packet sizes
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-system.physmem.totQLat 393224294250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 485624283000 # Sum of mem lat for all requests
-system.physmem.totBusLat 75482470000 # Total cycles spent in databus access
-system.physmem.totBankLat 16917518750 # Total cycles spent in bank access
-system.physmem.avgQLat 26047.39 # Average queueing delay per request
-system.physmem.avgBankLat 1120.63 # Average bank access latency per request
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+system.physmem.bytesPerActivate::samples 42559 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 23924.789210 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 1816.195393 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 32272.883514 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-95 8308 19.52% 19.52% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::7552-7583 9 0.02% 63.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7616-7647 2 0.00% 63.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7680-7711 6 0.01% 63.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7808-7839 3 0.01% 63.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7872-7903 3 0.01% 63.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7936-7967 4 0.01% 63.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8000-8031 5 0.01% 63.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8064-8095 7 0.02% 63.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8128-8159 4 0.01% 63.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8223 322 0.76% 64.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8704-8735 1 0.00% 64.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8960-8991 1 0.00% 64.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::9152-9183 1 0.00% 64.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::9216-9247 2 0.00% 64.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::9472-9503 1 0.00% 64.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::9536-9567 1 0.00% 64.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::10240-10271 19 0.04% 64.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::10496-10527 1 0.00% 64.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::11008-11039 1 0.00% 64.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::11264-11295 1 0.00% 64.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::11520-11551 2 0.00% 64.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::11904-11935 1 0.00% 64.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::12288-12319 1 0.00% 64.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::12544-12575 2 0.00% 64.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::13312-13343 4 0.01% 64.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::13568-13599 1 0.00% 64.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::13824-13855 1 0.00% 64.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::14336-14367 2 0.00% 64.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::14592-14623 1 0.00% 64.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::14848-14879 2 0.00% 64.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15040-15071 1 0.00% 64.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15168-15199 1 0.00% 64.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15360-15391 3 0.01% 64.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15616-15647 2 0.00% 64.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::16128-16159 1 0.00% 64.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::16384-16415 2 0.00% 64.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::16640-16671 1 0.00% 64.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::16896-16927 3 0.01% 64.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::17152-17183 2 0.00% 64.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::17216-17247 2 0.00% 64.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::17344-17375 1 0.00% 64.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::17408-17439 2 0.00% 64.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::17792-17823 1 0.00% 64.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::17920-17951 2 0.00% 64.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::17984-18015 1 0.00% 64.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::18176-18207 2 0.00% 64.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::18432-18463 2 0.00% 64.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::19200-19231 2 0.00% 64.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::19840-19871 1 0.00% 64.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::20224-20255 3 0.01% 64.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::20544-20575 1 0.00% 64.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::20736-20767 1 0.00% 64.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::21248-21279 1 0.00% 64.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::21312-21343 1 0.00% 64.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::21504-21535 2 0.00% 64.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::22016-22047 1 0.00% 64.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::22272-22303 1 0.00% 64.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::22400-22431 1 0.00% 64.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::22528-22559 1 0.00% 64.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::22592-22623 1 0.00% 64.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::22784-22815 1 0.00% 64.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::23040-23071 1 0.00% 64.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::23552-23583 2 0.00% 64.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::23808-23839 2 0.00% 64.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::24320-24351 2 0.00% 64.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::24576-24607 4 0.01% 64.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::25088-25119 1 0.00% 64.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::25600-25631 3 0.01% 64.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::25664-25695 1 0.00% 64.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::25728-25759 1 0.00% 64.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::26368-26399 1 0.00% 64.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::26624-26655 2 0.00% 64.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::27328-27359 1 0.00% 64.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::27456-27487 1 0.00% 64.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::27648-27679 1 0.00% 64.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::28416-28447 1 0.00% 64.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::28672-28703 1 0.00% 64.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::28736-28767 1 0.00% 64.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::28928-28959 2 0.00% 64.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::29184-29215 1 0.00% 64.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::29376-29407 1 0.00% 64.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::29440-29471 1 0.00% 64.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::29696-29727 1 0.00% 64.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::29952-29983 1 0.00% 64.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::30016-30047 1 0.00% 64.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::30208-30239 3 0.01% 64.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::30592-30623 1 0.00% 64.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::30720-30751 1 0.00% 64.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::31104-31135 1 0.00% 64.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::31232-31263 1 0.00% 64.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::31424-31455 1 0.00% 64.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::31488-31519 1 0.00% 64.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::31744-31775 2 0.00% 64.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::32256-32287 1 0.00% 64.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::33664-33695 2 0.00% 64.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::33728-33759 1 0.00% 64.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::33792-33823 44 0.10% 65.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::34176-34207 1 0.00% 65.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::34752-34783 1 0.00% 65.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::36608-36639 1 0.00% 65.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::36864-36895 2 0.00% 65.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::37248-37279 1 0.00% 65.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::39296-39327 1 0.00% 65.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::39808-39839 1 0.00% 65.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::40000-40031 1 0.00% 65.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41984-42015 1 0.00% 65.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::42048-42079 1 0.00% 65.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::42496-42527 2 0.00% 65.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::43264-43295 1 0.00% 65.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44672-44703 1 0.00% 65.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44800-44831 1 0.00% 65.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::45312-45343 1 0.00% 65.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47616-47647 1 0.00% 65.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47936-47967 1 0.00% 65.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48128-48159 1 0.00% 65.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48640-48671 1 0.00% 65.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48896-48927 1 0.00% 65.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::49152-49183 1 0.00% 65.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::49920-49951 1 0.00% 65.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::50176-50207 2 0.00% 65.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::50432-50463 1 0.00% 65.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::50688-50719 1 0.00% 65.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::54272-54303 1 0.00% 65.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::56000-56031 1 0.00% 65.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::56832-56863 1 0.00% 65.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::57344-57375 1 0.00% 65.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::58368-58399 1 0.00% 65.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::58944-58975 1 0.00% 65.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::59840-59871 1 0.00% 65.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::62208-62239 1 0.00% 65.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::62848-62879 1 0.00% 65.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::63232-63263 1 0.00% 65.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::63488-63519 2 0.00% 65.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64256-64287 1 0.00% 65.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64704-64735 1 0.00% 65.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65024-65055 13 0.03% 65.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65152-65183 18 0.04% 65.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65344-65375 8 0.02% 65.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65472-65503 18 0.04% 65.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65536-65567 14406 33.85% 99.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::113216-113247 1 0.00% 99.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::129664-129695 1 0.00% 99.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::129792-129823 1 0.00% 99.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::129984-130015 1 0.00% 99.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::130432-130463 1 0.00% 99.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::131072-131103 325 0.76% 99.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::132096-132127 3 0.01% 99.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::168704-168735 1 0.00% 99.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::169664-169695 1 0.00% 99.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::190464-190495 1 0.00% 99.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::196608-196639 9 0.02% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 42559 # Bytes accessed per row activation
+system.physmem.totQLat 355117101750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 446336213000 # Sum of mem lat for all requests
+system.physmem.totBusLat 75488575000 # Total cycles spent in databus access
+system.physmem.totBankLat 15730536250 # Total cycles spent in bank access
+system.physmem.avgQLat 23521.25 # Average queueing delay per request
+system.physmem.avgBankLat 1041.92 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 32168.02 # Average memory access latency
-system.physmem.avgRdBW 381.43 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 51.10 # Average consumed read bandwidth in MB/s
+system.physmem.avgMemAccLat 29563.16 # Average memory access latency
+system.physmem.avgRdBW 381.28 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 20.53 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 51.08 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.14 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.19 # Average read queue length over time
-system.physmem.avgWrQLen 11.11 # Average write queue length over time
-system.physmem.readRowHits 15020181 # Number of row buffer hits during reads
-system.physmem.writeRowHits 793022 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes
-system.physmem.avgGap 159216.11 # Average gap between requests
+system.physmem.avgRdQLen 0.18 # Average read queue length over time
+system.physmem.avgWrQLen 11.71 # Average write queue length over time
+system.physmem.readRowHits 15070837 # Number of row buffer hits during reads
+system.physmem.writeRowHits 797438 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.82 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 98.07 # Row buffer hit rate for writes
+system.physmem.avgGap 159276.56 # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 54705448 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 16150672 # Transaction distribution
+system.membus.trans_dist::ReadResp 16150669 # Transaction distribution
+system.membus.trans_dist::WriteReq 763336 # Transaction distribution
+system.membus.trans_dist::WriteResp 763336 # Transaction distribution
+system.membus.trans_dist::Writeback 59115 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4669 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4672 # Transaction distribution
+system.membus.trans_dist::ReadExReq 131424 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131424 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885755 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272475 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29886845 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 29886845 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port 31772600 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 34159320 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091509 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119547368 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total 119547368 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.physmem.port 136240960 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 138638877 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 138638877 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 1491846000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 17371820500 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.7 # Layer utilization (%)
+system.membus.reqLayer3.occupancy 3645000 # Layer occupancy (ticks)
+system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4719558707 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.membus.respLayer2.occupancy 33739093743 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 14672817 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11756302 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 704420 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9794195 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7944325 # Number of BTB hits
+system.iobus.throughput 48115298 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 16126739 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16126726 # Transaction distribution
+system.iobus.trans_dist::WriteReq 8158 # Transaction distribution
+system.iobus.trans_dist::WriteResp 8158 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2382946 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total 29886835 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 32269781 # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 2390309 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119547288 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 121937597 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 121937597 # Total data (bytes)
+system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 518000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 519000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
+system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 14943424000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 2374788000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.iobus.respLayer1.occupancy 29886822000 # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization 1.2 # Layer utilization (%)
+system.cpu.branchPred.lookups 14673159 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11756965 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 704729 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9767663 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7945266 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 81.112588 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1400354 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 72452 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 81.342548 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1399657 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 72413 # Number of incorrect RAS predictions.
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 14987449 # DTB read hits
-system.cpu.checker.dtb.read_misses 7302 # DTB read misses
-system.cpu.checker.dtb.write_hits 11227758 # DTB write hits
+system.cpu.checker.dtb.read_hits 14987453 # DTB read hits
+system.cpu.checker.dtb.read_misses 7307 # DTB read misses
+system.cpu.checker.dtb.write_hits 11227781 # DTB write hits
system.cpu.checker.dtb.write_misses 2189 # DTB write misses
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries 6416 # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 14994751 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 11229947 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 14994760 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 11229970 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 26215207 # DTB hits
-system.cpu.checker.dtb.misses 9491 # DTB misses
-system.cpu.checker.dtb.accesses 26224698 # DTB accesses
-system.cpu.checker.itb.inst_hits 61481725 # ITB inst hits
+system.cpu.checker.dtb.hits 26215234 # DTB hits
+system.cpu.checker.dtb.misses 9496 # DTB misses
+system.cpu.checker.dtb.accesses 26224730 # DTB accesses
+system.cpu.checker.itb.inst_hits 61481893 # ITB inst hits
system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 61486196 # ITB inst accesses
-system.cpu.checker.itb.hits 61481725 # DTB hits
+system.cpu.checker.itb.inst_accesses 61486364 # ITB inst accesses
+system.cpu.checker.itb.hits 61481893 # DTB hits
system.cpu.checker.itb.misses 4471 # DTB misses
-system.cpu.checker.itb.accesses 61486196 # DTB accesses
-system.cpu.checker.numCycles 77885092 # number of cpu cycles simulated
+system.cpu.checker.itb.accesses 61486364 # DTB accesses
+system.cpu.checker.numCycles 77885319 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51400888 # DTB read hits
-system.cpu.dtb.read_misses 64225 # DTB read misses
-system.cpu.dtb.write_hits 11700104 # DTB write hits
-system.cpu.dtb.write_misses 15848 # DTB write misses
+system.cpu.dtb.read_hits 51397173 # DTB read hits
+system.cpu.dtb.read_misses 63986 # DTB read misses
+system.cpu.dtb.write_hits 11699533 # DTB write hits
+system.cpu.dtb.write_misses 15890 # DTB write misses
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 6555 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2395 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 6549 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2402 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1336 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51465113 # DTB read accesses
-system.cpu.dtb.write_accesses 11715952 # DTB write accesses
+system.cpu.dtb.perms_faults 1410 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51461159 # DTB read accesses
+system.cpu.dtb.write_accesses 11715423 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63100992 # DTB hits
-system.cpu.dtb.misses 80073 # DTB misses
-system.cpu.dtb.accesses 63181065 # DTB accesses
-system.cpu.itb.inst_hits 12331220 # ITB inst hits
-system.cpu.itb.inst_misses 11422 # ITB inst misses
+system.cpu.dtb.hits 63096706 # DTB hits
+system.cpu.dtb.misses 79876 # DTB misses
+system.cpu.dtb.accesses 63176582 # DTB accesses
+system.cpu.itb.inst_hits 12260245 # ITB inst hits
+system.cpu.itb.inst_misses 11468 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 4954 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 4980 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2905 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2998 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 12342642 # ITB inst accesses
-system.cpu.itb.hits 12331220 # DTB hits
-system.cpu.itb.misses 11422 # DTB misses
-system.cpu.itb.accesses 12342642 # DTB accesses
-system.cpu.numCycles 471822965 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 12271713 # ITB inst accesses
+system.cpu.itb.hits 12260245 # DTB hits
+system.cpu.itb.misses 11468 # DTB misses
+system.cpu.itb.accesses 12271713 # DTB accesses
+system.cpu.numCycles 475189978 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 30573370 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 96017663 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14672817 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9344679 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 21160566 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5295047 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 124247 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 93127049 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 86502 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 2607471 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 357 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 12327822 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 900542 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5477 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 151317698 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.785150 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.150169 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 30497823 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 96057374 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14673159 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9344923 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 21151922 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5296118 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 123395 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 94706901 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2678 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 86562 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 2683934 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 445 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 12256747 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 864492 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5531 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 152887644 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.777320 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.141699 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 130172761 86.03% 86.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1303441 0.86% 86.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1712324 1.13% 88.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2496425 1.65% 89.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2221306 1.47% 91.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1109073 0.73% 91.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2756927 1.82% 93.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 745885 0.49% 94.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8799556 5.82% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 131751310 86.18% 86.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1303513 0.85% 87.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1714679 1.12% 88.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2493622 1.63% 89.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2205066 1.44% 91.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1108856 0.73% 91.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2738323 1.79% 93.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 743817 0.49% 94.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8828458 5.77% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 151317698 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.031098 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.203504 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 32529947 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 95168576 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19190992 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 961902 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3466281 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1957763 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 171745 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 112647177 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 568207 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3466281 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 34471547 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36699353 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 52502253 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18154395 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6023869 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 106113727 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 20537 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 985646 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4066140 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 795 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 110515015 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 485506390 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 485415520 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 90870 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78390038 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 32124976 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 830416 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 736951 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12148327 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 20331207 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13516553 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1968455 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2470685 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 97921870 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1983479 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 124325634 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 167955 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 21739212 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 56995294 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 501084 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 151317698 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.821620 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.535306 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 152887644 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.030879 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.202145 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 32458089 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 96821111 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 19172249 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 971461 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3464734 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1958214 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 171741 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 112504503 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 568893 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3464734 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 34365136 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 38157390 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 52654113 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 18177530 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6068741 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 106257538 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 20628 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1016430 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4078403 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 665 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 110740396 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 486151881 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 486061534 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 90347 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78390288 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 32350107 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 830682 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 737164 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12219946 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 20282216 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13494315 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1963339 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2435947 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 97859231 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1984036 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 124319403 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 165680 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 21668523 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 56420296 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 501641 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 152887644 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.813142 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::2 7070833 4.67% 84.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5935604 3.92% 88.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12601558 8.33% 96.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2800079 1.85% 98.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1698500 1.12% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 464413 0.31% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 126203 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 108584137 71.02% 71.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13613798 8.90% 79.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7066944 4.62% 84.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5988746 3.92% 88.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12566780 8.22% 96.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2768589 1.81% 98.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1723460 1.13% 99.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 446866 0.29% 99.92% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 151317698 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 152887644 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 62151 0.70% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 62053 0.70% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 3 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8366348 94.60% 95.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 415303 4.70% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8365072 94.62% 95.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 413828 4.68% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 58625951 47.16% 47.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 93085 0.07% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 52921154 42.57% 90.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12319608 9.91% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 58665929 47.19% 47.48% # Type of FU issued
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+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 16 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52876194 42.53% 90.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12318342 9.91% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 124325634 # Type of FU issued
-system.cpu.iq.rate 0.263501 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8843805 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.071134 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 409037091 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 121660776 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 85961644 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 23336 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12538 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10309 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 132793364 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12409 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 623444 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 124319403 # Type of FU issued
+system.cpu.iq.rate 0.261620 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8840956 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071115 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 410589228 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 121528348 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 86069861 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23359 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12446 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10285 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 132784241 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12452 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 624311 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4676644 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6237 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 29883 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1784459 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4627641 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6443 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 30069 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1762200 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34107775 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 892558 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34107875 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 918337 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3466281 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 27944782 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 433344 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 100126481 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 202692 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 20331207 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13516553 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1410337 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 113091 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3418 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 29883 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 350144 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 269265 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 619409 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 121539796 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52087723 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2785838 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3464734 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 29357042 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 436051 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 100064926 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 205472 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 20282216 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13494315 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1410818 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 114442 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3537 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 30069 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 350642 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 268888 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 619530 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 121646726 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 52084248 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2672677 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 221132 # number of nop insts executed
-system.cpu.iew.exec_refs 64299655 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11557425 # Number of branches executed
-system.cpu.iew.exec_stores 12211932 # Number of stores executed
-system.cpu.iew.exec_rate 0.257596 # Inst execution rate
-system.cpu.iew.wb_sent 120381824 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 85971953 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47248258 # num instructions producing a value
-system.cpu.iew.wb_consumers 88196266 # num instructions consuming a value
+system.cpu.iew.exec_nop 221659 # number of nop insts executed
+system.cpu.iew.exec_refs 64295158 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11560329 # Number of branches executed
+system.cpu.iew.exec_stores 12210910 # Number of stores executed
+system.cpu.iew.exec_rate 0.255996 # Inst execution rate
+system.cpu.iew.wb_sent 120490085 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 86080146 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47268053 # num instructions producing a value
+system.cpu.iew.wb_consumers 88199499 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.182212 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.535717 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.181149 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.535922 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 21471534 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 21408137 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1482395 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 535206 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 147851417 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.525864 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.516226 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 535479 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 149422910 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.520334 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.507055 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 120424253 81.45% 81.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13319272 9.01% 90.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3880838 2.62% 93.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2123082 1.44% 94.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1929256 1.30% 95.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 967576 0.65% 96.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1605493 1.09% 97.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 701565 0.47% 98.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2900082 1.96% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 121949451 81.61% 81.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13299405 8.90% 90.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3946740 2.64% 93.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2141050 1.43% 94.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1955041 1.31% 95.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 959721 0.64% 96.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1537792 1.03% 97.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 781343 0.52% 98.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2852367 1.91% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 147851417 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60458107 # Number of instructions committed
-system.cpu.commit.committedOps 77749667 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 149422910 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60458274 # Number of instructions committed
+system.cpu.commit.committedOps 77749893 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27386657 # Number of memory references committed
-system.cpu.commit.loads 15654563 # Number of loads committed
-system.cpu.commit.membars 403601 # Number of memory barriers committed
-system.cpu.commit.branches 9961339 # Number of branches committed
+system.cpu.commit.refs 27386690 # Number of memory references committed
+system.cpu.commit.loads 15654575 # Number of loads committed
+system.cpu.commit.membars 403596 # Number of memory barriers committed
+system.cpu.commit.branches 9961373 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 68854898 # Number of committed integer instructions.
-system.cpu.commit.function_calls 991261 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2900082 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 68855105 # Number of committed integer instructions.
+system.cpu.commit.function_calls 991268 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2852367 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 242323943 # The number of ROB reads
-system.cpu.rob.rob_writes 202004834 # The number of ROB writes
-system.cpu.timesIdled 1771447 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 320505267 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4594325554 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60307726 # Number of Instructions Simulated
-system.cpu.committedOps 77599286 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 60307726 # Number of Instructions Simulated
-system.cpu.cpi 7.823591 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.823591 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.127819 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.127819 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 550297303 # number of integer regfile reads
-system.cpu.int_regfile_writes 88455601 # number of integer regfile writes
-system.cpu.fp_regfile_reads 8347 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2910 # number of floating regfile writes
-system.cpu.misc_regfile_reads 30123534 # number of misc regfile reads
-system.cpu.misc_regfile_writes 831893 # number of misc regfile writes
-system.cpu.icache.replacements 979954 # number of replacements
-system.cpu.icache.tagsinuse 511.616585 # Cycle average of tags in use
-system.cpu.icache.total_refs 11267650 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 980466 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 11.492137 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 6410377000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 511.616585 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.999251 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.999251 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 11267650 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 11267650 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 11267650 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 11267650 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 11267650 # number of overall hits
-system.cpu.icache.overall_hits::total 11267650 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1060047 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1060047 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1060047 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1060047 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1060047 # number of overall misses
-system.cpu.icache.overall_misses::total 1060047 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 14006301995 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 14006301995 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 14006301995 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 14006301995 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 14006301995 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 14006301995 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 12327697 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 12327697 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 12327697 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 12327697 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 12327697 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 12327697 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085989 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.085989 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.085989 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.085989 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.085989 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.085989 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13212.906593 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13212.906593 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13212.906593 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13212.906593 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13212.906593 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13212.906593 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 5383 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 802 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 290 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 18.562069 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 802 # average number of cycles each access was blocked
+system.cpu.rob.rob_reads 243879966 # The number of ROB reads
+system.cpu.rob.rob_writes 201882555 # The number of ROB writes
+system.cpu.timesIdled 1780421 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 322302334 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 4593285278 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 60307893 # Number of Instructions Simulated
+system.cpu.committedOps 77599512 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 60307893 # Number of Instructions Simulated
+system.cpu.cpi 7.879399 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.879399 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.126913 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.126913 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 550704703 # number of integer regfile reads
+system.cpu.int_regfile_writes 88578313 # number of integer regfile writes
+system.cpu.fp_regfile_reads 8302 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2882 # number of floating regfile writes
+system.cpu.misc_regfile_reads 30116391 # number of misc regfile reads
+system.cpu.misc_regfile_writes 831896 # number of misc regfile writes
+system.cpu.toL2Bus.throughput 58661050 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 2657246 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2657245 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 763336 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 763336 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 607669 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2958 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2973 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 246055 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 246055 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1960500 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5796171 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 30982 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 126318 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 7913971 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62698816 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 85512245 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 42284 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 208804 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 148462149 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 148462149 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 201328 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 3128322117 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1471549889 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 2533210636 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy 20419483 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer3.occupancy 74237753 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu.icache.replacements 980157 # number of replacements
+system.cpu.icache.tagsinuse 511.579914 # Cycle average of tags in use
+system.cpu.icache.total_refs 11196212 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 980669 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 11.416912 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 6837358000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst 511.579914 # Average occupied blocks per requestor
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-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000069 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.149668 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.149668 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.149668 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.149668 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13229.919338 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13229.919338 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35337.426328 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35337.426328 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.213679 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.213679 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15117.647059 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15117.647059 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 30938.185392 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 30938.185392 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 30938.185392 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 30938.185392 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 30435 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 19416 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 2583 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 249 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.782811 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 77.975904 # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 24713467 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 24713467 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 24713467 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 24713467 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050893 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.050893 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289946 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.289946 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052806 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052806 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000061 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000061 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.149774 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.149774 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.149774 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.149774 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13651.653971 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13651.653971 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44736.245086 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 44736.245086 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13575.670286 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13575.670286 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15400 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15400 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 38542.757206 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 38542.757206 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 38542.757206 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 38542.757206 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 32274 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 26462 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2637 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 287 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.238908 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 92.202091 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 607758 # number of writebacks
-system.cpu.dcache.writebacks::total 607758 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350427 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 350427 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714248 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2714248 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3064675 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3064675 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3064675 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3064675 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385729 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 385729 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249001 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 249001 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12195 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 12195 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 634730 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 634730 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 634730 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 634730 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4803158500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4803158500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8205851415 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8205851415 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 142277500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 142277500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 223000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 223000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13009009915 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 13009009915 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13009009915 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 13009009915 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395749000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395749000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36727240405 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36727240405 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219122989405 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 219122989405 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026611 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026611 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024358 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047552 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047552 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000069 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000069 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.025679 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.025679 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12452.158121 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12452.158121 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32955.094216 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32955.094216 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11666.871669 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11666.871669 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13117.647059 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13117.647059 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20495.344343 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20495.344343 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20495.344343 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20495.344343 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 607669 # number of writebacks
+system.cpu.dcache.writebacks::total 607669 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351798 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 351798 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2715004 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2715004 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1354 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1354 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3066802 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3066802 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3066802 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3066802 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385700 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 385700 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248938 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 248938 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12185 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 15 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 15 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4965601859 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4965601859 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10500826931 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 10500826931 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144262002 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144262002 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15466428790 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 15466428790 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15466428790 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 15466428790 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182333907000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182333907000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 35770060494 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 35770060494 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218103967494 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 218103967494 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026616 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026616 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024352 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024352 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047525 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047525 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000061 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000061 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025680 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025680 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025680 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025680 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12874.259422 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12874.259422 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42182.498980 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42182.498980 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11839.310792 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11839.310792 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13400 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24370.473861 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24370.473861 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24370.473861 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24370.473861 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229569916889 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1229569916889 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229569916889 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1229569916889 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1488848485257 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1488848485257 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 83043 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 83044 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 1.102954 # Number of seconds simulated
-sim_ticks 1102954033500 # Number of ticks simulated
-final_tick 1102954033500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.613797 # Number of seconds simulated
+sim_ticks 2613796876500 # Number of ticks simulated
+final_tick 2613796876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 66183 # Simulator instruction rate (inst/s)
-host_op_rate 85190 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1185337549 # Simulator tick rate (ticks/s)
-host_mem_usage 402972 # Number of bytes of host memory used
-host_seconds 930.50 # Real time elapsed on the host
-sim_insts 61582952 # Number of instructions simulated
-sim_ops 79269552 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory
+host_inst_rate 54493 # Simulator instruction rate (inst/s)
+host_op_rate 70162 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2268463215 # Simulator tick rate (ticks/s)
+host_mem_usage 404628 # Number of bytes of host memory used
+host_seconds 1152.23 # Real time elapsed on the host
+sim_insts 62788171 # Number of instructions simulated
+sim_ops 80843130 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 410112 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4380532 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 404608 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 5226032 # Number of bytes read from this memory
-system.physmem.bytes_read::total 59181988 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 410112 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory
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system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
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-system.physmem.bw_read::cpu0.dtb.walker 638 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 371831 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 3971636 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_read::cpu1.inst 366840 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 4738214 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_inst_read::cpu0.inst 371831 # Instruction read bandwidth from this memory (bytes/s)
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-system.physmem.bw_inst_read::total 738671 # Instruction read bandwidth from this memory (bytes/s)
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-system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 2729347 # Write bandwidth from this memory (bytes/s)
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-system.physmem.bw_total::realview.clcd 44207449 # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 371831 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3987049 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 928 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 366840 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 7467561 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 60265202 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 6257809 # Total number of read requests seen
-system.physmem.writeReqs 823405 # Total number of write requests seen
-system.physmem.cpureqs 242034 # Reqs generatd by CPU via cache - shady
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-system.physmem.bytesWritten 52697920 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 59181988 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7287760 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 69 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 12609 # Reqs where no action is needed
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-system.physmem.perBankRdReqs::3 391605 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 391533 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 390879 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 390924 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 391633 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 391393 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 390703 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 390862 # Track reads on a per bank basis
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-system.physmem.perBankRdReqs::12 391232 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 390529 # Track reads on a per bank basis
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-system.physmem.perBankRdReqs::15 391266 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 51407 # Track writes on a per bank basis
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-system.physmem.perBankWrReqs::2 51010 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51679 # Track writes on a per bank basis
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-system.physmem.perBankWrReqs::5 50964 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50973 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 51667 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 52037 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51352 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 51503 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51884 # Track writes on a per bank basis
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-system.physmem.perBankWrReqs::14 51170 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51891 # Track writes on a per bank basis
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+system.physmem.perBankRdReqs::2 956336 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 956715 # Track reads on a per bank basis
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+system.physmem.perBankRdReqs::6 956165 # Track reads on a per bank basis
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+system.physmem.perBankRdReqs::15 956256 # Track reads on a per bank basis
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+system.physmem.perBankWrReqs::15 51508 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 32620 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1102952897500 # Total gap between requests
+system.physmem.numWrRetry 32582 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2613795718500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 105 # Categorize read packet sizes
-system.physmem.readPktSize::3 6094848 # Categorize read packet sizes
+system.physmem.readPktSize::3 15138816 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 162856 # Categorize read packet sizes
+system.physmem.readPktSize::6 163351 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
-system.physmem.writePktSize::2 756836 # Categorize write packet sizes
+system.physmem.writePktSize::2 757284 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 66569 # Categorize write packet sizes
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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-system.physmem.wrQLenPdf::17 35800 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::20 35800 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 35800 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 35800 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 32910 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::26 32757 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::31 32633 # What write queue length does an incoming req see
-system.physmem.totQLat 199184958750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 239005190000 # Sum of mem lat for all requests
-system.physmem.totBusLat 31288700000 # Total cycles spent in databus access
-system.physmem.totBankLat 8531531250 # Total cycles spent in bank access
-system.physmem.avgQLat 31830.17 # Average queueing delay per request
-system.physmem.avgBankLat 1363.36 # Average bank access latency per request
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+system.physmem.wrQLenPdf::7 3211 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 3225 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 35830 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::13 35830 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 35830 # What write queue length does an incoming req see
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+system.physmem.bytesPerActivate::samples 48021 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 21491.760022 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 1412.636943 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 31347.507834 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-95 10706 22.29% 22.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-159 4255 8.86% 31.16% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::256-287 2034 4.24% 40.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-351 1364 2.84% 43.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-415 1232 2.57% 46.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-479 971 2.02% 48.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-543 916 1.91% 50.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-607 629 1.31% 51.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-671 621 1.29% 52.86% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::896-927 288 0.60% 56.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-991 206 0.43% 56.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1055 291 0.61% 57.10% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1280-1311 142 0.30% 58.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1375 76 0.16% 58.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1439 430 0.90% 59.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1503 2116 4.41% 63.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1567 511 1.06% 64.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1631 96 0.20% 64.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1695 187 0.39% 65.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1759 61 0.13% 65.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1823 129 0.27% 65.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1887 42 0.09% 65.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1951 82 0.17% 65.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-2015 32 0.07% 66.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2079 81 0.17% 66.21% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::2176-2207 40 0.08% 66.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2271 20 0.04% 66.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2335 38 0.08% 66.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2399 8 0.02% 66.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2463 24 0.05% 66.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2527 13 0.03% 66.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2591 21 0.04% 66.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2655 4 0.01% 66.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2719 15 0.03% 66.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2783 7 0.01% 66.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2847 25 0.05% 66.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2911 10 0.02% 66.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2975 14 0.03% 66.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3039 5 0.01% 66.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3103 16 0.03% 66.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3167 3 0.01% 66.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3231 10 0.02% 66.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3295 6 0.01% 66.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3359 12 0.02% 66.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3423 3 0.01% 66.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3487 12 0.02% 66.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520-3551 7 0.01% 66.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3615 8 0.02% 66.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648-3679 5 0.01% 66.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3743 6 0.01% 66.97% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::3840-3871 10 0.02% 67.00% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::39616-39647 1 0.00% 68.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::40384-40415 1 0.00% 68.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41216-41247 2 0.00% 68.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41984-42015 2 0.00% 68.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::42240-42271 1 0.00% 68.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::42688-42719 1 0.00% 68.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::42752-42783 1 0.00% 68.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::43008-43039 1 0.00% 68.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44032-44063 3 0.01% 68.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44416-44447 1 0.00% 68.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44672-44703 1 0.00% 68.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::46592-46623 1 0.00% 68.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::46912-46943 1 0.00% 68.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::46976-47007 1 0.00% 68.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48640-48671 1 0.00% 68.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48896-48927 1 0.00% 68.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::49408-49439 2 0.00% 68.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::50688-50719 1 0.00% 68.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::50880-50911 1 0.00% 68.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::51200-51231 2 0.00% 68.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::52224-52255 2 0.00% 68.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::52608-52639 1 0.00% 68.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::53248-53279 1 0.00% 68.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::54784-54815 1 0.00% 68.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::55296-55327 1 0.00% 68.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::55616-55647 1 0.00% 68.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::56064-56095 1 0.00% 68.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::56832-56863 1 0.00% 68.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::57088-57119 2 0.00% 68.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::58112-58143 1 0.00% 68.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::59584-59615 1 0.00% 68.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::59648-59679 1 0.00% 68.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::59840-59871 1 0.00% 68.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::60416-60447 1 0.00% 68.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::61184-61215 1 0.00% 68.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::61568-61599 1 0.00% 68.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::61952-61983 1 0.00% 68.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::62976-63007 1 0.00% 68.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::63488-63519 1 0.00% 68.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64064-64095 1 0.00% 68.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64512-64543 1 0.00% 68.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65024-65055 25 0.05% 68.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65088-65119 6 0.01% 68.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65152-65183 7 0.01% 68.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65280-65311 19 0.04% 68.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65408-65439 7 0.01% 68.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65472-65503 18 0.04% 68.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65536-65567 14562 30.32% 99.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::97536-97567 1 0.00% 99.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::103680-103711 1 0.00% 99.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::129664-129695 1 0.00% 99.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::130176-130207 1 0.00% 99.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::130624-130655 1 0.00% 99.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::130688-130719 1 0.00% 99.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::131072-131103 321 0.67% 99.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::131328-131359 1 0.00% 99.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::132096-132127 2 0.00% 99.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::140032-140063 1 0.00% 99.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::162560-162591 1 0.00% 99.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::169728-169759 1 0.00% 99.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::182528-182559 1 0.00% 99.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::196608-196639 8 0.02% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 48021 # Bytes accessed per row activation
+system.physmem.totQLat 359781455750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 452374882000 # Sum of mem lat for all requests
+system.physmem.totBusLat 76509130000 # Total cycles spent in databus access
+system.physmem.totBankLat 16084296250 # Total cycles spent in bank access
+system.physmem.avgQLat 23512.32 # Average queueing delay per request
+system.physmem.avgBankLat 1051.14 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 38193.53 # Average memory access latency
-system.physmem.avgRdBW 363.12 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 47.78 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 53.66 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 29563.46 # Average memory access latency
+system.physmem.avgRdBW 374.68 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 20.18 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 50.33 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 2.79 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 3.21 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.22 # Average read queue length over time
-system.physmem.avgWrQLen 10.07 # Average write queue length over time
-system.physmem.readRowHits 6213915 # Number of row buffer hits during reads
-system.physmem.writeRowHits 799980 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 97.16 # Row buffer hit rate for writes
-system.physmem.avgGap 155757.60 # Average gap between requests
+system.physmem.busUtil 3.08 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.17 # Average read queue length over time
+system.physmem.avgWrQLen 13.40 # Average write queue length over time
+system.physmem.readRowHits 15272830 # Number of row buffer hits during reads
+system.physmem.writeRowHits 805042 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.81 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 97.69 # Row buffer hit rate for writes
+system.physmem.avgGap 162082.23 # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 72561 # number of replacements
-system.l2c.tagsinuse 53740.730134 # Cycle average of tags in use
-system.l2c.total_refs 1839807 # Total number of references to valid blocks.
-system.l2c.sampled_refs 137757 # Sample count of references to valid blocks.
-system.l2c.avg_refs 13.355452 # Average number of references to valid blocks.
+system.realview.nvmem.bw_read::cpu0.inst 24 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 171 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 24 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 171 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 24 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 171 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 54057191 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 16352590 # Transaction distribution
+system.membus.trans_dist::ReadResp 16352590 # Transaction distribution
+system.membus.trans_dist::WriteReq 769166 # Transaction distribution
+system.membus.trans_dist::WriteResp 769166 # Transaction distribution
+system.membus.trans_dist::Writeback 66800 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 35679 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 18283 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 14097 # Transaction distribution
+system.membus.trans_dist::ReadExReq 138270 # Transaction distribution
+system.membus.trans_dist::ReadExResp 137887 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384276 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1976722 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13830 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 4376896 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.bridge.slave 2384276 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port 32254354 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.realview.gic.pio 13830 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 34654528 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392552 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17759220 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27660 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total 20183988 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.bridge.slave 2392552 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.physmem.port 138869748 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.realview.gic.pio 27660 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 141294516 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 141294516 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 1493240500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 17657749750 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.7 # Layer utilization (%)
+system.membus.reqLayer3.occupancy 11792000 # Layer occupancy (ticks)
+system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 3000 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer6.occupancy 1805500 # Layer occupancy (ticks)
+system.membus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4833822840 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.membus.respLayer2.occupancy 34180950731 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
+system.l2c.replacements 73069 # number of replacements
+system.l2c.tagsinuse 53059.477869 # Cycle average of tags in use
+system.l2c.total_refs 1873536 # Total number of references to valid blocks.
+system.l2c.sampled_refs 138222 # Sample count of references to valid blocks.
+system.l2c.avg_refs 13.554543 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 39373.368087 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.dtb.walker 3.826392 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.itb.walker 0.258184 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 4017.777159 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 2831.337785 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.dtb.walker 9.908379 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 3708.426786 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 3795.827361 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.600790 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.dtb.walker 0.000058 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.061306 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.043203 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.dtb.walker 0.000151 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.056586 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.057920 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.820018 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker 21639 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 4056 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 386080 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 166672 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 30823 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 4930 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 589304 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 198131 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1401635 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 581048 # number of Writeback hits
-system.l2c.Writeback_hits::total 581048 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 1122 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 742 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 1864 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 191 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 146 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 337 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 48001 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 58894 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 106895 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 21639 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 4056 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 386080 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 214673 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 30823 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 4930 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 589304 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 257025 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1508530 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 21639 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 4056 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 386080 # number of overall hits
-system.l2c.overall_hits::cpu0.data 214673 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 30823 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 4930 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 589304 # number of overall hits
-system.l2c.overall_hits::cpu1.data 257025 # number of overall hits
-system.l2c.overall_hits::total 1508530 # number of overall hits
+system.l2c.occ_blocks::writebacks 37743.094868 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.dtb.walker 4.500926 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.itb.walker 0.000358 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 4196.922721 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 2968.415869 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker 13.090066 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 4030.052193 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 4103.400867 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.575914 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.dtb.walker 0.000069 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst 0.064040 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.045294 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.dtb.walker 0.000200 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst 0.061494 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data 0.062613 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.809623 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.dtb.walker 23020 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker 4625 # number of ReadReq hits
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-system.cpu0.branchPred.lookups 5994746 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 4572445 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 294986 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 3765254 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 2911375 # Number of BTB hits
+system.toL2Bus.throughput 58542991 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 2739841 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2739840 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 769166 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 769166 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 583280 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 34832 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 18657 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 53489 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 259511 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 259511 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 800088 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1073172 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 13793 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 57051 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 1229933 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 4820895 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 15468 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 74350 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count 8084750 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 25585472 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 34695904 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 18508 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 92124 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 39339008 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 48266196 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 22912 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 131012 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size 148151136 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 148151136 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 4868352 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 4921338984 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 1802175919 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 1506283904 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 9191448 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 34164696 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy 2769642515 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy 3249270250 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 9767440 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy 41898883 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.throughput 47250451 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 16322888 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16322888 # Transaction distribution
+system.iobus.trans_dist::WriteReq 8066 # Transaction distribution
+system.iobus.trans_dist::WriteResp 8066 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30842 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8848 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2384276 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart.pio 30842 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.realview_io.pio 8848 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 32661908 # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40560 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17696 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 2392552 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart.pio 40560 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.realview_io.pio 17696 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 123503080 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 123503080 # Total data (bytes)
+system.iobus.reqLayer0.occupancy 21645000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 4430000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 522000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
+system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 440000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 2376210000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.iobus.respLayer1.occupancy 30277632000 # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization 1.2 # Layer utilization (%)
+system.cpu0.branchPred.lookups 6073314 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 4627623 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 295826 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 3795187 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 2949225 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 77.322141 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 671631 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 28577 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 77.709610 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 683153 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 28183 # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 8900432 # DTB read hits
-system.cpu0.dtb.read_misses 28720 # DTB read misses
-system.cpu0.dtb.write_hits 5136537 # DTB write hits
-system.cpu0.dtb.write_misses 5640 # DTB write misses
+system.cpu0.dtb.read_hits 8970256 # DTB read hits
+system.cpu0.dtb.read_misses 29375 # DTB read misses
+system.cpu0.dtb.write_hits 5214738 # DTB write hits
+system.cpu0.dtb.write_misses 5731 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 1815 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1027 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 311 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 1812 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1038 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 270 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 8929152 # DTB read accesses
-system.cpu0.dtb.write_accesses 5142177 # DTB write accesses
+system.cpu0.dtb.perms_faults 591 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 8999631 # DTB read accesses
+system.cpu0.dtb.write_accesses 5220469 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 14036969 # DTB hits
-system.cpu0.dtb.misses 34360 # DTB misses
-system.cpu0.dtb.accesses 14071329 # DTB accesses
-system.cpu0.itb.inst_hits 4213831 # ITB inst hits
-system.cpu0.itb.inst_misses 5055 # ITB inst misses
+system.cpu0.dtb.hits 14184994 # DTB hits
+system.cpu0.dtb.misses 35106 # DTB misses
+system.cpu0.dtb.accesses 14220100 # DTB accesses
+system.cpu0.itb.inst_hits 4276462 # ITB inst hits
+system.cpu0.itb.inst_misses 5070 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1341 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1351 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1480 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1356 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 4218886 # ITB inst accesses
-system.cpu0.itb.hits 4213831 # DTB hits
-system.cpu0.itb.misses 5055 # DTB misses
-system.cpu0.itb.accesses 4218886 # DTB accesses
-system.cpu0.numCycles 67827180 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 4281532 # ITB inst accesses
+system.cpu0.itb.hits 4276462 # DTB hits
+system.cpu0.itb.misses 5070 # DTB misses
+system.cpu0.itb.accesses 4281532 # DTB accesses
+system.cpu0.numCycles 69613456 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 11769589 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 31997398 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 5994746 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 3583006 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 7510057 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1450935 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 59891 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles 19410639 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 4833 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 47194 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 1299057 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 233 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 4212263 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 157193 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 2052 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 41143300 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 1.004817 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.385260 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 11926468 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 32461716 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 6073314 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 3632378 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 7613392 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1460130 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 63151 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 20074417 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 5834 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 46093 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 1371911 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 4274981 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 157877 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 2111 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 42149460 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.995068 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.376418 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 33640645 81.76% 81.76% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 563027 1.37% 83.13% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 816788 1.99% 85.12% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 677485 1.65% 86.76% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 772099 1.88% 88.64% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 558236 1.36% 90.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 667723 1.62% 91.62% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 351865 0.86% 92.48% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 3095432 7.52% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 34543319 81.95% 81.95% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 572779 1.36% 83.31% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 825233 1.96% 85.27% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 684006 1.62% 86.89% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 778589 1.85% 88.74% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 565339 1.34% 90.08% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 679715 1.61% 91.70% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 356870 0.85% 92.54% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 3143610 7.46% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 41143300 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.088383 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.471749 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 12271204 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 20567331 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 6814121 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 512354 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 978290 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 934838 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 64553 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 39983053 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 212073 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 978290 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 12839379 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 5742381 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 12712172 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 6708467 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 2162611 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 38883586 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 1814 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 436137 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1233923 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents 17 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 39230664 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 175613245 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 175579140 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 34105 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 30916187 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 8314476 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 411042 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 370243 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 5355635 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 7643947 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5684540 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1124242 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1215247 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 36809311 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 895353 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 37222613 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 81088 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 6285112 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 13160919 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 256794 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 41143300 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.904707 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.513127 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 42149460 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.087243 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.466314 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 12452855 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 21284567 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 6905227 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 522550 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 984261 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 948796 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 64785 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 40574738 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 212216 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 984261 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 13028707 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 5941224 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 13201317 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 6800913 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 2193038 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 39456506 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 1875 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 442978 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 1248488 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents 66 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 39834265 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 178291734 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 178257443 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 34291 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 31450110 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 8384154 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 420012 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 376763 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 5452877 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 7762434 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 5776236 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1132872 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1233884 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 37360552 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 904892 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 37716432 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 82271 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 6323448 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 13282471 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 257104 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 42149460 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.894826 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.507768 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 26016757 63.23% 63.23% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 5731331 13.93% 77.16% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 3155319 7.67% 84.83% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2471251 6.01% 90.84% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2103314 5.11% 95.95% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 932641 2.27% 98.22% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 493188 1.20% 99.42% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 184690 0.45% 99.87% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 54809 0.13% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 26809075 63.60% 63.60% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 5821539 13.81% 77.42% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 3209963 7.62% 85.03% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2497911 5.93% 90.96% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2123670 5.04% 96.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 939017 2.23% 98.22% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 502938 1.19% 99.42% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 188935 0.45% 99.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 56412 0.13% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 41143300 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 42149460 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 26572 2.49% 2.49% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 453 0.04% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 841830 78.79% 81.32% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 199561 18.68% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 27471 2.55% 2.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 463 0.04% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.60% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 839894 78.10% 80.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 207538 19.30% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 22321556 59.97% 60.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 46948 0.13% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 9357811 25.14% 85.38% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5443427 14.62% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 22648900 60.05% 60.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 47937 0.13% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 9431477 25.01% 85.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5535066 14.68% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 37222613 # Type of FU issued
-system.cpu0.iq.rate 0.548786 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 1068416 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.028703 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 116763775 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 43997708 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 34321266 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 8390 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 4632 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 3861 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 38234480 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 4400 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 306660 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 37716432 # Type of FU issued
+system.cpu0.iq.rate 0.541798 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 1075366 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.028512 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 118766388 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 44596758 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 34851054 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 8389 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 3872 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 38735073 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 4381 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 316422 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1372064 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2343 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 13106 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 537968 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1379018 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2578 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 13049 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 541624 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 2192754 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 5299 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 2149592 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 6129 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 978290 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 4120588 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 98455 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 37822346 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 84553 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 7643947 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 5684540 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 571228 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 39920 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 2911 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 13106 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 150072 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 117309 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 267381 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 36846322 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 9215739 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 376291 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 984261 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 4297602 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 105996 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 38383622 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 87186 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 7762434 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 5776236 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 577553 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 40750 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 2975 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 13049 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 150118 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 117853 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 267971 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 37335026 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 9287293 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 381406 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 117682 # number of nop insts executed
-system.cpu0.iew.exec_refs 14611771 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 4852307 # Number of branches executed
-system.cpu0.iew.exec_stores 5396032 # Number of stores executed
-system.cpu0.iew.exec_rate 0.543238 # Inst execution rate
-system.cpu0.iew.wb_sent 36653422 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 34325127 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 18280728 # num instructions producing a value
-system.cpu0.iew.wb_consumers 35164479 # num instructions consuming a value
+system.cpu0.iew.exec_nop 118178 # number of nop insts executed
+system.cpu0.iew.exec_refs 14774953 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 4916788 # Number of branches executed
+system.cpu0.iew.exec_stores 5487660 # Number of stores executed
+system.cpu0.iew.exec_rate 0.536319 # Inst execution rate
+system.cpu0.iew.wb_sent 37140556 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 34854926 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 18563816 # num instructions producing a value
+system.cpu0.iew.wb_consumers 35689656 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.506067 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.519863 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.500692 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.520146 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 6092264 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 638559 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 231469 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 40165010 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.778528 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.739872 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 6130188 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 647788 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 232202 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 41165199 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.772263 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.733134 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 28490647 70.93% 70.93% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 5723698 14.25% 85.18% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 1913208 4.76% 89.95% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 977623 2.43% 92.38% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 784001 1.95% 94.33% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 521196 1.30% 95.63% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 385694 0.96% 96.59% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 221095 0.55% 97.14% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1147848 2.86% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 29286812 71.14% 71.14% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 5810011 14.11% 85.26% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 1968218 4.78% 90.04% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 996844 2.42% 92.46% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 804428 1.95% 94.42% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 515457 1.25% 95.67% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 392582 0.95% 96.62% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 223885 0.54% 97.17% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1166962 2.83% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 40165010 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 23670535 # Number of instructions committed
-system.cpu0.commit.committedOps 31269580 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 41165199 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 24069809 # Number of instructions committed
+system.cpu0.commit.committedOps 31790359 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 11418455 # Number of memory references committed
-system.cpu0.commit.loads 6271883 # Number of loads committed
-system.cpu0.commit.membars 229601 # Number of memory barriers committed
-system.cpu0.commit.branches 4243632 # Number of branches committed
+system.cpu0.commit.refs 11618028 # Number of memory references committed
+system.cpu0.commit.loads 6383416 # Number of loads committed
+system.cpu0.commit.membars 231880 # Number of memory barriers committed
+system.cpu0.commit.branches 4307208 # Number of branches committed
system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 27627385 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 489162 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 1147848 # number cycles where commit BW limit reached
+system.cpu0.commit.int_insts 28099612 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 498731 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 1166962 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 75528065 # The number of ROB reads
-system.cpu0.rob.rob_writes 75703855 # The number of ROB writes
-system.cpu0.timesIdled 360661 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 26683880 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 2138039181 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 23589793 # Number of Instructions Simulated
-system.cpu0.committedOps 31188838 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 23589793 # Number of Instructions Simulated
-system.cpu0.cpi 2.875277 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.875277 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.347793 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.347793 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 171736211 # number of integer regfile reads
-system.cpu0.int_regfile_writes 34071636 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 3249 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 898 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 12999243 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 450984 # number of misc regfile writes
-system.cpu0.icache.replacements 392403 # number of replacements
-system.cpu0.icache.tagsinuse 511.011252 # Cycle average of tags in use
-system.cpu0.icache.total_refs 3789022 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 392915 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 9.643363 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 6567370000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 511.011252 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.998069 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.998069 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 3789022 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 3789022 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 3789022 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 3789022 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 3789022 # number of overall hits
-system.cpu0.icache.overall_hits::total 3789022 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 423106 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 423106 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 423106 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 423106 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 423106 # number of overall misses
-system.cpu0.icache.overall_misses::total 423106 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5802286496 # number of ReadReq miss cycles
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12656.489914 # average ReadReq mshr miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8096.148498 # average LoadLockedReq mshr miss latency
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+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4410.140756 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23463.940097 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23463.940097 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23463.940097 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23463.940097 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 9076266 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 7463483 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 407973 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 6084116 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 5247879 # Number of BTB hits
+system.cpu1.branchPred.lookups 9253585 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 7592303 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 416171 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 6192388 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 5325484 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 86.255407 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 773475 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 42302 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 86.000490 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 798470 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 43798 # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 42903620 # DTB read hits
-system.cpu1.dtb.read_misses 37068 # DTB read misses
-system.cpu1.dtb.write_hits 6823215 # DTB write hits
-system.cpu1.dtb.write_misses 10679 # DTB write misses
+system.cpu1.dtb.read_hits 43179554 # DTB read hits
+system.cpu1.dtb.read_misses 37431 # DTB read misses
+system.cpu1.dtb.write_hits 6972554 # DTB write hits
+system.cpu1.dtb.write_misses 10848 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2009 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 2777 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 305 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 2005 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 2926 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 258 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 663 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 42940688 # DTB read accesses
-system.cpu1.dtb.write_accesses 6833894 # DTB write accesses
+system.cpu1.dtb.perms_faults 669 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 43216985 # DTB read accesses
+system.cpu1.dtb.write_accesses 6983402 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 49726835 # DTB hits
-system.cpu1.dtb.misses 47747 # DTB misses
-system.cpu1.dtb.accesses 49774582 # DTB accesses
-system.cpu1.itb.inst_hits 8394995 # ITB inst hits
-system.cpu1.itb.inst_misses 5378 # ITB inst misses
+system.cpu1.dtb.hits 50152108 # DTB hits
+system.cpu1.dtb.misses 48279 # DTB misses
+system.cpu1.dtb.accesses 50200387 # DTB accesses
+system.cpu1.itb.inst_hits 8467709 # ITB inst hits
+system.cpu1.itb.inst_misses 5542 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1532 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1527 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1500 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1492 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 8400373 # ITB inst accesses
-system.cpu1.itb.hits 8394995 # DTB hits
-system.cpu1.itb.misses 5378 # DTB misses
-system.cpu1.itb.accesses 8400373 # DTB accesses
-system.cpu1.numCycles 408777731 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 8473251 # ITB inst accesses
+system.cpu1.itb.hits 8467709 # DTB hits
+system.cpu1.itb.misses 5542 # DTB misses
+system.cpu1.itb.accesses 8473251 # DTB accesses
+system.cpu1.numCycles 412553366 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 19817241 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 66077936 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 9076266 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 6021354 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 14149044 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 3958978 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 63415 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles 75978247 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 4643 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 42826 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 1407438 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 103 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 8393192 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 739597 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 2716 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 114161892 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.700766 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.044841 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 20142179 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 67124404 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 9253585 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 6123954 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 14367636 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 3996679 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 69030 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 77666254 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 5814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 41513 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 1490350 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 198 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 8465907 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 710561 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 2899 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 116503477 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.698188 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.043258 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 100020305 87.61% 87.61% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 795953 0.70% 88.31% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 939001 0.82% 89.13% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 1889167 1.65% 90.79% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1518004 1.33% 92.12% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 578108 0.51% 92.62% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 2132011 1.87% 94.49% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 410005 0.36% 94.85% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 5879338 5.15% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 102143196 87.67% 87.67% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 814134 0.70% 88.37% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 962782 0.83% 89.20% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 1912655 1.64% 90.84% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1508621 1.29% 92.14% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 586161 0.50% 92.64% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 2143967 1.84% 94.48% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 421141 0.36% 94.84% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 6010820 5.16% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 114161892 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.022203 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.161648 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 21336269 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 76905312 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 12792890 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 524784 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 2602637 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 1103950 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 97871 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 75228090 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 324995 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 2602637 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 22719770 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 31941572 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 40729697 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 11839035 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 4329181 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 69767929 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 18791 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 669754 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 3086107 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents 334 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 73761871 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 321211401 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 321151882 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 59519 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 49052831 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 24709040 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 445091 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 388163 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 7873081 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 13208830 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 8144792 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 1029727 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1553546 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 63522315 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 1158429 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 89134167 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 94409 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 16267434 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 45777798 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 277724 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 114161892 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.780770 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.519105 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 116503477 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.022430 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.162705 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 21695015 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 78657608 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 12988209 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 540911 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 2621734 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1137928 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 100371 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 76331637 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 334218 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 2621734 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 23056356 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 33279261 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 41089956 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 12073504 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 4382666 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 71129037 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 18835 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 684998 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 3107715 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents 374 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 75211284 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 327489941 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 327430919 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 59022 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 50108296 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 25102988 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 461152 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 401338 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 8025308 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 13414582 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 8304810 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 1056481 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1432553 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 64611179 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1174620 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 90302569 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 94169 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 16313013 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 45540722 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 275640 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 116503477 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.775106 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.513735 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 83758719 73.37% 73.37% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 8417078 7.37% 80.74% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 4293584 3.76% 84.50% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 3776789 3.31% 87.81% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 10574202 9.26% 97.07% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1966117 1.72% 98.80% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 1029866 0.90% 99.70% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 271331 0.24% 99.93% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 74206 0.07% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 85607171 73.48% 73.48% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 8609069 7.39% 80.87% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 4398916 3.78% 84.65% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 3887525 3.34% 87.98% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 10612061 9.11% 97.09% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1964931 1.69% 98.78% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 1085414 0.93% 99.71% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 259410 0.22% 99.93% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 78980 0.07% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 114161892 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 116503477 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 32060 0.41% 0.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 998 0.01% 0.42% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 32357 0.41% 0.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 996 0.01% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 7549280 95.84% 96.26% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 294896 3.74% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 7572484 95.70% 96.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 307046 3.88% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 37620086 42.21% 42.56% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 59138 0.07% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.62% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.63% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 43968936 49.33% 91.96% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 7170532 8.04% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 38359652 42.48% 42.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 61197 0.07% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 14 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.89% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 1701 0.00% 42.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 42.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.90% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 44223929 48.97% 91.87% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 7342124 8.13% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 89134167 # Type of FU issued
-system.cpu1.iq.rate 0.218050 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 7877234 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.088375 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 300434418 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 80956642 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 53641825 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 15018 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 8136 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 6869 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 96689561 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 7908 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 342287 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 90302569 # Type of FU issued
+system.cpu1.iq.rate 0.218887 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 7912883 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.087626 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 305148356 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 82107584 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 54845197 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 15407 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 8039 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 6808 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 97893314 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 8206 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 355446 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 3455090 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 3893 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 17135 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1305851 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 3436601 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 3841 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 17378 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1303587 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 31905929 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 888458 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 31958921 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 917809 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 2602637 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 24185109 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 359685 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 64785366 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 111899 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 13208830 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 8144792 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 869085 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 64974 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 3561 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 17135 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 202123 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 154728 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 356851 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 86703480 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 43273897 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 2430687 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 2621734 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 25482277 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 363023 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 65889169 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 115264 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 13414582 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 8304810 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 878172 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 66494 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 3874 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 17378 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 205598 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 157346 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 362944 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 87965313 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 43561744 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 2337256 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 104622 # number of nop insts executed
-system.cpu1.iew.exec_refs 50383100 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 6997981 # Number of branches executed
-system.cpu1.iew.exec_stores 7109203 # Number of stores executed
-system.cpu1.iew.exec_rate 0.212104 # Inst execution rate
-system.cpu1.iew.wb_sent 85724428 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 53648694 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 29926721 # num instructions producing a value
-system.cpu1.iew.wb_consumers 53389506 # num instructions consuming a value
+system.cpu1.iew.exec_nop 103370 # number of nop insts executed
+system.cpu1.iew.exec_refs 50840273 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 7156944 # Number of branches executed
+system.cpu1.iew.exec_stores 7278529 # Number of stores executed
+system.cpu1.iew.exec_rate 0.213222 # Inst execution rate
+system.cpu1.iew.wb_sent 86983330 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 54852005 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 30529736 # num instructions producing a value
+system.cpu1.iew.wb_consumers 54511543 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.131242 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.560536 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.132957 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.560060 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 16147511 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 880705 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 311675 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 111559255 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.431612 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.399673 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 16208484 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 898980 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 317402 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 113881743 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.432055 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.398122 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 94810700 84.99% 84.99% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 8240774 7.39% 92.37% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 2114811 1.90% 94.27% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1254575 1.12% 95.39% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1245157 1.12% 96.51% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 568382 0.51% 97.02% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 999815 0.90% 97.92% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 505524 0.45% 98.37% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1819517 1.63% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 96739305 84.95% 84.95% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 8399776 7.38% 92.32% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 2206670 1.94% 94.26% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1295256 1.14% 95.40% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1289720 1.13% 96.53% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 586162 0.51% 97.05% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 954092 0.84% 97.88% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 596070 0.52% 98.41% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1814692 1.59% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 111559255 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 38062798 # Number of instructions committed
-system.cpu1.commit.committedOps 48150353 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 113881743 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 38868743 # Number of instructions committed
+system.cpu1.commit.committedOps 49203152 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 16592681 # Number of memory references committed
-system.cpu1.commit.loads 9753740 # Number of loads committed
-system.cpu1.commit.membars 190132 # Number of memory barriers committed
-system.cpu1.commit.branches 5967363 # Number of branches committed
-system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 42685619 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 534609 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 1819517 # number cycles where commit BW limit reached
+system.cpu1.commit.refs 16979204 # Number of memory references committed
+system.cpu1.commit.loads 9977981 # Number of loads committed
+system.cpu1.commit.membars 195491 # Number of memory barriers committed
+system.cpu1.commit.branches 6119212 # Number of branches committed
+system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 43616743 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 553203 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 1814692 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 172993511 # The number of ROB reads
-system.cpu1.rob.rob_writes 131291211 # The number of ROB writes
-system.cpu1.timesIdled 1408204 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 294615839 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 1796493799 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 37993159 # Number of Instructions Simulated
-system.cpu1.committedOps 48080714 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 37993159 # Number of Instructions Simulated
-system.cpu1.cpi 10.759246 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 10.759246 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.092943 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.092943 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 387964882 # number of integer regfile reads
-system.cpu1.int_regfile_writes 56217113 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 4997 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 2346 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 18468785 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 405479 # number of misc regfile writes
-system.cpu1.icache.replacements 595625 # number of replacements
-system.cpu1.icache.tagsinuse 480.695488 # Cycle average of tags in use
-system.cpu1.icache.total_refs 7752260 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 596137 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 13.004158 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 74233129000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 480.695488 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.938858 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.938858 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 7752260 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 7752260 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 7752260 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 7752260 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 7752260 # number of overall hits
-system.cpu1.icache.overall_hits::total 7752260 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 640881 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 640881 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 640881 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 640881 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 640881 # number of overall misses
-system.cpu1.icache.overall_misses::total 640881 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8621805995 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 8621805995 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 8621805995 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 8621805995 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 8621805995 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 8621805995 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 8393141 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 8393141 # number of ReadReq accesses(hits+misses)
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+system.cpu1.cpi_total 10.633064 # CPI: Total CPI of All Threads
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system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu1.dcache.demand_avg_miss_latency::total 34542.633899 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34542.633899 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 34542.633899 # average overall miss latency
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-system.cpu1.dcache.blocked::no_mshrs 3330 # number of cycles access was blocked
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+system.cpu1.dcache.avg_refs 35.759131 # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 70879256000 # Cycle when the warmup percentage was hit.
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system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu1.dcache.writebacks::total 324632 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171788 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 171788 # number of ReadReq MSHR hits
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-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1443 # number of LoadLockedReq MSHR hits
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-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12506.579985 # average ReadReq mshr miss latency
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-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31671.295408 # average WriteReq mshr miss latency
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-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20449.563317 # average overall mshr miss latency
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+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026755 # mshr miss rate for overall accesses
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+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12531.617115 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12531.617115 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39988.349389 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 39988.349389 # average WriteReq mshr miss latency
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+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7063.392986 # average LoadLockedReq mshr miss latency
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+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3300.476802 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23879.172168 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23879.172168 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23879.172168 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23879.172168 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540125454155 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 540125454155 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540125454155 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 540125454155 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1508067529269 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1508067529269 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1508067529269 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1508067529269 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 41707 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 42383 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 48865 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 50336 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 2.533116 # Number of seconds simulated
-sim_ticks 2533115780500 # Number of ticks simulated
-final_tick 2533115780500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.534279 # Number of seconds simulated
+sim_ticks 2534279149500 # Number of ticks simulated
+final_tick 2534279149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 64757 # Simulator instruction rate (inst/s)
-host_op_rate 83325 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2720016614 # Simulator tick rate (ticks/s)
-host_mem_usage 398876 # Number of bytes of host memory used
-host_seconds 931.29 # Real time elapsed on the host
-sim_insts 60307726 # Number of instructions simulated
-sim_ops 77599286 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory
+host_inst_rate 51469 # Simulator instruction rate (inst/s)
+host_op_rate 66227 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2162854547 # Simulator tick rate (ticks/s)
+host_mem_usage 400508 # Number of bytes of host memory used
+host_seconds 1171.73 # Real time elapsed on the host
+sim_insts 60307893 # Number of instructions simulated
+sim_ops 77599512 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd 119547392 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 796160 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9093200 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129429776 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 796160 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 796160 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3781760 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9094160 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129441552 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3783360 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6797832 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 6799432 # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd 14943424 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12440 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142115 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096806 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59090 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142130 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15098054 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59115 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813108 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47189972 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 813133 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47172148 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1136 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 314301 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3589729 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51095089 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 314301 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 314301 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1492928 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1190657 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2683585 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1492928 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47189972 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 314485 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3588460 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51076280 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 314485 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 314485 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1492874 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1190110 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2682985 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1492874 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47172148 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1136 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 314301 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4780386 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53778674 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15096806 # Total number of read requests seen
-system.physmem.writeReqs 813108 # Total number of write requests seen
-system.physmem.cpureqs 218339 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 966195584 # Total number of bytes read from memory
-system.physmem.bytesWritten 52038912 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 129429776 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6797832 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 312 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 943937 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 943392 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 944197 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 943973 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 943153 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 943272 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 943794 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 943286 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 943217 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 943610 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 943691 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 942979 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 943602 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50406 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50439 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51150 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 50184 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50277 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 50865 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51361 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 50798 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51185 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51244 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 50627 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51225 # Track writes on a per bank basis
+system.physmem.bw_total::cpu.inst 314485 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4778571 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53759265 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15098054 # Total number of read requests seen
+system.physmem.writeReqs 813133 # Total number of write requests seen
+system.physmem.cpureqs 218381 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 966275456 # Total number of bytes read from memory
+system.physmem.bytesWritten 52040512 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 129441552 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6799432 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 339 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4672 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 944601 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 943433 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 943409 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 943592 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 943465 # Track reads on a per bank basis
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+system.physmem.perBankWrReqs::3 51086 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 51003 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 51258 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 51261 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 51198 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51347 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 51095 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 50750 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 50404 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 50977 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 51264 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51120 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 32506 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2533114676500 # Total gap between requests
+system.physmem.numWrRetry 32444 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2534279100000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 36 # Categorize read packet sizes
-system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
+system.physmem.readPktSize::3 14943424 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154562 # Categorize read packet sizes
+system.physmem.readPktSize::6 154594 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 754018 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 59090 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 1040416 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2575 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 2624 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 2659 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 2706 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 2730 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 2756 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 2782 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 2805 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::12 35352 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 35352 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 35352 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 35352 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 35352 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 32778 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::25 32694 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 32647 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 32623 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 32597 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 32571 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 32548 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 32524 # What write queue length does an incoming req see
-system.physmem.totQLat 393224294250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 485624283000 # Sum of mem lat for all requests
-system.physmem.totBusLat 75482470000 # Total cycles spent in databus access
-system.physmem.totBankLat 16917518750 # Total cycles spent in bank access
-system.physmem.avgQLat 26047.39 # Average queueing delay per request
-system.physmem.avgBankLat 1120.63 # Average bank access latency per request
+system.physmem.wrQLenPdf::0 2591 # What write queue length does an incoming req see
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+system.physmem.bytesPerActivate::samples 42559 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 23924.789210 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 1816.195393 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 32272.883514 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-95 8308 19.52% 19.52% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::256-287 1796 4.22% 37.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-351 1258 2.96% 39.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-415 1103 2.59% 42.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-479 837 1.97% 44.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-543 830 1.95% 46.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-607 538 1.26% 47.75% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::768-799 384 0.90% 50.88% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::896-927 273 0.64% 52.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-991 193 0.45% 52.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1055 240 0.56% 53.14% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1472-1503 1932 4.54% 60.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1567 440 1.03% 61.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1631 89 0.21% 61.28% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1856-1887 40 0.09% 62.07% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::2304-2335 37 0.09% 62.70% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::2560-2591 25 0.06% 62.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2655 7 0.02% 62.91% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::2752-2783 4 0.01% 62.96% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::39296-39327 1 0.00% 65.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::39808-39839 1 0.00% 65.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::40000-40031 1 0.00% 65.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41984-42015 1 0.00% 65.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::42048-42079 1 0.00% 65.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::42496-42527 2 0.00% 65.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::43264-43295 1 0.00% 65.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44672-44703 1 0.00% 65.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44800-44831 1 0.00% 65.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::45312-45343 1 0.00% 65.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47616-47647 1 0.00% 65.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::47936-47967 1 0.00% 65.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48128-48159 1 0.00% 65.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48640-48671 1 0.00% 65.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48896-48927 1 0.00% 65.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::49152-49183 1 0.00% 65.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::49920-49951 1 0.00% 65.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::50176-50207 2 0.00% 65.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::50432-50463 1 0.00% 65.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::50688-50719 1 0.00% 65.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::54272-54303 1 0.00% 65.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::56000-56031 1 0.00% 65.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::56832-56863 1 0.00% 65.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::57344-57375 1 0.00% 65.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::58368-58399 1 0.00% 65.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::58944-58975 1 0.00% 65.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::59840-59871 1 0.00% 65.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::62208-62239 1 0.00% 65.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::62848-62879 1 0.00% 65.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::63232-63263 1 0.00% 65.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::63488-63519 2 0.00% 65.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64256-64287 1 0.00% 65.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64704-64735 1 0.00% 65.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65024-65055 13 0.03% 65.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65152-65183 18 0.04% 65.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65344-65375 8 0.02% 65.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65472-65503 18 0.04% 65.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65536-65567 14406 33.85% 99.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::113216-113247 1 0.00% 99.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::129664-129695 1 0.00% 99.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::129792-129823 1 0.00% 99.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::129984-130015 1 0.00% 99.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::130432-130463 1 0.00% 99.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::131072-131103 325 0.76% 99.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::132096-132127 3 0.01% 99.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::168704-168735 1 0.00% 99.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::169664-169695 1 0.00% 99.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::190464-190495 1 0.00% 99.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::196608-196639 9 0.02% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 42559 # Bytes accessed per row activation
+system.physmem.totQLat 355117101750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 446336213000 # Sum of mem lat for all requests
+system.physmem.totBusLat 75488575000 # Total cycles spent in databus access
+system.physmem.totBankLat 15730536250 # Total cycles spent in bank access
+system.physmem.avgQLat 23521.25 # Average queueing delay per request
+system.physmem.avgBankLat 1041.92 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 32168.02 # Average memory access latency
-system.physmem.avgRdBW 381.43 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 51.10 # Average consumed read bandwidth in MB/s
+system.physmem.avgMemAccLat 29563.16 # Average memory access latency
+system.physmem.avgRdBW 381.28 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 20.53 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 51.08 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.14 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.19 # Average read queue length over time
-system.physmem.avgWrQLen 11.11 # Average write queue length over time
-system.physmem.readRowHits 15020181 # Number of row buffer hits during reads
-system.physmem.writeRowHits 793022 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes
-system.physmem.avgGap 159216.11 # Average gap between requests
+system.physmem.avgRdQLen 0.18 # Average read queue length over time
+system.physmem.avgWrQLen 11.71 # Average write queue length over time
+system.physmem.readRowHits 15070837 # Number of row buffer hits during reads
+system.physmem.writeRowHits 797438 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.82 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 98.07 # Row buffer hit rate for writes
+system.physmem.avgGap 159276.56 # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 54705448 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 16150672 # Transaction distribution
+system.membus.trans_dist::ReadResp 16150669 # Transaction distribution
+system.membus.trans_dist::WriteReq 763336 # Transaction distribution
+system.membus.trans_dist::WriteResp 763336 # Transaction distribution
+system.membus.trans_dist::Writeback 59115 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4669 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4672 # Transaction distribution
+system.membus.trans_dist::ReadExReq 131424 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131424 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885755 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272475 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29886845 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 29886845 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port 31772600 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 34159320 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091509 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119547368 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total 119547368 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.physmem.port 136240960 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 138638877 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 138638877 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 1491846000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 17371820500 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.7 # Layer utilization (%)
+system.membus.reqLayer3.occupancy 3645000 # Layer occupancy (ticks)
+system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4719558707 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.membus.respLayer2.occupancy 33739093743 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 14672817 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11756302 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 704420 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9794195 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7944325 # Number of BTB hits
+system.iobus.throughput 48115298 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 16126739 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16126726 # Transaction distribution
+system.iobus.trans_dist::WriteReq 8158 # Transaction distribution
+system.iobus.trans_dist::WriteResp 8158 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2382946 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total 29886835 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 32269781 # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 2390309 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119547288 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 121937597 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 121937597 # Total data (bytes)
+system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 518000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 519000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
+system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 14943424000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 2374788000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.iobus.respLayer1.occupancy 29886822000 # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization 1.2 # Layer utilization (%)
+system.cpu.branchPred.lookups 14673159 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11756965 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 704729 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9767663 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7945266 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 81.112588 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1400354 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 72452 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 81.342548 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1399657 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 72413 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51400888 # DTB read hits
-system.cpu.dtb.read_misses 64225 # DTB read misses
-system.cpu.dtb.write_hits 11700104 # DTB write hits
-system.cpu.dtb.write_misses 15848 # DTB write misses
+system.cpu.dtb.read_hits 51397173 # DTB read hits
+system.cpu.dtb.read_misses 63986 # DTB read misses
+system.cpu.dtb.write_hits 11699533 # DTB write hits
+system.cpu.dtb.write_misses 15890 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 3565 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2395 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 3562 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2402 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1336 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51465113 # DTB read accesses
-system.cpu.dtb.write_accesses 11715952 # DTB write accesses
+system.cpu.dtb.perms_faults 1410 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51461159 # DTB read accesses
+system.cpu.dtb.write_accesses 11715423 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63100992 # DTB hits
-system.cpu.dtb.misses 80073 # DTB misses
-system.cpu.dtb.accesses 63181065 # DTB accesses
-system.cpu.itb.inst_hits 12331220 # ITB inst hits
-system.cpu.itb.inst_misses 11422 # ITB inst misses
+system.cpu.dtb.hits 63096706 # DTB hits
+system.cpu.dtb.misses 79876 # DTB misses
+system.cpu.dtb.accesses 63176582 # DTB accesses
+system.cpu.itb.inst_hits 12260245 # ITB inst hits
+system.cpu.itb.inst_misses 11468 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2480 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2492 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2905 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2998 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 12342642 # ITB inst accesses
-system.cpu.itb.hits 12331220 # DTB hits
-system.cpu.itb.misses 11422 # DTB misses
-system.cpu.itb.accesses 12342642 # DTB accesses
-system.cpu.numCycles 471822965 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 12271713 # ITB inst accesses
+system.cpu.itb.hits 12260245 # DTB hits
+system.cpu.itb.misses 11468 # DTB misses
+system.cpu.itb.accesses 12271713 # DTB accesses
+system.cpu.numCycles 475189978 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 30573370 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 96017663 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14672817 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9344679 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 21160566 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5295047 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 124247 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 93127049 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 86502 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 2607471 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 357 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 12327822 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 900542 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5477 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 151317698 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.785150 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.150169 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 30497823 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 96057374 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14673159 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9344923 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 21151922 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5296118 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 123395 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 94706901 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2678 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 86562 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 2683934 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 445 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 12256747 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 864492 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5531 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 152887644 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.777320 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.141699 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 130172761 86.03% 86.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1303441 0.86% 86.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1712324 1.13% 88.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2496425 1.65% 89.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2221306 1.47% 91.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1109073 0.73% 91.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2756927 1.82% 93.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 745885 0.49% 94.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8799556 5.82% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 131751310 86.18% 86.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1303513 0.85% 87.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1714679 1.12% 88.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2493622 1.63% 89.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2205066 1.44% 91.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1108856 0.73% 91.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2738323 1.79% 93.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 743817 0.49% 94.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8828458 5.77% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 151317698 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.031098 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.203504 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 32529947 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 95168576 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19190992 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 961902 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3466281 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1957763 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 171745 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 112647177 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 568207 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3466281 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 34471547 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36699353 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 52502253 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18154395 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6023869 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 106113727 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 20537 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 985646 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4066140 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 795 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 110515015 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 485506390 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 485415520 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 90870 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78390038 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 32124976 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 830416 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 736951 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12148327 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 20331207 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13516553 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1968455 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2470685 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 97921870 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1983479 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 124325634 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 167955 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 21739212 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 56995294 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 501084 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 151317698 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.821620 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.535306 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 152887644 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.030879 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.202145 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 32458089 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 96821111 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 19172249 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 971461 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3464734 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1958214 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 171741 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 112504503 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 568893 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3464734 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 34365136 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 38157390 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 52654113 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 18177530 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6068741 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 106257538 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 20628 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1016430 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4078403 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 665 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 110740396 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 486151881 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 486061534 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 90347 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78390288 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 32350107 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 830682 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 737164 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12219946 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 20282216 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13494315 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1963339 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2435947 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 97859231 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1984036 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 124319403 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 165680 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 21668523 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 56420296 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 501641 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 152887644 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.813142 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.528360 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 107101494 70.78% 70.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13519014 8.93% 79.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7070833 4.67% 84.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5935604 3.92% 88.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12601558 8.33% 96.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2800079 1.85% 98.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1698500 1.12% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 464413 0.31% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 126203 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 108584137 71.02% 71.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13613798 8.90% 79.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7066944 4.62% 84.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5988746 3.92% 88.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12566780 8.22% 96.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2768589 1.81% 98.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1723460 1.13% 99.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 446866 0.29% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 128324 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 151317698 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 152887644 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 62151 0.70% 0.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 62053 0.70% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 3 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8366348 94.60% 95.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 415303 4.70% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8365072 94.62% 95.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 413828 4.68% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 58625951 47.16% 47.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 93085 0.07% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 52921154 42.57% 90.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12319608 9.91% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 58665929 47.19% 47.48% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 93120 0.07% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 16 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.56% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52876194 42.53% 90.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12318342 9.91% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 124325634 # Type of FU issued
-system.cpu.iq.rate 0.263501 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8843805 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.071134 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 409037091 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 121660776 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 85961644 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 23336 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12538 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10309 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 132793364 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12409 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 623444 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 124319403 # Type of FU issued
+system.cpu.iq.rate 0.261620 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8840956 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071115 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 410589228 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 121528348 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 86069861 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23359 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12446 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10285 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 132784241 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12452 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 624311 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4676644 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6237 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 29883 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1784459 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4627641 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6443 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 30069 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1762200 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34107775 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 892558 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34107875 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 918337 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3466281 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 27944782 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 433344 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 100126481 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 202692 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 20331207 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13516553 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1410337 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 113091 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3418 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 29883 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 350144 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 269265 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 619409 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 121539796 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52087723 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2785838 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3464734 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 29357042 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 436051 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 100064926 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 205472 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 20282216 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13494315 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1410818 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 114442 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3537 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 30069 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 350642 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 268888 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 619530 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 121646726 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 52084248 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2672677 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 221132 # number of nop insts executed
-system.cpu.iew.exec_refs 64299655 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11557425 # Number of branches executed
-system.cpu.iew.exec_stores 12211932 # Number of stores executed
-system.cpu.iew.exec_rate 0.257596 # Inst execution rate
-system.cpu.iew.wb_sent 120381824 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 85971953 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47248258 # num instructions producing a value
-system.cpu.iew.wb_consumers 88196266 # num instructions consuming a value
+system.cpu.iew.exec_nop 221659 # number of nop insts executed
+system.cpu.iew.exec_refs 64295158 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11560329 # Number of branches executed
+system.cpu.iew.exec_stores 12210910 # Number of stores executed
+system.cpu.iew.exec_rate 0.255996 # Inst execution rate
+system.cpu.iew.wb_sent 120490085 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 86080146 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47268053 # num instructions producing a value
+system.cpu.iew.wb_consumers 88199499 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.182212 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.535717 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.181149 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.535922 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 21471534 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 21408137 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1482395 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 535206 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 147851417 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.525864 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.516226 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 535479 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 149422910 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.520334 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.507055 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 120424253 81.45% 81.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13319272 9.01% 90.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3880838 2.62% 93.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2123082 1.44% 94.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1929256 1.30% 95.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 967576 0.65% 96.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1605493 1.09% 97.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 701565 0.47% 98.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2900082 1.96% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 121949451 81.61% 81.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13299405 8.90% 90.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3946740 2.64% 93.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2141050 1.43% 94.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1955041 1.31% 95.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 959721 0.64% 96.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1537792 1.03% 97.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 781343 0.52% 98.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2852367 1.91% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 147851417 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60458107 # Number of instructions committed
-system.cpu.commit.committedOps 77749667 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 149422910 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60458274 # Number of instructions committed
+system.cpu.commit.committedOps 77749893 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27386657 # Number of memory references committed
-system.cpu.commit.loads 15654563 # Number of loads committed
-system.cpu.commit.membars 403601 # Number of memory barriers committed
-system.cpu.commit.branches 9961339 # Number of branches committed
+system.cpu.commit.refs 27386690 # Number of memory references committed
+system.cpu.commit.loads 15654575 # Number of loads committed
+system.cpu.commit.membars 403596 # Number of memory barriers committed
+system.cpu.commit.branches 9961373 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 68854898 # Number of committed integer instructions.
-system.cpu.commit.function_calls 991261 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2900082 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 68855105 # Number of committed integer instructions.
+system.cpu.commit.function_calls 991268 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2852367 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 242323943 # The number of ROB reads
-system.cpu.rob.rob_writes 202004834 # The number of ROB writes
-system.cpu.timesIdled 1771447 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 320505267 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4594325554 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60307726 # Number of Instructions Simulated
-system.cpu.committedOps 77599286 # Number of Ops (including micro ops) Simulated
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+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12185 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 15 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 15 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4965601859 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4965601859 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10500826931 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 10500826931 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144262002 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144262002 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15466428790 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 15466428790 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15466428790 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 15466428790 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182333907000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182333907000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 35770060494 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 35770060494 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218103967494 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 218103967494 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026616 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026616 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024352 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024352 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047525 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047525 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000061 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000061 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025680 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025680 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025680 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025680 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12874.259422 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12874.259422 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42182.498980 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42182.498980 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11839.310792 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11839.310792 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13400 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24370.473861 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24370.473861 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24370.473861 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24370.473861 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229569916889 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1229569916889 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229569916889 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1229569916889 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1488848485257 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1488848485257 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 83043 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 83044 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 2.401343 # Number of seconds simulated
-sim_ticks 2401342505500 # Number of ticks simulated
-final_tick 2401342505500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.401127 # Number of seconds simulated
+sim_ticks 2401127269500 # Number of ticks simulated
+final_tick 2401127269500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 199955 # Simulator instruction rate (inst/s)
-host_op_rate 256803 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 7959007704 # Simulator tick rate (ticks/s)
-host_mem_usage 399904 # Number of bytes of host memory used
-host_seconds 301.71 # Real time elapsed on the host
-sim_insts 60329298 # Number of instructions simulated
-sim_ops 77481139 # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 142330 # Simulator instruction rate (inst/s)
+host_op_rate 182788 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5664980832 # Simulator tick rate (ticks/s)
+host_mem_usage 401540 # Number of bytes of host memory used
+host_seconds 423.85 # Real time elapsed on the host
+sim_insts 60327009 # Number of instructions simulated
+sim_ops 77475387 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 502112 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 7093136 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 511520 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 7145552 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 84928 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 676160 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 78912 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 687680 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 384 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 175680 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 1309048 # Number of bytes read from this memory
-system.physmem.bytes_read::total 124660776 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 502112 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 84928 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 175680 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 762720 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3745536 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1490604 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 199456 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2.data 1325756 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6761352 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu2.inst 173184 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 1243936 # Number of bytes read from this memory
+system.physmem.bytes_read::total 124660496 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 511520 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 78912 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 173184 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 763616 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3744064 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 1523456 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 157860 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2.data 1334500 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6759880 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 14048 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 110864 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 14195 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 111683 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1327 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 10565 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 1233 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 10745 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 6 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 2745 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 20467 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 14512410 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 58524 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 372651 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 49864 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2.data 331439 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 812478 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47814534 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu2.inst 2706 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 19444 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 14512400 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 58501 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 380864 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 39465 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2.data 333625 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 812455 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47818820 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 209096 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 2953821 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 213033 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 2975916 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 35367 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 281576 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 32865 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 286399 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 160 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 73159 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 545132 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51912951 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 209096 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 35367 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 73159 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 317622 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1559768 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 620738 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 83060 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2.data 552090 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2815655 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1559768 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47814534 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 72126 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 518063 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51917488 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 213033 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 32865 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 72126 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 318024 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1559294 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 634475 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 65744 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2.data 555781 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2815294 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1559294 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47818820 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 209096 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3574559 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 213033 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 3610391 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 35367 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 364636 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 32865 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 352143 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 73159 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 1097221 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54728606 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 12618023 # Total number of read requests seen
-system.physmem.writeReqs 398732 # Total number of write requests seen
-system.physmem.cpureqs 54886 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 807553472 # Total number of bytes read from memory
-system.physmem.bytesWritten 25518848 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 102909560 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 2640668 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 2360 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 789126 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 788779 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 788883 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 789203 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 789028 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 788746 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 788896 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 788935 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 788618 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 788026 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 788041 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 788281 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 788275 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 788125 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 788319 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 788742 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 24962 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 24831 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 24770 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 25056 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 24828 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 24649 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 24736 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 24783 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 25151 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 24834 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 24774 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 24883 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 25404 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 24880 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 24969 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 25222 # Track writes on a per bank basis
+system.physmem.bw_total::cpu2.inst 72126 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 1073844 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 54732782 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 12420439 # Total number of read requests seen
+system.physmem.writeReqs 390212 # Total number of write requests seen
+system.physmem.cpureqs 53603 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 794908096 # Total number of bytes read from memory
+system.physmem.bytesWritten 24973568 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 101274592 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 2588168 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 1 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 2354 # Reqs where no action is needed
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 14347 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2400307282000 # Total gap between requests
+system.physmem.numWrRetry 14413 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2400092064000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 35097 # Categorize read packet sizes
+system.physmem.readPktSize::6 34127 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
-system.physmem.writePktSize::2 381303 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 17429 # Categorize write packet sizes
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-system.physmem.totQLat 277119182500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 352940243750 # Sum of mem lat for all requests
-system.physmem.totBusLat 63090115000 # Total cycles spent in databus access
-system.physmem.totBankLat 12730946250 # Total cycles spent in bank access
-system.physmem.avgQLat 21962.17 # Average queueing delay per request
-system.physmem.avgBankLat 1008.95 # Average bank access latency per request
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+system.physmem.bytesPerActivate::samples 20861 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 39302.074493 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 6009.687839 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 33098.413312 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-95 3004 14.40% 14.40% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::192-223 811 3.89% 24.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-287 565 2.71% 27.36% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::384-415 362 1.74% 30.92% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::512-543 238 1.14% 33.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-607 172 0.82% 34.16% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::11776-11807 1 0.00% 41.12% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::127424-127455 1 0.00% 99.13% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::total 20861 # Bytes accessed per row activation
+system.physmem.totQLat 241895050750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 315493767000 # Sum of mem lat for all requests
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+system.physmem.totBankLat 11496526250 # Total cycles spent in bank access
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 27971.12 # Average memory access latency
-system.physmem.avgRdBW 336.29 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 10.63 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 42.86 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s
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+system.physmem.avgConsumedRdBW 42.18 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 1.08 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 2.71 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.15 # Average read queue length over time
-system.physmem.avgWrQLen 0.39 # Average write queue length over time
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-system.physmem.writeRowHits 392399 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 98.41 # Row buffer hit rate for writes
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-system.l2c.occ_blocks::writebacks 36827.136068 # Average occupied blocks per requestor
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+system.physmem.writeRowHits 385376 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.87 # Row buffer hit rate for reads
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+system.l2c.overall_mshr_miss_latency::total 1988246370 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25115656000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26467069000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 51582725000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 935834000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9813018750 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 10748852750 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 26051490000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data 36280087750 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 62331577750 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000381 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009032 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017943 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000327 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009493 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.017665 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.005856 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991632 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.987292 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.505622 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.334800 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.343891 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.110562 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000381 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009032 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.114423 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000327 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009493 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data 0.102934 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.022440 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000381 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009032 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.114423 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000327 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009493 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data 0.102934 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.022440 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60302.311436 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61622.920133 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 71666.666667 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65644.401330 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 63731.587239 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 63532.977755 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10022.798658 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32483.490935 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40717.622247 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 37892.626884 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43207.669179 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33876.402251 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 104667.666667 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 51137.767577 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41759.345527 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40163.838908 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43207.669179 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33876.402251 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 104667.666667 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 51137.767577 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41759.345527 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40163.838908 # average overall mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50485.006212 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 57409.873306 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 54920.116075 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60302.311436 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51699.757372 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 71666.666667 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65644.401330 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 58211.212881 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 56811.908735 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60302.311436 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51699.757372 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 71666.666667 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65644.401330 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 58211.212881 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 56811.908735 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.toL2Bus.throughput 58868329 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 1038711 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 1038710 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 375940 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 375940 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 275281 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 1501 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 1503 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 80190 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 80190 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 843862 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2343005 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 15512 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 51160 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count 3253539 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 26980864 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 38469375 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 21900 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 84004 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size 65556143 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 141250094 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 100256 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 2175069728 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 1900577406 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 1863798035 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 10055959 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 30318675 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.throughput 48814240 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 12751762 # Transaction distribution
+system.iobus.trans_dist::ReadResp 12751762 # Transaction distribution
+system.iobus.trans_dist::WriteReq 2783 # Transaction distribution
+system.iobus.trans_dist::WriteResp 2783 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11428 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3102 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 262 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 721384 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 736482 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 24772608 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total 24772608 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart.pio 11428 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.realview_io.pio 3102 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.timer1.pio 262 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.cf_ctrl.pio 721384 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.sp810_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.iocache.cpu_side 24772608 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 25509090 # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15392 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6204 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 524 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 717707 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 740439 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 99090432 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::total 99090432 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart.pio 15392 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.realview_io.pio 6204 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.timer1.pio 524 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 717707 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
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system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
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system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed
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system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
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system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions
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system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed
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system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
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system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
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-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033321 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028970 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014672 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021547 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019429 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008082 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048269 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044950 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020668 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000016 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028455 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025495 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.011872 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028455 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025495 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.011872 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11938.226767 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13012.144312 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12668.859595 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22637.159303 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27034.857496 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25461.720983 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11091.014493 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11689.459930 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11489.746566 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 597640 # number of writebacks
+system.cpu0.dcache.writebacks::total 597640 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 147191 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 147191 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 530305 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 530305 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 415 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 415 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data 677496 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 677496 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data 677496 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 677496 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65203 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 140329 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 205532 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29806 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 51832 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 81638 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1787 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3452 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5239 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data 95009 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data 192161 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 287170 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data 95009 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data 192161 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 287170 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 798657500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1814845381 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2613502881 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 853492500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1663883074 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2517375574 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19875000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 39692503 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59567503 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1652150000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3478728455 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 5130878455 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1652150000 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3478728455 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 5130878455 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27438525500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28895903000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56334428500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1439019500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13930302419 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15369321919 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28877545000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42826205419 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71703750419 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033512 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029420 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014862 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021489 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019306 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007991 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049609 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044631 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020906 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028508 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025777 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.011943 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028508 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025777 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.011943 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12248.784565 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12932.789238 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12715.795501 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28634.922499 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32101.463845 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30835.831035 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11121.992166 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11498.407590 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11370.013934 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15286.425718 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16904.712140 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16369.598173 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15286.425718 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16904.712140 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16369.598173 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17389.405214 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18103.197085 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17867.042013 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17389.405214 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18103.197085 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17867.042013 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 2161402 # DTB read hits
-system.cpu1.dtb.read_misses 2114 # DTB read misses
-system.cpu1.dtb.write_hits 1457218 # DTB write hits
-system.cpu1.dtb.write_misses 386 # DTB write misses
+system.cpu1.dtb.read_hits 2160353 # DTB read hits
+system.cpu1.dtb.read_misses 2072 # DTB read misses
+system.cpu1.dtb.write_hits 1463428 # DTB write hits
+system.cpu1.dtb.write_misses 375 # DTB write misses
system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 237 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1711 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 1741 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 41 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 2163516 # DTB read accesses
-system.cpu1.dtb.write_accesses 1457604 # DTB write accesses
+system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 2162425 # DTB read accesses
+system.cpu1.dtb.write_accesses 1463803 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 3618620 # DTB hits
-system.cpu1.dtb.misses 2500 # DTB misses
-system.cpu1.dtb.accesses 3621120 # DTB accesses
-system.cpu1.itb.inst_hits 8380082 # ITB inst hits
-system.cpu1.itb.inst_misses 1132 # ITB inst misses
+system.cpu1.dtb.hits 3623781 # DTB hits
+system.cpu1.dtb.misses 2447 # DTB misses
+system.cpu1.dtb.accesses 3626228 # DTB accesses
+system.cpu1.itb.inst_hits 8343384 # ITB inst hits
+system.cpu1.itb.inst_misses 1170 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 237 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 830 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 867 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 8381214 # ITB inst accesses
-system.cpu1.itb.hits 8380082 # DTB hits
-system.cpu1.itb.misses 1132 # DTB misses
-system.cpu1.itb.accesses 8381214 # DTB accesses
-system.cpu1.numCycles 574618954 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 8344554 # ITB inst accesses
+system.cpu1.itb.hits 8343384 # DTB hits
+system.cpu1.itb.misses 1170 # DTB misses
+system.cpu1.itb.accesses 8344554 # DTB accesses
+system.cpu1.numCycles 576594127 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 8175033 # Number of instructions committed
-system.cpu1.committedOps 10410069 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 9322021 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 1998 # Number of float alu accesses
-system.cpu1.num_func_calls 315375 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 1140852 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 9322021 # number of integer instructions
-system.cpu1.num_fp_insts 1998 # number of float instructions
-system.cpu1.num_int_register_reads 53738545 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 10097471 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 1549 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written
-system.cpu1.num_mem_refs 3791152 # number of memory refs
-system.cpu1.num_load_insts 2256757 # Number of load instructions
-system.cpu1.num_store_insts 1534395 # Number of store instructions
-system.cpu1.num_idle_cycles 532868716.793879 # Number of idle cycles
-system.cpu1.num_busy_cycles 41750237.206121 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.072657 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.927343 # Percentage of idle cycles
+system.cpu1.committedInsts 8139213 # Number of instructions committed
+system.cpu1.committedOps 10387341 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 9296011 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 2143 # Number of float alu accesses
+system.cpu1.num_func_calls 319457 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 1149983 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 9296011 # number of integer instructions
+system.cpu1.num_fp_insts 2143 # number of float instructions
+system.cpu1.num_int_register_reads 53626328 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 10059981 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 1630 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written
+system.cpu1.num_mem_refs 3800206 # number of memory refs
+system.cpu1.num_load_insts 2257531 # Number of load instructions
+system.cpu1.num_store_insts 1542675 # Number of store instructions
+system.cpu1.num_idle_cycles 550949024.070645 # Number of idle cycles
+system.cpu1.num_busy_cycles 25645102.929355 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.044477 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.955523 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.branchPred.lookups 4722397 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 3838487 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 221435 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 2952816 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 2527233 # Number of BTB hits
+system.cpu2.branchPred.lookups 4706679 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 3828645 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 220746 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 3114772 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 2519361 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 85.587216 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 411089 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 21408 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct 80.884283 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 411150 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 21524 # Number of incorrect RAS predictions.
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
-system.cpu2.dtb.read_hits 10881575 # DTB read hits
-system.cpu2.dtb.read_misses 22640 # DTB read misses
-system.cpu2.dtb.write_hits 3277177 # DTB write hits
-system.cpu2.dtb.write_misses 5849 # DTB write misses
+system.cpu2.dtb.read_hits 10881090 # DTB read hits
+system.cpu2.dtb.read_misses 22334 # DTB read misses
+system.cpu2.dtb.write_hits 3233578 # DTB write hits
+system.cpu2.dtb.write_misses 5962 # DTB write misses
system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu2.dtb.flush_tlb_mva_asid 512 # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dtb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries 2319 # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults 814 # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults 160 # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_entries 2292 # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults 695 # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults 165 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults 478 # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses 10904215 # DTB read accesses
-system.cpu2.dtb.write_accesses 3283026 # DTB write accesses
+system.cpu2.dtb.perms_faults 471 # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses 10903424 # DTB read accesses
+system.cpu2.dtb.write_accesses 3239540 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu2.dtb.hits 14158752 # DTB hits
-system.cpu2.dtb.misses 28489 # DTB misses
-system.cpu2.dtb.accesses 14187241 # DTB accesses
-system.cpu2.itb.inst_hits 4065885 # ITB inst hits
-system.cpu2.itb.inst_misses 4502 # ITB inst misses
+system.cpu2.dtb.hits 14114668 # DTB hits
+system.cpu2.dtb.misses 28296 # DTB misses
+system.cpu2.dtb.accesses 14142964 # DTB accesses
+system.cpu2.itb.inst_hits 3988029 # ITB inst hits
+system.cpu2.itb.inst_misses 4597 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu2.itb.flush_tlb_mva_asid 512 # Number of times TLB was flushed by MVA & ASID
+system.cpu2.itb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries 1576 # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_entries 1713 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults 1005 # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults 994 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
-system.cpu2.itb.inst_accesses 4070387 # ITB inst accesses
-system.cpu2.itb.hits 4065885 # DTB hits
-system.cpu2.itb.misses 4502 # DTB misses
-system.cpu2.itb.accesses 4070387 # DTB accesses
-system.cpu2.numCycles 88259873 # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses 3992626 # ITB inst accesses
+system.cpu2.itb.hits 3988029 # DTB hits
+system.cpu2.itb.misses 4597 # DTB misses
+system.cpu2.itb.accesses 3992626 # DTB accesses
+system.cpu2.numCycles 88357796 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 9453176 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 32426467 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 4722397 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 2938322 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 6835194 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 1814499 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles 51467 # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.BlockedCycles 18689225 # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 953 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 32914 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 708494 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 306 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 4064555 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 309850 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes 1926 # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples 37018169 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.050897 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.436881 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles 9310481 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 32575007 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 4706679 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 2930511 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 6844695 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 1834626 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles 50535 # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.BlockedCycles 18792292 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles 211 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 834 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 32689 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 721380 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 3986556 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 271694 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes 2030 # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples 37012176 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.054575 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.442886 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 30188064 81.55% 81.55% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 383346 1.04% 82.58% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 510640 1.38% 83.96% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 813031 2.20% 86.16% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 657801 1.78% 87.94% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 343878 0.93% 88.87% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 1012409 2.73% 91.60% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 238466 0.64% 92.25% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 2870534 7.75% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 30172484 81.52% 81.52% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 383589 1.04% 82.56% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 509700 1.38% 83.93% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 816595 2.21% 86.14% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 649845 1.76% 87.90% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 340688 0.92% 88.82% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 1002283 2.71% 91.52% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 233105 0.63% 92.15% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 2903887 7.85% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 37018169 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.053506 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 0.367398 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 10067654 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 19275483 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 6184949 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 295259 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 1193811 # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved 613325 # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred 53657 # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts 36756215 # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts 182103 # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles 1193811 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 10642239 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 6572797 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 11156885 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 5885889 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 1565553 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 34514239 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 2456 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 419835 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents 882809 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.FullRegisterEvents 92 # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands 37003284 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 157776579 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 157748805 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 27774 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 25809996 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 11193287 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 230807 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 207161 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 3357083 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 6535673 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 3850744 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 536963 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 792176 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 31747463 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 511528 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 34289699 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 55083 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 7395646 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 19879544 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 155324 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 37018169 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 0.926294 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.580927 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 37012176 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.053268 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 0.368672 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 9923582 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 19398911 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 6192413 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 289708 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 1206624 # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved 608704 # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred 53227 # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts 36668894 # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts 179672 # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles 1206624 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 10457732 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 6796532 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 11090349 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 5929465 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 1530564 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 34717207 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 2441 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 375073 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents 892617 # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.FullRegisterEvents 118 # Number of times there has been no free registers
+system.cpu2.rename.RenamedOperands 37295857 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 158754403 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 158727276 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 27127 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 25598469 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 11697387 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 231672 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 208131 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 3300393 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 6518889 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 3789656 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 530954 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 691805 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 31588093 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 511099 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 34136489 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 54725 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 7434189 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 19599124 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 154239 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 37012176 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 0.922304 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.578312 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 24442328 66.03% 66.03% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 3909913 10.56% 76.59% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 2354045 6.36% 82.95% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 1974122 5.33% 88.28% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 2799200 7.56% 95.84% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 884316 2.39% 98.23% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 484064 1.31% 99.54% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 134882 0.36% 99.90% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 35299 0.10% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 24481195 66.14% 66.14% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 3912173 10.57% 76.71% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 2318887 6.27% 82.98% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 2014061 5.44% 88.42% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 2743513 7.41% 95.83% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 884212 2.39% 98.22% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 492586 1.33% 99.55% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 130661 0.35% 99.91% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 34888 0.09% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 37018169 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 37012176 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 18550 1.21% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 1.21% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 18493 1.21% 1.21% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 1 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.21% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.21% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 1408407 91.61% 92.81% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 110486 7.19% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 1405660 91.60% 92.81% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 110389 7.19% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass 61448 0.18% 0.18% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 19376629 56.51% 56.69% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 26012 0.08% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 8 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 8 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 381 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 11380471 33.19% 89.95% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 3444734 10.05% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::No_OpClass 61311 0.18% 0.18% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 19306288 56.56% 56.74% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 26277 0.08% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 7 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 369 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.81% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 11344167 33.23% 90.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 3398057 9.95% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 34289699 # Type of FU issued
-system.cpu2.iq.rate 0.388508 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 1537443 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.044837 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 107211457 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 39659859 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 27420215 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 6989 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 3825 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 3150 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 35761973 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 3721 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 208327 # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total 34136489 # Type of FU issued
+system.cpu2.iq.rate 0.386344 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 1534543 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.044953 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 106895526 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 39538518 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 27366143 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 7075 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 3717 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_wakeup_accesses 3145 # Number of floating instruction queue wakeup accesses
+system.cpu2.iq.int_alu_accesses 35605938 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 3783 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 206498 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 1579914 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 1893 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 9373 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 582518 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 1561517 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 1841 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 9166 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 566678 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 5363105 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 352533 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 5349938 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 380447 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 1193811 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 4877812 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 91796 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 32340028 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 60265 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 6535673 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 3850744 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 369403 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 31610 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 2472 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 9373 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 105135 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 88586 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 193721 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 33297921 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 11093060 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 991778 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 1206624 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 5097630 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 92333 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 32182024 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 61203 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 6518889 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 3789656 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 368677 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 31621 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 2335 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 9166 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 105355 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 88176 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 193531 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 33238932 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 11092763 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 897557 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 81037 # number of nop insts executed
-system.cpu2.iew.exec_refs 14504508 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 3695173 # Number of branches executed
-system.cpu2.iew.exec_stores 3411448 # Number of stores executed
-system.cpu2.iew.exec_rate 0.377271 # Inst execution rate
-system.cpu2.iew.wb_sent 32878469 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 27423365 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 15687848 # num instructions producing a value
-system.cpu2.iew.wb_consumers 28539684 # num instructions consuming a value
+system.cpu2.iew.exec_nop 82832 # number of nop insts executed
+system.cpu2.iew.exec_refs 14457569 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 3671446 # Number of branches executed
+system.cpu2.iew.exec_stores 3364806 # Number of stores executed
+system.cpu2.iew.exec_rate 0.376186 # Inst execution rate
+system.cpu2.iew.wb_sent 32811396 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 27369288 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 15602510 # num instructions producing a value
+system.cpu2.iew.wb_consumers 28268763 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 0.310712 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.549685 # average fanout of values written-back
+system.cpu2.iew.wb_rate 0.309755 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.551935 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 7335381 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 356204 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 168508 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 35824220 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 0.690433 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.719118 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 7374898 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 356860 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 168297 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 35805367 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 0.685358 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 1.714033 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 27176930 75.86% 75.86% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 4185525 11.68% 87.55% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1261410 3.52% 91.07% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 649563 1.81% 92.88% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 571804 1.60% 94.48% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 316250 0.88% 95.36% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 400543 1.12% 96.48% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 292091 0.82% 97.29% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 970104 2.71% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 27231349 76.05% 76.05% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 4142496 11.57% 87.62% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1257531 3.51% 91.14% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 645964 1.80% 92.94% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 562986 1.57% 94.51% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 317406 0.89% 95.40% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 386660 1.08% 96.48% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 302677 0.85% 97.32% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 958298 2.68% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 35824220 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 20010366 # Number of instructions committed
-system.cpu2.commit.committedOps 24734227 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 35805367 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 19842604 # Number of instructions committed
+system.cpu2.commit.committedOps 24539507 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 8223985 # Number of memory references committed
-system.cpu2.commit.loads 4955759 # Number of loads committed
-system.cpu2.commit.membars 94186 # Number of memory barriers committed
-system.cpu2.commit.branches 3169280 # Number of branches committed
-system.cpu2.commit.fp_insts 3103 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 21954082 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 294910 # Number of function calls committed.
-system.cpu2.commit.bw_lim_events 970104 # number cycles where commit BW limit reached
+system.cpu2.commit.refs 8180350 # Number of memory references committed
+system.cpu2.commit.loads 4957372 # Number of loads committed
+system.cpu2.commit.membars 94561 # Number of memory barriers committed
+system.cpu2.commit.branches 3152552 # Number of branches committed
+system.cpu2.commit.fp_insts 3091 # Number of committed floating point instructions.
+system.cpu2.commit.int_insts 21772655 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 294654 # Number of function calls committed.
+system.cpu2.commit.bw_lim_events 958298 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 66398809 # The number of ROB reads
-system.cpu2.rob.rob_writes 65374131 # The number of ROB writes
-system.cpu2.timesIdled 360148 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 51241704 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 3567295976 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 19956402 # Number of Instructions Simulated
-system.cpu2.committedOps 24680263 # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total 19956402 # Number of Instructions Simulated
-system.cpu2.cpi 4.422635 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 4.422635 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.226110 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.226110 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 153855471 # number of integer regfile reads
-system.cpu2.int_regfile_writes 29258344 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 22383 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 20838 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 9035132 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 240694 # number of misc regfile writes
+system.cpu2.rob.rob_reads 66237138 # The number of ROB reads
+system.cpu2.rob.rob_writes 65080734 # The number of ROB writes
+system.cpu2.timesIdled 362582 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 51345620 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 3559271384 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 19787102 # Number of Instructions Simulated
+system.cpu2.committedOps 24484005 # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total 19787102 # Number of Instructions Simulated
+system.cpu2.cpi 4.465424 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 4.465424 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.223943 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.223943 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 153570043 # number of integer regfile reads
+system.cpu2.int_regfile_writes 29228694 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 22407 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 20832 # number of floating regfile writes
+system.cpu2.misc_regfile_reads 8993137 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 241651 # number of misc regfile writes
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981038235668 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 981038235668 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981038235668 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 981038235668 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1181598504500 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1181598504500 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1181598504500 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1181598504500 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 2.543311 # Number of seconds simulated
-sim_ticks 2543310963000 # Number of ticks simulated
-final_tick 2543310963000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.548434 # Number of seconds simulated
+sim_ticks 2548433543500 # Number of ticks simulated
+final_tick 2548433543500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 64896 # Simulator instruction rate (inst/s)
-host_op_rate 83503 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2736674491 # Simulator tick rate (ticks/s)
-host_mem_usage 401948 # Number of bytes of host memory used
-host_seconds 929.34 # Real time elapsed on the host
-sim_insts 60310426 # Number of instructions simulated
-sim_ops 77602848 # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 62524 # Simulator instruction rate (inst/s)
+host_op_rate 80452 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2641694597 # Simulator tick rate (ticks/s)
+host_mem_usage 403600 # Number of bytes of host memory used
+host_seconds 964.70 # Real time elapsed on the host
+sim_insts 60316814 # Number of instructions simulated
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system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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-system.physmem.totGap 2543309787500 # Total gap between requests
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+system.physmem.totGap 2548432371500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 15138816 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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-system.physmem.wrQLenPdf::24 32651 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::28 32507 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 32498 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 32487 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 32480 # What write queue length does an incoming req see
-system.physmem.totQLat 346644691750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 439813624250 # Sum of mem lat for all requests
-system.physmem.totBusLat 76467385000 # Total cycles spent in databus access
-system.physmem.totBankLat 16701547500 # Total cycles spent in bank access
-system.physmem.avgQLat 22666.18 # Average queueing delay per request
-system.physmem.avgBankLat 1092.07 # Average bank access latency per request
+system.physmem.wrQLenPdf::17 35276 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 35260 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::23 32740 # What write queue length does an incoming req see
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+system.physmem.bytesPerActivate::samples 40040 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 25744.741658 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 2072.132686 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 32880.697508 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-95 6923 17.29% 17.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-159 3475 8.68% 25.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-223 2293 5.73% 31.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-287 1778 4.44% 36.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-351 1271 3.17% 39.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-415 1070 2.67% 41.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-479 793 1.98% 43.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-543 869 2.17% 46.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-607 551 1.38% 47.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-671 489 1.22% 48.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-735 420 1.05% 49.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-799 393 0.98% 50.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-863 261 0.65% 51.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-927 255 0.64% 52.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-991 183 0.46% 52.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1055 282 0.70% 53.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1119 123 0.31% 53.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1183 156 0.39% 53.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1247 102 0.25% 54.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1311 126 0.31% 54.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1375 80 0.20% 54.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1439 383 0.96% 55.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1503 613 1.53% 57.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1567 451 1.13% 58.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1631 81 0.20% 58.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1695 160 0.40% 58.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1759 53 0.13% 59.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1823 109 0.27% 59.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1887 41 0.10% 59.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1951 74 0.18% 59.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-2015 31 0.08% 59.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2079 65 0.16% 59.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2143 23 0.06% 59.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2207 42 0.10% 59.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2271 15 0.04% 60.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2335 29 0.07% 60.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2399 18 0.04% 60.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2463 27 0.07% 60.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2527 12 0.03% 60.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2591 20 0.05% 60.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2655 7 0.02% 60.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2719 22 0.05% 60.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2783 8 0.02% 60.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2847 11 0.03% 60.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2911 11 0.03% 60.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2975 16 0.04% 60.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3039 6 0.01% 60.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3103 19 0.05% 60.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3167 8 0.02% 60.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3231 9 0.02% 60.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3295 8 0.02% 60.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3359 9 0.02% 60.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3423 6 0.01% 60.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3487 6 0.01% 60.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520-3551 4 0.01% 60.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3615 9 0.02% 60.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648-3679 4 0.01% 60.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3743 9 0.02% 60.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776-3807 6 0.01% 60.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840-3871 4 0.01% 60.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904-3935 3 0.01% 60.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3968-3999 10 0.02% 60.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4063 5 0.01% 60.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4096-4127 40 0.10% 60.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4160-4191 3 0.01% 60.90% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::4608-4639 3 0.01% 60.96% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::5440-5471 5 0.01% 61.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5504-5535 7 0.02% 61.07% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::5824-5855 1 0.00% 61.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5888-5919 3 0.01% 61.08% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::65536-65567 14762 36.87% 99.10% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::total 40040 # Bytes accessed per row activation
+system.physmem.totQLat 308881805250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 400754322750 # Sum of mem lat for all requests
+system.physmem.totBusLat 76467100000 # Total cycles spent in databus access
+system.physmem.totBankLat 15405417500 # Total cycles spent in bank access
+system.physmem.avgQLat 20197.04 # Average queueing delay per request
+system.physmem.avgBankLat 1007.32 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 28758.25 # Average memory access latency
-system.physmem.avgRdBW 384.85 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 20.46 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 51.51 # Average consumed read bandwidth in MB/s
+system.physmem.avgMemAccLat 26204.36 # Average memory access latency
+system.physmem.avgRdBW 384.07 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 20.42 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 51.41 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.67 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 3.17 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.17 # Average read queue length over time
-system.physmem.avgWrQLen 1.13 # Average write queue length over time
-system.physmem.readRowHits 15218324 # Number of row buffer hits during reads
-system.physmem.writeRowHits 794497 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 97.70 # Row buffer hit rate for writes
-system.physmem.avgGap 157904.04 # Average gap between requests
-system.l2c.replacements 64400 # number of replacements
-system.l2c.tagsinuse 51409.834545 # Cycle average of tags in use
-system.l2c.total_refs 1903586 # Total number of references to valid blocks.
-system.l2c.sampled_refs 129789 # Sample count of references to valid blocks.
-system.l2c.avg_refs 14.666775 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 2531435998500 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 36958.443874 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.dtb.walker 20.878124 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.itb.walker 0.000349 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 5181.005742 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 3269.589268 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.dtb.walker 7.697989 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 3013.641151 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 2958.578047 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.563941 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.dtb.walker 0.000319 # Average percentage of cache occupancy
+system.physmem.busUtil 3.16 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.16 # Average read queue length over time
+system.physmem.avgWrQLen 1.10 # Average write queue length over time
+system.physmem.readRowHits 15267875 # Number of row buffer hits during reads
+system.physmem.writeRowHits 798648 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 98.22 # Row buffer hit rate for writes
+system.physmem.avgGap 158223.12 # Average gap between requests
+system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 55014580 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 16346067 # Transaction distribution
+system.membus.trans_dist::ReadResp 16346070 # Transaction distribution
+system.membus.trans_dist::WriteReq 763348 # Transaction distribution
+system.membus.trans_dist::WriteResp 763348 # Transaction distribution
+system.membus.trans_dist::Writeback 59118 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4682 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4684 # Transaction distribution
+system.membus.trans_dist::ReadExReq 131411 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131411 # Transaction distribution
+system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution
+system.membus.trans_dist::StoreCondReq 3 # Transaction distribution
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+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000286 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013395 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.241204 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011705 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.205460 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.091591 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 84486.111111 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61959.893837 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61674.135507 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74375 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60868.919886 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62787.378534 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 61810.745390 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10005.201034 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.731529 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10003.573439 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39988.226573 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37119.935476 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 38432.465895 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62932.787879 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 43001.703766 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40475.095470 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44757.096380 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37683.798886 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 39359.547770 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62932.787879 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43001.703766 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40475.095470 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44757.096380 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37683.798886 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 39359.547770 # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56143.257661 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55885.895105 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 56022.680137 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84486.111111 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61959.893837 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56582.283589 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74375 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60868.919886 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56352.841447 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 56876.555548 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84486.111111 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61959.893837 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56582.283589 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74375 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60868.919886 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56352.841447 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 56876.555548 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 7600384 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 6061207 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 379102 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 4941026 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 4041960 # Number of BTB hits
+system.toL2Bus.throughput 58505331 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 2677704 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2677706 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 608398 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 2960 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 246173 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 246173 # Transaction distribution
+system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution
+system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution
+system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1969441 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5798176 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 37507 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 149666 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count 7954790 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 62986112 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 85598825 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 54648 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 253968 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size 148893553 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 148893553 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 203396 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 4965063678 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 4434793437 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 4469014832 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 23886909 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 86662497 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.throughput 48461480 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 16322135 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16322135 # Transaction distribution
+system.iobus.trans_dist::WriteReq 8160 # Transaction distribution
+system.iobus.trans_dist::WriteResp 8160 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2382958 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 32660590 # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 2390333 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 123500861 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 123500861 # Total data (bytes)
+system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 521000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
+system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 2374798000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.iobus.respLayer1.occupancy 30277632000 # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization 1.2 # Layer utilization (%)
+system.cpu0.branchPred.lookups 7472736 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 5963732 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 379354 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 4914816 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 4037140 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 81.804063 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 728879 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 39033 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 82.142241 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 698266 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 38240 # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 26040938 # DTB read hits
-system.cpu0.dtb.read_misses 40555 # DTB read misses
-system.cpu0.dtb.write_hits 5901951 # DTB write hits
-system.cpu0.dtb.write_misses 9434 # DTB write misses
-system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits 25723416 # DTB read hits
+system.cpu0.dtb.read_misses 39440 # DTB read misses
+system.cpu0.dtb.write_hits 6006462 # DTB write hits
+system.cpu0.dtb.write_misses 9528 # DTB write misses
+system.cpu0.dtb.flush_tlb 258 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 5623 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1361 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 276 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid 791 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 5597 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1333 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 268 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 633 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 26081493 # DTB read accesses
-system.cpu0.dtb.write_accesses 5911385 # DTB write accesses
+system.cpu0.dtb.perms_faults 680 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 25762856 # DTB read accesses
+system.cpu0.dtb.write_accesses 6015990 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 31942889 # DTB hits
-system.cpu0.dtb.misses 49989 # DTB misses
-system.cpu0.dtb.accesses 31992878 # DTB accesses
-system.cpu0.itb.inst_hits 6096045 # ITB inst hits
-system.cpu0.itb.inst_misses 7428 # ITB inst misses
+system.cpu0.dtb.hits 31729878 # DTB hits
+system.cpu0.dtb.misses 48968 # DTB misses
+system.cpu0.dtb.accesses 31778846 # DTB accesses
+system.cpu0.itb.inst_hits 6261683 # ITB inst hits
+system.cpu0.itb.inst_misses 7235 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb 258 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_tlb_mva_asid 791 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1569 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1762 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 6103473 # ITB inst accesses
-system.cpu0.itb.hits 6096045 # DTB hits
-system.cpu0.itb.misses 7428 # DTB misses
-system.cpu0.itb.accesses 6103473 # DTB accesses
-system.cpu0.numCycles 239139269 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 6268918 # ITB inst accesses
+system.cpu0.itb.hits 6261683 # DTB hits
+system.cpu0.itb.misses 7235 # DTB misses
+system.cpu0.itb.accesses 6268918 # DTB accesses
+system.cpu0.numCycles 237920120 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 15469651 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 47735703 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 7600384 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 4770839 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 10588915 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 2554228 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 92050 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles 48266741 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 1619 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles 2012 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles 51922 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 1409369 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 188 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 6094028 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 397204 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 3100 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 77649364 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.760813 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.117939 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 15748746 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 49352173 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 7472736 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 4735406 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 10833707 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 2792544 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 84623 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 47712542 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 1287 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles 1922 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles 50902 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 1299242 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 340 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 6259599 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 422561 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 2976 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 77655749 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.785029 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.152550 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 67068023 86.37% 86.37% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 685973 0.88% 87.26% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 883508 1.14% 88.39% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 1225779 1.58% 89.97% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 1145464 1.48% 91.45% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 573659 0.74% 92.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 1320882 1.70% 93.89% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 397746 0.51% 94.40% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 4348330 5.60% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 66829888 86.06% 86.06% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 668416 0.86% 86.92% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 858180 1.11% 88.03% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 1304413 1.68% 89.70% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 1126910 1.45% 91.16% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 549966 0.71% 91.86% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 1380247 1.78% 93.64% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 376750 0.49% 94.13% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4560979 5.87% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 77649364 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.031782 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.199615 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 16523555 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 49304070 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 9588345 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 552618 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1678659 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 1021998 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 90748 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 56218321 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 303479 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1678659 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 17458336 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 19025484 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 27018348 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 9133613 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 3332888 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 53403158 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 13481 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 625557 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 2163090 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents 470 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 55533202 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 243132036 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 243084049 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 47987 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 40330710 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 15202492 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 427890 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 379964 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 6776397 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 10330089 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 6786263 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1056196 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1308824 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 49548242 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1040790 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 63116713 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 95333 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 10484602 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 26435485 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 265976 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 77649364 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.812843 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.518782 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 77655749 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.031409 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.207432 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 16823690 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 48684179 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 9802416 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 509733 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1833567 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 1006000 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 91487 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 57560969 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 307020 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1833567 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 17765952 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 19652864 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 25831801 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 9294758 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 3274685 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 54590229 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 7255 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 552363 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 2204905 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents 211 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 56896376 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 249980910 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 249932531 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 48379 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 39701074 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 17195302 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 410578 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 363043 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 6638624 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 10379903 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 6907552 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1064074 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1362159 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 50052762 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 969661 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 62837234 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 92382 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 11367794 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 29332821 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 250599 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 77655749 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.809177 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.518047 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 54835526 70.62% 70.62% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 7206411 9.28% 79.90% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 3684013 4.74% 84.64% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 3126457 4.03% 88.67% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 6296301 8.11% 96.78% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1390393 1.79% 98.57% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 812577 1.05% 99.62% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 231214 0.30% 99.91% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 66472 0.09% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 55074638 70.92% 70.92% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 6993608 9.01% 79.93% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 3678555 4.74% 84.66% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 3117743 4.01% 88.68% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 6240678 8.04% 96.72% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1479911 1.91% 98.62% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 787330 1.01% 99.64% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 219248 0.28% 99.92% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 64038 0.08% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 77649364 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 77655749 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 32527 0.73% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 4 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 4227565 94.61% 95.34% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 208097 4.66% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 30466 0.70% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 2 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 4143838 94.53% 95.23% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 209138 4.77% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 195790 0.31% 0.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 29888266 47.35% 47.66% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 47148 0.07% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 1209 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.74% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 26756071 42.39% 90.13% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 6228206 9.87% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 167413 0.27% 0.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 29876413 47.55% 47.81% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 48260 0.08% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 15 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 946 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.89% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 26437550 42.07% 89.96% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 6306621 10.04% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 63116713 # Type of FU issued
-system.cpu0.iq.rate 0.263933 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 4468193 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.070793 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 208483702 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 61082486 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 44086612 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 12401 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 6581 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 5541 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 67382548 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 6568 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 320496 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 62837234 # Type of FU issued
+system.cpu0.iq.rate 0.264111 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 4383444 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.069759 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 207842642 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 62399132 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 43895220 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 12180 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 6627 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 5522 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 67046851 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 6414 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 320881 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 2269255 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 3561 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 15997 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 887357 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 2431860 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 3521 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 16133 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 922699 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 17163539 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 367436 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 16864632 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 486760 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1678659 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 14252559 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 235358 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 50705856 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 106082 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 10330089 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 6786263 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 740769 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 57048 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 3493 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 15997 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 185463 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 146727 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 332190 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 61942896 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 26397875 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 1173817 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1833567 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 14994749 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 240124 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 51146104 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 107104 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 10379903 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 6907552 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 682007 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 55746 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 3189 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 16133 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 183360 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 147814 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 331174 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 61530066 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 26055329 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 1307168 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 116824 # number of nop insts executed
-system.cpu0.iew.exec_refs 32569629 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 6012851 # Number of branches executed
-system.cpu0.iew.exec_stores 6171754 # Number of stores executed
-system.cpu0.iew.exec_rate 0.259024 # Inst execution rate
-system.cpu0.iew.wb_sent 61414090 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 44092153 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 24268667 # num instructions producing a value
-system.cpu0.iew.wb_consumers 44593954 # num instructions consuming a value
+system.cpu0.iew.exec_nop 123681 # number of nop insts executed
+system.cpu0.iew.exec_refs 32305514 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 5821167 # Number of branches executed
+system.cpu0.iew.exec_stores 6250185 # Number of stores executed
+system.cpu0.iew.exec_rate 0.258616 # Inst execution rate
+system.cpu0.iew.wb_sent 60920832 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 43900742 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 23943541 # num instructions producing a value
+system.cpu0.iew.wb_consumers 43567103 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.184379 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.544214 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.184519 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.549578 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 10328850 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 774814 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 289634 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 75970705 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.524893 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.506232 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 11253313 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 719062 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 289317 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 75822182 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.520093 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.499421 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 61754720 81.29% 81.29% # Number of insts commited each cycle
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system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu0.committedOps 39797141 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 31137553 # Number of Instructions Simulated
-system.cpu0.cpi 7.680092 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 7.680092 # CPI: Total CPI of All Threads
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+system.cpu0.dcache.overall_mshr_miss_latency::total 16018672592 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 90317850501 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 92017839000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182335689501 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 18608772616 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 14303930851 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 32912703467 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 156000 # number of LoadLockedReq MSHR uncacheable cycles
+system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 156000 # number of LoadLockedReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 96000 # number of StoreCondReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 96000 # number of StoreCondReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 108926623117 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 106321769851 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215248392968 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024709 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028567 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026587 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024933 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023757 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024356 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.051475 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043710 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047379 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000043 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000038 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024801 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026572 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.025666 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.024801 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026572 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.025666 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13896.184228 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13279.234055 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13573.459198 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43991.095531 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42494.536818 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43275.068377 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12463.001758 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11481.453718 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11985.354775 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13400 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12090.909091 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20823.372030 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22427.821552 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21585.947400 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20823.372030 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22427.821552 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21585.947400 # average overall mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 13400 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26341.010256 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24116.618773 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25216.368057 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26341.010256 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24116.618773 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25216.368057 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 7054454 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 5657096 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 345347 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 4549622 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 3820237 # Number of BTB hits
+system.cpu1.branchPred.lookups 7176614 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 5748558 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 346164 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 4712171 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 3815419 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 83.968229 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 674890 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 35092 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 80.969451 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 703194 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 35756 # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 25326740 # DTB read hits
-system.cpu1.dtb.read_misses 36422 # DTB read misses
-system.cpu1.dtb.write_hits 5812086 # DTB write hits
-system.cpu1.dtb.write_misses 9253 # DTB write misses
-system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits 25652921 # DTB read hits
+system.cpu1.dtb.read_misses 36442 # DTB read misses
+system.cpu1.dtb.write_hits 5708219 # DTB write hits
+system.cpu1.dtb.write_misses 9483 # DTB write misses
+system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 5525 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 1356 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 233 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid 648 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 5550 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 1291 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 249 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 644 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 25363162 # DTB read accesses
-system.cpu1.dtb.write_accesses 5821339 # DTB write accesses
+system.cpu1.dtb.perms_faults 574 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 25689363 # DTB read accesses
+system.cpu1.dtb.write_accesses 5717702 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 31138826 # DTB hits
-system.cpu1.dtb.misses 45675 # DTB misses
-system.cpu1.dtb.accesses 31184501 # DTB accesses
-system.cpu1.itb.inst_hits 6017589 # ITB inst hits
-system.cpu1.itb.inst_misses 6780 # ITB inst misses
+system.cpu1.dtb.hits 31361140 # DTB hits
+system.cpu1.dtb.misses 45925 # DTB misses
+system.cpu1.dtb.accesses 31407065 # DTB accesses
+system.cpu1.itb.inst_hits 5722854 # ITB inst hits
+system.cpu1.itb.inst_misses 6790 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb 255 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_tlb_mva_asid 648 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 2604 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1493 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1206 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 6024369 # ITB inst accesses
-system.cpu1.itb.hits 6017589 # DTB hits
-system.cpu1.itb.misses 6780 # DTB misses
-system.cpu1.itb.accesses 6024369 # DTB accesses
-system.cpu1.numCycles 234207757 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 5729644 # ITB inst accesses
+system.cpu1.itb.hits 5722854 # DTB hits
+system.cpu1.itb.misses 6790 # DTB misses
+system.cpu1.itb.accesses 5729644 # DTB accesses
+system.cpu1.numCycles 238719781 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 15218240 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 46698589 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 7054454 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 4495127 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 10302624 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 2620130 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 82175 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles 46347162 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 1067 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles 2022 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles 43841 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 1251673 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 166 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 6015552 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 445431 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 2871 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 75042047 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.773320 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.138232 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 14663434 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 45610232 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 7176614 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 4518613 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 10115214 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 2414166 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 79241 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 48437095 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 1565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles 1874 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles 41135 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 1402245 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 183 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 5721051 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 343472 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 3001 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 76398004 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.741963 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.097795 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 64747187 86.28% 86.28% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 625900 0.83% 87.12% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 833929 1.11% 88.23% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 1208466 1.61% 89.84% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1046555 1.39% 91.23% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 538335 0.72% 91.95% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1373859 1.83% 93.78% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 351234 0.47% 94.25% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 4316582 5.75% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 66290194 86.77% 86.77% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 639384 0.84% 87.61% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 858446 1.12% 88.73% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 1141205 1.49% 90.22% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1054322 1.38% 91.60% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 565766 0.74% 92.34% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1279029 1.67% 94.02% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 372986 0.49% 94.51% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 4196672 5.49% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 75042047 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.030120 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.199390 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 16229024 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 47299345 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 9347740 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 453958 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 1709750 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 948283 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 85990 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 54953007 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 286020 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 1709750 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 17168291 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 18529773 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 25747808 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 8785346 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 3098929 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 51771461 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 7122 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 486511 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 2115721 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents 96 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 53850166 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 237651325 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 237608915 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 42410 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 38062786 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 15787379 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 405266 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 358955 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 6248671 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 9866186 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 6689314 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 887473 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1140418 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 47717114 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 944883 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 60871845 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 81909 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 10575332 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 28005773 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 237169 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 75042047 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.811170 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.521401 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 76398004 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.030063 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.191062 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 15662136 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 49485106 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 9174118 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 502006 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 1572389 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 964164 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 86078 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 53732667 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 284993 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 1572389 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 16517156 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 19371694 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 27019391 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 8745759 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 3169437 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 51316953 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 13347 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 558580 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 2084092 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents 533 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 53384018 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 234291448 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 234248948 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 42500 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 38701877 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 14682140 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 422621 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 375998 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 6399704 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 9755366 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 6540913 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 899316 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1131463 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 47221133 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1016692 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 61223636 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 83704 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 9695690 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 24360360 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 252773 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 76398004 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.801377 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.509980 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 53284770 71.01% 71.01% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 6662382 8.88% 79.88% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 3536622 4.71% 84.60% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 2873956 3.83% 88.43% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 6247532 8.33% 96.75% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1425164 1.90% 98.65% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 742478 0.99% 99.64% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 209609 0.28% 99.92% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 59534 0.08% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 54279894 71.05% 71.05% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 6964982 9.12% 80.17% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 3572105 4.68% 84.84% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 2997144 3.92% 88.76% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 6191464 8.10% 96.87% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1336331 1.75% 98.62% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 781274 1.02% 99.64% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 210623 0.28% 99.92% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 64187 0.08% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 75042047 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 76398004 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 26737 0.61% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 1 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 4146600 94.82% 95.43% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 199958 4.57% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 28625 0.64% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 4232850 94.77% 95.41% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 204916 4.59% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 167876 0.28% 0.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 28487291 46.80% 47.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 46424 0.08% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 902 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.15% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 26063934 42.82% 89.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 6105398 10.03% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 196253 0.32% 0.32% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 28636645 46.77% 47.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 45275 0.07% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 1166 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.17% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 26314487 42.98% 90.15% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 6029771 9.85% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 60871845 # Type of FU issued
-system.cpu1.iq.rate 0.259905 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 4373296 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.071844 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 201275709 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 59245662 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 41829457 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 10720 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 5895 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 4750 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 65071600 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 5665 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 304013 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 61223636 # Type of FU issued
+system.cpu1.iq.rate 0.256467 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 4466394 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.072952 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 203430011 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 57942058 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 42278659 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 11099 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 5883 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 4799 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 65487820 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 5957 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 306320 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 2271620 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 3204 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 14692 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 855526 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2045827 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 3210 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 14938 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 792022 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 16940305 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 458975 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 17238980 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 391927 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 1709750 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 13959970 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 234377 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 48767354 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 97921 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 9866186 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 6689314 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 671038 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 52079 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 3815 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 14692 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 167743 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 133124 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 300867 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 59498020 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 25657253 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 1373825 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 1572389 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 14646185 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 228906 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 48337037 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 102627 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 9755366 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 6540913 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 729665 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 50173 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 3845 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 14938 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 169845 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 132330 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 302175 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 60177661 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 26008514 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1045975 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 105357 # number of nop insts executed
-system.cpu1.iew.exec_refs 31711723 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 5535621 # Number of branches executed
-system.cpu1.iew.exec_stores 6054470 # Number of stores executed
-system.cpu1.iew.exec_rate 0.254039 # Inst execution rate
-system.cpu1.iew.wb_sent 58916799 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 41834207 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 22806182 # num instructions producing a value
-system.cpu1.iew.wb_consumers 41818913 # num instructions consuming a value
+system.cpu1.iew.exec_nop 99212 # number of nop insts executed
+system.cpu1.iew.exec_refs 31985233 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 5705434 # Number of branches executed
+system.cpu1.iew.exec_stores 5976719 # Number of stores executed
+system.cpu1.iew.exec_rate 0.252085 # Inst execution rate
+system.cpu1.iew.wb_sent 59667880 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 42283458 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 23216135 # num instructions producing a value
+system.cpu1.iew.wb_consumers 42895102 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.178620 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.545356 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.177126 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.541230 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 10492813 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 707714 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 260708 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 73332297 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.516509 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.496867 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 9567940 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 763919 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 261423 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 74825615 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.512228 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.487191 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 59797837 81.54% 81.54% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 6663272 9.09% 90.63% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 1912982 2.61% 93.24% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1016048 1.39% 94.62% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 959954 1.31% 95.93% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 526368 0.72% 96.65% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 702800 0.96% 97.61% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 373366 0.51% 98.12% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1379670 1.88% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 61056295 81.60% 81.60% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 6800068 9.09% 90.69% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 1929591 2.58% 93.26% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1057405 1.41% 94.68% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1013455 1.35% 96.03% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 520209 0.70% 96.73% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 685711 0.92% 97.64% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 375889 0.50% 98.15% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1386992 1.85% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 73332297 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 29243924 # Number of instructions committed
-system.cpu1.commit.committedOps 37876758 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 74825615 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 29838157 # Number of instructions committed
+system.cpu1.commit.committedOps 38327755 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 13428354 # Number of memory references committed
-system.cpu1.commit.loads 7594566 # Number of loads committed
-system.cpu1.commit.membars 191899 # Number of memory barriers committed
-system.cpu1.commit.branches 4767702 # Number of branches committed
-system.cpu1.commit.fp_insts 4715 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 33624060 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 478655 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 1379670 # number cycles where commit BW limit reached
+system.cpu1.commit.refs 13458430 # Number of memory references committed
+system.cpu1.commit.loads 7709539 # Number of loads committed
+system.cpu1.commit.membars 201879 # Number of memory barriers committed
+system.cpu1.commit.branches 4970440 # Number of branches committed
+system.cpu1.commit.fp_insts 4743 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 33879408 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 500692 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 1386992 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 119446868 # The number of ROB reads
-system.cpu1.rob.rob_writes 98500710 # The number of ROB writes
-system.cpu1.timesIdled 873517 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 159165710 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 2285782593 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 29172873 # Number of Instructions Simulated
-system.cpu1.committedOps 37805707 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 29172873 # Number of Instructions Simulated
-system.cpu1.cpi 8.028272 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 8.028272 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.124560 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.124560 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 269572472 # number of integer regfile reads
-system.cpu1.int_regfile_writes 42951903 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 22113 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 19714 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 14815337 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 403940 # number of misc regfile writes
+system.cpu1.rob.rob_reads 120414089 # The number of ROB reads
+system.cpu1.rob.rob_writes 97409741 # The number of ROB writes
+system.cpu1.timesIdled 885352 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 162321777 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 2286481516 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 29771274 # Number of Instructions Simulated
+system.cpu1.committedOps 38260872 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 29771274 # Number of Instructions Simulated
+system.cpu1.cpi 8.018460 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 8.018460 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.124712 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.124712 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 271859015 # number of integer regfile reads
+system.cpu1.int_regfile_writes 43450852 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 22226 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 19958 # number of floating regfile writes
+system.cpu1.misc_regfile_reads 14811721 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 428358 # number of misc regfile writes
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192618547941 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1192618547941 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192618547941 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1192618547941 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1456504103755 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1456504103755 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1456504103755 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1456504103755 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 83057 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 83064 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- Begin Simulation Statistics ----------
-sim_seconds 2.610012 # Number of seconds simulated
-sim_ticks 2610011895000 # Number of ticks simulated
-final_tick 2610011895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.627154 # Number of seconds simulated
+sim_ticks 2627154206500 # Number of ticks simulated
+final_tick 2627154206500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 531747 # Simulator instruction rate (inst/s)
-host_op_rate 676644 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 23052454652 # Simulator tick rate (ticks/s)
-host_mem_usage 397728 # Number of bytes of host memory used
-host_seconds 113.22 # Real time elapsed on the host
-sim_insts 60204721 # Number of instructions simulated
-sim_ops 76610045 # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
+host_inst_rate 361221 # Simulator instruction rate (inst/s)
+host_op_rate 459651 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 15759970234 # Simulator tick rate (ticks/s)
+host_mem_usage 398468 # Number of bytes of host memory used
+host_seconds 166.70 # Real time elapsed on the host
+sim_insts 60214798 # Number of instructions simulated
+sim_ops 76622863 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 356960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4558796 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 347904 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4486256 # Number of bytes read from this memory
-system.physmem.bytes_read::total 132433500 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 356960 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 347904 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 704864 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3672640 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1510336 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 1505932 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6688908 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu0.inst 292384 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4914704 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 411968 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 4151472 # Number of bytes read from this memory
+system.physmem.bytes_read::total 134026976 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 292384 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 411968 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 704352 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3695296 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 1534856 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 1481296 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6711448 # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 11780 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 71264 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 5436 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 70124 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15494031 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 57385 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 377584 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 376483 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 811452 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47004917 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 25 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu0.inst 10771 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 76826 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 6437 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 64893 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15690962 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 57739 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 383714 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 370324 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 811777 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47296902 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 136766 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1746657 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 133296 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1718864 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50740573 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 136766 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 133296 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 270062 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1407135 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 578670 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 576983 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2562788 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1407135 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47004917 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 111293 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1870733 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 156812 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 1580216 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51016029 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 111293 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 156812 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 268105 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1406578 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 584228 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 563841 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2554646 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1406578 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47296902 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 136766 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 2325327 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 133296 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 2295847 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53303362 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15494031 # Total number of read requests seen
-system.physmem.writeReqs 811452 # Total number of write requests seen
-system.physmem.cpureqs 213827 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 991617984 # Total number of bytes read from memory
-system.physmem.bytesWritten 51932928 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 132433500 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6688908 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 27 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4514 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 974843 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 967897 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 967762 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 968563 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 968385 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 967634 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 967724 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 968241 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 968097 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 967669 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 967710 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 968022 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 968146 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 967643 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 967509 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 968159 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50752 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50352 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50308 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 50998 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 50782 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 50138 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50199 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 50736 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51142 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 50724 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51047 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51142 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 50663 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 50585 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51197 # Track writes on a per bank basis
+system.physmem.bw_total::cpu0.inst 111293 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 2454961 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 156812 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 2144057 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53570675 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15690962 # Total number of read requests seen
+system.physmem.writeReqs 811777 # Total number of write requests seen
+system.physmem.cpureqs 214505 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1004221568 # Total number of bytes read from memory
+system.physmem.bytesWritten 51953728 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 134026976 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6711448 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 26 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4516 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 980549 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 980310 # Track reads on a per bank basis
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+system.physmem.perBankRdReqs::15 980129 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 49310 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2610007487000 # Total gap between requests
+system.physmem.totGap 2627149788000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
-system.physmem.readPktSize::2 6679 # Categorize read packet sizes
-system.physmem.readPktSize::3 15335424 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 151928 # Categorize read packet sizes
+system.physmem.readPktSize::6 152250 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
-system.physmem.writePktSize::2 754067 # Categorize write packet sizes
+system.physmem.writePktSize::2 754038 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 57385 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 1116599 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::16 50 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 57739 # Categorize write packet sizes
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 338127200750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 432998808250 # Sum of mem lat for all requests
-system.physmem.totBusLat 77470020000 # Total cycles spent in databus access
-system.physmem.totBankLat 17401587500 # Total cycles spent in bank access
-system.physmem.avgQLat 21823.10 # Average queueing delay per request
-system.physmem.avgBankLat 1123.12 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 38107 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 27715.971974 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 2557.155392 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 33302.761922 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-127 5424 14.23% 14.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-191 3316 8.70% 22.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-255 2198 5.77% 28.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-319 1686 4.42% 33.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-383 1157 3.04% 36.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-447 1029 2.70% 38.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-511 812 2.13% 41.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-575 726 1.91% 42.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-639 578 1.52% 44.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-703 463 1.21% 45.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-767 465 1.22% 46.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-831 413 1.08% 47.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-895 261 0.68% 48.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-959 269 0.71% 49.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-1023 229 0.60% 49.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1087 239 0.63% 50.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1151 133 0.35% 50.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1215 136 0.36% 51.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1279 99 0.26% 51.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1343 99 0.26% 51.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1407 86 0.23% 52.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1471 150 0.39% 52.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1535 761 2.00% 54.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1599 211 0.55% 54.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1663 139 0.36% 55.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1727 123 0.32% 55.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1791 64 0.17% 55.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1855 78 0.20% 56.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1919 56 0.15% 56.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1983 58 0.15% 56.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-2047 48 0.13% 56.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2111 69 0.18% 56.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2175 34 0.09% 56.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2239 27 0.07% 56.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2303 25 0.07% 56.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2367 25 0.07% 56.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2431 9 0.02% 56.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2495 23 0.06% 56.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2559 23 0.06% 57.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2623 14 0.04% 57.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2687 10 0.03% 57.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2751 11 0.03% 57.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2815 14 0.04% 57.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2879 8 0.02% 57.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2943 10 0.03% 57.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-3007 9 0.02% 57.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3071 8 0.02% 57.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3135 19 0.05% 57.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3199 5 0.01% 57.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3263 6 0.02% 57.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3327 10 0.03% 57.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3391 10 0.03% 57.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3455 4 0.01% 57.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3519 8 0.02% 57.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520-3583 4 0.01% 57.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3647 7 0.02% 57.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648-3711 11 0.03% 57.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3775 11 0.03% 57.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776-3839 9 0.02% 57.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840-3903 3 0.01% 57.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904-3967 6 0.02% 57.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3968-4031 10 0.03% 57.60% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::4160-4223 2 0.01% 57.71% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::4288-4351 6 0.02% 57.73% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::4672-4735 2 0.01% 57.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4736-4799 1 0.00% 57.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4800-4863 5 0.01% 57.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4864-4927 3 0.01% 57.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4928-4991 1 0.00% 57.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4992-5055 2 0.01% 57.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5056-5119 3 0.01% 57.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5120-5183 7 0.02% 57.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5248-5311 5 0.01% 57.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5312-5375 2 0.01% 57.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5376-5439 4 0.01% 57.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5440-5503 2 0.01% 57.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5504-5567 4 0.01% 57.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5568-5631 2 0.01% 57.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5632-5695 3 0.01% 57.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5696-5759 2 0.01% 57.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5824-5887 1 0.00% 57.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5888-5951 2 0.01% 57.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6016-6079 1 0.00% 57.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6080-6143 1 0.00% 57.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6144-6207 23 0.06% 57.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6208-6271 4 0.01% 58.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6272-6335 3 0.01% 58.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6464-6527 2 0.01% 58.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6528-6591 2 0.01% 58.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6656-6719 2 0.01% 58.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6720-6783 1 0.00% 58.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6784-6847 18 0.05% 58.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6912-6975 1 0.00% 58.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6976-7039 1 0.00% 58.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7168-7231 5 0.01% 58.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7232-7295 1 0.00% 58.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7360-7423 3 0.01% 58.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7424-7487 4 0.01% 58.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7488-7551 2 0.01% 58.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7552-7615 5 0.01% 58.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7616-7679 4 0.01% 58.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7680-7743 6 0.02% 58.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7744-7807 6 0.02% 58.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7808-7871 4 0.01% 58.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7872-7935 6 0.02% 58.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7936-7999 2 0.01% 58.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8000-8063 3 0.01% 58.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8064-8127 6 0.02% 58.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8128-8191 5 0.01% 58.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8255 310 0.81% 59.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::9216-9279 1 0.00% 59.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::9408-9471 1 0.00% 59.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::9792-9855 1 0.00% 59.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::9984-10047 1 0.00% 59.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::10240-10303 17 0.04% 59.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::10496-10559 1 0.00% 59.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::11264-11327 2 0.01% 59.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::12032-12095 2 0.01% 59.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::12288-12351 1 0.00% 59.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::13056-13119 1 0.00% 59.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::13312-13375 2 0.01% 59.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::14080-14143 1 0.00% 59.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::14592-14655 1 0.00% 59.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::14848-14911 1 0.00% 59.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::17408-17471 2 0.01% 59.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::18688-18751 2 0.01% 59.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::19712-19775 1 0.00% 59.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::19968-20031 1 0.00% 59.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::20736-20799 1 0.00% 59.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::21504-21567 3 0.01% 59.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::22016-22079 1 0.00% 59.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::22784-22847 1 0.00% 59.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::23552-23615 1 0.00% 59.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::24576-24639 3 0.01% 59.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::24832-24895 1 0.00% 59.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::25600-25663 1 0.00% 59.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::25920-25983 1 0.00% 59.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::26624-26687 1 0.00% 59.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::27392-27455 2 0.01% 59.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::28416-28479 1 0.00% 59.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::28672-28735 3 0.01% 59.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::28928-28991 1 0.00% 59.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::29952-30015 1 0.00% 59.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::30208-30271 1 0.00% 59.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::30464-30527 1 0.00% 59.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::31040-31103 2 0.01% 59.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::32000-32063 1 0.00% 59.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::32512-32575 1 0.00% 59.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::33024-33087 1 0.00% 59.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::33472-33535 2 0.01% 59.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::33536-33599 19 0.05% 59.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::35328-35391 1 0.00% 59.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::36864-36927 2 0.01% 59.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::38144-38207 1 0.00% 59.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::40960-41023 1 0.00% 59.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::41984-42047 1 0.00% 59.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::43008-43071 1 0.00% 59.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::44032-44095 2 0.01% 59.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48128-48191 1 0.00% 59.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::48384-48447 1 0.00% 59.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::49152-49215 1 0.00% 59.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::50688-50751 1 0.00% 59.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::51456-51519 1 0.00% 59.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::52480-52543 1 0.00% 59.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::54272-54335 1 0.00% 59.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::56128-56191 1 0.00% 59.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::58624-58687 1 0.00% 59.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::60032-60095 1 0.00% 59.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::60672-60735 1 0.00% 59.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::63488-63551 1 0.00% 59.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::65536-65599 15122 39.68% 99.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::71808-71871 1 0.00% 99.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::82176-82239 1 0.00% 99.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::88064-88127 1 0.00% 99.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::99712-99775 1 0.00% 99.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::129856-129919 1 0.00% 99.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::130176-130239 1 0.00% 99.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::131072-131135 356 0.93% 99.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::136576-136639 1 0.00% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 38107 # Bytes accessed per row activation
+system.physmem.totQLat 304254816750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 398977768000 # Sum of mem lat for all requests
+system.physmem.totBusLat 78454680000 # Total cycles spent in databus access
+system.physmem.totBankLat 16268271250 # Total cycles spent in bank access
+system.physmem.avgQLat 19390.48 # Average queueing delay per request
+system.physmem.avgBankLat 1036.79 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 27946.22 # Average memory access latency
-system.physmem.avgRdBW 379.93 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 19.90 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 50.74 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 2.56 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 25427.28 # Average memory access latency
+system.physmem.avgRdBW 382.25 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 19.78 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 51.02 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 2.55 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 3.12 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.17 # Average read queue length over time
-system.physmem.avgWrQLen 1.25 # Average write queue length over time
-system.physmem.readRowHits 15419474 # Number of row buffer hits during reads
-system.physmem.writeRowHits 794097 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 97.86 # Row buffer hit rate for writes
-system.physmem.avgGap 160069.31 # Average gap between requests
-system.l2c.replacements 61815 # number of replacements
-system.l2c.tagsinuse 50922.556971 # Cycle average of tags in use
-system.l2c.total_refs 1697645 # Total number of references to valid blocks.
-system.l2c.sampled_refs 127200 # Sample count of references to valid blocks.
-system.l2c.avg_refs 13.346266 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 2558113998500 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 37911.407860 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.dtb.walker 0.000184 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.itb.walker 0.000643 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 3494.638706 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 3026.772488 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 3500.625095 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 2989.111995 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.578482 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
+system.physmem.busUtil 3.14 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.15 # Average read queue length over time
+system.physmem.avgWrQLen 1.26 # Average write queue length over time
+system.physmem.readRowHits 15666209 # Number of row buffer hits during reads
+system.physmem.writeRowHits 798397 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 98.35 # Row buffer hit rate for writes
+system.physmem.avgGap 159194.77 # Average gap between requests
+system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 54483503 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 16743616 # Transaction distribution
+system.membus.trans_dist::ReadResp 16743616 # Transaction distribution
+system.membus.trans_dist::WriteReq 763392 # Transaction distribution
+system.membus.trans_dist::WriteResp 763392 # Transaction distribution
+system.membus.trans_dist::Writeback 57739 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution
+system.membus.trans_dist::ReadExReq 131423 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131423 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382990 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892707 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 4279569 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.bridge.slave 2382990 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port 32956771 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 35343633 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390397 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16482168 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::total 18880309 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.bridge.slave 2390397 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.physmem.port 140738424 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 143136565 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 143136565 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 1225633000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 18165198500 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.7 # Layer utilization (%)
+system.membus.reqLayer3.occupancy 3755000 # Layer occupancy (ticks)
+system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4987617364 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.membus.respLayer2.occupancy 35065696500 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
+system.l2c.replacements 62136 # number of replacements
+system.l2c.tagsinuse 51567.664706 # Cycle average of tags in use
+system.l2c.total_refs 1698783 # Total number of references to valid blocks.
+system.l2c.sampled_refs 127519 # Sample count of references to valid blocks.
+system.l2c.avg_refs 13.321803 # Average number of references to valid blocks.
+system.l2c.warmup_cycle 2572304327500 # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks 38171.110682 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.itb.walker 0.000688 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 2904.028598 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 3024.624697 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker 0.000186 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 4116.712903 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 3351.186952 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.582445 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.053324 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.046185 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.053415 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.045610 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.777017 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker 10043 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 3654 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 407563 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 186718 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 9399 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 3346 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 436384 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 183760 # number of ReadReq hits
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-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40958.639427 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33836.052948 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 39945.214496 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33766.513716 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 34259.809163 # average overall mshr miss latency
+system.l2c.overall_mshr_misses::cpu0.inst 4155 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data 77570 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 6437 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 65720 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 153885 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 97500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 233588500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data 301025250 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 76250 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 374548500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 291235750 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 1200571750 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13881388 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14932493 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 28813881 # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3735280780 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3118346355 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 6853627135 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 97500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst 233588500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data 4036306030 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 374548500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 3409582105 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 8054198885 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 97500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst 233588500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data 4036306030 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 76250 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 374548500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 3409582105 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 8054198885 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 339371500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 83784654250 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82893132500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 167017158250 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 8360925069 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8338711051 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 16699636120 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 339371500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 92145579319 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 91231843551 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 183716794370 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000556 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009810 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.028784 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014914 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025064 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.016492 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.990014 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992027 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.991056 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.560527 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.512527 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.537517 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000556 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009810 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.246971 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014914 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.209163 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.101885 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000556 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009810 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.246971 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014914 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.209163 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.101885 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56218.652226 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 56466.938661 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58186.810626 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 59423.740053 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 57644.968070 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.669792 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.347102 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 51707.260344 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51272.568687 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 51508.568707 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56218.652226 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 52034.369344 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58186.810626 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51880.433734 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 52339.077136 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56218.652226 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 52034.369344 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58186.810626 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51880.433734 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 52339.077136 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
-system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
-system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
-system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.toL2Bus.throughput 52848676 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 2471696 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2471696 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 763392 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 763392 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 596576 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 2907 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 2907 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 247542 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 247542 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1725238 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5754024 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 19969 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 50318 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count 7549549 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 54758516 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 83805889 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 28400 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 79212 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size 138672017 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 138672017 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 169604 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 4809056500 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 3862257000 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 4394586000 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 12869000 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 30515000 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.throughput 48206783 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 16715360 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16715360 # Transaction distribution
+system.iobus.trans_dist::WriteReq 8167 # Transaction distribution
+system.iobus.trans_dist::WriteResp 8167 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2382990 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 33447054 # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 2390397 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 126646653 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 126646653 # Total data (bytes)
+system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
+system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
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+system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
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+system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
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+system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
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+system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
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+system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 2374823000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.iobus.respLayer1.occupancy 31064064000 # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization 1.2 # Layer utilization (%)
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 7403435 # DTB read hits
-system.cpu0.dtb.read_misses 6873 # DTB read misses
-system.cpu0.dtb.write_hits 5501198 # DTB write hits
-system.cpu0.dtb.write_misses 1842 # DTB write misses
-system.cpu0.dtb.flush_tlb 1277 # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits 7331530 # DTB read hits
+system.cpu0.dtb.read_misses 6749 # DTB read misses
+system.cpu0.dtb.write_hits 5629181 # DTB write hits
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system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
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+system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 6355 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 225 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 7410308 # DTB read accesses
-system.cpu0.dtb.write_accesses 5503040 # DTB write accesses
+system.cpu0.dtb.perms_faults 224 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 7338279 # DTB read accesses
+system.cpu0.dtb.write_accesses 5631019 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 12904633 # DTB hits
-system.cpu0.dtb.misses 8715 # DTB misses
-system.cpu0.dtb.accesses 12913348 # DTB accesses
-system.cpu0.itb.inst_hits 30303054 # ITB inst hits
-system.cpu0.itb.inst_misses 3598 # ITB inst misses
+system.cpu0.dtb.hits 12960711 # DTB hits
+system.cpu0.dtb.misses 8587 # DTB misses
+system.cpu0.dtb.accesses 12969298 # DTB accesses
+system.cpu0.itb.inst_hits 29905877 # ITB inst hits
+system.cpu0.itb.inst_misses 3541 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 1277 # Number of times complete TLB was flushed
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system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2696 # Number of entries that have been flushed from TLB
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+system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 2713 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 30306652 # ITB inst accesses
-system.cpu0.itb.hits 30303054 # DTB hits
-system.cpu0.itb.misses 3598 # DTB misses
-system.cpu0.itb.accesses 30306652 # DTB accesses
-system.cpu0.numCycles 2668342955 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 29909418 # ITB inst accesses
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+system.cpu0.itb.accesses 29909418 # DTB accesses
+system.cpu0.numCycles 2625614654 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 29632666 # Number of instructions committed
-system.cpu0.committedOps 37682860 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 33888276 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 5192 # Number of float alu accesses
-system.cpu0.num_func_calls 1024744 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 3926833 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 33888276 # number of integer instructions
-system.cpu0.num_fp_insts 5192 # number of float instructions
-system.cpu0.num_int_register_reads 194247325 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 36521977 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 3842 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 1352 # number of times the floating registers were written
-system.cpu0.num_mem_refs 13487423 # number of memory refs
-system.cpu0.num_load_insts 7732203 # Number of load instructions
-system.cpu0.num_store_insts 5755220 # Number of store instructions
-system.cpu0.num_idle_cycles -6063478143.749568 # Number of idle cycles
-system.cpu0.num_busy_cycles 8731821098.749567 # Number of busy cycles
-system.cpu0.not_idle_fraction 3.272376 # Percentage of non-idle cycles
-system.cpu0.idle_fraction -2.272376 # Percentage of idle cycles
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+system.cpu0.num_fp_alu_accesses 4399 # Number of float alu accesses
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+system.cpu0.num_int_insts 33819709 # number of integer instructions
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+system.cpu0.num_int_register_writes 36222671 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 2980 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 1422 # number of times the floating registers were written
+system.cpu0.num_mem_refs 13528220 # number of memory refs
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
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-system.cpu0.icache.replacements 855673 # number of replacements
-system.cpu0.icache.tagsinuse 510.972312 # Cycle average of tags in use
-system.cpu0.icache.total_refs 60642600 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 856185 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 70.828851 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 18907162000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 150.590700 # Average occupied blocks per requestor
-system.cpu0.icache.occ_blocks::cpu1.inst 360.381612 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.294122 # Average percentage of cache occupancy
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-system.cpu0.icache.occ_percent::total 0.997993 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 29889509 # number of ReadReq hits
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-system.cpu0.icache.ReadReq_hits::total 60642600 # number of ReadReq hits
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-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013647 # miss rate for ReadReq accesses
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-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013647 # miss rate for demand accesses
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-system.cpu0.icache.overall_miss_rate::total 0.013922 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13565.961383 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13545.133743 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13555.193679 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13565.961383 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13545.133743 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13555.193679 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13565.961383 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13545.133743 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13555.193679 # average overall miss latency
+system.cpu0.kern.inst.quiesce 83030 # number of quiesce instructions executed
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+system.cpu0.icache.sampled_refs 856808 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 70.788428 # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 19951126000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst 211.269662 # Average occupied blocks per requestor
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system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7667890500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7012616000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 14680506500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7667890500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7012616000 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 14680506500 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91527278500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90544684500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182071963000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13203337000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13032051000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26235388000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104730615500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103576735500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208307351000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027115 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027305 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027212 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025436 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023544 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024492 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.047860 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044973 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046412 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026382 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025713 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.026043 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026382 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025713 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.026043 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12804.377653 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12618.131709 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12708.568272 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41235.379455 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38410.705667 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39880.049431 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11481.052275 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12456.887299 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11955.351709 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24769.008256 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22612.661591 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23689.890188 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24769.008256 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22612.661591 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23689.890188 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 7594461 # DTB read hits
-system.cpu1.dtb.read_misses 6935 # DTB read misses
-system.cpu1.dtb.write_hits 5731015 # DTB write hits
-system.cpu1.dtb.write_misses 1760 # DTB write misses
-system.cpu1.dtb.flush_tlb 1276 # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits 7669515 # DTB read hits
+system.cpu1.dtb.read_misses 7262 # DTB read misses
+system.cpu1.dtb.write_hits 5604176 # DTB write hits
+system.cpu1.dtb.write_misses 1826 # DTB write misses
+system.cpu1.dtb.flush_tlb 1246 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 6595 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 227 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 7601396 # DTB read accesses
-system.cpu1.dtb.write_accesses 5732775 # DTB write accesses
+system.cpu1.dtb.perms_faults 228 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 7676777 # DTB read accesses
+system.cpu1.dtb.write_accesses 5606002 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 13325476 # DTB hits
-system.cpu1.dtb.misses 8695 # DTB misses
-system.cpu1.dtb.accesses 13334171 # DTB accesses
-system.cpu1.itb.inst_hits 31195731 # ITB inst hits
-system.cpu1.itb.inst_misses 3619 # ITB inst misses
+system.cpu1.dtb.hits 13273691 # DTB hits
+system.cpu1.dtb.misses 9088 # DTB misses
+system.cpu1.dtb.accesses 13282779 # DTB accesses
+system.cpu1.itb.inst_hits 31603022 # ITB inst hits
+system.cpu1.itb.inst_misses 3724 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 1276 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb 1246 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 2687 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 2827 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 31199350 # ITB inst accesses
-system.cpu1.itb.hits 31195731 # DTB hits
-system.cpu1.itb.misses 3619 # DTB misses
-system.cpu1.itb.accesses 31199350 # DTB accesses
-system.cpu1.numCycles 2551680835 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 31606746 # ITB inst accesses
+system.cpu1.itb.hits 31603022 # DTB hits
+system.cpu1.itb.misses 3724 # DTB misses
+system.cpu1.itb.accesses 31606746 # DTB accesses
+system.cpu1.numCycles 2628693759 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 30572055 # Number of instructions committed
-system.cpu1.committedOps 38927185 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 34988619 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 5077 # Number of float alu accesses
-system.cpu1.num_func_calls 1115365 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 4021820 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 34988619 # number of integer instructions
-system.cpu1.num_fp_insts 5077 # number of float instructions
-system.cpu1.num_int_register_reads 200559291 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 37663256 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 3651 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 1428 # number of times the floating registers were written
-system.cpu1.num_mem_refs 13910241 # number of memory refs
-system.cpu1.num_load_insts 7929873 # Number of load instructions
-system.cpu1.num_store_insts 5980368 # Number of store instructions
-system.cpu1.num_idle_cycles 10585260303.338047 # Number of idle cycles
-system.cpu1.num_busy_cycles -8033579468.338046 # Number of busy cycles
-system.cpu1.not_idle_fraction -3.148348 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 4.148348 # Percentage of idle cycles
+system.cpu1.committedInsts 30860361 # Number of instructions committed
+system.cpu1.committedOps 39028594 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 35068610 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 5870 # Number of float alu accesses
+system.cpu1.num_func_calls 1089512 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 4048013 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 35068610 # number of integer instructions
+system.cpu1.num_fp_insts 5870 # number of float instructions
+system.cpu1.num_int_register_reads 201015882 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 37978161 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 4513 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 1358 # number of times the floating registers were written
+system.cpu1.num_mem_refs 13873832 # number of memory refs
+system.cpu1.num_load_insts 8013211 # Number of load instructions
+system.cpu1.num_store_insts 5860621 # Number of store instructions
+system.cpu1.num_idle_cycles 952679619.816103 # Number of idle cycles
+system.cpu1.num_busy_cycles 1676014139.183897 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.637584 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.362416 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.iocache.replacements 0 # number of replacements
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1195947261004 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1195947261004 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1195947261004 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1195947261004 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1482619780500 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1482619780500 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1482619780500 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1482619780500 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 5.140938 # Number of seconds simulated
-sim_ticks 5140937585000 # Number of ticks simulated
-final_tick 5140937585000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.125717 # Number of seconds simulated
+sim_ticks 5125716951000 # Number of ticks simulated
+final_tick 5125716951000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 121697 # Simulator instruction rate (inst/s)
-host_op_rate 240559 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1534230705 # Simulator tick rate (ticks/s)
-host_mem_usage 773616 # Number of bytes of host memory used
-host_seconds 3350.82 # Real time elapsed on the host
-sim_insts 407786881 # Number of instructions simulated
-sim_ops 806071515 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide 2479872 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 3712 # Number of bytes read from this memory
+host_inst_rate 203249 # Simulator instruction rate (inst/s)
+host_op_rate 401765 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2555120499 # Simulator tick rate (ticks/s)
+host_mem_usage 728844 # Number of bytes of host memory used
+host_seconds 2006.06 # Real time elapsed on the host
+sim_insts 407728401 # Number of instructions simulated
+sim_ops 805963181 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide 2441920 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1026240 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10765120 # Number of bytes read from this memory
-system.physmem.bytes_read::total 14275328 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1026240 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1026240 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9536256 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9536256 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 38748 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 58 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst 1027200 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10734912 # Number of bytes read from this memory
+system.physmem.bytes_read::total 14208320 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1027200 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1027200 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9480000 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9480000 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 38155 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 16035 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 168205 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 223052 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 149004 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 149004 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 482377 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 722 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu.inst 16050 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 167733 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 222005 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 148125 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 148125 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 476406 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 762 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 199621 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2093999 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2776795 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 199621 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 199621 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1854964 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1854964 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1854964 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 482377 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 722 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 200401 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2094324 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2771967 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 200401 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 200401 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1849497 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1849497 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1849497 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 476406 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 762 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 199621 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2093999 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4631759 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 223052 # Total number of read requests seen
-system.physmem.writeReqs 149004 # Total number of write requests seen
-system.physmem.cpureqs 373790 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 14275328 # Total number of bytes read from memory
-system.physmem.bytesWritten 9536256 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 14275328 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 9536256 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 71 # Number of read reqs serviced by write Q
+system.physmem.bw_total::cpu.inst 200401 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2094324 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4621465 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 222005 # Total number of read requests seen
+system.physmem.writeReqs 148125 # Total number of write requests seen
+system.physmem.cpureqs 371863 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 14208320 # Total number of bytes read from memory
+system.physmem.bytesWritten 9480000 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 14208320 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 9480000 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 92 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 1726 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 13636 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 12914 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 13124 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 16345 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 13470 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 13111 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 13382 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 16266 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 13519 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 13235 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 13394 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 15885 # Track reads on a per bank basis
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-system.physmem.perBankRdReqs::14 13202 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 15809 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 8837 # Track writes on a per bank basis
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-system.physmem.perBankWrReqs::4 8818 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::0 9305 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry
-system.physmem.totGap 5140937531500 # Total gap between requests
+system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry
+system.physmem.totGap 5125716897500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 223052 # Categorize read packet sizes
+system.physmem.readPktSize::6 222005 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 149004 # Categorize write packet sizes
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-system.physmem.totQLat 4794975750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 9301923250 # Sum of mem lat for all requests
-system.physmem.totBusLat 1114905000 # Total cycles spent in databus access
-system.physmem.totBankLat 3392042500 # Total cycles spent in bank access
-system.physmem.avgQLat 21503.97 # Average queueing delay per request
-system.physmem.avgBankLat 15212.25 # Average bank access latency per request
+system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 62409 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 379.447836 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 154.150732 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 1279.689060 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-67 27741 44.45% 44.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-131 9677 15.51% 59.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-195 5899 9.45% 69.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-259 3942 6.32% 75.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-323 2509 4.02% 79.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-387 2016 3.23% 82.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-451 1522 2.44% 85.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-515 1230 1.97% 87.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-579 938 1.50% 88.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-643 940 1.51% 90.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-707 553 0.89% 91.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-771 567 0.91% 92.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-835 409 0.66% 92.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-899 381 0.61% 93.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-963 350 0.56% 94.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1027 427 0.68% 94.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1091 299 0.48% 95.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1155 221 0.35% 95.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1219 157 0.25% 95.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1283 165 0.26% 96.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1347 170 0.27% 96.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1411 190 0.30% 96.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1475 458 0.73% 97.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1539 188 0.30% 97.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1603 102 0.16% 97.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1667 75 0.12% 97.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1731 65 0.10% 98.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1795 60 0.10% 98.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1859 37 0.06% 98.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1923 23 0.04% 98.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1987 21 0.03% 98.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2051 32 0.05% 98.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2115 22 0.04% 98.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2179 13 0.02% 98.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2243 10 0.02% 98.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2307 21 0.03% 98.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2371 16 0.03% 98.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2435 12 0.02% 98.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2499 13 0.02% 98.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2563 12 0.02% 98.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2627 9 0.01% 98.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2691 5 0.01% 98.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2755 7 0.01% 98.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2819 5 0.01% 98.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2883 4 0.01% 98.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2947 10 0.02% 98.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3011 4 0.01% 98.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3075 9 0.01% 98.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3139 9 0.01% 98.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3203 1 0.00% 98.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3331 6 0.01% 98.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3395 2 0.00% 98.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3459 9 0.01% 98.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520-3523 3 0.00% 98.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3587 2 0.00% 98.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648-3651 3 0.00% 98.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3715 5 0.01% 98.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776-3779 13 0.02% 98.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840-3843 3 0.00% 98.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904-3907 5 0.01% 98.71% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::4032-4035 3 0.00% 98.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4096-4099 22 0.04% 98.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4160-4163 5 0.01% 98.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4224-4227 1 0.00% 98.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4288-4291 2 0.00% 98.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4352-4355 3 0.00% 98.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4416-4419 3 0.00% 98.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4480-4483 5 0.01% 98.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4672-4675 2 0.00% 98.79% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::4992-4995 1 0.00% 98.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5056-5059 2 0.00% 98.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5120-5123 3 0.00% 98.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5184-5187 6 0.01% 98.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5248-5251 5 0.01% 98.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5376-5379 2 0.00% 98.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5440-5443 1 0.00% 98.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5760-5763 1 0.00% 98.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5888-5891 1 0.00% 98.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6016-6019 3 0.00% 98.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6080-6083 1 0.00% 98.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6144-6147 2 0.00% 98.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6208-6211 1 0.00% 98.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6400-6403 2 0.00% 98.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6464-6467 3 0.00% 98.86% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::6720-6723 7 0.01% 98.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6784-6787 4 0.01% 98.88% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::6912-6915 3 0.00% 98.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6976-6979 4 0.01% 98.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7040-7043 4 0.01% 98.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7104-7107 1 0.00% 98.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7168-7171 5 0.01% 98.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7232-7235 1 0.00% 98.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7360-7363 2 0.00% 98.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7424-7427 1 0.00% 98.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7552-7555 2 0.00% 98.92% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7872-7875 2 0.00% 98.93% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::8000-8003 1 0.00% 98.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8064-8067 2 0.00% 98.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8195 337 0.54% 99.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8320-8323 1 0.00% 99.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.48% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.48% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::9088-9091 2 0.00% 99.49% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.49% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::9600-9603 2 0.00% 99.51% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::10880-10883 1 0.00% 99.55% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::12288-12291 1 0.00% 99.56% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::12480-12483 2 0.00% 99.56% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::12992-12995 2 0.00% 99.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::13440-13443 1 0.00% 99.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::13504-13507 1 0.00% 99.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::13568-13571 2 0.00% 99.58% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::13952-13955 1 0.00% 99.58% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.59% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::14656-14659 1 0.00% 99.59% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::14912-14915 34 0.05% 99.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::14976-14979 14 0.02% 99.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15040-15043 8 0.01% 99.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15104-15107 9 0.01% 99.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15168-15171 4 0.01% 99.71% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::15296-15299 6 0.01% 99.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15360-15363 4 0.01% 99.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15424-15427 4 0.01% 99.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15488-15491 5 0.01% 99.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15552-15555 5 0.01% 99.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15616-15619 3 0.00% 99.76% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::15744-15747 2 0.00% 99.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15808-15811 7 0.01% 99.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15872-15875 5 0.01% 99.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::15936-15939 5 0.01% 99.79% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::16064-16067 6 0.01% 99.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::16128-16131 6 0.01% 99.83% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::16256-16259 11 0.02% 99.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::16320-16323 13 0.02% 99.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::16384-16387 65 0.10% 99.98% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::16512-16515 1 0.00% 99.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::16576-16579 3 0.00% 99.99% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::total 62409 # Bytes accessed per row activation
+system.physmem.totQLat 4001177249 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 8265005999 # Sum of mem lat for all requests
+system.physmem.totBusLat 1109565000 # Total cycles spent in databus access
+system.physmem.totBankLat 3154263750 # Total cycles spent in bank access
+system.physmem.avgQLat 18030.39 # Average queueing delay per request
+system.physmem.avgBankLat 14213.97 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 41716.21 # Average memory access latency
-system.physmem.avgRdBW 2.78 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 37244.35 # Average memory access latency
+system.physmem.avgRdBW 2.77 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 2.78 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 2.77 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 1.85 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 15.58 # Average write queue length over time
-system.physmem.readRowHits 191257 # Number of row buffer hits during reads
-system.physmem.writeRowHits 105612 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 85.77 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 70.88 # Row buffer hit rate for writes
-system.physmem.avgGap 13817644.47 # Average gap between requests
-system.iocache.replacements 47576 # number of replacements
-system.iocache.tagsinuse 0.128763 # Cycle average of tags in use
+system.physmem.avgWrQLen 11.40 # Average write queue length over time
+system.physmem.readRowHits 198637 # Number of row buffer hits during reads
+system.physmem.writeRowHits 108987 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 89.51 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.58 # Row buffer hit rate for writes
+system.physmem.avgGap 13848423.25 # Average gap between requests
+system.membus.throughput 5098961 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 662131 # Transaction distribution
+system.membus.trans_dist::ReadResp 662131 # Transaction distribution
+system.membus.trans_dist::WriteReq 13694 # Transaction distribution
+system.membus.trans_dist::WriteResp 13694 # Transaction distribution
+system.membus.trans_dist::Writeback 148125 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 2235 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 1745 # Transaction distribution
+system.membus.trans_dist::ReadExReq 179249 # Transaction distribution
+system.membus.trans_dist::ReadExResp 179246 # Transaction distribution
+system.membus.trans_dist::MessageReq 1640 # Transaction distribution
+system.membus.trans_dist::MessageResp 1640 # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3280 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total 3280 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473788 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 470782 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1719634 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 132454 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 132454 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port 606242 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.bridge.slave 470782 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.cpu.interrupts.int_slave 3280 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1855368 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6560 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::total 6560 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18259712 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20051511 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5428608 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total 5428608 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.physmem.port 23688320 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.bridge.slave 241674 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6560 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 25486679 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 25486679 # Total data (bytes)
+system.membus.snoop_data_through_bus 649152 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 1603689497 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 250319000 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 583198000 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer3.occupancy 3280000 # Layer occupancy (ticks)
+system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer0.occupancy 1640000 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 3152452403 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer4.occupancy 429424246 # Layer occupancy (ticks)
+system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.iocache.replacements 47577 # number of replacements
+system.iocache.tagsinuse 0.079131 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 47592 # Sample count of references to valid blocks.
+system.iocache.sampled_refs 47593 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 4991974997000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide 0.128763 # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide 0.008048 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.008048 # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 911 # number of ReadReq misses
+system.iocache.warmup_cycle 4992752531000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::pc.south_bridge.ide 0.079131 # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide 0.004946 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.004946 # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 912 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 47631 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47631 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 47631 # number of overall misses
-system.iocache.overall_misses::total 47631 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 147497397 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 147497397 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10072244306 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10072244306 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 10219741703 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10219741703 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 10219741703 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10219741703 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses
+system.iocache.demand_misses::total 47632 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses
+system.iocache.overall_misses::total 47632 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152414185 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 152414185 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10346136346 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 10346136346 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 10498550531 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 10498550531 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 10498550531 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 10498550531 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 47631 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47631 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 47631 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47631 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 161907.131723 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 161907.131723 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 215587.420933 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 215587.420933 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 214560.721022 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 214560.721022 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 214560.721022 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 214560.721022 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 139153 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167120.816886 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 167120.816886 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 221449.836173 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 221449.836173 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 220409.609737 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 220409.609737 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 220409.609737 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 220409.609737 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 148997 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 12645 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 13662 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 11.004587 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 10.905943 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 47631 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 47631 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 47631 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 47631 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100104427 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 100104427 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7641446543 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 7641446543 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7741550970 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 7741550970 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7741550970 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 7741550970 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104973685 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 104973685 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7915976600 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 7915976600 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8020950285 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 8020950285 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8020950285 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 8020950285 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 109884.113063 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 109884.113063 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 163558.359225 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 163558.359225 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162531.774895 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 162531.774895 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162531.774895 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 162531.774895 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115102.724781 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 115102.724781 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 169434.430651 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 169434.430651 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 168394.152775 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 168394.152775 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 168394.152775 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 168394.152775 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 85620726 # Number of BP lookups
-system.cpu.branchPred.condPredicted 85620726 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 882198 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 79268619 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 77534559 # Number of BTB hits
+system.iobus.throughput 639145 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 225496 # Transaction distribution
+system.iobus.trans_dist::ReadResp 225496 # Transaction distribution
+system.iobus.trans_dist::WriteReq 57527 # Transaction distribution
+system.iobus.trans_dist::WriteResp 57527 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1640 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1640 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 470782 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95264 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95264 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3280 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3280 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.apicbridge.slave 3280 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.iocache.cpu_side 95264 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 569326 # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 241674 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027840 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027840 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6560 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6560 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.apicbridge.slave 6560 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.iocache.cpu_side 3027840 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 3276074 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 3276074 # Total data (bytes)
+system.iobus.reqLayer0.occupancy 3909656 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
+system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
+system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks)
+system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
+system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
+system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 20182000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 424474531 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 459975000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer1.occupancy 52352000 # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer2.occupancy 1640000 # Layer occupancy (ticks)
+system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu.branchPred.lookups 85601186 # Number of BP lookups
+system.cpu.branchPred.condPredicted 85601186 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 878782 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 79197718 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 77534768 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.812426 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1442315 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 180251 # Number of incorrect RAS predictions.
-system.cpu.numCycles 447791761 # number of cpu cycles simulated
+system.cpu.branchPred.BTBHitPct 97.900255 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1440711 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 178764 # Number of incorrect RAS predictions.
+system.cpu.numCycles 453375451 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 25559948 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 422856490 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 85620726 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 78976874 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 162677741 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4000997 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 98298 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 65919320 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 43594 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 86507 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 459 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 8492083 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 383635 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 2345 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 257461374 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 3.243647 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.415529 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 25513858 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 422800544 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 85601186 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 78975479 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 162663365 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 3996734 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 101966 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 70853615 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 42658 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 89309 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 281 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 8479708 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 381834 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 2341 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 262338796 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 3.182647 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.411668 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 95198026 36.98% 36.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1534816 0.60% 37.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 71825104 27.90% 65.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 895357 0.35% 65.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1570607 0.61% 66.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2391332 0.93% 67.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1020158 0.40% 67.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1325162 0.51% 68.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 81700812 31.73% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 100089762 38.15% 38.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1543248 0.59% 38.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 71824716 27.38% 66.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 898472 0.34% 66.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1568808 0.60% 67.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2394853 0.91% 67.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1014354 0.39% 68.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1328708 0.51% 68.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 81675875 31.13% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 257461374 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.191207 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.944315 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 29461192 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 63064302 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 158550724 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3309649 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3075507 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 832761340 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 863 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3075507 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 32153278 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 38465118 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 12079112 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 158824437 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 12863922 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 829829025 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 19879 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 6055166 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4924546 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 11525 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 991492877 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1800847756 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1800847292 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 464 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 963999366 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 27493506 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 456551 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 462682 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 29304477 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 16752339 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 9837983 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1099709 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 928773 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 825036488 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1186686 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 821069910 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 146070 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 19309743 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 29357166 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 131932 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 257461374 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 3.189099 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.383585 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 262338796 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.188809 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.932562 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 29417456 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 68001358 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 158506679 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3339559 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3073744 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 832592947 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 926 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3073744 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 32109829 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 42827309 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 12461023 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 158801746 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 13065145 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 829696742 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 21430 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 6044181 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 5137835 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 10653 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 991365298 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1800497636 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1800497180 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 456 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 963871300 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 27493996 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 453983 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 458205 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 29510312 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 16729516 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 9820056 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1138043 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 956999 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 824928716 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1184630 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 820966425 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 150849 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 19304203 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 29360127 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 130755 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 262338796 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 3.129413 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.399539 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 71259249 27.68% 27.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 15575755 6.05% 33.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 10479111 4.07% 37.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7383615 2.87% 40.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 75752504 29.42% 70.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3772068 1.47% 71.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 72307575 28.08% 99.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 782694 0.30% 99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 148803 0.06% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 75996420 28.97% 28.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 15740261 6.00% 34.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 10531012 4.01% 38.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7367834 2.81% 41.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 75736075 28.87% 70.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 3750663 1.43% 72.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 72297854 27.56% 99.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 773517 0.29% 99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 145160 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 257461374 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 262338796 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 356313 33.63% 33.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 241 0.02% 33.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 2452 0.23% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.89% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 547502 51.68% 85.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 152922 14.43% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 351269 33.33% 33.33% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 200 0.02% 33.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 1810 0.17% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 547247 51.93% 85.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 153387 14.55% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 308526 0.04% 0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 793557907 96.65% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 150412 0.02% 96.71% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 124298 0.02% 96.72% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 304863 0.04% 0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 793498796 96.65% 96.69% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 149830 0.02% 96.71% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 124227 0.02% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.72% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.72% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 17694567 2.16% 98.88% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 9234200 1.12% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 17669358 2.15% 98.88% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 9219351 1.12% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 821069910 # Type of FU issued
-system.cpu.iq.rate 1.833598 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1059430 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001290 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1900915279 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 845543458 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 817157785 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 194 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 821820724 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1686147 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 820966425 # Type of FU issued
+system.cpu.iq.rate 1.810787 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1053913 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.001284 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1905583532 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 845427964 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 817056658 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 193 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 210 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 821715388 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 87 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1694689 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 2748440 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 17101 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 11930 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1411969 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 2746767 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 18051 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 12083 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1403061 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 1931504 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 11624 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 1931249 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 12313 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3075507 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 26873503 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 2150322 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 826223174 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 241070 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 16752339 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 9837983 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 692103 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1621529 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 12267 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 11930 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 498132 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 506603 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1004735 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 819660888 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 17391685 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1409021 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3073744 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 30976434 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 2152665 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 826113346 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 242094 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 16729516 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 9820056 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 689859 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1619870 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 14784 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 12083 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 494405 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 508019 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1002424 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 819559028 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 17368747 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1407396 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 26440023 # number of memory reference insts executed
-system.cpu.iew.exec_branches 83107253 # Number of branches executed
-system.cpu.iew.exec_stores 9048338 # Number of stores executed
-system.cpu.iew.exec_rate 1.830451 # Inst execution rate
-system.cpu.iew.wb_sent 819258374 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 817157837 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 638799704 # num instructions producing a value
-system.cpu.iew.wb_consumers 1044337102 # num instructions consuming a value
+system.cpu.iew.exec_refs 26403485 # number of memory reference insts executed
+system.cpu.iew.exec_branches 83095032 # Number of branches executed
+system.cpu.iew.exec_stores 9034738 # Number of stores executed
+system.cpu.iew.exec_rate 1.807683 # Inst execution rate
+system.cpu.iew.wb_sent 819157526 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 817056708 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 638600685 # num instructions producing a value
+system.cpu.iew.wb_consumers 1043925557 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.824861 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.611680 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.802164 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.611730 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 20042352 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1054753 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 891546 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 254385866 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 3.168696 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.858566 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 20041054 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1053875 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 888667 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 259265052 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 3.108646 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.863485 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 82972146 32.62% 32.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11724447 4.61% 37.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3813249 1.50% 38.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 74747378 29.38% 68.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2384925 0.94% 69.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1476326 0.58% 69.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 865615 0.34% 69.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 70850824 27.85% 97.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5550956 2.18% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 87759364 33.85% 33.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11842879 4.57% 38.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3826328 1.48% 39.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 74742270 28.83% 68.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2381968 0.92% 69.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1473831 0.57% 70.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 858574 0.33% 70.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 70846339 27.33% 97.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5533499 2.13% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 254385866 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 407786881 # Number of instructions committed
-system.cpu.commit.committedOps 806071515 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 259265052 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 407728401 # Number of instructions committed
+system.cpu.commit.committedOps 805963181 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 22429911 # Number of memory references committed
-system.cpu.commit.loads 14003897 # Number of loads committed
-system.cpu.commit.membars 474463 # Number of memory barriers committed
-system.cpu.commit.branches 82163817 # Number of branches committed
+system.cpu.commit.refs 22399743 # Number of memory references committed
+system.cpu.commit.loads 13982748 # Number of loads committed
+system.cpu.commit.membars 474399 # Number of memory barriers committed
+system.cpu.commit.branches 82153759 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 735061477 # Number of committed integer instructions.
-system.cpu.commit.function_calls 1156045 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5550956 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 734952654 # Number of committed integer instructions.
+system.cpu.commit.function_calls 1154691 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 5533499 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1074870508 # The number of ROB reads
-system.cpu.rob.rob_writes 1655318425 # The number of ROB writes
-system.cpu.timesIdled 1256763 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 190330387 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 9834088814 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 407786881 # Number of Instructions Simulated
-system.cpu.committedOps 806071515 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 407786881 # Number of Instructions Simulated
-system.cpu.cpi 1.098102 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.098102 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.910662 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.910662 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1504614065 # number of integer regfile reads
-system.cpu.int_regfile_writes 975429838 # number of integer regfile writes
-system.cpu.fp_regfile_reads 52 # number of floating regfile reads
-system.cpu.misc_regfile_reads 264130300 # number of misc regfile reads
-system.cpu.misc_regfile_writes 403010 # number of misc regfile writes
-system.cpu.icache.replacements 955437 # number of replacements
-system.cpu.icache.tagsinuse 509.903328 # Cycle average of tags in use
-system.cpu.icache.total_refs 7482159 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 955949 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 7.826944 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 146514700000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 509.903328 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.995905 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.995905 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 7482159 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 7482159 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 7482159 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 7482159 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 7482159 # number of overall hits
-system.cpu.icache.overall_hits::total 7482159 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1009922 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1009922 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1009922 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1009922 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1009922 # number of overall misses
-system.cpu.icache.overall_misses::total 1009922 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 13938284992 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 13938284992 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 13938284992 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 13938284992 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 13938284992 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 13938284992 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 8492081 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 8492081 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 8492081 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 8492081 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 8492081 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 8492081 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.118925 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.118925 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.118925 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.118925 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.118925 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.118925 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13801.348017 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13801.348017 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13801.348017 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13801.348017 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13801.348017 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13801.348017 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 8199 # number of cycles access was blocked
+system.cpu.rob.rob_reads 1079657633 # The number of ROB reads
+system.cpu.rob.rob_writes 1655096826 # The number of ROB writes
+system.cpu.timesIdled 1258785 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 191036655 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 9798064041 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 407728401 # Number of Instructions Simulated
+system.cpu.committedOps 805963181 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 407728401 # Number of Instructions Simulated
+system.cpu.cpi 1.111955 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.111955 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.899317 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.899317 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1504349061 # number of integer regfile reads
+system.cpu.int_regfile_writes 975319683 # number of integer regfile writes
+system.cpu.fp_regfile_reads 50 # number of floating regfile reads
+system.cpu.misc_regfile_reads 264080509 # number of misc regfile reads
+system.cpu.misc_regfile_writes 401987 # number of misc regfile writes
+system.cpu.toL2Bus.throughput 53625221 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 3010668 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 3010129 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 13694 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 13694 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 1578360 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2289 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2289 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 334262 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 287551 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1907708 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6121795 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 17377 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 150658 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 8197538 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61043136 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 207549047 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 553408 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 5256448 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 274402039 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 274377591 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 490112 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 4031070918 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy 573000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1431698822 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 3102593965 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy 13102485 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
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-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15725947 # number of UpgradeReq MSHR miss cycles
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-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89236811500 # number of ReadReq MSHR uncacheable cycles
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56752.997758 # average ReadReq mshr miss latency
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-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10705.205582 # average UpgradeReq mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43321.480878 # average overall mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
---------- Begin Simulation Statistics ----------
sim_seconds 5.205149 # Number of seconds simulated
-sim_ticks 5205148879000 # Number of ticks simulated
-final_tick 5205148879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 5205149326500 # Number of ticks simulated
+final_tick 5205149326500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 131600 # Simulator instruction rate (inst/s)
-host_op_rate 252290 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6421585329 # Simulator tick rate (ticks/s)
-host_mem_usage 872300 # Number of bytes of host memory used
-host_seconds 810.57 # Real time elapsed on the host
-sim_insts 106671342 # Number of instructions simulated
-sim_ops 204498751 # Number of ops (including micro ops) simulated
+host_inst_rate 156279 # Simulator instruction rate (inst/s)
+host_op_rate 299599 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 7625516175 # Simulator tick rate (ticks/s)
+host_mem_usage 825184 # Number of bytes of host memory used
+host_seconds 682.60 # Real time elapsed on the host
+sim_insts 106675228 # Number of instructions simulated
+sim_ops 204505420 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 35240 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 160344 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 75328 # Number of bytes read from this memory
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-system.physmem.bytes_read::cpu0.data 41978278 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.itb.walker 30152 # Number of bytes read from this memory
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-system.physmem.bytes_read::total 1104699086 # Number of bytes read from this memory
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-system.physmem.bytes_inst_read::total 1011015424 # Number of instructions bytes read from this memory
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+system.physmem.bytes_inst_read::total 1011060864 # Number of instructions bytes read from this memory
system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 33612947 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 34199698 # Number of bytes written to this memory
-system.physmem.bytes_written::total 70803765 # Number of bytes written to this memory
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+system.physmem.bytes_written::total 70810904 # Number of bytes written to this memory
system.physmem.num_reads::pc.south_bridge.ide 821 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 9416 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.itb.walker 3769 # Number of read requests responded to by this memory
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-system.physmem.num_reads::total 142080513 # Number of read requests responded to by this memory
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system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory
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-system.physmem.num_writes::total 9853761 # Number of write requests responded to by this memory
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system.physmem.bw_read::pc.south_bridge.ide 6770 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 30805 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.itb.walker 14472 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 108151409 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 8064760 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.itb.walker 5793 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 86082310 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 9863584 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 212231986 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 108151409 # Instruction read bandwidth from this memory (bytes/s)
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-system.physmem.bw_inst_read::total 194233719 # Instruction read bandwidth from this memory (bytes/s)
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+system.physmem.bw_inst_read::cpu0.inst 108163541 # Instruction read bandwidth from this memory (bytes/s)
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+system.physmem.bw_inst_read::total 194242432 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::pc.south_bridge.ide 574643 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 6457634 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 6570359 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 13602640 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 581414 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 30805 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 6459099 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 6570265 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 13604010 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 581413 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 30817 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 14475 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 108151409 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 14522394 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 12083 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 108163541 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 14526025 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 12096 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 5793 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 86082310 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 16433943 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 225834626 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 86078891 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 16433426 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 225846477 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 821 # Total number of read requests seen
system.physmem.writeReqs 46736 # Total number of write requests seen
-system.physmem.cpureqs 47279 # Reqs generatd by CPU via cache - shady
+system.physmem.cpureqs 47259 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 52544 # Total number of bytes read from memory
system.physmem.bytesWritten 2991104 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 35240 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 2991104 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 32 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 48 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 64 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 309 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 32 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 64 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 64 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 48 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 80 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 48 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 16 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 16 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 32 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 48 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 48 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 32 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 48 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 32 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 16 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 16 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 32 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 80 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 325 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 16 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 2992 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 2832 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 3024 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 2944 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 2992 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 2960 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 2968 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 2992 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 2856 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 2864 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 2896 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 2800 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 2864 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 2864 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 2960 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 2928 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::0 2816 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 2864 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 2640 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 2768 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 2768 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 3064 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 2648 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 2816 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 3232 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 3312 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 3248 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 3024 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 2976 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 2672 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 2880 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 3008 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 31 # Number of times wr buffer was full causing retry
-system.physmem.totGap 64277169000 # Total gap between requests
+system.physmem.numWrRetry 11 # Number of times wr buffer was full causing retry
+system.physmem.totGap 64277565999 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 2 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1965 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1974 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1995 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1997 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1997 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1997 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1997 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1998 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1999 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 2010 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 2020 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 2020 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 2020 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 2020 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 2020 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 2020 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 2021 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 2021 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 2032 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 67 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 58 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 37 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 35 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 35 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 35 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 35 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 34 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 33 # What write queue length does an incoming req see
-system.physmem.totQLat 41690522 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 53523022 # Sum of mem lat for all requests
+system.physmem.wrQLenPdf::23 22 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 11 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 539 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 5552.207792 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 3362.695639 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 3316.858883 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 30 5.57% 5.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 2 0.37% 5.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 6 1.11% 7.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 9 1.67% 8.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 2 0.37% 9.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 3 0.56% 9.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 1 0.19% 9.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 1 0.19% 10.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 1 0.19% 10.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 2 0.37% 10.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 2 0.37% 10.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 1 0.19% 11.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 2 0.37% 11.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 1 0.19% 11.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 2 0.37% 12.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 69 12.80% 24.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 1 0.19% 25.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 3 0.56% 25.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 2 0.37% 25.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 2 0.37% 26.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 1 0.19% 26.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 1 0.19% 26.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 1 0.19% 26.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2049 11 2.04% 28.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2817 1 0.19% 29.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3073 9 1.67% 30.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3201 1 0.19% 30.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904-3905 1 0.19% 31.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3968-3969 1 0.19% 31.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4096-4097 41 7.61% 38.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5120-5121 6 1.11% 40.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5888-5889 1 0.19% 40.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6144-6145 4 0.74% 41.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6656-6657 1 0.19% 41.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7168-7169 5 0.93% 42.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7552-7553 1 0.19% 42.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7808-7809 1 0.19% 42.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 310 57.51% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 539 # Bytes accessed per row activation
+system.physmem.totQLat 47710768 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 58058268 # Sum of mem lat for all requests
system.physmem.totBusLat 4105000 # Total cycles spent in databus access
-system.physmem.totBankLat 7727500 # Total cycles spent in bank access
-system.physmem.avgQLat 50780.17 # Average queueing delay per request
-system.physmem.avgBankLat 9412.30 # Average bank access latency per request
+system.physmem.totBankLat 6242500 # Total cycles spent in bank access
+system.physmem.avgQLat 58112.99 # Average queueing delay per request
+system.physmem.avgBankLat 7603.53 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 65192.48 # Average memory access latency
+system.physmem.avgMemAccLat 70716.53 # Average memory access latency
system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s
system.physmem.busUtil 0.00 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.15 # Average write queue length over time
-system.physmem.readRowHits 704 # Number of row buffer hits during reads
-system.physmem.writeRowHits 45223 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 85.75 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 96.76 # Row buffer hit rate for writes
-system.physmem.avgGap 1351581.66 # Average gap between requests
+system.physmem.readRowHits 756 # Number of row buffer hits during reads
+system.physmem.writeRowHits 46262 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 92.08 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 98.99 # Row buffer hit rate for writes
+system.physmem.avgGap 1351590.01 # Average gap between requests
+system.piobus.throughput 974238 # Throughput (bytes/s)
+system.piobus.trans_dist::ReadReq 863748 # Transaction distribution
+system.piobus.trans_dist::ReadResp 863748 # Transaction distribution
+system.piobus.trans_dist::WriteReq 83560 # Transaction distribution
+system.piobus.trans_dist::WriteResp 83560 # Transaction distribution
+system.piobus.trans_dist::MessageReq 1915 # Transaction distribution
+system.piobus.trans_dist::MessageResp 1915 # Transaction distribution
+system.piobus.pkt_count_system.pc.south_bridge.ide.dma::system.physmem.port 95114 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.pc.south_bridge.ide.dma::total 95114 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 1680 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 1624 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3304 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 6496 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 732 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 90 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic2.pio 42 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.speaker.pio 938970 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 1000 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.i_dont_exist.pio 90 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 15614 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 748796 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::total 1714112 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 4730 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 632 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 4 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic2.pio 12 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pit.pio 31770 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 328 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.i_dont_exist.pio 31858 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 10796 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 5100 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::total 85390 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 330 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.cpu0.interrupts.int_master::total 330 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 196 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.cpu1.interrupts.int_master::total 196 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.physmem.port 95114 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.pc.south_bridge.cmos.pio 52 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.pc.south_bridge.ide.pio 11226 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.pc.south_bridge.pic1.pio 94 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.pc.south_bridge.pit.pio 31800 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.pc.south_bridge.speaker.pio 938970 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.pc.south_bridge.io_apic.pio 1328 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.pc.i_dont_exist.pio 31948 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.pc.com_1.pio 26410 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.cpu0.interrupts.pio 748796 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.cpu0.interrupts.int_slave 1876 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.cpu1.interrupts.pio 5100 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.cpu1.interrupts.int_slave 1954 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::total 1898446 # Packet count per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.physmem.port 3026344 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3026344 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 3360 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 3248 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6608 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 3698 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 366 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 45 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic2.pio 21 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.speaker.pio 469485 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 2000 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.i_dont_exist.pio 45 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 7807 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 1497586 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::total 1985488 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 3066 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 316 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 2 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic2.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pit.pio 15885 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 656 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.i_dont_exist.pio 15929 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 5398 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 10197 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::total 51561 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 660 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::total 660 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 392 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::total 392 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.physmem.port 3026344 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 26 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6764 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 47 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.pc.south_bridge.pit.pio 15900 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 469485 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2656 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.pc.i_dont_exist.pio 15974 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.pc.com_1.pio 13205 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.cpu0.interrupts.pio 1497586 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.cpu0.interrupts.int_slave 3752 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.cpu1.interrupts.pio 10197 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.cpu1.interrupts.int_slave 3908 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::total 5071053 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.data_through_bus 5071053 # Total data (bytes)
+system.piobus.reqLayer0.occupancy 421750668 # Layer occupancy (ticks)
+system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer1.occupancy 46000 # Layer occupancy (ticks)
+system.piobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer2.occupancy 6500 # Layer occupancy (ticks)
+system.piobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer3.occupancy 10348000 # Layer occupancy (ticks)
+system.piobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer4.occupancy 140500 # Layer occupancy (ticks)
+system.piobus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer5.occupancy 1063000 # Layer occupancy (ticks)
+system.piobus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer6.occupancy 95500 # Layer occupancy (ticks)
+system.piobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer7.occupancy 56000 # Layer occupancy (ticks)
+system.piobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer8.occupancy 21210500 # Layer occupancy (ticks)
+system.piobus.reqLayer8.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer9.occupancy 586857500 # Layer occupancy (ticks)
+system.piobus.reqLayer9.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer10.occupancy 1290500 # Layer occupancy (ticks)
+system.piobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer11.occupancy 39914000 # Layer occupancy (ticks)
+system.piobus.reqLayer11.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer12.occupancy 2500 # Layer occupancy (ticks)
+system.piobus.reqLayer12.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer13.occupancy 23057500 # Layer occupancy (ticks)
+system.piobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks)
+system.piobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks)
+system.piobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks)
+system.piobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks)
+system.piobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer18.occupancy 470748000 # Layer occupancy (ticks)
+system.piobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer19.occupancy 2244320 # Layer occupancy (ticks)
+system.piobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer20.occupancy 5358000 # Layer occupancy (ticks)
+system.piobus.reqLayer20.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer21.occupancy 2333580 # Layer occupancy (ticks)
+system.piobus.reqLayer21.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer22.occupancy 1074500 # Layer occupancy (ticks)
+system.piobus.reqLayer22.utilization 0.0 # Layer utilization (%)
+system.piobus.respLayer0.occupancy 52258179 # Layer occupancy (ticks)
+system.piobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.piobus.respLayer1.occupancy 2331400 # Layer occupancy (ticks)
+system.piobus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.piobus.respLayer2.occupancy 1919239500 # Layer occupancy (ticks)
+system.piobus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.piobus.respLayer3.occupancy 68175500 # Layer occupancy (ticks)
+system.piobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.piobus.respLayer4.occupancy 210500 # Layer occupancy (ticks)
+system.piobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.piobus.respLayer5.occupancy 121000 # Layer occupancy (ticks)
+system.piobus.respLayer5.utilization 0.0 # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 11503621 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 550662 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 12054283 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 70015833 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 352190 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 70368023 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 11506236 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses 550740 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 12056976 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits 70023521 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses 352402 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses 70375923 # Number of cache demand accesses
system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl1.L1Dcache.demand_hits 12163827 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses 1291679 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses 13455506 # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Icache.demand_hits 55549058 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Icache.demand_misses 459847 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Icache.demand_accesses 56008905 # Number of cache demand accesses
+system.ruby.l1_cntrl1.L1Dcache.demand_hits 12162992 # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Dcache.demand_misses 1291757 # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Dcache.demand_accesses 13454749 # Number of cache demand accesses
+system.ruby.l1_cntrl1.L1Icache.demand_hits 55546818 # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Icache.demand_misses 459867 # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Icache.demand_accesses 56006685 # Number of cache demand accesses
system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed
system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made
system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l2_cntrl0.L2cache.demand_hits 2426575 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 227803 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 2654378 # Number of cache demand accesses
-system.cpu0.numCycles 10410297758 # number of cpu cycles simulated
+system.ruby.l2_cntrl0.L2cache.demand_hits 2426890 # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses 227876 # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses 2654766 # Number of cache demand accesses
+system.cpu0.numCycles 10410298653 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 60288276 # Number of instructions committed
-system.cpu0.committedOps 115773079 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 108731496 # Number of integer alu accesses
+system.cpu0.committedInsts 60294243 # Number of instructions committed
+system.cpu0.committedOps 115784968 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 108743289 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu0.num_func_calls 1065656 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 10277696 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 108731496 # number of integer instructions
+system.cpu0.num_func_calls 1066196 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 10278204 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 108743289 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
-system.cpu0.num_int_register_reads 267473663 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 137108635 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 267504308 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 137121782 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_mem_refs 12880520 # number of memory refs
-system.cpu0.num_load_insts 7843945 # Number of load instructions
-system.cpu0.num_store_insts 5036575 # Number of store instructions
-system.cpu0.num_idle_cycles 9879714305.974102 # Number of idle cycles
-system.cpu0.num_busy_cycles 530583452.025898 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.050967 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.949033 # Percentage of idle cycles
+system.cpu0.num_mem_refs 12883291 # number of memory refs
+system.cpu0.num_load_insts 7845612 # Number of load instructions
+system.cpu0.num_store_insts 5037679 # Number of store instructions
+system.cpu0.num_idle_cycles 9879654975.894102 # Number of idle cycles
+system.cpu0.num_busy_cycles 530643677.105898 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.050973 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.949027 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu1.numCycles 10407399002 # number of cpu cycles simulated
+system.cpu1.numCycles 10407399919 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 46383066 # Number of instructions committed
-system.cpu1.committedOps 88725672 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 85218419 # Number of integer alu accesses
+system.cpu1.committedInsts 46380985 # Number of instructions committed
+system.cpu1.committedOps 88720452 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 85213748 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu1.num_func_calls 1670749 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 7955161 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 85218419 # number of integer instructions
+system.cpu1.num_func_calls 1670555 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 7954622 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 85213748 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
-system.cpu1.num_int_register_reads 213998429 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 102139748 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 213988355 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 102135039 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_mem_refs 13480502 # number of memory refs
-system.cpu1.num_load_insts 8673583 # Number of load instructions
-system.cpu1.num_store_insts 4806919 # Number of store instructions
-system.cpu1.num_idle_cycles 10081113907.619320 # Number of idle cycles
-system.cpu1.num_busy_cycles 326285094.380681 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.031351 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.968649 # Percentage of idle cycles
+system.cpu1.num_mem_refs 13479662 # number of memory refs
+system.cpu1.num_load_insts 8672840 # Number of load instructions
+system.cpu1.num_store_insts 4806822 # Number of store instructions
+system.cpu1.num_idle_cycles 10081140022.903200 # Number of idle cycles
+system.cpu1.num_busy_cycles 326259896.096799 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.031349 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.968651 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- Begin Simulation Statistics ----------
-sim_seconds 5.139557 # Number of seconds simulated
-sim_ticks 5139557121500 # Number of ticks simulated
-final_tick 5139557121500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.143601 # Number of seconds simulated
+sim_ticks 5143601047500 # Number of ticks simulated
+final_tick 5143601047500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 183644 # Simulator instruction rate (inst/s)
-host_op_rate 364835 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3871369364 # Simulator tick rate (ticks/s)
-host_mem_usage 967408 # Number of bytes of host memory used
-host_seconds 1327.58 # Real time elapsed on the host
-sim_insts 243802016 # Number of instructions simulated
-sim_ops 484348047 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide 2455296 # Number of bytes read from this memory
+host_inst_rate 337830 # Simulator instruction rate (inst/s)
+host_op_rate 671266 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 7140786618 # Simulator tick rate (ticks/s)
+host_mem_usage 909440 # Number of bytes of host memory used
+host_seconds 720.31 # Real time elapsed on the host
+sim_insts 243343656 # Number of instructions simulated
+sim_ops 483521256 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide 2435392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 466944 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 5828928 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 127616 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 1842944 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker 1536 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 356032 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 2734144 # Number of bytes read from this memory
-system.physmem.bytes_read::total 13813760 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 466944 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 127616 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 356032 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 950592 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9154048 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9154048 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 38364 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu0.inst 488448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 6105280 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 134592 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 1637632 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker 1280 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 319296 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 2611264 # Number of bytes read from this memory
+system.physmem.bytes_read::total 13733504 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 488448 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 134592 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 319296 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 942336 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9060160 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9060160 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 38053 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 7296 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 91077 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1994 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 28796 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker 24 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 5563 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 42721 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 215840 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 143032 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 143032 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 477725 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu0.inst 7632 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 95395 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 2103 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 25588 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker 20 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 4989 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 40801 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 214586 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 141565 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 141565 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 473480 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 90853 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1134130 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 24830 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 358580 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker 299 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 69273 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 531980 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2687734 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 90853 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 24830 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 69273 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 184956 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1781097 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1781097 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1781097 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 477725 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 94962 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1186966 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 26167 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 318382 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker 249 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 62076 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 507672 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2670017 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 94962 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 26167 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 62076 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 183205 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1761443 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1761443 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1761443 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 473480 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 90853 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 1134130 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 24830 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 358580 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker 299 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 69273 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 531980 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4468830 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 99105 # Total number of read requests seen
-system.physmem.writeReqs 78746 # Total number of write requests seen
-system.physmem.cpureqs 178569 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 6342720 # Total number of bytes read from memory
-system.physmem.bytesWritten 5039744 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 6342720 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 5039744 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 712 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 6100 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 5671 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 5539 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 6946 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 5876 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 5654 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 5883 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 7012 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 6334 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 6064 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 5868 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 7100 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 5762 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 5656 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 6255 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 7374 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 4754 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 4366 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 4230 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 5859 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 4494 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 4387 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 4605 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 5921 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 5001 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 4809 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 4668 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 5984 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 4422 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 4352 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 4757 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 6137 # Track writes on a per bank basis
+system.physmem.bw_total::cpu0.inst 94962 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1186966 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 26167 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 318382 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker 249 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 62076 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 507672 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4431460 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 90446 # Total number of read requests seen
+system.physmem.writeReqs 70433 # Total number of write requests seen
+system.physmem.cpureqs 161351 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 5788544 # Total number of bytes read from memory
+system.physmem.bytesWritten 4507712 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 5788544 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 4507712 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 26 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 472 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 5853 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 5374 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 5163 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 5410 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 5863 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 6188 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 5951 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 6069 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 4925 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 4669 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 5184 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 5694 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 5956 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 5914 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 6273 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 5934 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 4493 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 4309 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 4025 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 4097 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 4752 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 4893 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 4726 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 4839 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 3464 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 3572 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 4023 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 4337 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 4609 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 4582 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 5213 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 4499 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 6 # Number of times wr buffer was full causing retry
-system.physmem.totGap 5135869541000 # Total gap between requests
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 5140092000000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 99105 # Categorize read packet sizes
+system.physmem.readPktSize::6 90446 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 78746 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 75637 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 7751 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 3409 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1725 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 1554 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1226 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 983 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 957 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 916 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 876 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 581 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 527 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 479 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 448 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 405 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 409 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 465 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 448 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 189 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 97 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 70433 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 70577 # What read queue length does an incoming req see
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-system.physmem.totQLat 2229520000 # Total cycles spent in queuing delays
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-system.physmem.totBusLat 495470000 # Total cycles spent in databus access
-system.physmem.totBankLat 1525920000 # Total cycles spent in bank access
-system.physmem.avgQLat 22499.04 # Average queueing delay per request
-system.physmem.avgBankLat 15398.71 # Average bank access latency per request
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+system.physmem.bytesPerActivate::mean 340.294645 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 151.805560 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 1124.042449 # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::total 30233 # Bytes accessed per row activation
+system.physmem.totQLat 1718746250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 3502520000 # Sum of mem lat for all requests
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+system.physmem.totBankLat 1331673750 # Total cycles spent in bank access
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 42897.75 # Average memory access latency
-system.physmem.avgRdBW 1.23 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 0.98 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1.23 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 0.98 # Average consumed write bandwidth in MB/s
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+system.physmem.avgWrBW 0.88 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1.13 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.88 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 0.10 # Average write queue length over time
-system.physmem.readRowHits 83478 # Number of row buffer hits during reads
-system.physmem.writeRowHits 56534 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 84.24 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 71.79 # Row buffer hit rate for writes
-system.physmem.avgGap 28877372.30 # Average gap between requests
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-system.l2c.avg_refs 21.487741 # Average number of references to valid blocks.
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+system.membus.snoop_data_through_bus 335808 # Total snoop data (bytes)
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system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.l2c.demand_mshr_miss_rate::cpu2.inst 0.016667 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data 0.065651 # mshr miss rate for demand accesses
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+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000504 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst 0.016667 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data 0.065651 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.028806 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67487.874941 # average ReadReq mshr miss latency
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 80487.500000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 77846.412508 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 70082.177762 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 70458.063675 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10658.881579 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10613.792683 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10635.481013 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57596.755932 # average ReadExReq mshr miss latency
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+system.l2c.ReadExReq_avg_mshr_miss_latency::total 59841.266901 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67487.874941 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58676.429218 # average overall mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 64587.759371 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 63501.423682 # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58676.429218 # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 64587.759371 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 63501.423682 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 47571 # number of replacements
-system.iocache.tagsinuse 0.100524 # Cycle average of tags in use
+system.iocache.replacements 47575 # number of replacements
+system.iocache.tagsinuse 0.112740 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 47587 # Sample count of references to valid blocks.
+system.iocache.sampled_refs 47591 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 4999700789059 # Cycle when the warmup percentage was hit.
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-system.iocache.occ_percent::pc.south_bridge.ide 0.006283 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.006283 # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide 906 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 906 # number of ReadReq misses
+system.iocache.warmup_cycle 4999844175559 # Cycle when the warmup percentage was hit.
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system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
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-system.iocache.overall_misses::total 47626 # number of overall misses
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-system.iocache.WriteReq_miss_latency::total 5260229904 # number of WriteReq miss cycles
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-system.iocache.demand_miss_latency::total 5281931900 # number of demand (read+write) miss cycles
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-system.iocache.overall_miss_latency::total 5281931900 # number of overall miss cycles
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system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
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system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
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-system.iocache.ReadReq_avg_miss_latency::total 23953.637969 # average ReadReq miss latency
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-system.iocache.demand_avg_miss_latency::total 110904.377861 # average overall miss latency
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-system.iocache.overall_avg_miss_latency::total 110904.377861 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 67344 # number of cycles access was blocked
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system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 6552 # number of cycles access was blocked
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system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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+system.iocache.avg_blocked_cycles::no_mshrs 10.503669 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 169 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses
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-system.iocache.WriteReq_mshr_misses::total 24864 # number of WriteReq MSHR misses
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-system.iocache.demand_mshr_misses::total 25033 # number of demand (read+write) MSHR misses
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-system.iocache.overall_mshr_misses::total 25033 # number of overall MSHR misses
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-system.iocache.WriteReq_mshr_miss_latency::total 3966572850 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3979485348 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 3979485348 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3979485348 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 3979485348 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.186534 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 0.186534 # mshr miss rate for ReadReq accesses
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-system.iocache.WriteReq_mshr_miss_rate::total 0.532192 # mshr miss rate for WriteReq accesses
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-system.iocache.demand_mshr_miss_rate::total 0.525616 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.525616 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 0.525616 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 76405.313609 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 76405.313609 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 159530.761342 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 159530.761342 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 158969.574082 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 158969.574082 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 158969.574082 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 158969.574082 # average overall mshr miss latency
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+system.iocache.ReadReq_mshr_misses::total 701 # number of ReadReq MSHR misses
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+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3626115840 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 3626115840 # number of demand (read+write) MSHR miss cycles
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+system.iocache.overall_mshr_miss_latency::total 3626115840 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.770330 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 0.770330 # mshr miss rate for ReadReq accesses
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+system.iocache.WriteReq_mshr_miss_rate::total 0.455137 # mshr miss rate for WriteReq accesses
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+system.iocache.demand_mshr_miss_rate::total 0.461159 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.461159 # mshr miss rate for overall accesses
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+system.iocache.ReadReq_avg_mshr_miss_latency::total 136788.951498 # average ReadReq mshr miss latency
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+system.iocache.overall_avg_mshr_miss_latency::total 165086.084225 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu0.numCycles 1838156995 # number of cpu cycles simulated
+system.toL2Bus.throughput 52020310 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 1696057 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 1695532 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 5631 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 5631 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 870189 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 384 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 384 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 160044 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 138785 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 912543 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3510594 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.port 23321 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port 95695 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count 4542153 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29200384 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 115384682 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port 82512 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port 359600 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size 145027178 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 267476487 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 95232 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 4838788408 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy 814500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 2054232112 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 4517736918 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 13025458 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 50823334 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.throughput 1261125 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 151553 # Transaction distribution
+system.iobus.trans_dist::ReadResp 151553 # Transaction distribution
+system.iobus.trans_dist::WriteReq 26624 # Transaction distribution
+system.iobus.trans_dist::WriteResp 26624 # Transaction distribution
+system.iobus.trans_dist::MessageReq 269 # Transaction distribution
+system.iobus.trans_dist::MessageResp 269 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 4120 # Packet count per connected master and slave (bytes)
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+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.126495 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.058734 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038803 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.030557 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016561 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.070573 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.091047 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.042337 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.070573 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.091047 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.042337 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12241.890997 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14886.086688 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14103.774986 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32198.474579 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33629.400830 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32993.654142 # average WriteReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16476.783023 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17210.416120 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16976.801470 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16476.783023 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17210.416120 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16976.801470 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.numCycles 2606004355 # number of cpu cycles simulated
+system.cpu1.numCycles 2608004713 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 34463532 # Number of instructions committed
-system.cpu1.committedOps 67005357 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 62150402 # Number of integer alu accesses
+system.cpu1.committedInsts 34942757 # Number of instructions committed
+system.cpu1.committedOps 68016284 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 63114732 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu1.num_func_calls 411236 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 6382216 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 62150402 # number of integer instructions
+system.cpu1.num_func_calls 430753 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 6467325 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 63114732 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
-system.cpu1.num_int_register_reads 149729485 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 79937808 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 152021040 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 81233840 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_mem_refs 4253944 # number of memory refs
-system.cpu1.num_load_insts 2634755 # Number of load instructions
-system.cpu1.num_store_insts 1619189 # Number of store instructions
-system.cpu1.num_idle_cycles 7677367348.593150 # Number of idle cycles
-system.cpu1.num_busy_cycles -5071362993.593150 # Number of busy cycles
-system.cpu1.not_idle_fraction -1.946030 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 2.946030 # Percentage of idle cycles
+system.cpu1.num_mem_refs 4322210 # number of memory refs
+system.cpu1.num_load_insts 2726743 # Number of load instructions
+system.cpu1.num_store_insts 1595467 # Number of store instructions
+system.cpu1.num_idle_cycles 9296961839.327438 # Number of idle cycles
+system.cpu1.num_busy_cycles -6688957126.327438 # Number of busy cycles
+system.cpu1.not_idle_fraction -2.564780 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 3.564780 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.branchPred.lookups 28657213 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 28657213 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 282528 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 26332341 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 25809696 # Number of BTB hits
+system.cpu2.branchPred.lookups 28107723 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 28107723 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 253065 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 25890078 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 25466613 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 98.015197 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 509678 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 56598 # Number of incorrect RAS predictions.
-system.cpu2.numCycles 152138342 # number of cpu cycles simulated
+system.cpu2.branchPred.BTBHitPct 98.364373 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 482621 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 53231 # Number of incorrect RAS predictions.
+system.cpu2.numCycles 150677905 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 8765036 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 141230370 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 28657213 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 26319374 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 54195726 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 1350224 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles 59186 # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.BlockedCycles 22546148 # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles 3184 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 6465 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 18223 # Number of stall cycles due to pending traps
-system.cpu2.fetch.IcacheWaitRetryStallCycles 777 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 2884967 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 126552 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes 1685 # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples 86648155 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 3.214672 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 3.414816 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles 8157389 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 138649085 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 28107723 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 25949234 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 53330196 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 1190060 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles 46897 # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.BlockedCycles 22689996 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles 1645 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 6110 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 10082 # Number of stall cycles due to pending traps
+system.cpu2.fetch.IcacheWaitRetryStallCycles 361 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 2679696 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 114342 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes 1368 # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples 85168083 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 3.213895 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 3.414010 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 32565830 37.58% 37.58% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 546380 0.63% 38.21% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 23846422 27.52% 65.74% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 287955 0.33% 66.07% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 558507 0.64% 66.71% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 803239 0.93% 67.64% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 320738 0.37% 68.01% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 484990 0.56% 68.57% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 27234094 31.43% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 31941663 37.50% 37.50% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 506826 0.60% 38.10% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 23646883 27.76% 65.86% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 259157 0.30% 66.17% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 526154 0.62% 66.79% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 751269 0.88% 67.67% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 273870 0.32% 67.99% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 459070 0.54% 68.53% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 26803191 31.47% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 86648155 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.188363 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 0.928302 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 10203383 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 21434341 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 42926723 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 1270829 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 1056674 # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts 277800524 # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts 10 # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles 1056674 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 11171095 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 12732005 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 3756843 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 43068844 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 5106557 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 276894625 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 6426 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 2483944 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents 1961652 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.FullRegisterEvents 2548 # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands 331033770 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 601753258 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 601753178 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 80 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 321557178 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 9476592 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 136008 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 137084 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 11206153 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 5917951 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 3223233 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 365517 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 302609 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 275352384 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 397965 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 273886109 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 53996 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 6700477 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 10323870 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 50144 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 86648155 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 3.160899 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 2.377923 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 85168083 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.186542 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 0.920169 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 9520844 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 21607924 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 39424228 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 1229084 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 928772 # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts 273051293 # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts 4 # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles 928772 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 10439907 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 13089260 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 3699901 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 39570553 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 4982521 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 272244708 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 6270 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 2417106 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents 1932594 # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.FullRegisterEvents 1355 # Number of times there has been no free registers
+system.cpu2.rename.RenamedOperands 325535285 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 590374943 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 590374855 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 88 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 317221539 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 8313746 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 122579 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 123510 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 10816950 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 5506267 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 2968253 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 324837 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 268098 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 270840712 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 382144 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 269680817 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 48233 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 5882884 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 8996381 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 45929 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 85168083 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 3.166454 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 2.381789 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 23779115 27.44% 27.44% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 5842995 6.74% 34.19% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 3792974 4.38% 38.56% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 2596888 3.00% 41.56% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 25119641 28.99% 70.55% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 1266341 1.46% 72.01% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 23944050 27.63% 99.65% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 257275 0.30% 99.94% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 48876 0.06% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 23491447 27.58% 27.58% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 5639421 6.62% 34.20% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 3592727 4.22% 38.42% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 2433201 2.86% 41.28% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 24826332 29.15% 70.43% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 1184872 1.39% 71.82% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 23718098 27.85% 99.67% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 237817 0.28% 99.95% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 44168 0.05% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 86648155 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 85168083 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 118795 33.06% 33.06% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 241 0.07% 33.13% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 86 0.02% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 33.15% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 188736 52.53% 85.68% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 51440 14.32% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 103037 31.19% 31.19% # attempts to use FU when none available
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+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 31.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 31.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 31.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 31.26% # attempts to use FU when none available
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+system.cpu2.iq.fu_full::SimdMult 0 0.00% 31.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 31.26% # attempts to use FU when none available
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+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 31.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 31.26% # attempts to use FU when none available
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+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 31.26% # attempts to use FU when none available
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+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 31.26% # attempts to use FU when none available
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+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 31.26% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 181800 55.03% 86.29% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 45300 13.71% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass 68063 0.02% 0.02% # Type of FU issued
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-system.cpu2.iq.FU_type_0::IntMult 51078 0.02% 96.61% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 47173 0.02% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 6223177 2.27% 98.90% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 3018393 1.10% 100.00% # Type of FU issued
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+system.cpu2.iq.FU_type_0::IntDiv 43696 0.02% 96.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.80% # Type of FU issued
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+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.80% # Type of FU issued
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+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.80% # Type of FU issued
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+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.80% # Type of FU issued
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+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.80% # Type of FU issued
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+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.80% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.80% # Type of FU issued
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+system.cpu2.iq.FU_type_0::MemWrite 2781872 1.03% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 273886109 # Type of FU issued
-system.cpu2.iq.rate 1.800244 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 359298 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.001312 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 634870698 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 282454128 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 272600027 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 31 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 8 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 274177330 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 14 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 614321 # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total 269680817 # Type of FU issued
+system.cpu2.iq.rate 1.789783 # Inst issue rate
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+system.cpu2.iq.fu_busy_rate 0.001225 # FU busy rate (busy events/executed inst)
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+system.cpu2.iq.int_inst_queue_writes 277108342 # Number of integer instruction queue writes
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+system.cpu2.iq.fp_inst_queue_reads 40 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 38 # Number of floating instruction queue writes
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+system.cpu2.iq.int_alu_accesses 269954173 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 21 # Number of floating point alu accesses
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system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 929558 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 6267 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 3704 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 478908 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 814531 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 6351 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 3024 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 433740 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 656133 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 10377 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 655738 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 10426 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 1056674 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 8226180 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 803204 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 275750349 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 63685 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 5917951 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 3223233 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 220549 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 623968 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 3956 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 3704 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 161931 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 157888 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 319819 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 273437676 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 6124763 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 448433 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 928772 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 8598252 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 798569 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 271222856 # Number of instructions dispatched to IQ
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+system.cpu2.iew.iewDispStoreInsts 2968253 # Number of dispatched store instructions
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+system.cpu2.iew.iewIQFullEvents 621407 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewLSQFullEvents 3570 # Number of times the LSQ has become full, causing a stall
+system.cpu2.iew.memOrderViolationEvents 3024 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 146514 # Number of branches that were predicted taken incorrectly
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+system.cpu2.iew.iewExecSquashedInsts 398089 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 0 # number of nop insts executed
-system.cpu2.iew.exec_refs 9083662 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 27821550 # Number of branches executed
-system.cpu2.iew.exec_stores 2958899 # Number of stores executed
-system.cpu2.iew.exec_rate 1.797296 # Inst execution rate
-system.cpu2.iew.wb_sent 273301697 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 272600035 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 212879972 # num instructions producing a value
-system.cpu2.iew.wb_consumers 348297595 # num instructions consuming a value
+system.cpu2.iew.exec_refs 8495654 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 27379135 # Number of branches executed
+system.cpu2.iew.exec_stores 2727538 # Number of stores executed
+system.cpu2.iew.exec_rate 1.787141 # Inst execution rate
+system.cpu2.iew.wb_sent 269160909 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 268465771 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 209852405 # num instructions producing a value
+system.cpu2.iew.wb_consumers 343221010 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 1.791790 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.611201 # average fanout of values written-back
+system.cpu2.iew.wb_rate 1.781720 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.611421 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 6973062 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 347821 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 284653 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 85591481 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 3.140222 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 2.867307 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 6125563 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 336215 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 254201 # The number of times a branch was mispredicted
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+system.cpu2.commit.committed_per_cycle::mean 3.146959 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 2.869440 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 28429929 33.22% 33.22% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 4148762 4.85% 38.06% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1193631 1.39% 39.46% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 24678313 28.83% 68.29% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 797871 0.93% 69.22% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 541346 0.63% 69.85% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 330295 0.39% 70.24% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 23445398 27.39% 97.63% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 2025936 2.37% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 28027655 33.27% 33.27% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 3948624 4.69% 37.96% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1090324 1.29% 39.25% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 24397189 28.96% 68.21% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 757994 0.90% 69.11% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 507340 0.60% 69.72% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 301970 0.36% 70.08% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 23269432 27.62% 97.70% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 1938783 2.30% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 85591481 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 136077221 # Number of instructions committed
-system.cpu2.commit.committedOps 268776221 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 84239311 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 134086437 # Number of instructions committed
+system.cpu2.commit.committedOps 265097623 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 7732718 # Number of memory references committed
-system.cpu2.commit.loads 4988393 # Number of loads committed
-system.cpu2.commit.membars 163760 # Number of memory barriers committed
-system.cpu2.commit.branches 27507890 # Number of branches committed
+system.cpu2.commit.refs 7226249 # Number of memory references committed
+system.cpu2.commit.loads 4691736 # Number of loads committed
+system.cpu2.commit.membars 162513 # Number of memory barriers committed
+system.cpu2.commit.branches 27101249 # Number of branches committed
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 245262632 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 414873 # Number of function calls committed.
-system.cpu2.commit.bw_lim_events 2025936 # number cycles where commit BW limit reached
+system.cpu2.commit.int_insts 241753447 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 394614 # Number of function calls committed.
+system.cpu2.commit.bw_lim_events 1938783 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 359289994 # The number of ROB reads
-system.cpu2.rob.rob_writes 552558663 # The number of ROB writes
-system.cpu2.timesIdled 454161 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 65490187 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 4914041775 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 136077221 # Number of Instructions Simulated
-system.cpu2.committedOps 268776221 # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total 136077221 # Number of Instructions Simulated
-system.cpu2.cpi 1.118029 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 1.118029 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.894431 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.894431 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 502349004 # number of integer regfile reads
-system.cpu2.int_regfile_writes 325553024 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 62552 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 62544 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 88383748 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 121022 # number of misc regfile writes
+system.cpu2.rob.rob_reads 353502675 # The number of ROB reads
+system.cpu2.rob.rob_writes 543377618 # The number of ROB writes
+system.cpu2.timesIdled 448607 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 65509822 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 4919608430 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 134086437 # Number of Instructions Simulated
+system.cpu2.committedOps 265097623 # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total 134086437 # Number of Instructions Simulated
+system.cpu2.cpi 1.123737 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 1.123737 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.889888 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.889888 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 494284042 # number of integer regfile reads
+system.cpu2.int_regfile_writes 320739139 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 62606 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 62592 # number of floating regfile writes
+system.cpu2.misc_regfile_reads 86692309 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 109016 # number of misc regfile writes
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
-
----------- Begin Simulation Statistics ----------
-sim_seconds 2.233778 # Number of seconds simulated
-sim_ticks 4467555024 # Number of ticks simulated
-final_tick 4467555024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 2000000000 # Frequency of simulated ticks
-host_inst_rate 3081772 # Simulator instruction rate (inst/s)
-host_op_rate 3082983 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6178737 # Simulator tick rate (ticks/s)
-host_mem_usage 519228 # Number of bytes of host memory used
-host_seconds 723.05 # Real time elapsed on the host
-sim_insts 2228284650 # Number of instructions simulated
-sim_ops 2229160714 # Number of ops (including micro ops) simulated
-system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory
-system.hypervisor_desc.bytes_read::total 16792 # Number of bytes read from this memory
-system.hypervisor_desc.num_reads::cpu.data 9024 # Number of read requests responded to by this memory
-system.hypervisor_desc.num_reads::total 9024 # Number of read requests responded to by this memory
-system.hypervisor_desc.bw_read::cpu.data 7517 # Total read bandwidth from this memory (bytes/s)
-system.hypervisor_desc.bw_read::total 7517 # Total read bandwidth from this memory (bytes/s)
-system.hypervisor_desc.bw_total::cpu.data 7517 # Total bandwidth to/from this memory (bytes/s)
-system.hypervisor_desc.bw_total::total 7517 # Total bandwidth to/from this memory (bytes/s)
-system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory
-system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory
-system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory
-system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory
-system.partition_desc.bw_read::cpu.data 2169 # Total read bandwidth from this memory (bytes/s)
-system.partition_desc.bw_read::total 2169 # Total read bandwidth from this memory (bytes/s)
-system.partition_desc.bw_total::cpu.data 2169 # Total bandwidth to/from this memory (bytes/s)
-system.partition_desc.bw_total::total 2169 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 97534024 # Number of bytes read from this memory
-system.physmem.bytes_read::total 709825348 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 612291324 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 612291324 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 15400223 # Number of bytes written to this memory
-system.physmem.bytes_written::total 15400223 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 153072831 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 12152054 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 165224885 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 1927067 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1927067 # Number of write requests responded to by this memory
-system.physmem.num_other::cpu.data 14 # Number of other requests responded to by this memory
-system.physmem.num_other::total 14 # Number of other requests responded to by this memory
-system.physmem.bw_read::cpu.inst 274105779 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 43663267 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 317769046 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 274105779 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 274105779 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 6894251 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6894251 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 274105779 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 50557518 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 324663297 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 0 # Total number of read requests seen
-system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 0 # Total number of bytes read from memory
-system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
-system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 0 # Total gap between requests
-system.physmem.readPktSize::0 0 # Categorize read packet sizes
-system.physmem.readPktSize::1 0 # Categorize read packet sizes
-system.physmem.readPktSize::2 0 # Categorize read packet sizes
-system.physmem.readPktSize::3 0 # Categorize read packet sizes
-system.physmem.readPktSize::4 0 # Categorize read packet sizes
-system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # Categorize write packet sizes
-system.physmem.writePktSize::1 0 # Categorize write packet sizes
-system.physmem.writePktSize::2 0 # Categorize write packet sizes
-system.physmem.writePktSize::3 0 # Categorize write packet sizes
-system.physmem.writePktSize::4 0 # Categorize write packet sizes
-system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 0 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
-system.physmem.totBusLat 0 # Total cycles spent in databus access
-system.physmem.totBankLat 0 # Total cycles spent in bank access
-system.physmem.avgQLat nan # Average queueing delay per request
-system.physmem.avgBankLat nan # Average bank access latency per request
-system.physmem.avgBusLat nan # Average bus latency per request
-system.physmem.avgMemAccLat nan # Average memory access latency
-system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 0.00 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 0 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate nan # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap nan # Average gap between requests
-system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory
-system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory
-system.rom.bytes_read::total 1128688 # Number of bytes read from this memory
-system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory
-system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory
-system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory
-system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory
-system.rom.num_reads::total 195123 # Number of read requests responded to by this memory
-system.rom.bw_read::cpu.inst 193527 # Total read bandwidth from this memory (bytes/s)
-system.rom.bw_read::cpu.data 311755 # Total read bandwidth from this memory (bytes/s)
-system.rom.bw_read::total 505282 # Total read bandwidth from this memory (bytes/s)
-system.rom.bw_inst_read::cpu.inst 193527 # Instruction read bandwidth from this memory (bytes/s)
-system.rom.bw_inst_read::total 193527 # Instruction read bandwidth from this memory (bytes/s)
-system.rom.bw_total::cpu.inst 193527 # Total bandwidth to/from this memory (bytes/s)
-system.rom.bw_total::cpu.data 311755 # Total bandwidth to/from this memory (bytes/s)
-system.rom.bw_total::total 505282 # Total bandwidth to/from this memory (bytes/s)
-system.physmem2.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory
-system.physmem2.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory
-system.physmem2.bytes_read::total 9813991967 # Number of bytes read from this memory
-system.physmem2.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory
-system.physmem2.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory
-system.physmem2.bytes_written::cpu.data 897268422 # Number of bytes written to this memory
-system.physmem2.bytes_written::total 897268422 # Number of bytes written to this memory
-system.physmem2.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory
-system.physmem2.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory
-system.physmem2.num_reads::total 2403489130 # Number of read requests responded to by this memory
-system.physmem2.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory
-system.physmem2.num_writes::total 187387796 # Number of write requests responded to by this memory
-system.physmem2.num_other::cpu.data 5403067 # Number of other requests responded to by this memory
-system.physmem2.num_other::total 5403067 # Number of other requests responded to by this memory
-system.physmem2.bw_read::cpu.inst 3723784842 # Total read bandwidth from this memory (bytes/s)
-system.physmem2.bw_read::cpu.data 669666123 # Total read bandwidth from this memory (bytes/s)
-system.physmem2.bw_read::total 4393450966 # Total read bandwidth from this memory (bytes/s)
-system.physmem2.bw_inst_read::cpu.inst 3723784842 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem2.bw_inst_read::total 3723784842 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem2.bw_write::cpu.data 401682091 # Write bandwidth from this memory (bytes/s)
-system.physmem2.bw_write::total 401682091 # Write bandwidth from this memory (bytes/s)
-system.physmem2.bw_total::cpu.inst 3723784842 # Total bandwidth to/from this memory (bytes/s)
-system.physmem2.bw_total::cpu.data 1071348214 # Total bandwidth to/from this memory (bytes/s)
-system.physmem2.bw_total::total 4795133057 # Total bandwidth to/from this memory (bytes/s)
-system.physmem2.readReqs 0 # Total number of read requests seen
-system.physmem2.writeReqs 0 # Total number of write requests seen
-system.physmem2.cpureqs 0 # Reqs generatd by CPU via cache - shady
-system.physmem2.bytesRead 0 # Total number of bytes read from memory
-system.physmem2.bytesWritten 0 # Total number of bytes written to memory
-system.physmem2.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
-system.physmem2.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-system.physmem2.servicedByWrQ 0 # Number of read reqs serviced by write Q
-system.physmem2.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem2.perBankRdReqs::0 0 # Track reads on a per bank basis
-system.physmem2.perBankRdReqs::1 0 # Track reads on a per bank basis
-system.physmem2.perBankRdReqs::2 0 # Track reads on a per bank basis
-system.physmem2.perBankRdReqs::3 0 # Track reads on a per bank basis
-system.physmem2.perBankRdReqs::4 0 # Track reads on a per bank basis
-system.physmem2.perBankRdReqs::5 0 # Track reads on a per bank basis
-system.physmem2.perBankRdReqs::6 0 # Track reads on a per bank basis
-system.physmem2.perBankRdReqs::7 0 # Track reads on a per bank basis
-system.physmem2.perBankRdReqs::8 0 # Track reads on a per bank basis
-system.physmem2.perBankRdReqs::9 0 # Track reads on a per bank basis
-system.physmem2.perBankRdReqs::10 0 # Track reads on a per bank basis
-system.physmem2.perBankRdReqs::11 0 # Track reads on a per bank basis
-system.physmem2.perBankRdReqs::12 0 # Track reads on a per bank basis
-system.physmem2.perBankRdReqs::13 0 # Track reads on a per bank basis
-system.physmem2.perBankRdReqs::14 0 # Track reads on a per bank basis
-system.physmem2.perBankRdReqs::15 0 # Track reads on a per bank basis
-system.physmem2.perBankWrReqs::0 0 # Track writes on a per bank basis
-system.physmem2.perBankWrReqs::1 0 # Track writes on a per bank basis
-system.physmem2.perBankWrReqs::2 0 # Track writes on a per bank basis
-system.physmem2.perBankWrReqs::3 0 # Track writes on a per bank basis
-system.physmem2.perBankWrReqs::4 0 # Track writes on a per bank basis
-system.physmem2.perBankWrReqs::5 0 # Track writes on a per bank basis
-system.physmem2.perBankWrReqs::6 0 # Track writes on a per bank basis
-system.physmem2.perBankWrReqs::7 0 # Track writes on a per bank basis
-system.physmem2.perBankWrReqs::8 0 # Track writes on a per bank basis
-system.physmem2.perBankWrReqs::9 0 # Track writes on a per bank basis
-system.physmem2.perBankWrReqs::10 0 # Track writes on a per bank basis
-system.physmem2.perBankWrReqs::11 0 # Track writes on a per bank basis
-system.physmem2.perBankWrReqs::12 0 # Track writes on a per bank basis
-system.physmem2.perBankWrReqs::13 0 # Track writes on a per bank basis
-system.physmem2.perBankWrReqs::14 0 # Track writes on a per bank basis
-system.physmem2.perBankWrReqs::15 0 # Track writes on a per bank basis
-system.physmem2.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem2.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem2.totGap 0 # Total gap between requests
-system.physmem2.readPktSize::0 0 # Categorize read packet sizes
-system.physmem2.readPktSize::1 0 # Categorize read packet sizes
-system.physmem2.readPktSize::2 0 # Categorize read packet sizes
-system.physmem2.readPktSize::3 0 # Categorize read packet sizes
-system.physmem2.readPktSize::4 0 # Categorize read packet sizes
-system.physmem2.readPktSize::5 0 # Categorize read packet sizes
-system.physmem2.readPktSize::6 0 # Categorize read packet sizes
-system.physmem2.writePktSize::0 0 # Categorize write packet sizes
-system.physmem2.writePktSize::1 0 # Categorize write packet sizes
-system.physmem2.writePktSize::2 0 # Categorize write packet sizes
-system.physmem2.writePktSize::3 0 # Categorize write packet sizes
-system.physmem2.writePktSize::4 0 # Categorize write packet sizes
-system.physmem2.writePktSize::5 0 # Categorize write packet sizes
-system.physmem2.writePktSize::6 0 # Categorize write packet sizes
-system.physmem2.rdQLenPdf::0 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::1 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::2 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::3 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem2.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem2.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem2.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem2.totQLat 0 # Total cycles spent in queuing delays
-system.physmem2.totMemAccLat 0 # Sum of mem lat for all requests
-system.physmem2.totBusLat 0 # Total cycles spent in databus access
-system.physmem2.totBankLat 0 # Total cycles spent in bank access
-system.physmem2.avgQLat nan # Average queueing delay per request
-system.physmem2.avgBankLat nan # Average bank access latency per request
-system.physmem2.avgBusLat nan # Average bus latency per request
-system.physmem2.avgMemAccLat nan # Average memory access latency
-system.physmem2.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
-system.physmem2.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem2.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
-system.physmem2.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
-system.physmem2.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem2.busUtil 0.00 # Data bus utilization in percentage
-system.physmem2.avgRdQLen 0.00 # Average read queue length over time
-system.physmem2.avgWrQLen 0.00 # Average write queue length over time
-system.physmem2.readRowHits 0 # Number of row buffer hits during reads
-system.physmem2.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem2.readRowHitRate nan # Row buffer hit rate for reads
-system.physmem2.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem2.avgGap nan # Average gap between requests
-system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory
-system.nvram.bytes_read::total 284 # Number of bytes read from this memory
-system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory
-system.nvram.bytes_written::total 92 # Number of bytes written to this memory
-system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory
-system.nvram.num_reads::total 284 # Number of read requests responded to by this memory
-system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory
-system.nvram.num_writes::total 92 # Number of write requests responded to by this memory
-system.nvram.bw_read::cpu.data 127 # Total read bandwidth from this memory (bytes/s)
-system.nvram.bw_read::total 127 # Total read bandwidth from this memory (bytes/s)
-system.nvram.bw_write::cpu.data 41 # Write bandwidth from this memory (bytes/s)
-system.nvram.bw_write::total 41 # Write bandwidth from this memory (bytes/s)
-system.nvram.bw_total::cpu.data 168 # Total bandwidth to/from this memory (bytes/s)
-system.nvram.bw_total::total 168 # Total bandwidth to/from this memory (bytes/s)
-system.cpu.numCycles 2233777513 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 2228284650 # Number of instructions committed
-system.cpu.committedOps 2229160714 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1839325658 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 14608322 # Number of float alu accesses
-system.cpu.num_func_calls 44037246 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 316367761 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1839325658 # number of integer instructions
-system.cpu.num_fp_insts 14608322 # number of float instructions
-system.cpu.num_int_register_reads 4305540407 # number of times the integer registers were read
-system.cpu.num_int_register_writes 2100562807 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 35401841 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 22917558 # number of times the floating registers were written
-system.cpu.num_mem_refs 547951940 # number of memory refs
-system.cpu.num_load_insts 349807670 # Number of load instructions
-system.cpu.num_store_insts 198144270 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 2233777513 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-
----------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.269669 # Number of seconds simulated
-sim_ticks 269668883500 # Number of ticks simulated
-final_tick 269668883500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.269772 # Number of seconds simulated
+sim_ticks 269771922500 # Number of ticks simulated
+final_tick 269771922500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 49435 # Simulator instruction rate (inst/s)
-host_op_rate 49435 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 22150100 # Simulator tick rate (ticks/s)
-host_mem_usage 271532 # Number of bytes of host memory used
-host_seconds 12174.61 # Real time elapsed on the host
+host_inst_rate 152624 # Simulator instruction rate (inst/s)
+host_op_rate 152624 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 68411173 # Simulator tick rate (ticks/s)
+host_mem_usage 225196 # Number of bytes of host memory used
+host_seconds 3943.39 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
system.physmem.num_reads::total 26294 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1014 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1014 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 199593 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 6040712 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 6240305 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 199593 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 199593 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 240651 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 240651 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 240651 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 199593 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 6040712 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6480955 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 199517 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 6038405 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 6237921 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 199517 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 199517 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 240559 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 240559 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 240559 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 199517 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 6038405 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6478480 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 26294 # Total number of read requests seen
system.physmem.writeReqs 1014 # Total number of write requests seen
system.physmem.cpureqs 27308 # Reqs generatd by CPU via cache - shady
system.physmem.bytesConsumedWr 64896 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 1624 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 1652 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 1674 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 1676 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 1610 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 1558 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 1549 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 1582 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 1650 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 1710 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 1645 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 1640 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 1713 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 1657 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 1668 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 1672 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 60 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 59 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 66 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 66 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 56 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 51 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 49 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 50 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 58 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 74 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 59 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 70 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 78 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::0 1672 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 1579 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 1690 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 1680 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1732 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 1719 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 1812 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 1867 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1778 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1570 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1650 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 1658 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 1444 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1431 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1493 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 1505 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 63 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 49 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 70 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 71 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 74 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 70 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 82 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 95 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 79 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 54 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 64 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 89 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 35 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 33 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 38 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 48 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 269668831500 # Total gap between requests
+system.physmem.totGap 269771850500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 1014 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 16677 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 6779 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 1891 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 928 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 17534 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 6823 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 1475 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 445 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 37 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 44 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 383236250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 1095312500 # Sum of mem lat for all requests
+system.physmem.bytesPerActivate::samples 8692 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 200.548550 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 81.216882 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 827.235747 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 7745 89.10% 89.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 118 1.36% 90.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 74 0.85% 91.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 56 0.64% 91.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 40 0.46% 92.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 23 0.26% 92.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 20 0.23% 92.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 390 4.49% 97.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 4 0.05% 97.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 9 0.10% 97.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 7 0.08% 97.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 6 0.07% 97.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 2 0.02% 97.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 4 0.05% 97.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 7 0.08% 97.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 4 0.05% 97.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 3 0.03% 97.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 2 0.02% 97.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 1 0.01% 97.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 9 0.10% 98.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 1 0.01% 98.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 2 0.02% 98.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1473 4 0.05% 98.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 2 0.02% 98.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1665 1 0.01% 98.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1729 2 0.02% 98.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1793 3 0.03% 98.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1857 4 0.05% 98.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1921 3 0.03% 98.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1985 4 0.05% 98.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2113 3 0.03% 98.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2177 1 0.01% 98.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2241 2 0.02% 98.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2305 3 0.03% 98.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2369 1 0.01% 98.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2689 2 0.02% 98.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2753 2 0.02% 98.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2817 2 0.02% 98.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2881 1 0.01% 98.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2945 2 0.02% 98.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3073 4 0.05% 98.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3329 2 0.02% 98.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3457 2 0.02% 98.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3585 2 0.02% 98.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3713 1 0.01% 98.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840-3841 1 0.01% 98.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4033 1 0.01% 98.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4096-4097 1 0.01% 98.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4352-4353 1 0.01% 98.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4480-4481 2 0.02% 98.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4544-4545 3 0.03% 98.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4608-4609 1 0.01% 98.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4864-4865 3 0.03% 98.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4928-4929 1 0.01% 98.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5312-5313 1 0.01% 98.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5376-5377 1 0.01% 98.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5440-5441 2 0.02% 98.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5568-5569 1 0.01% 98.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5760-5761 1 0.01% 98.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5888-5889 2 0.02% 98.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5952-5953 1 0.01% 98.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6080-6081 1 0.01% 98.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6144-6145 2 0.02% 99.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6272-6273 2 0.02% 99.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6720-6721 4 0.05% 99.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6784-6785 1 0.01% 99.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6912-6913 2 0.02% 99.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7296-7297 1 0.01% 99.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7488-7489 1 0.01% 99.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7616-7617 1 0.01% 99.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7680-7681 44 0.51% 99.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7744-7745 9 0.10% 99.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7808-7809 5 0.06% 99.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7936-7937 1 0.01% 99.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8128-8129 2 0.02% 99.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 11 0.13% 99.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8576-8577 2 0.02% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 8692 # Bytes accessed per row activation
+system.physmem.totQLat 332225750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 999160750 # Sum of mem lat for all requests
system.physmem.totBusLat 131400000 # Total cycles spent in databus access
-system.physmem.totBankLat 580676250 # Total cycles spent in bank access
-system.physmem.avgQLat 14582.81 # Average queueing delay per request
-system.physmem.avgBankLat 22095.75 # Average bank access latency per request
+system.physmem.totBankLat 535535000 # Total cycles spent in bank access
+system.physmem.avgQLat 12641.77 # Average queueing delay per request
+system.physmem.avgBankLat 20378.04 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 41678.56 # Average memory access latency
+system.physmem.avgMemAccLat 38019.82 # Average memory access latency
system.physmem.avgRdBW 6.24 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 6.24 # Average consumed read bandwidth in MB/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 12.19 # Average write queue length over time
-system.physmem.readRowHits 16315 # Number of row buffer hits during reads
-system.physmem.writeRowHits 296 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 62.08 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 29.19 # Row buffer hit rate for writes
-system.physmem.avgGap 9875085.38 # Average gap between requests
-system.cpu.branchPred.lookups 86401588 # Number of BP lookups
-system.cpu.branchPred.condPredicted 81471319 # Number of conditional branches predicted
+system.physmem.readRowHits 18015 # Number of row buffer hits during reads
+system.physmem.writeRowHits 585 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 68.55 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 57.69 # Row buffer hit rate for writes
+system.physmem.avgGap 9878857.86 # Average gap between requests
+system.membus.throughput 6478480 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 4966 # Transaction distribution
+system.membus.trans_dist::ReadResp 4966 # Transaction distribution
+system.membus.trans_dist::Writeback 1014 # Transaction distribution
+system.membus.trans_dist::ReadExReq 21328 # Transaction distribution
+system.membus.trans_dist::ReadExResp 21328 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 53602 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 53602 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1747712 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 1747712 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 1747712 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 40219500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 248608250 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.cpu.branchPred.lookups 86401392 # Number of BP lookups
+system.cpu.branchPred.condPredicted 81471121 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 36340860 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 45048223 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 34648139 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 45048026 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 34648141 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 76.913442 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 76.913783 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1197609 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 114517866 # DTB read hits
+system.cpu.dtb.read_hits 114525360 # DTB read hits
system.cpu.dtb.read_misses 2631 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 114520497 # DTB read accesses
-system.cpu.dtb.write_hits 39453488 # DTB write hits
+system.cpu.dtb.read_accesses 114527991 # DTB read accesses
+system.cpu.dtb.write_hits 39455215 # DTB write hits
system.cpu.dtb.write_misses 2302 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 39455790 # DTB write accesses
-system.cpu.dtb.data_hits 153971354 # DTB hits
+system.cpu.dtb.write_accesses 39457517 # DTB write accesses
+system.cpu.dtb.data_hits 153980575 # DTB hits
system.cpu.dtb.data_misses 4933 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 153976287 # DTB accesses
+system.cpu.dtb.data_accesses 153985508 # DTB accesses
system.cpu.itb.fetch_hits 24966979 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 539337768 # number of cpu cycles simulated
+system.cpu.numCycles 539543846 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.predictedTaken 37213741 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 49187847 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 541069811 # Number of Reads from Int. Register File
+system.cpu.branch_predictor.predictedTaken 37213743 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken 49187649 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 541069671 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 463854846 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 1004924657 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses 1004924517 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 162 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 42 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 204 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 255160339 # Number of Registers Read Through Forwarding Logic
+system.cpu.regfile_manager.regForwards 255160482 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 154930401 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 34118747 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 2217126 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 36335873 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 26212045 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 58.092858 # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions 412134920 # Number of Instructions Executed.
+system.cpu.execution_unit.executions 412134922 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 6482 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 535759851 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 535782792 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 296128 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 50805895 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 488531873 # Number of cycles cpu stages are processed.
-system.cpu.activity 90.579949 # Percentage of cycles cpu is active
+system.cpu.timesIdled 294264 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 51002909 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 488540937 # Number of cycles cpu stages are processed.
+system.cpu.activity 90.547032 # Percentage of cycles cpu is active
system.cpu.comLoads 114514042 # Number of Load instructions committed
system.cpu.comStores 39451321 # Number of Store instructions committed
system.cpu.comBranches 62547159 # Number of Branches instructions committed
system.cpu.committedOps 601856964 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 601856964 # Number of Instructions committed (Total)
-system.cpu.cpi 0.896123 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 0.896465 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 0.896123 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.115918 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 0.896465 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.115492 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 1.115918 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 200608412 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 338729356 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 62.804679 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 228909431 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 310428337 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 57.557315 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 197773731 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 341564037 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 63.330265 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 427958956 # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 111378812 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 20.651031 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 192540057 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 346797711 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 64.300654 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total 1.115492 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 200810173 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 338733673 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 62.781491 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 229113520 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 310430326 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 57.535700 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 197979216 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 341564630 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 63.306186 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 428164340 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 111379506 # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 20.643272 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 192742225 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 346801621 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 64.276819 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 30 # number of replacements
-system.cpu.icache.tagsinuse 729.833568 # Cycle average of tags in use
-system.cpu.icache.total_refs 24965946 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 729.672642 # Cycle average of tags in use
+system.cpu.icache.total_refs 24965940 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 855 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 29199.936842 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 29199.929825 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 729.833568 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.356364 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.356364 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 24965946 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 24965946 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 24965946 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 24965946 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 24965946 # number of overall hits
-system.cpu.icache.overall_hits::total 24965946 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1033 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1033 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1033 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1033 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1033 # number of overall misses
-system.cpu.icache.overall_misses::total 1033 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 55677000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 55677000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 55677000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 55677000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 55677000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 55677000 # number of overall miss cycles
+system.cpu.icache.occ_blocks::cpu.inst 729.672642 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.356285 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.356285 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 24965940 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 24965940 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 24965940 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 24965940 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 24965940 # number of overall hits
+system.cpu.icache.overall_hits::total 24965940 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1039 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1039 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1039 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1039 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1039 # number of overall misses
+system.cpu.icache.overall_misses::total 1039 # number of overall misses
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69407.407771 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69042.794934 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 451299 # number of replacements
-system.cpu.dcache.tagsinuse 4093.423663 # Cycle average of tags in use
-system.cpu.dcache.total_refs 151786149 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 4093.048176 # Cycle average of tags in use
+system.cpu.dcache.total_refs 151792699 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 333.306578 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 332192000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4093.423663 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999371 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999371 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 114120800 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 114120800 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 37665349 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 37665349 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 151786149 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 151786149 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 151786149 # number of overall hits
-system.cpu.dcache.overall_hits::total 151786149 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 393242 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 393242 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1785972 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1785972 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2179214 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2179214 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2179214 # number of overall misses
-system.cpu.dcache.overall_misses::total 2179214 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 5984700000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 5984700000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 23169621500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 23169621500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 29154321500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 29154321500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 29154321500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 29154321500 # number of overall miss cycles
+system.cpu.dcache.avg_refs 333.320961 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 382930000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4093.048176 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999279 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999279 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 114127941 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 114127941 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 37664758 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 37664758 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 151792699 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 151792699 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 151792699 # number of overall hits
+system.cpu.dcache.overall_hits::total 151792699 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 386101 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 386101 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1786563 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1786563 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 2172664 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2172664 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2172664 # number of overall misses
+system.cpu.dcache.overall_misses::total 2172664 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 6056986500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 6056986500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 25183645000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 25183645000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 31240631500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 31240631500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 31240631500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 31240631500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003434 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.003434 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045270 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.045270 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.014154 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.014154 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.014154 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.014154 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15218.872857 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15218.872857 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12973.115760 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 12973.115760 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 13378.365548 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 13378.365548 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 13378.365548 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 13378.365548 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 191067 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 560 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 6052 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.570886 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 62.222222 # average number of cycles each access was blocked
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003372 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.003372 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045285 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.045285 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.014111 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.014111 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.014111 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.014111 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15687.570092 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15687.570092 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14096.141586 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 14096.141586 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14378.952061 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 14378.952061 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14378.952061 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 14378.952061 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 376840 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 954 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 17814 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.154148 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 95.400000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks
system.cpu.dcache.writebacks::total 436887 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 192010 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 192010 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1531809 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1531809 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1723819 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1723819 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1723819 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1723819 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 184869 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 184869 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1532400 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1532400 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1717269 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1717269 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1717269 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1717269 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643678500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643678500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3782203500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3782203500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6425882000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6425882000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6425882000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6425882000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2727636001 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2727636001 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4113048000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4113048000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6840684001 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6840684001 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6840684001 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6840684001 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13137.465711 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13137.465711 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14881.015333 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14881.015333 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14110.567749 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 14110.567749 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14110.567749 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 14110.567749 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13554.683157 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13554.683157 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16182.717390 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16182.717390 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15021.429750 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 15021.429750 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15021.429750 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 15021.429750 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.133697 # Number of seconds simulated
-sim_ticks 133696809500 # Number of ticks simulated
-final_tick 133696809500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.133885 # Number of seconds simulated
+sim_ticks 133884967500 # Number of ticks simulated
+final_tick 133884967500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 77616 # Simulator instruction rate (inst/s)
-host_op_rate 77616 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 18348551 # Simulator tick rate (ticks/s)
-host_mem_usage 272684 # Number of bytes of host memory used
-host_seconds 7286.51 # Real time elapsed on the host
+host_inst_rate 162173 # Simulator instruction rate (inst/s)
+host_op_rate 162173 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 38391719 # Simulator tick rate (ticks/s)
+host_mem_usage 228276 # Number of bytes of host memory used
+host_seconds 3487.34 # Real time elapsed on the host
sim_insts 565552443 # Number of instructions simulated
sim_ops 565552443 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 61120 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1636544 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1697664 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 61120 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 61120 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 67072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 67072 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 955 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 25571 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 26526 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1048 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1048 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 457154 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 12240711 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 12697865 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 457154 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 457154 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 501672 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 501672 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 501672 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 457154 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 12240711 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 13199537 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 26526 # Total number of read requests seen
-system.physmem.writeReqs 1048 # Total number of write requests seen
-system.physmem.cpureqs 27574 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 1697664 # Total number of bytes read from memory
-system.physmem.bytesWritten 67072 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 1697664 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 67072 # bytesWritten derated as per pkt->getSize()
+system.physmem.bytes_read::cpu.inst 61056 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1636160 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1697216 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 61056 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 61056 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 66944 # Number of bytes written to this memory
+system.physmem.bytes_written::total 66944 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 954 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 25565 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 26519 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1046 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1046 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 456033 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 12220640 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 12676673 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 456033 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 456033 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 500011 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 500011 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 500011 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 456033 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 12220640 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 13176685 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 26519 # Total number of read requests seen
+system.physmem.writeReqs 1046 # Total number of write requests seen
+system.physmem.cpureqs 27565 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1697216 # Total number of bytes read from memory
+system.physmem.bytesWritten 66944 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 1697216 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 66944 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 1631 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 1662 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 1680 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 1686 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 1627 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 1603 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 1584 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 1608 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 1666 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 1722 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 1648 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 1646 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 1723 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 1665 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 1676 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 1684 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 60 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 60 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 68 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 66 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 56 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 58 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 53 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 56 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 64 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 75 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 63 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 60 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 83 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 73 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 72 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 81 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::0 1674 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 1678 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 1699 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 1688 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1739 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 1730 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 1813 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 1871 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1787 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1570 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1661 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 1675 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 1459 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1440 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1505 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 1515 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 64 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 61 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 71 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 72 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 74 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 73 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 82 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 95 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 80 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 54 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 65 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 90 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 35 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 34 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 44 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 52 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 133696776000 # Total gap between requests
+system.physmem.totGap 133884902000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 26526 # Categorize read packet sizes
+system.physmem.readPktSize::6 26519 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 1048 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 9044 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 11316 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 5069 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1070 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1046 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 11989 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 9624 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 4320 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 566 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 37 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 42 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 44 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 46 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 46 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 46 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 46 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 45 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 45 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 45 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 652146750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 1350583000 # Sum of mem lat for all requests
-system.physmem.totBusLat 132555000 # Total cycles spent in databus access
-system.physmem.totBankLat 565881250 # Total cycles spent in bank access
-system.physmem.avgQLat 24599.10 # Average queueing delay per request
-system.physmem.avgBankLat 21345.15 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 8244 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 213.286754 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 86.643190 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 848.319386 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 6744 81.80% 81.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 612 7.42% 89.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 105 1.27% 90.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 71 0.86% 91.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 43 0.52% 91.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 25 0.30% 92.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 16 0.19% 92.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 389 4.72% 97.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 10 0.12% 97.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 9 0.11% 97.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 3 0.04% 97.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 3 0.04% 97.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 5 0.06% 97.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 8 0.10% 97.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 9 0.11% 97.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 7 0.08% 97.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 5 0.06% 97.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 3 0.04% 97.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 7 0.08% 97.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 6 0.07% 98.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 4 0.05% 98.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 2 0.02% 98.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1473 2 0.02% 98.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 2 0.02% 98.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 1 0.01% 98.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1729 1 0.01% 98.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1793 3 0.04% 98.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1857 4 0.05% 98.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1921 4 0.05% 98.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2049 1 0.01% 98.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2177 2 0.02% 98.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2241 2 0.02% 98.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2305 2 0.02% 98.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2369 3 0.04% 98.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2497 1 0.01% 98.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2625 2 0.02% 98.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2753 2 0.02% 98.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2817 1 0.01% 98.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2881 1 0.01% 98.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2945 1 0.01% 98.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3073 1 0.01% 98.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3201 2 0.02% 98.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3265 1 0.01% 98.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3329 1 0.01% 98.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3393 2 0.02% 98.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3457 2 0.02% 98.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520-3521 1 0.01% 98.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648-3649 1 0.01% 98.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3713 1 0.01% 98.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840-3841 1 0.01% 98.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4033 1 0.01% 98.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4096-4097 1 0.01% 98.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4160-4161 2 0.02% 98.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4352-4353 2 0.02% 98.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4416-4417 1 0.01% 98.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4544-4545 1 0.01% 98.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4736-4737 1 0.01% 98.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4864-4865 1 0.01% 98.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4928-4929 1 0.01% 98.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5184-5185 3 0.04% 98.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5312-5313 1 0.01% 98.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5376-5377 1 0.01% 98.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5440-5441 1 0.01% 98.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5760-5761 1 0.01% 98.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5888-5889 1 0.01% 98.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6016-6017 1 0.01% 98.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6144-6145 1 0.01% 98.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6272-6273 2 0.02% 98.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6464-6465 1 0.01% 98.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6720-6721 6 0.07% 99.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6784-6785 1 0.01% 99.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6912-6913 1 0.01% 99.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7488-7489 1 0.01% 99.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7552-7553 2 0.02% 99.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7680-7681 43 0.52% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7744-7745 11 0.13% 99.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7808-7809 4 0.05% 99.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7936-7937 1 0.01% 99.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8128-8129 3 0.04% 99.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 13 0.16% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 8244 # Bytes accessed per row activation
+system.physmem.totQLat 457304500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 1107883250 # Sum of mem lat for all requests
+system.physmem.totBusLat 132520000 # Total cycles spent in databus access
+system.physmem.totBankLat 518058750 # Total cycles spent in bank access
+system.physmem.avgQLat 17254.17 # Average queueing delay per request
+system.physmem.avgBankLat 19546.44 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 50944.25 # Average memory access latency
-system.physmem.avgRdBW 12.70 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 41800.61 # Average memory access latency
+system.physmem.avgRdBW 12.68 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.50 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 12.70 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 12.68 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.50 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.10 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 9.33 # Average write queue length over time
-system.physmem.readRowHits 16975 # Number of row buffer hits during reads
-system.physmem.writeRowHits 275 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 64.03 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 26.24 # Row buffer hit rate for writes
-system.physmem.avgGap 4848653.66 # Average gap between requests
-system.cpu.branchPred.lookups 76441752 # Number of BP lookups
-system.cpu.branchPred.condPredicted 70864410 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 2706781 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 43062122 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 41938047 # Number of BTB hits
+system.physmem.avgWrQLen 7.87 # Average write queue length over time
+system.physmem.readRowHits 18718 # Number of row buffer hits during reads
+system.physmem.writeRowHits 577 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 70.62 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 55.16 # Row buffer hit rate for writes
+system.physmem.avgGap 4857061.56 # Average gap between requests
+system.membus.throughput 13176685 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 5255 # Transaction distribution
+system.membus.trans_dist::ReadResp 5255 # Transaction distribution
+system.membus.trans_dist::Writeback 1046 # Transaction distribution
+system.membus.trans_dist::ReadExReq 21264 # Transaction distribution
+system.membus.trans_dist::ReadExResp 21264 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 54084 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 54084 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1764160 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 1764160 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 1764160 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 40437500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 246430250 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.cpu.branchPred.lookups 76481142 # Number of BP lookups
+system.cpu.branchPred.condPredicted 70905485 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2712830 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 43152568 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 41951176 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.389643 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1605813 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 97.215943 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1604071 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 238 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 122608255 # DTB read hits
-system.cpu.dtb.read_misses 28801 # DTB read misses
+system.cpu.dtb.read_hits 122621956 # DTB read hits
+system.cpu.dtb.read_misses 28776 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 122637056 # DTB read accesses
-system.cpu.dtb.write_hits 40754827 # DTB write hits
-system.cpu.dtb.write_misses 25617 # DTB write misses
-system.cpu.dtb.write_acv 1 # DTB write access violations
-system.cpu.dtb.write_accesses 40780444 # DTB write accesses
-system.cpu.dtb.data_hits 163363082 # DTB hits
-system.cpu.dtb.data_misses 54418 # DTB misses
-system.cpu.dtb.data_acv 1 # DTB access violations
-system.cpu.dtb.data_accesses 163417500 # DTB accesses
-system.cpu.itb.fetch_hits 65484737 # ITB hits
+system.cpu.dtb.read_accesses 122650732 # DTB read accesses
+system.cpu.dtb.write_hits 40755113 # DTB write hits
+system.cpu.dtb.write_misses 25625 # DTB write misses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 40780738 # DTB write accesses
+system.cpu.dtb.data_hits 163377069 # DTB hits
+system.cpu.dtb.data_misses 54401 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 163431470 # DTB accesses
+system.cpu.itb.fetch_hits 65530786 # ITB hits
system.cpu.itb.fetch_misses 41 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 65484778 # ITB accesses
+system.cpu.itb.fetch_accesses 65530827 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 267393620 # number of cpu cycles simulated
+system.cpu.numCycles 267769936 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 67132788 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 699091920 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 76441752 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 43543860 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 117791826 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 11623941 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 73287443 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1199 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 65484737 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 927172 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 267096777 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.617373 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.445045 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 67189108 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 699431830 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 76481142 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 43555247 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 117843991 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 11666830 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 73504935 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 68 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1313 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 19 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 65530786 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 931341 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 267451900 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.615169 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.444449 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 149304951 55.90% 55.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 10344865 3.87% 59.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 11847519 4.44% 64.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 10566772 3.96% 68.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 7010837 2.62% 70.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2867971 1.07% 71.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 3579531 1.34% 73.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 3103336 1.16% 74.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 68470995 25.64% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 149607909 55.94% 55.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 10348918 3.87% 59.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 11847203 4.43% 64.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 10573344 3.95% 68.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 7008253 2.62% 70.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2869794 1.07% 71.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 3587132 1.34% 73.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 3111076 1.16% 74.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 68498271 25.61% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 267096777 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.285877 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.614467 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 84255179 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 57589844 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 102698571 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 13670600 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 8882583 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3874487 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 931 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 691126555 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 3231 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 8882583 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 92229912 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 12770086 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 1212 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 103061748 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 50151236 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 680987279 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 426 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 38480754 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 5456693 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 520711815 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 896998441 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 896995902 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 2539 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 267451900 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.285623 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.612063 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 84322843 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 57802490 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 102700565 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 13714405 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 8911597 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3873381 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 948 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 691440481 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 3137 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 8911597 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 92312573 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 12823003 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 1534 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 103090752 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 50312441 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 681258889 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 435 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 38630282 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 5470230 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 520856634 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 897283230 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 897280730 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 2500 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 463854889 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 56856926 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 56 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 61 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 112143528 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 126973457 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 42377854 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 14839100 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 10235293 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 621082747 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 48 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 604577802 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 299631 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 54891737 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 29918454 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 31 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 267096777 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.263516 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.822324 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 57001745 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 66 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 72 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 112491401 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 126996487 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 42388542 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 14811954 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 10030949 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 621209385 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 604684391 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 299599 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 55017699 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 29989465 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 267451900 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.260909 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.823825 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 52289348 19.58% 19.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 55783537 20.89% 40.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 53427937 20.00% 60.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 36631888 13.71% 74.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 31292246 11.72% 85.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 23678415 8.87% 94.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 10025583 3.75% 98.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3414414 1.28% 99.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 553409 0.21% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 52525807 19.64% 19.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 56031435 20.95% 40.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 53465406 19.99% 60.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 36379699 13.60% 74.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 31195818 11.66% 85.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 23840953 8.91% 94.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 10047725 3.76% 98.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3411796 1.28% 99.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 553261 0.21% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 267096777 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 267451900 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 2692091 70.58% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 42 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 70.58% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 729838 19.13% 89.71% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 392410 10.29% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 2753778 71.24% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 45 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.24% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 726781 18.80% 90.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 385136 9.96% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 439064264 72.62% 72.62% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 7069 0.00% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 439140797 72.62% 72.62% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 7079 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 6 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 72.62% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 72.62% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 124327148 20.56% 93.19% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 41179273 6.81% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 124346650 20.56% 93.19% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 41189817 6.81% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 604577802 # Type of FU issued
-system.cpu.iq.rate 2.261003 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 3814381 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006309 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1480362706 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 675977802 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 596495784 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 3687 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 2189 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 1715 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 608390320 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 1863 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 12281051 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 604684391 # Type of FU issued
+system.cpu.iq.rate 2.258224 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 3865740 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.006393 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1480982314 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 676230303 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 596557394 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 3707 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 2213 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 1724 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 608548258 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 1873 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 12279987 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 12459415 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 35750 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 5512 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2926533 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 12482445 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 36037 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 5437 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 2937221 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 6468 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 56300 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 6392 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 65545 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 8882583 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1439479 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 190555 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 663921502 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1696631 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 126973457 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 42377854 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 142659 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 7414 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 5512 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1334753 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1804223 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 3138976 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 599473269 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 122637223 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 5104533 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 8911597 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1457895 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 191973 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 664097895 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 1705444 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 126996487 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 42388542 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 56 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 144321 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 7199 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 5437 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1338458 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1807769 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 3146227 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 599553495 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 122650887 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 5130896 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 42838707 # number of nop insts executed
-system.cpu.iew.exec_refs 163435917 # number of memory reference insts executed
-system.cpu.iew.exec_branches 66623579 # Number of branches executed
-system.cpu.iew.exec_stores 40798694 # Number of stores executed
-system.cpu.iew.exec_rate 2.241913 # Inst execution rate
-system.cpu.iew.wb_sent 597432372 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 596497499 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 415924305 # num instructions producing a value
-system.cpu.iew.wb_consumers 530247239 # num instructions consuming a value
+system.cpu.iew.exec_nop 42888454 # number of nop insts executed
+system.cpu.iew.exec_refs 163450221 # number of memory reference insts executed
+system.cpu.iew.exec_branches 66634078 # Number of branches executed
+system.cpu.iew.exec_stores 40799334 # Number of stores executed
+system.cpu.iew.exec_rate 2.239062 # Inst execution rate
+system.cpu.iew.wb_sent 597495724 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 596559118 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 415919830 # num instructions producing a value
+system.cpu.iew.wb_consumers 530239470 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.230784 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.784397 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.227879 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.784400 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 61940872 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 62116663 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 2705903 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 258214194 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.330844 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.692748 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 2711961 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 258540303 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.327904 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.691623 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 79436879 30.76% 30.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 72473576 28.07% 58.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 25624236 9.92% 68.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 9154468 3.55% 72.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 10267531 3.98% 76.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 21039855 8.15% 84.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 6818360 2.64% 87.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3702360 1.43% 88.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 29696929 11.50% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 79687582 30.82% 30.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 72573675 28.07% 58.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 25533783 9.88% 68.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 9229698 3.57% 72.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 10307338 3.99% 76.33% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 20995746 8.12% 84.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 6840090 2.65% 87.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3701122 1.43% 88.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 29671269 11.48% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 258214194 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 258540303 # Number of insts commited each cycle
system.cpu.commit.committedInsts 601856963 # Number of instructions committed
system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 1520 # Number of committed floating point instructions.
system.cpu.commit.int_insts 563954763 # Number of committed integer instructions.
system.cpu.commit.function_calls 1197610 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 29696929 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 29671269 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 892250711 # The number of ROB reads
-system.cpu.rob.rob_writes 1336492363 # The number of ROB writes
-system.cpu.timesIdled 34289 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 296843 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 892778271 # The number of ROB reads
+system.cpu.rob.rob_writes 1336872912 # The number of ROB writes
+system.cpu.timesIdled 34547 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 318036 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
system.cpu.committedOps 565552443 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
-system.cpu.cpi 0.472801 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.472801 # CPI: Total CPI of All Threads
-system.cpu.ipc 2.115056 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 2.115056 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 844981893 # number of integer regfile reads
-system.cpu.int_regfile_writes 490535855 # number of integer regfile writes
-system.cpu.fp_regfile_reads 379 # number of floating regfile reads
+system.cpu.cpi 0.473466 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.473466 # CPI: Total CPI of All Threads
+system.cpu.ipc 2.112083 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 2.112083 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 845093769 # number of integer regfile reads
+system.cpu.int_regfile_writes 490581182 # number of integer regfile writes
+system.cpu.fp_regfile_reads 382 # number of floating regfile reads
system.cpu.fp_regfile_writes 54 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.icache.replacements 39 # number of replacements
-system.cpu.icache.tagsinuse 825.626517 # Cycle average of tags in use
-system.cpu.icache.total_refs 65483355 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 973 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 67300.467626 # Average number of references to valid blocks.
+system.cpu.toL2Bus.throughput 435443419 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 211400 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 211400 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 444967 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 254560 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 254560 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1944 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1374943 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 1376887 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62208 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 58237120 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 58299328 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 58299328 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 900430500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1458499 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 697482499 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
+system.cpu.icache.replacements 40 # number of replacements
+system.cpu.icache.tagsinuse 824.576664 # Cycle average of tags in use
+system.cpu.icache.total_refs 65529394 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 972 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 67417.072016 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 825.626517 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.403138 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.403138 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 65483355 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 65483355 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 65483355 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 65483355 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 65483355 # number of overall hits
-system.cpu.icache.overall_hits::total 65483355 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1381 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1381 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1381 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1381 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1381 # number of overall misses
-system.cpu.icache.overall_misses::total 1381 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 73729000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 73729000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 73729000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 73729000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 73729000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 73729000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 65484736 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 65484736 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 65484736 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 65484736 # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total 65484736 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 824.576664 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.402625 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.402625 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 65529394 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 65529394 # number of ReadReq hits
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+system.cpu.icache.overall_hits::total 65529394 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1391 # number of ReadReq misses
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+system.cpu.icache.overall_misses::total 1391 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 90149500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 90149500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 90149500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 90149500 # number of demand (read+write) miss cycles
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+system.cpu.icache.overall_miss_latency::total 90149500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 65530785 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 65530785 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total 65530785 # number of demand (read+write) accesses
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+system.cpu.icache.overall_accesses::total 65530785 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000021 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000021 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000021 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000021 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000021 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000021 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53388.124547 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 53388.124547 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 53388.124547 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 53388.124547 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 53388.124547 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 53388.124547 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 166 # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64809.130122 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 64809.130122 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 64809.130122 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 64809.130122 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 64809.130122 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 64809.130122 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 350 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 33.200000 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 58.333333 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 408 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 408 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 408 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 408 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 408 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 408 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 973 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 973 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 973 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 973 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 973 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 973 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54179000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 54179000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54179000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 54179000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54179000 # number of overall MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003105 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.003105 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12819.570238 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12819.570238 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16127.399352 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16127.399352 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14630.193979 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 14630.193979 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14630.193979 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 14630.193979 # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006453 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006453 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.003106 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003106 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.003106 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12874.320437 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12874.320437 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17119.663305 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17119.663305 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15198.454567 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 15198.454567 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15198.454567 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 15198.454567 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 300930958000 # Number of ticks simulated
final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2641824 # Simulator instruction rate (inst/s)
-host_op_rate 2641824 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1320922836 # Simulator tick rate (ticks/s)
-host_mem_usage 264040 # Number of bytes of host memory used
-host_seconds 227.82 # Real time elapsed on the host
+host_inst_rate 3984763 # Simulator instruction rate (inst/s)
+host_op_rate 3984763 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1992397518 # Simulator tick rate (ticks/s)
+host_mem_usage 217612 # Number of bytes of host memory used
+host_seconds 151.04 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 2407447588 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7999999747 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1755262561 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9755262308 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 9755262308 # Throughput (bytes/s)
+system.membus.data_through_bus 2935660432 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
sim_ticks 762403375000 # Number of ticks simulated
final_tick 762403375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1151537 # Simulator instruction rate (inst/s)
-host_op_rate 1151537 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1458711281 # Simulator tick rate (ticks/s)
-host_mem_usage 272496 # Number of bytes of host memory used
-host_seconds 522.66 # Real time elapsed on the host
+host_inst_rate 1417339 # Simulator instruction rate (inst/s)
+host_op_rate 1417339 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1795416637 # Simulator tick rate (ticks/s)
+host_mem_usage 225056 # Number of bytes of host memory used
+host_seconds 424.64 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 65729 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2136486 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2286664 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 2286664 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 4910 # Transaction distribution
+system.membus.trans_dist::ReadResp 4910 # Transaction distribution
+system.membus.trans_dist::Writeback 1006 # Transaction distribution
+system.membus.trans_dist::ReadExReq 21324 # Transaction distribution
+system.membus.trans_dist::ReadExResp 21324 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 53474 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 53474 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1743360 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 1743360 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 1743360 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 35288000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 236106000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 74969406 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 202027 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 202027 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 436887 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 254163 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 254163 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1590 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1347677 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 1349267 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50880 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 57106048 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 57156928 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 57156928 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 883425500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1192500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 683092500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.164563 # Number of seconds simulated
-sim_ticks 164562530500 # Number of ticks simulated
-final_tick 164562530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.164717 # Number of seconds simulated
+sim_ticks 164716794500 # Number of ticks simulated
+final_tick 164716794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 62422 # Simulator instruction rate (inst/s)
-host_op_rate 65960 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 18020016 # Simulator tick rate (ticks/s)
-host_mem_usage 288128 # Number of bytes of host memory used
-host_seconds 9132.21 # Real time elapsed on the host
+host_inst_rate 131424 # Simulator instruction rate (inst/s)
+host_op_rate 138873 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 37975042 # Simulator tick rate (ticks/s)
+host_mem_usage 246336 # Number of bytes of host memory used
+host_seconds 4337.50 # Real time elapsed on the host
sim_insts 570051585 # Number of instructions simulated
sim_ops 602359791 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 46976 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1701120 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1748096 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 46976 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 46976 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 47232 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1701568 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1748800 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 47232 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 47232 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 162368 # Number of bytes written to this memory
system.physmem.bytes_written::total 162368 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 734 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 26580 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 27314 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 738 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 26587 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 27325 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 2537 # Number of write requests responded to by this memory
system.physmem.num_writes::total 2537 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 285460 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 10337226 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 10622685 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 285460 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 285460 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 986664 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 986664 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 986664 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 285460 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 10337226 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 11609350 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 27315 # Total number of read requests seen
+system.physmem.bw_read::cpu.inst 286747 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 10330264 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 10617011 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 286747 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 286747 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 985740 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 985740 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 985740 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 286747 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 10330264 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 11602751 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 27326 # Total number of read requests seen
system.physmem.writeReqs 2537 # Total number of write requests seen
-system.physmem.cpureqs 29852 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 1748096 # Total number of bytes read from memory
+system.physmem.cpureqs 29863 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1748800 # Total number of bytes read from memory
system.physmem.bytesWritten 162368 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 1748096 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 1748800 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 162368 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 1691 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 1726 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 1689 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 1687 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 1721 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 1753 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 1671 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 1696 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 1674 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 1668 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 1702 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 1735 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 1759 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 1740 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 1723 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 1680 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 161 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 158 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 158 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 159 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 158 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 156 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 157 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 158 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 156 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 157 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 160 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 163 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 162 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 160 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 157 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::0 1621 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 1642 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 1738 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 1816 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1755 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 1757 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 1715 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 1788 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1779 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1795 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1657 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 1653 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 1640 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1650 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1673 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 1647 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 155 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 156 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 161 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 166 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 164 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 157 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 158 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 163 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 163 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 162 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 155 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 154 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 153 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 155 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 157 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 158 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 164562514500 # Total gap between requests
+system.physmem.totGap 164716777500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 27315 # Categorize read packet sizes
+system.physmem.readPktSize::6 27326 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 2537 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 14709 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 3454 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 8340 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 806 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 15477 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 2877 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 8554 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 414 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 71 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 93 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 40 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 18 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 922192000 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 1672085750 # Sum of mem lat for all requests
-system.physmem.totBusLat 136575000 # Total cycles spent in databus access
-system.physmem.totBankLat 613318750 # Total cycles spent in bank access
-system.physmem.avgQLat 33761.38 # Average queueing delay per request
-system.physmem.avgBankLat 22453.55 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 9336 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 204.188518 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 86.332799 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 802.540236 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 7834 83.91% 83.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 317 3.40% 87.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 190 2.04% 89.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 83 0.89% 90.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 60 0.64% 90.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 70 0.75% 91.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 60 0.64% 92.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 493 5.28% 97.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 6 0.06% 97.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 7 0.07% 97.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 3 0.03% 97.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 4 0.04% 97.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 3 0.03% 97.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 4 0.04% 97.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 5 0.05% 97.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 7 0.07% 97.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 5 0.05% 98.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 5 0.05% 98.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 4 0.04% 98.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 6 0.06% 98.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 1 0.01% 98.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 2 0.02% 98.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 1 0.01% 98.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 4 0.04% 98.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1665 3 0.03% 98.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1729 1 0.01% 98.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1793 2 0.02% 98.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1857 2 0.02% 98.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1921 7 0.07% 98.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1985 2 0.02% 98.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2049 2 0.02% 98.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2177 4 0.04% 98.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2241 1 0.01% 98.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2305 1 0.01% 98.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2369 1 0.01% 98.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2433 1 0.01% 98.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2753 1 0.01% 98.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2817 1 0.01% 98.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2945 5 0.05% 98.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3009 1 0.01% 98.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3073 3 0.03% 98.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3137 1 0.01% 98.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3201 4 0.04% 98.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3265 2 0.02% 98.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3457 1 0.01% 98.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3585 1 0.01% 98.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3968-3969 6 0.06% 98.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4224-4225 7 0.07% 98.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4544-4545 2 0.02% 98.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4864-4865 1 0.01% 98.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4928-4929 1 0.01% 98.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4992-4993 4 0.04% 98.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5056-5057 2 0.02% 99.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5120-5121 2 0.02% 99.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5248-5249 4 0.04% 99.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5824-5825 1 0.01% 99.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5952-5953 2 0.02% 99.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6016-6017 3 0.03% 99.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6144-6145 2 0.02% 99.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6208-6209 1 0.01% 99.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6272-6273 6 0.06% 99.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6912-6913 1 0.01% 99.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6976-6977 1 0.01% 99.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7040-7041 4 0.04% 99.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7296-7297 1 0.01% 99.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8064-8065 3 0.03% 99.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8128-8129 1 0.01% 99.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 60 0.64% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 9336 # Bytes accessed per row activation
+system.physmem.totQLat 724618250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 1428985750 # Sum of mem lat for all requests
+system.physmem.totBusLat 136630000 # Total cycles spent in databus access
+system.physmem.totBankLat 567737500 # Total cycles spent in bank access
+system.physmem.avgQLat 26517.54 # Average queueing delay per request
+system.physmem.avgBankLat 20776.46 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 61214.93 # Average memory access latency
+system.physmem.avgMemAccLat 52294.00 # Average memory access latency
system.physmem.avgRdBW 10.62 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.99 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 10.62 # Average consumed read bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.09 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 5.61 # Average write queue length over time
-system.physmem.readRowHits 16878 # Number of row buffer hits during reads
-system.physmem.writeRowHits 1046 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 61.79 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 41.23 # Row buffer hit rate for writes
-system.physmem.avgGap 5512612.71 # Average gap between requests
-system.cpu.branchPred.lookups 85150983 # Number of BP lookups
-system.cpu.branchPred.condPredicted 79934550 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 2340692 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 47125153 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 46874770 # Number of BTB hits
+system.physmem.avgWrQLen 5.04 # Average write queue length over time
+system.physmem.readRowHits 18612 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1908 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 68.11 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 75.21 # Row buffer hit rate for writes
+system.physmem.avgGap 5515747.83 # Average gap between requests
+system.membus.throughput 11602751 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 5535 # Transaction distribution
+system.membus.trans_dist::ReadResp 5534 # Transaction distribution
+system.membus.trans_dist::Writeback 2537 # Transaction distribution
+system.membus.trans_dist::ReadExReq 21791 # Transaction distribution
+system.membus.trans_dist::ReadExResp 21791 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 57188 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 57188 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1911168 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 1911168 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 1911168 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 59882500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 257832500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.cpu.branchPred.lookups 85149850 # Number of BP lookups
+system.cpu.branchPred.condPredicted 79935034 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2341119 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 47171100 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 46877755 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.468685 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1426734 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1006 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 99.378126 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1426315 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1039 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 48 # Number of system calls
-system.cpu.numCycles 329125062 # number of cpu cycles simulated
+system.cpu.numCycles 329433590 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 68488081 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 666859732 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 85150983 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 48301504 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 129623989 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 13095310 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 119330996 # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles 68491080 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 666869934 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 85149850 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 48304070 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 129626718 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 13098656 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 119406737 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 265 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 67073182 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 755353 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 328169942 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.165410 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.193997 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 278 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 67075214 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 755042 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 328254094 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.164915 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.193789 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 198546194 60.50% 60.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 20910126 6.37% 66.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 4967453 1.51% 68.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 14343462 4.37% 72.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 8888191 2.71% 75.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 9444820 2.88% 78.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 4399595 1.34% 79.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 5788141 1.76% 81.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 60881960 18.55% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 198627609 60.51% 60.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 20909439 6.37% 66.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 4965485 1.51% 68.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 14345312 4.37% 72.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 8888539 2.71% 75.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 9448384 2.88% 78.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 4398392 1.34% 79.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 5788124 1.76% 81.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 60882810 18.55% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 328169942 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.258719 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.026159 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 92898933 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 96237751 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 107895398 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 20412735 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 10725125 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 4735181 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 1555 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 703255584 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 5767 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 10725125 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 107098247 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 14386106 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 39798 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 114033717 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 81886949 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 694825042 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 45 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 59412332 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 20333868 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 677 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 721309974 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3230585653 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3230585525 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 328254094 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.258473 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.024292 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 92927462 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 96288420 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 107921370 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 20389102 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 10727740 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 4734116 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 1608 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 703272688 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 6032 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 10727740 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 107129786 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 14463787 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 40672 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 114031737 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 81860372 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 694842750 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 61 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 59365311 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 20352093 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 658 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 721318867 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3230668466 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3230668338 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 627417373 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 93892601 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1652 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1598 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 170754110 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 172203089 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 80461729 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 21612175 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 28771400 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 679988719 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2878 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 645594653 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1373062 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 77449325 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 193321568 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 174 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 328169942 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.967257 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.725062 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 93901494 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1663 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1606 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 170675033 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 172203367 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 80466872 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 21668199 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 28984539 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 680005400 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2870 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 645602000 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1370838 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 77464153 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 193377702 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 166 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 328254094 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.966775 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.724168 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 68186439 20.78% 20.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 85247300 25.98% 46.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 75946350 23.14% 69.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 40813735 12.44% 82.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 28838397 8.79% 91.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 14924394 4.55% 95.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 5564389 1.70% 97.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 6539948 1.99% 99.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 2108990 0.64% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 68222380 20.78% 20.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 85248644 25.97% 46.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 76005248 23.15% 69.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 40782290 12.42% 82.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 28865696 8.79% 91.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 14929305 4.55% 95.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 5554109 1.69% 97.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 6609349 2.01% 99.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 2037073 0.62% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 328169942 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 328254094 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 216923 5.73% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 2702396 71.39% 77.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 865914 22.88% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 217031 5.77% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 2685741 71.41% 77.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 858362 22.82% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 403371824 62.48% 62.48% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 6559 0.00% 62.48% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 403375767 62.48% 62.48% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 6562 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.48% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.48% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 165561293 25.64% 88.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 76654974 11.87% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 165561645 25.64% 88.13% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 76658023 11.87% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 645594653 # Type of FU issued
-system.cpu.iq.rate 1.961548 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 3785233 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.005863 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1624517507 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 757453052 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 637549292 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 645602000 # Type of FU issued
+system.cpu.iq.rate 1.959733 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 3761134 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.005826 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1624590030 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 757484567 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 637551440 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 649379866 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 649363114 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 30368159 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 30365020 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 23250496 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 123413 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 12359 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 10240716 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 23250774 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 122077 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 12388 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 10245859 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 12899 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 36224 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 12881 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 36063 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 10725125 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 795867 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 92517 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 679994676 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 687635 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 172203089 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 80461729 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1550 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 32824 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 16429 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 12359 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1356301 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1461196 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 2817497 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 641509024 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 163485499 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 4085629 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 10727740 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 829837 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 90327 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 680011324 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 689748 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 172203367 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 80466872 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1542 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 33020 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 14329 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 12388 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1357418 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1460538 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 2817956 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 641515531 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 163488286 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 4086469 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 3079 # number of nop insts executed
-system.cpu.iew.exec_refs 239366742 # number of memory reference insts executed
-system.cpu.iew.exec_branches 74672084 # Number of branches executed
-system.cpu.iew.exec_stores 75881243 # Number of stores executed
-system.cpu.iew.exec_rate 1.949135 # Inst execution rate
-system.cpu.iew.wb_sent 638953926 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 637549308 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 418527294 # num instructions producing a value
-system.cpu.iew.wb_consumers 649860425 # num instructions consuming a value
+system.cpu.iew.exec_nop 3054 # number of nop insts executed
+system.cpu.iew.exec_refs 239371647 # number of memory reference insts executed
+system.cpu.iew.exec_branches 74671273 # Number of branches executed
+system.cpu.iew.exec_stores 75883361 # Number of stores executed
+system.cpu.iew.exec_rate 1.947329 # Inst execution rate
+system.cpu.iew.wb_sent 638961836 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 637551456 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 418605320 # num instructions producing a value
+system.cpu.iew.wb_consumers 649951687 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.937103 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.644026 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.935296 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.644056 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 77643008 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 77660016 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2704 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 2339215 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 317444817 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.897526 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.237559 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 2339596 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 317526354 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.897039 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.237311 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 93252713 29.38% 29.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 104341557 32.87% 62.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 42984071 13.54% 75.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 8786627 2.77% 78.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 25947006 8.17% 86.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 12913913 4.07% 90.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 7624115 2.40% 93.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1170537 0.37% 93.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 20424278 6.43% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 93315961 29.39% 29.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 104358414 32.87% 62.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 42989043 13.54% 75.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 8780083 2.77% 78.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 25952112 8.17% 86.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 12911096 4.07% 90.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 7631938 2.40% 93.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 1174119 0.37% 93.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 20413588 6.43% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 317444817 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 317526354 # Number of insts commited each cycle
system.cpu.commit.committedInsts 570051636 # Number of instructions committed
system.cpu.commit.committedOps 602359842 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 533522631 # Number of committed integer instructions.
system.cpu.commit.function_calls 997573 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 20424278 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 20413588 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 977022777 # The number of ROB reads
-system.cpu.rob.rob_writes 1370762747 # The number of ROB writes
-system.cpu.timesIdled 43954 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 955120 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 977132012 # The number of ROB reads
+system.cpu.rob.rob_writes 1370799549 # The number of ROB writes
+system.cpu.timesIdled 46711 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 1179496 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 570051585 # Number of Instructions Simulated
system.cpu.committedOps 602359791 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 570051585 # Number of Instructions Simulated
-system.cpu.cpi 0.577360 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.577360 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.732021 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.732021 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3204272502 # number of integer regfile reads
-system.cpu.int_regfile_writes 663034338 # number of integer regfile writes
+system.cpu.cpi 0.577901 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.577901 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.730399 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.730399 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3204308856 # number of integer regfile reads
+system.cpu.int_regfile_writes 663036750 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 234758554 # number of misc regfile reads
+system.cpu.misc_regfile_reads 234764578 # number of misc regfile reads
system.cpu.misc_regfile_writes 2656 # number of misc regfile writes
-system.cpu.icache.replacements 49 # number of replacements
-system.cpu.icache.tagsinuse 688.587828 # Cycle average of tags in use
-system.cpu.icache.total_refs 67072069 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
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+system.cpu.dcache.demand_misses::total 3720449 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3720449 # number of overall misses
+system.cpu.dcache.overall_misses::total 3720449 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 5118261000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 5118261000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 44228568380 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 44228568380 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 392500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 392500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 49346829380 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 49346829380 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 49346829380 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 49346829380 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 131860086 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 131860086 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1348 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 1348 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1346 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 1346 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 201271526 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 201271526 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 201271526 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 201271526 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002591 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.002591 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048547 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.048547 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.016320 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016320 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.018441 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.018441 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.018441 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.018441 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14823.490935 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14823.490935 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12079.285112 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 12079.285112 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15363.636364 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15363.636364 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12331.904777 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12331.904777 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12331.904777 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12331.904777 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 146535 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 32 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 5250 # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 201277617 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 201277617 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 201277617 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 201277617 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002592 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.002592 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.048671 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.048671 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017088 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017088 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.018484 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.018484 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.018484 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.018484 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14974.125749 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14974.125749 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13090.634752 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 13090.634752 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17065.217391 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17065.217391 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 13263.675804 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 13263.675804 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 13263.675804 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 13263.675804 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 148047 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 158 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 5424 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.911429 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 27.294801 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 39.500000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 421641 # number of writebacks
-system.cpu.dcache.writebacks::total 421641 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144151 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 144151 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3122863 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 3122863 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 22 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3267014 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3267014 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3267014 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3267014 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197534 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 197534 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247174 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 247174 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 444708 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 444708 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 444708 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 444708 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2832398000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2832398000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4097760821 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4097760821 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6930158821 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6930158821 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6930158821 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6930158821 # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks 421602 # number of writebacks
+system.cpu.dcache.writebacks::total 421602 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 144306 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 144306 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3131471 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 3131471 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 23 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 23 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3275777 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3275777 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3275777 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3275777 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197501 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 197501 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247171 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 247171 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 444672 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 444672 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 444672 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 444672 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2858072011 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2858072011 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4363789439 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4363789439 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7221861450 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7221861450 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7221861450 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7221861450 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001498 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001498 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003561 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002209 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14338.787247 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14338.787247 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16578.446038 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16578.446038 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15583.616263 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 15583.616263 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15583.616263 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 15583.616263 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14471.177417 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14471.177417 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17654.941069 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17654.941069 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16240.872936 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 16240.872936 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16240.872936 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16240.872936 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 301191365000 # Number of ticks simulated
final_tick 301191365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1714897 # Simulator instruction rate (inst/s)
-host_op_rate 1812090 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 906079333 # Simulator tick rate (ticks/s)
-host_mem_usage 278712 # Number of bytes of host memory used
-host_seconds 332.41 # Real time elapsed on the host
+host_inst_rate 1664644 # Simulator instruction rate (inst/s)
+host_op_rate 1758990 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 879528148 # Simulator tick rate (ticks/s)
+host_mem_usage 233480 # Number of bytes of host memory used
+host_seconds 342.45 # Real time elapsed on the host
sim_insts 570051636 # Number of instructions simulated
sim_ops 602359842 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 2280298100 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7570927872 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2112350170 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9683278042 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 9683278042 # Throughput (bytes/s)
+system.membus.data_through_bus 2916519731 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
sim_ticks 793670137000 # Number of ticks simulated
final_tick 793670137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 904187 # Simulator instruction rate (inst/s)
-host_op_rate 954854 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1262227313 # Simulator tick rate (ticks/s)
-host_mem_usage 287296 # Number of bytes of host memory used
-host_seconds 628.79 # Real time elapsed on the host
+host_inst_rate 583678 # Simulator instruction rate (inst/s)
+host_op_rate 616385 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 814802699 # Simulator tick rate (ticks/s)
+host_mem_usage 241980 # Number of bytes of host memory used
+host_seconds 974.06 # Real time elapsed on the host
sim_insts 568539335 # Number of instructions simulated
sim_ops 600398272 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 38592 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 48625 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2110539 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2360195 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 2360195 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 4941 # Transaction distribution
+system.membus.trans_dist::ReadResp 4941 # Transaction distribution
+system.membus.trans_dist::Writeback 2493 # Transaction distribution
+system.membus.trans_dist::ReadExReq 21835 # Transaction distribution
+system.membus.trans_dist::ReadExResp 21835 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 56045 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 56045 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1873216 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 1873216 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 1873216 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 49213000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 240984000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 69093329 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 190459 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 190459 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 418626 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 247748 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 247748 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1286 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1293754 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 1295040 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 41152 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 54796160 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 54837312 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 54837312 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 847042500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 964500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 656346000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.387291 # Number of seconds simulated
-sim_ticks 387290918500 # Number of ticks simulated
-final_tick 387290918500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.387399 # Number of seconds simulated
+sim_ticks 387398892000 # Number of ticks simulated
+final_tick 387398892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 75176 # Simulator instruction rate (inst/s)
-host_op_rate 75413 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 20778674 # Simulator tick rate (ticks/s)
-host_mem_usage 280588 # Number of bytes of host memory used
-host_seconds 18638.87 # Real time elapsed on the host
+host_inst_rate 157866 # Simulator instruction rate (inst/s)
+host_op_rate 158364 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 43646663 # Simulator tick rate (ticks/s)
+host_mem_usage 236680 # Number of bytes of host memory used
+host_seconds 8875.80 # Real time elapsed on the host
sim_insts 1401188945 # Number of instructions simulated
sim_ops 1405604139 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 76672 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1678656 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1755328 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 76672 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 76672 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory
-system.physmem.bytes_written::total 162112 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1198 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 26229 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 27427 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 197970 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 4334354 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4532324 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 197970 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 197970 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 418579 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 418579 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 418579 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 197970 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4334354 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4950904 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 27428 # Total number of read requests seen
-system.physmem.writeReqs 2533 # Total number of write requests seen
-system.physmem.cpureqs 29961 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 1755328 # Total number of bytes read from memory
-system.physmem.bytesWritten 162112 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 1755328 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize()
+system.physmem.bytes_read::cpu.inst 76288 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1678592 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1754880 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 76288 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 76288 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 162048 # Number of bytes written to this memory
+system.physmem.bytes_written::total 162048 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 1192 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 26228 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 27420 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 2532 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 2532 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 196924 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 4332981 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4529905 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 196924 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 196924 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 418298 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 418298 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 418298 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 196924 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4332981 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4948202 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 27421 # Total number of read requests seen
+system.physmem.writeReqs 2532 # Total number of write requests seen
+system.physmem.cpureqs 29953 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1754880 # Total number of bytes read from memory
+system.physmem.bytesWritten 162048 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 1754880 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 162048 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 1660 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 1716 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 1723 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 1743 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 1702 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 1708 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 1721 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 1696 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 1770 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 1765 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 1770 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 1755 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 1736 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 1674 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 1661 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 1628 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 157 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 155 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 162 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 157 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 160 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 156 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 157 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 157 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 162 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 165 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 160 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 161 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 160 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 157 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 154 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 153 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::0 1884 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 1775 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 1871 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 1665 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1646 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 1602 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 1689 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 1531 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1534 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1671 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1702 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 1701 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 1777 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1778 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1794 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 1801 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 168 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 163 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 167 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 156 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 152 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 149 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 158 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 148 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 150 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 155 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 159 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 158 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 161 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 163 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 163 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 162 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 387290890500 # Total gap between requests
+system.physmem.totGap 387398864000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 27428 # Categorize read packet sizes
+system.physmem.readPktSize::6 27421 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 2533 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 8079 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 13230 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 5144 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 974 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 2532 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 9983 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 11822 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 5095 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 520 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 88 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 107 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 97 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 110 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 23 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 716281750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 1441798000 # Sum of mem lat for all requests
-system.physmem.totBusLat 137140000 # Total cycles spent in databus access
-system.physmem.totBankLat 588376250 # Total cycles spent in bank access
-system.physmem.avgQLat 26114.98 # Average queueing delay per request
-system.physmem.avgBankLat 21451.66 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 9394 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 203.806685 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 84.980950 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 820.153394 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 8091 86.13% 86.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 139 1.48% 87.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 97 1.03% 88.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 115 1.22% 89.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 131 1.39% 91.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 46 0.49% 91.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 57 0.61% 92.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 495 5.27% 97.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 5 0.05% 97.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 8 0.09% 97.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 8 0.09% 97.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 6 0.06% 97.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 6 0.06% 97.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 3 0.03% 98.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 3 0.03% 98.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 5 0.05% 98.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 1 0.01% 98.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 1 0.01% 98.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 3 0.03% 98.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 7 0.07% 98.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 3 0.03% 98.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 3 0.03% 98.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1473 2 0.02% 98.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 2 0.02% 98.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1665 1 0.01% 98.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1729 1 0.01% 98.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1793 2 0.02% 98.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1857 3 0.03% 98.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1921 1 0.01% 98.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1985 3 0.03% 98.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2113 3 0.03% 98.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2177 1 0.01% 98.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2241 3 0.03% 98.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2305 2 0.02% 98.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2369 3 0.03% 98.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2433 2 0.02% 98.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2625 2 0.02% 98.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2689 1 0.01% 98.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2753 1 0.01% 98.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2817 3 0.03% 98.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2881 2 0.02% 98.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2945 1 0.01% 98.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3137 1 0.01% 98.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3201 2 0.02% 98.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3265 1 0.01% 98.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3329 1 0.01% 98.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520-3521 1 0.01% 98.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776-3777 1 0.01% 98.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840-3841 1 0.01% 98.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904-3905 2 0.02% 98.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3968-3969 1 0.01% 98.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4033 1 0.01% 98.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4160-4161 1 0.01% 98.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4224-4225 2 0.02% 98.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4288-4289 2 0.02% 98.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4352-4353 2 0.02% 98.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4544-4545 1 0.01% 98.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4864-4865 1 0.01% 98.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4928-4929 1 0.01% 98.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4992-4993 1 0.01% 98.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5248-5249 1 0.01% 98.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5312-5313 3 0.03% 98.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5376-5377 2 0.02% 99.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5504-5505 1 0.01% 99.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5824-5825 1 0.01% 99.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5888-5889 2 0.02% 99.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5952-5953 1 0.01% 99.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6080-6081 2 0.02% 99.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6336-6337 2 0.02% 99.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6400-6401 2 0.02% 99.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6848-6849 1 0.01% 99.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6912-6913 3 0.03% 99.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6976-6977 1 0.01% 99.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7296-7297 1 0.01% 99.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7360-7361 4 0.04% 99.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7424-7425 2 0.02% 99.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7744-7745 1 0.01% 99.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7936-7937 3 0.03% 99.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8128-8129 3 0.03% 99.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 63 0.67% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 9394 # Bytes accessed per row activation
+system.physmem.totQLat 539470500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 1246251750 # Sum of mem lat for all requests
+system.physmem.totBusLat 137105000 # Total cycles spent in databus access
+system.physmem.totBankLat 569676250 # Total cycles spent in bank access
+system.physmem.avgQLat 19673.63 # Average queueing delay per request
+system.physmem.avgBankLat 20775.18 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 52566.65 # Average memory access latency
+system.physmem.avgMemAccLat 45448.81 # Average memory access latency
system.physmem.avgRdBW 4.53 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.42 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 4.53 # Average consumed read bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 17.33 # Average write queue length over time
-system.physmem.readRowHits 17584 # Number of row buffer hits during reads
-system.physmem.writeRowHits 1051 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 64.11 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 41.49 # Row buffer hit rate for writes
-system.physmem.avgGap 12926500.80 # Average gap between requests
-system.cpu.branchPred.lookups 97760274 # Number of BP lookups
-system.cpu.branchPred.condPredicted 88050389 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 3615826 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 65794197 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 65495164 # Number of BTB hits
+system.physmem.avgWrQLen 16.43 # Average write queue length over time
+system.physmem.readRowHits 18651 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1906 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 68.02 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 75.28 # Row buffer hit rate for writes
+system.physmem.avgGap 12933558.04 # Average gap between requests
+system.membus.throughput 4948202 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 5633 # Transaction distribution
+system.membus.trans_dist::ReadResp 5632 # Transaction distribution
+system.membus.trans_dist::Writeback 2532 # Transaction distribution
+system.membus.trans_dist::ReadExReq 21788 # Transaction distribution
+system.membus.trans_dist::ReadExResp 21788 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 57373 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 57373 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1916928 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 1916928 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 1916928 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 57596000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 256936750 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.cpu.branchPred.lookups 97761890 # Number of BP lookups
+system.cpu.branchPred.condPredicted 88051950 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 3615398 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 65795011 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 65493795 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.545502 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1327 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 219 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 99.542190 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1333 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 221 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 49 # Number of system calls
-system.cpu.numCycles 774581838 # number of cpu cycles simulated
+system.cpu.numCycles 774797785 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 164861421 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1642294018 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 97760274 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 65496491 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 329212106 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 20844019 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 263270886 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 67 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 2530 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 161941896 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 736850 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 774347981 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.126883 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.146753 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 164870049 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1642248421 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 97761890 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 65495128 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 329214190 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 20840770 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 263425370 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 72 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 2796 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 36 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 161945451 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 735894 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 774503521 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.126508 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.146615 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 445135875 57.49% 57.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 74066133 9.56% 67.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 37898132 4.89% 71.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 9078559 1.17% 73.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 28105360 3.63% 76.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 18771878 2.42% 79.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 11487710 1.48% 80.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 3792341 0.49% 81.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 146011993 18.86% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 445289331 57.49% 57.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 74062894 9.56% 67.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 37897346 4.89% 71.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 9078563 1.17% 73.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 28105911 3.63% 76.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 18772818 2.42% 79.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 11485706 1.48% 80.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 3794812 0.49% 81.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 146016140 18.85% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 774347981 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.126210 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.120233 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 216009984 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 214299096 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 284224623 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 42813319 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 17000959 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 1636588191 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 17000959 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 239857670 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36775472 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 52409372 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 302053149 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 126251359 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 1625741176 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 144 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 30927043 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 73283464 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 3120923 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 1356412040 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 2746512805 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 2712406209 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 34106596 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 774503521 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.126177 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.119583 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 216045393 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 214430589 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 284206110 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 42830421 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 16991008 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 1636611354 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 16991008 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 239885098 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 36871695 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 52473274 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 302059993 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 126222453 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 1625714374 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 30924746 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 73227733 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 3172404 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 1356421780 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 2746534895 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 2712238159 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 34296736 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 111641601 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2643056 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2663342 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 271532800 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 436949673 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 179753673 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 254530912 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 83488154 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1512578374 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2608372 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1459383903 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 52245 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 109279211 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 130205744 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 364701 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 774347981 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.884662 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.431358 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 111651341 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2642938 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2663443 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 271529341 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 436963345 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 179743092 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 254343956 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 83161988 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 1512506564 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2608276 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1459339733 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 53312 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 109205745 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 130222811 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 364605 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 774503521 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.884226 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.431683 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 145644273 18.81% 18.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 184515384 23.83% 42.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 209689604 27.08% 69.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 131356597 16.96% 86.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 70636694 9.12% 95.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 20383529 2.63% 98.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8079794 1.04% 99.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3860513 0.50% 99.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 181593 0.02% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 145873373 18.83% 18.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 184398139 23.81% 42.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 209824996 27.09% 69.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 131195131 16.94% 86.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 70728709 9.13% 95.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 20383962 2.63% 98.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8004266 1.03% 99.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3913593 0.51% 99.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 181352 0.02% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 774347981 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 774503521 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 108798 6.48% 6.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 6.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 95504 5.69% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1157743 69.01% 81.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 315646 18.81% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 114122 6.75% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 6.75% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 97466 5.77% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1164668 68.90% 81.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 314034 18.58% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 866498027 59.37% 59.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 866437474 59.37% 59.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 59.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 59.37% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2644895 0.18% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.56% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 419117526 28.72% 88.27% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 171123455 11.73% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2644764 0.18% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 419138356 28.72% 88.27% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 171119139 11.73% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1459383903 # Type of FU issued
-system.cpu.iq.rate 1.884093 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1677691 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001150 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 3677006053 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 1615499463 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1443256661 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 17839670 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 9205608 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 8545927 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1451932919 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 9128675 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 215271062 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1459339733 # Type of FU issued
+system.cpu.iq.rate 1.883510 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1690290 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.001158 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 3677004243 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 1615280670 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1443165364 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 17922346 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 9279147 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 8546420 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1451856157 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 9173866 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 215403822 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 34436830 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 58273 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 245758 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 12905531 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 34450502 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 58568 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 246048 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 12894950 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 3343 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 99974 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 3290 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 138899 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 17000959 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 3021185 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 246438 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1608872021 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 4125769 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 436949673 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 179753673 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2525299 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 148197 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 1793 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 245758 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 2269874 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1473729 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 3743603 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1454064480 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 416571691 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 5319423 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 16991008 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 3096733 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 244441 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 1608794631 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 4137633 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 436963345 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 179743092 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 2525201 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 147095 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 1875 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 246048 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 2270642 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1473051 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 3743693 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1454012420 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 416588335 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 5327313 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 93685275 # number of nop insts executed
-system.cpu.iew.exec_refs 587019661 # number of memory reference insts executed
-system.cpu.iew.exec_branches 89035299 # Number of branches executed
-system.cpu.iew.exec_stores 170447970 # Number of stores executed
-system.cpu.iew.exec_rate 1.877225 # Inst execution rate
-system.cpu.iew.wb_sent 1452686018 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1451802588 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1153472607 # num instructions producing a value
-system.cpu.iew.wb_consumers 1204727325 # num instructions consuming a value
+system.cpu.iew.exec_nop 93679791 # number of nop insts executed
+system.cpu.iew.exec_refs 587032224 # number of memory reference insts executed
+system.cpu.iew.exec_branches 89032109 # Number of branches executed
+system.cpu.iew.exec_stores 170443889 # Number of stores executed
+system.cpu.iew.exec_rate 1.876635 # Inst execution rate
+system.cpu.iew.wb_sent 1452595352 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1451711784 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1153369073 # num instructions producing a value
+system.cpu.iew.wb_consumers 1204594740 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.874305 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.957455 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.873665 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.957475 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 119253312 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 119176384 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 3615826 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 757347022 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.966765 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.509958 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 3615398 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 757512513 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.966335 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.509470 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 240030131 31.69% 31.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 275730182 36.41% 68.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 42558160 5.62% 73.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 54684817 7.22% 80.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 19637761 2.59% 83.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 13291596 1.76% 85.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 30564343 4.04% 89.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 10573009 1.40% 90.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 70277023 9.28% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 240122511 31.70% 31.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 275742858 36.40% 68.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 42578645 5.62% 73.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 54721179 7.22% 80.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 19701382 2.60% 83.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 13286584 1.75% 85.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 30581396 4.04% 89.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 10490891 1.38% 90.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 70287067 9.28% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 757347022 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 757512513 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1485108088 # Number of instructions committed
system.cpu.commit.committedOps 1489523282 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 8452036 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1319476376 # Number of committed integer instructions.
system.cpu.commit.function_calls 1206914 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 70277023 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 70287067 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2295781723 # The number of ROB reads
-system.cpu.rob.rob_writes 3234577019 # The number of ROB writes
-system.cpu.timesIdled 25986 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 233857 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 2295860242 # The number of ROB reads
+system.cpu.rob.rob_writes 3234413109 # The number of ROB writes
+system.cpu.timesIdled 27770 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 294264 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1401188945 # Number of Instructions Simulated
system.cpu.committedOps 1405604139 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1401188945 # Number of Instructions Simulated
-system.cpu.cpi 0.552803 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.552803 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.808962 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.808962 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1979163604 # number of integer regfile reads
-system.cpu.int_regfile_writes 1275210426 # number of integer regfile writes
-system.cpu.fp_regfile_reads 16962684 # number of floating regfile reads
-system.cpu.fp_regfile_writes 10491940 # number of floating regfile writes
-system.cpu.misc_regfile_reads 592672173 # number of misc regfile reads
+system.cpu.cpi 0.552957 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.552957 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.808458 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.808458 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1979095871 # number of integer regfile reads
+system.cpu.int_regfile_writes 1275125772 # number of integer regfile writes
+system.cpu.fp_regfile_reads 16962854 # number of floating regfile reads
+system.cpu.fp_regfile_writes 10491602 # number of floating regfile writes
+system.cpu.misc_regfile_reads 592684666 # number of misc regfile reads
system.cpu.misc_regfile_writes 2190883 # number of misc regfile writes
-system.cpu.icache.replacements 197 # number of replacements
-system.cpu.icache.tagsinuse 1035.819290 # Cycle average of tags in use
-system.cpu.icache.total_refs 161939953 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 1338 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 121031.355007 # Average number of references to valid blocks.
+system.cpu.toL2Bus.throughput 150116939 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 202209 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 202208 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 444002 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 262464 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 262464 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2671 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1370676 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 1373347 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 85440 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 58069696 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 58155136 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 58155136 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 898339500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 2002500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 695005500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.cpu.icache.replacements 199 # number of replacements
+system.cpu.icache.tagsinuse 1032.766528 # Cycle average of tags in use
+system.cpu.icache.total_refs 161943463 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 1335 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 121305.964794 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1035.819290 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.505771 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.505771 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 161939953 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 161939953 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 161939953 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 161939953 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 161939953 # number of overall hits
-system.cpu.icache.overall_hits::total 161939953 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1943 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1943 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1943 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1943 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1943 # number of overall misses
-system.cpu.icache.overall_misses::total 1943 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 84888000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 84888000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 84888000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 84888000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 84888000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 84888000 # number of overall miss cycles
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+system.cpu.dcache.SwapReq_avg_miss_latency::total 20285.714286 # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 17333.995832 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 17333.995832 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 17333.995832 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 17333.995832 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 694627 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 46 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 38063 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.249402 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 46 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 443878 # number of writebacks
-system.cpu.dcache.writebacks::total 443878 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 721765 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 721765 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628742 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1628742 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 2350507 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 2350507 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 2350507 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 2350507 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200829 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 200829 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262415 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 262415 # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks 444002 # number of writebacks
+system.cpu.dcache.writebacks::total 444002 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 706801 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 706801 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1628976 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1628976 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 2335777 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 2335777 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2335777 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 2335777 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 200873 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 200873 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 262457 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 262457 # number of WriteReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses
system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 463244 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 463244 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 463244 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 463244 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2611858000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2611858000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4360853500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4360853500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 136000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::total 136000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6972711500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6972711500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6972711500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6972711500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000998 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000998 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data 463330 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 463330 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 463330 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 463330 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2643681500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2643681500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4650895000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4650895000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 128000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total 128000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7294576500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7294576500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7294576500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7294576500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000999 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001573 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.001259 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001259 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.001259 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13005.382689 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13005.382689 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16618.156355 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16618.156355 # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 19428.571429 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 19428.571429 # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15051.919723 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 15051.919723 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15051.919723 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 15051.919723 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13160.959910 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13160.959910 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17720.598041 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 17720.598041 # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 18285.714286 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 18285.714286 # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15743.803553 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 15743.803553 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15743.803553 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 15743.803553 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 744764112500 # Number of ticks simulated
final_tick 744764112500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2243211 # Simulator instruction rate (inst/s)
-host_op_rate 2249879 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1124943447 # Simulator tick rate (ticks/s)
-host_mem_usage 273192 # Number of bytes of host memory used
-host_seconds 662.05 # Real time elapsed on the host
+host_inst_rate 3917871 # Simulator instruction rate (inst/s)
+host_op_rate 3929519 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1964765726 # Simulator tick rate (ticks/s)
+host_mem_usage 224984 # Number of bytes of host memory used
+host_seconds 379.06 # Real time elapsed on the host
sim_insts 1485108088 # Number of instructions simulated
sim_ops 1489523282 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 5940451992 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7976286575 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2686071498 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10662358072 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 10662372316 # Throughput (bytes/s)
+system.membus.data_through_bus 7940952255 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 1489528226 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
sim_ticks 2061066313000 # Number of ticks simulated
final_tick 2061066313000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1083437 # Simulator instruction rate (inst/s)
-host_op_rate 1086658 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1503618533 # Simulator tick rate (ticks/s)
-host_mem_usage 281644 # Number of bytes of host memory used
-host_seconds 1370.74 # Real time elapsed on the host
+host_inst_rate 684045 # Simulator instruction rate (inst/s)
+host_op_rate 686079 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 949333559 # Simulator tick rate (ticks/s)
+host_mem_usage 233488 # Number of bytes of host memory used
+host_seconds 2171.07 # Real time elapsed on the host
sim_insts 1485108088 # Number of instructions simulated
sim_ops 1489523282 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 31642 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 811479 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 921310 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 921310 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 5293 # Transaction distribution
+system.membus.trans_dist::ReadResp 5293 # Transaction distribution
+system.membus.trans_dist::Writeback 2518 # Transaction distribution
+system.membus.trans_dist::ReadExReq 21859 # Transaction distribution
+system.membus.trans_dist::ReadExResp 21859 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 56822 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 56822 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 1898880 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 1898880 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 1898880 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 49814000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 244368000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 4122132626 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 27625902 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 194593 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 194593 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 435341 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 259735 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 259735 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 2214 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1341783 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 1343997 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 70848 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 56867968 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 56938816 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 56938816 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 880175500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1660500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 679831500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.602332 # Number of seconds simulated
-sim_ticks 602332345500 # Number of ticks simulated
-final_tick 602332345500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.602519 # Number of seconds simulated
+sim_ticks 602519213000 # Number of ticks simulated
+final_tick 602519213000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 59375 # Simulator instruction rate (inst/s)
-host_op_rate 109402 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 40639301 # Simulator tick rate (ticks/s)
-host_mem_usage 298404 # Number of bytes of host memory used
-host_seconds 14821.42 # Real time elapsed on the host
+host_inst_rate 94132 # Simulator instruction rate (inst/s)
+host_op_rate 173444 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 64448799 # Simulator tick rate (ticks/s)
+host_mem_usage 251596 # Number of bytes of host memory used
+host_seconds 9348.80 # Real time elapsed on the host
sim_insts 880025277 # Number of instructions simulated
sim_ops 1621493927 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 57280 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1693184 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 57152 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1693312 # Number of bytes read from this memory
system.physmem.bytes_read::total 1750464 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 57280 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 57280 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 162240 # Number of bytes written to this memory
-system.physmem.bytes_written::total 162240 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 895 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 26456 # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::cpu.inst 57152 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 57152 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 162112 # Number of bytes written to this memory
+system.physmem.bytes_written::total 162112 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 893 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 26458 # Number of read requests responded to by this memory
system.physmem.num_reads::total 27351 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 2535 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 2535 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 95097 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2811046 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2906143 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 95097 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 95097 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 269353 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 269353 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 269353 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 95097 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2811046 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3175496 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_writes::writebacks 2533 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 2533 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 94855 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2810387 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2905242 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 94855 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 94855 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 269057 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 269057 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 269057 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 94855 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2810387 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3174299 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 27351 # Total number of read requests seen
-system.physmem.writeReqs 2535 # Total number of write requests seen
-system.physmem.cpureqs 29886 # Reqs generatd by CPU via cache - shady
+system.physmem.writeReqs 2533 # Total number of write requests seen
+system.physmem.cpureqs 29884 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 1750464 # Total number of bytes read from memory
-system.physmem.bytesWritten 162240 # Total number of bytes written to memory
+system.physmem.bytesWritten 162112 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 1750464 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 162240 # bytesWritten derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 162112 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 1741 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 1716 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 1707 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 1642 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 1657 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 1659 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 1713 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 1703 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 1711 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 1703 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 1718 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 1725 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 1737 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 1725 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 1752 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 1742 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 159 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 161 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 160 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 155 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::0 1686 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 1661 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 1729 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 1834 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1605 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 1565 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 1603 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 1731 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1748 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1766 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1802 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 1763 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 1767 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1734 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1727 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 1630 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 157 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 157 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 161 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 168 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 155 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 155 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 158 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 158 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 156 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 160 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 158 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 159 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 159 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 158 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 164 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 160 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 147 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 150 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 159 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 161 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 161 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 162 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 162 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 162 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 160 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 159 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 152 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 602332206500 # Total gap between requests
+system.physmem.totGap 602519006000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 2535 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 26932 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 329 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 72 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 2533 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 26975 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 303 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 111 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 111 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 111 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 111 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 110 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 110 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 88037750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 893262750 # Sum of mem lat for all requests
+system.physmem.bytesPerActivate::samples 9709 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 196.647235 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 83.287733 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 790.384353 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 8486 87.40% 87.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 125 1.29% 88.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 100 1.03% 89.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 90 0.93% 90.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 83 0.85% 91.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 70 0.72% 92.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 47 0.48% 92.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 479 4.93% 97.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 8 0.08% 97.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 3 0.03% 97.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 4 0.04% 97.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 2 0.02% 97.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 5 0.05% 97.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 2 0.02% 97.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 8 0.08% 97.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 3 0.03% 98.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 9 0.09% 98.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 5 0.05% 98.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 3 0.03% 98.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 2 0.02% 98.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 4 0.04% 98.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 4 0.04% 98.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 3 0.03% 98.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 4 0.04% 98.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1665 3 0.03% 98.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1729 2 0.02% 98.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1793 1 0.01% 98.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1857 1 0.01% 98.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1985 5 0.05% 98.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2113 7 0.07% 98.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2177 2 0.02% 98.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2241 2 0.02% 98.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2433 2 0.02% 98.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2689 1 0.01% 98.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2817 1 0.01% 98.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2881 1 0.01% 98.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2945 1 0.01% 98.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3009 4 0.04% 98.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3137 4 0.04% 98.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3457 1 0.01% 98.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4033 9 0.09% 98.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4096-4097 1 0.01% 98.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4160-4161 13 0.13% 98.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4480-4481 1 0.01% 98.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4736-4737 1 0.01% 99.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4864-4865 1 0.01% 99.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5056-5057 3 0.03% 99.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5120-5121 1 0.01% 99.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5184-5185 5 0.05% 99.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5952-5953 2 0.02% 99.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6080-6081 4 0.04% 99.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6208-6209 5 0.05% 99.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6400-6401 1 0.01% 99.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6464-6465 1 0.01% 99.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6528-6529 1 0.01% 99.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6720-6721 1 0.01% 99.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6848-6849 2 0.02% 99.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7040-7041 1 0.01% 99.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7104-7105 4 0.04% 99.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7232-7233 2 0.02% 99.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7424-7425 1 0.01% 99.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8128-8129 2 0.02% 99.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 60 0.62% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 9709 # Bytes accessed per row activation
+system.physmem.totQLat 62966000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 815954750 # Sum of mem lat for all requests
system.physmem.totBusLat 136755000 # Total cycles spent in databus access
-system.physmem.totBankLat 668470000 # Total cycles spent in bank access
-system.physmem.avgQLat 3218.81 # Average queueing delay per request
-system.physmem.avgBankLat 24440.42 # Average bank access latency per request
+system.physmem.totBankLat 616233750 # Total cycles spent in bank access
+system.physmem.avgQLat 2302.15 # Average queueing delay per request
+system.physmem.avgBankLat 22530.57 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 32659.24 # Average memory access latency
+system.physmem.avgMemAccLat 29832.72 # Average memory access latency
system.physmem.avgRdBW 2.91 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.27 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2.91 # Average consumed read bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 8.01 # Average write queue length over time
-system.physmem.readRowHits 16404 # Number of row buffer hits during reads
-system.physmem.writeRowHits 1020 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 59.98 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 40.24 # Row buffer hit rate for writes
-system.physmem.avgGap 20154326.66 # Average gap between requests
-system.cpu.branchPred.lookups 155894666 # Number of BP lookups
-system.cpu.branchPred.condPredicted 155894666 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 25699129 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 80742532 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 80542859 # Number of BTB hits
+system.physmem.avgWrQLen 7.81 # Average write queue length over time
+system.physmem.readRowHits 18284 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1888 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 66.85 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 74.54 # Row buffer hit rate for writes
+system.physmem.avgGap 20161926.32 # Average gap between requests
+system.membus.throughput 3174299 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 5448 # Transaction distribution
+system.membus.trans_dist::ReadResp 5448 # Transaction distribution
+system.membus.trans_dist::Writeback 2533 # Transaction distribution
+system.membus.trans_dist::ReadExReq 21903 # Transaction distribution
+system.membus.trans_dist::ReadExResp 21903 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 57235 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 57235 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port 57235 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 57235 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1912576 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1912576 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.physmem.port 1912576 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 1912576 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 1912576 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 54010000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 256633000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu.branchPred.lookups 156229699 # Number of BP lookups
+system.cpu.branchPred.condPredicted 156229699 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 25700090 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 80130735 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 79954590 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.752704 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 2586842 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 5513 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 99.780178 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 2760708 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 5575 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 48 # Number of system calls
-system.cpu.numCycles 1204664695 # number of cpu cycles simulated
+system.cpu.numCycles 1205038430 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 175314236 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1434822441 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 155894666 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 83129701 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 393116244 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 83893731 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 577823849 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 123 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 791 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 184597714 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 11658023 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1204295068 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.043367 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.243240 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 175276442 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1436709759 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 156229699 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 82715298 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 393071073 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 83888584 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 578277772 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 906 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 2 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 184712777 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 11835246 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1204659879 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.045547 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.246119 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 818096949 67.93% 67.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 26918487 2.24% 70.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 12895052 1.07% 71.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 20223867 1.68% 72.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 26382325 2.19% 75.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 18061341 1.50% 76.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 31920988 2.65% 79.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 38294164 3.18% 82.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 211501895 17.56% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 818506882 67.95% 67.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 26870857 2.23% 70.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 12535228 1.04% 71.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 20195142 1.68% 72.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 26380482 2.19% 75.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 18063889 1.50% 76.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 31357703 2.60% 79.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 38322925 3.18% 82.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 212426771 17.63% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1204295068 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.129409 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.191055 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 284492311 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 500325603 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 268669661 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 92767668 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 58039825 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2310318754 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 58039825 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 333414311 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 124348906 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 3625 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 298566996 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 389921405 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2218156227 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 521 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 243059098 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 121762189 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2583430749 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5648758417 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 5648752173 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 6244 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1204659879 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.129647 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.192252 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 284492310 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 500755512 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 268717714 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 92660799 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 58033544 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2310812595 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 58033544 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 333444734 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 124733131 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 3847 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 298470128 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 389974495 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2217748571 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 12521 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 243097280 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 121807098 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2582807342 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5647663149 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 5647656949 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 6200 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1886895260 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 696535489 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 103 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 103 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 737453259 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 525280959 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 216617119 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 339037703 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 144743699 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1968663502 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 332 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1774132594 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 144752 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 346851970 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 707722705 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 283 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1204295068 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.473171 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.418728 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 695912082 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 105 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 105 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 737293343 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 525275195 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 216586351 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 339249104 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 144696192 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 1968455796 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 343 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1773948225 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 152074 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 346640912 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 707550278 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 294 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1204659879 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.472572 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.418644 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 354010440 29.40% 29.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 362491598 30.10% 59.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 234089313 19.44% 78.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 140647652 11.68% 90.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 60236623 5.00% 95.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 39446291 3.28% 98.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 10873538 0.90% 99.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1896665 0.16% 99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 602948 0.05% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 354366536 29.42% 29.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 362605011 30.10% 59.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 234071294 19.43% 78.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 140518579 11.66% 90.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 60300441 5.01% 95.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 39440661 3.27% 98.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 10869049 0.90% 99.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1880938 0.16% 99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 607370 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1204295068 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1204659879 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 400252 14.21% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.21% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 2198563 78.06% 92.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 217598 7.73% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 405736 14.35% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 2202072 77.90% 92.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 219007 7.75% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 46812295 2.64% 2.64% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1058825283 59.68% 62.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 18980 0.00% 62.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 398 0.00% 62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 46812378 2.64% 2.64% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1058677272 59.68% 62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 18975 0.00% 62.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 392 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 476287231 26.85% 89.17% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 192188407 10.83% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 476256932 26.85% 89.17% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 192182276 10.83% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1774132594 # Type of FU issued
-system.cpu.iq.rate 1.472719 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2816413 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001587 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4755521042 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2315690389 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1716753140 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 379 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1840 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 92 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1730136533 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 179 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 210301951 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1773948225 # Type of FU issued
+system.cpu.iq.rate 1.472109 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2826815 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.001594 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4755534756 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2315271702 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1716628380 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 462 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1804 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 116 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1729962441 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 221 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 210357388 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 106238837 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 40588 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 180694 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 28431061 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 106233073 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 38741 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 180751 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 28400293 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2329 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 64 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2345 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 48 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 58039825 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1222123 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 102210 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1968663834 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 63066910 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 525280959 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 216617119 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 49147 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 2813 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 180694 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1387767 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 24439207 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 25826974 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1757694663 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 472697091 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 16437931 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 58033544 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1572366 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 106573 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 1968456139 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 63007739 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 525275195 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 216586351 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 94 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 49655 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 2783 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 180751 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1386811 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 24440636 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 25827447 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1757502391 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 472605363 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 16445834 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 664152329 # number of memory reference insts executed
-system.cpu.iew.exec_branches 110147604 # Number of branches executed
-system.cpu.iew.exec_stores 191455238 # Number of stores executed
-system.cpu.iew.exec_rate 1.459074 # Inst execution rate
-system.cpu.iew.wb_sent 1717478326 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1716753232 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1259860051 # num instructions producing a value
-system.cpu.iew.wb_consumers 1819503625 # num instructions consuming a value
+system.cpu.iew.exec_refs 664057082 # number of memory reference insts executed
+system.cpu.iew.exec_branches 110136743 # Number of branches executed
+system.cpu.iew.exec_stores 191451719 # Number of stores executed
+system.cpu.iew.exec_rate 1.458462 # Inst execution rate
+system.cpu.iew.wb_sent 1717351615 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1716628496 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1259714523 # num instructions producing a value
+system.cpu.iew.wb_consumers 1819339484 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.425088 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.692420 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.424543 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.692402 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 347171319 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 346963425 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 49 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 25699242 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1146255243 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.414601 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.834752 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 25700222 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1146626335 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.414143 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.834829 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 413178457 36.05% 36.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 412793718 36.01% 72.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 87651437 7.65% 79.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 122127525 10.65% 90.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 23936453 2.09% 92.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 25493357 2.22% 94.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 16343741 1.43% 96.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 12104723 1.06% 97.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 32625832 2.85% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 413585484 36.07% 36.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 412792006 36.00% 72.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 87637452 7.64% 79.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 122098814 10.65% 90.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 23946599 2.09% 92.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 25447448 2.22% 94.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 16362955 1.43% 96.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 12115407 1.06% 97.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 32640170 2.85% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1146255243 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1146626335 # Number of insts commited each cycle
system.cpu.commit.committedInsts 880025277 # Number of instructions committed
system.cpu.commit.committedOps 1621493927 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1621354439 # Number of committed integer instructions.
system.cpu.commit.function_calls 1061692 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 32625832 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 32640170 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3082294657 # The number of ROB reads
-system.cpu.rob.rob_writes 3995391584 # The number of ROB writes
-system.cpu.timesIdled 60284 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 369627 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3082443517 # The number of ROB reads
+system.cpu.rob.rob_writes 3994969913 # The number of ROB writes
+system.cpu.timesIdled 60378 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 378551 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 880025277 # Number of Instructions Simulated
system.cpu.committedOps 1621493927 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 880025277 # Number of Instructions Simulated
-system.cpu.cpi 1.368898 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.368898 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.730515 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.730515 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3534938952 # number of integer regfile reads
-system.cpu.int_regfile_writes 1966276795 # number of integer regfile writes
-system.cpu.fp_regfile_reads 92 # number of floating regfile reads
-system.cpu.misc_regfile_reads 906122047 # number of misc regfile reads
+system.cpu.cpi 1.369323 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.369323 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.730288 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.730288 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3534639638 # number of integer regfile reads
+system.cpu.int_regfile_writes 1966129317 # number of integer regfile writes
+system.cpu.fp_regfile_reads 116 # number of floating regfile reads
+system.cpu.misc_regfile_reads 905981948 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.icache.replacements 34 # number of replacements
-system.cpu.icache.tagsinuse 799.517991 # Cycle average of tags in use
-system.cpu.icache.total_refs 184596362 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 919 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 200866.552775 # Average number of references to valid blocks.
+system.cpu.toL2Bus.throughput 93457946 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 204658 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 204658 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 428893 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 4 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 4 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 246296 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 246296 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1854 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1328951 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 1330805 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 59200 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 56250752 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 56309952 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 56309952 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 256 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 868818500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1393500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 675040498 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.cpu.icache.replacements 41 # number of replacements
+system.cpu.icache.tagsinuse 797.090296 # Cycle average of tags in use
+system.cpu.icache.total_refs 184711350 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 925 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 199687.945946 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 799.517991 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.390390 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.390390 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 184596362 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 184596362 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 184596362 # number of demand (read+write) hits
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-system.cpu.icache.overall_hits::total 184596362 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1352 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1352 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1352 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1352 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1352 # number of overall misses
-system.cpu.icache.overall_misses::total 1352 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 65001000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 65001000 # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total 65001000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 65001000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 65001000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 184597714 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 184597714 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total 184597714 # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total 184597714 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48077.662722 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 48077.662722 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 48077.662722 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 48077.662722 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 48077.662722 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 48077.662722 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 237 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst 797.090296 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.389204 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.389204 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 184711350 # number of ReadReq hits
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+system.cpu.icache.demand_hits::total 184711350 # number of demand (read+write) hits
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+system.cpu.icache.ReadReq_misses::cpu.inst 1427 # number of ReadReq misses
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+system.cpu.icache.overall_misses::total 1427 # number of overall misses
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+system.cpu.icache.ReadReq_accesses::cpu.inst 184712777 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.overall_miss_rate::total 0.000008 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62981.779958 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 62981.779958 # average ReadReq miss latency
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 62981.779958 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 62981.779958 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 295 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 21 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked
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-system.cpu.icache.avg_blocked_cycles::no_mshrs 59.250000 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu.icache.avg_blocked_cycles::no_targets 21 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 430 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 430 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 430 # number of demand (read+write) MSHR hits
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-system.cpu.icache.overall_mshr_hits::total 430 # number of overall MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses::total 922 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 922 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 922 # number of demand (read+write) MSHR misses
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-system.cpu.icache.overall_mshr_misses::total 922 # number of overall MSHR misses
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+system.cpu.icache.overall_mshr_hits::total 498 # number of overall MSHR hits
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+system.cpu.icache.ReadReq_mshr_misses::total 929 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51872.017354 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51872.017354 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51872.017354 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 51872.017354 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51872.017354 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 51872.017354 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67507.534984 # average ReadReq mshr miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67507.534984 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 67507.534984 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67507.534984 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 67507.534984 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 2557 # number of replacements
-system.cpu.l2cache.tagsinuse 22244.474628 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 531898 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 24190 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 21.988342 # Average number of references to valid blocks.
+system.cpu.l2cache.replacements 2555 # number of replacements
+system.cpu.l2cache.tagsinuse 22235.283270 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 531263 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 24186 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 21.965724 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 20784.853808 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 785.459531 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 674.161290 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.634303 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.023970 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.020574 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.678847 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56406.215006 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60018.151410 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59900.223027 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 446134 # number of replacements
-system.cpu.dcache.tagsinuse 4092.678697 # Cycle average of tags in use
-system.cpu.dcache.total_refs 450120039 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 450230 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 999.755767 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 862286000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4092.678697 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999189 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999189 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 262180372 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 262180372 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 187939664 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 187939664 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 450120036 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 450120036 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 450120036 # number of overall hits
-system.cpu.dcache.overall_hits::total 450120036 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 211406 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 211406 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 246394 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 246394 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 457800 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 457800 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 457800 # number of overall misses
-system.cpu.dcache.overall_misses::total 457800 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 3024053500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 3024053500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4115325499 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4115325499 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 7139378999 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 7139378999 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 7139378999 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 7139378999 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 262391778 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 262391778 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements 445929 # number of replacements
+system.cpu.dcache.tagsinuse 4092.296880 # Cycle average of tags in use
+system.cpu.dcache.total_refs 449973128 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 450025 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 999.884735 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 960887000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4092.296880 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999096 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999096 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 262033427 # number of ReadReq hits
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+system.cpu.dcache.demand_hits::total 449973124 # number of demand (read+write) hits
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+system.cpu.dcache.overall_hits::total 449973124 # number of overall hits
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+system.cpu.dcache.ReadReq_misses::total 211198 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 246361 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 246361 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 457559 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 457559 # number of demand (read+write) misses
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+system.cpu.dcache.ReadReq_miss_latency::cpu.data 3104170500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 3104170500 # number of ReadReq miss cycles
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+system.cpu.dcache.WriteReq_miss_latency::total 4487459000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 7591629500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 7591629500 # number of demand (read+write) miss cycles
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+system.cpu.dcache.ReadReq_accesses::cpu.data 262244625 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 450577836 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 450577836 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 450577836 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 450577836 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000806 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000806 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 450430683 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 450430683 # number of demand (read+write) accesses
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+system.cpu.dcache.overall_accesses::total 450430683 # number of overall (read+write) accesses
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+system.cpu.dcache.ReadReq_miss_rate::total 0.000805 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001309 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001309 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.001016 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.001016 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.001016 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.001016 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14304.482843 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14304.482843 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16702.214741 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 16702.214741 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 15594.973785 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 15594.973785 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 15594.973785 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 15594.973785 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 342 # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14697.916173 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14697.916173 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 18214.973149 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 18214.973149 # average WriteReq miss latency
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+system.cpu.dcache.demand_avg_miss_latency::total 16591.586003 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16591.586003 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 16591.586003 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 322 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 43 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 37 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 7.953488 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.702703 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 429005 # number of writebacks
-system.cpu.dcache.writebacks::total 429005 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7496 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 7496 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 71 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 71 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 7567 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 7567 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 7567 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 7567 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203910 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 203910 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246323 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 246323 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 450233 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 450233 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 450233 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 450233 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2529393000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2529393000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3622096999 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3622096999 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6151489999 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6151489999 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6151489999 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6151489999 # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks 428893 # number of writebacks
+system.cpu.dcache.writebacks::total 428893 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7460 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 7460 # number of ReadReq MSHR hits
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+system.cpu.dcache.WriteReq_mshr_hits::total 70 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 7530 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 7530 # number of demand (read+write) MSHR hits
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+system.cpu.dcache.overall_mshr_hits::total 7530 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 203738 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 203738 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 246291 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 246291 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 450029 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 450029 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 450029 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 450029 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2608561002 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2608561002 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3994205500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3994205500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6602766502 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6602766502 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6602766502 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6602766502 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000777 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000777 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001309 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000999 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000999 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000999 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12404.457849 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12404.457849 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14704.664197 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14704.664197 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13662.903428 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13662.903428 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13662.903428 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13662.903428 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12803.507456 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12803.507456 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16217.423698 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16217.423698 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14671.868928 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 14671.868928 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14671.868928 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 14671.868928 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
system.physmem.bw_total::cpu.inst 9846686428 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2808012957 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12654699384 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 12654699384 # Throughput (bytes/s)
+system.membus.data_through_bus 12199037473 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1927985345 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.physmem.bw_total::cpu.inst 25668 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 934548 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1049487 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 1049487 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 5039 # Transaction distribution
+system.membus.trans_dist::ReadResp 5039 # Transaction distribution
+system.membus.trans_dist::Writeback 2511 # Transaction distribution
+system.membus.trans_dist::ReadExReq 21970 # Transaction distribution
+system.membus.trans_dist::ReadExResp 21970 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 56529 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 56529 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port 56529 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 56529 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1889280 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1889280 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.physmem.port 1889280 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 1889280 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 1889280 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 49608000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 243081000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 3600386796 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 30778915 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 198048 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 198048 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 422980 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 244722 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 244722 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1444 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 1307076 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 1308520 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46208 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 55361792 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 55408000 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 55408000 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 855855000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1083000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 663072000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.026781 # Number of seconds simulated
-sim_ticks 26780899500 # Number of ticks simulated
-final_tick 26780899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.026877 # Number of seconds simulated
+sim_ticks 26876770500 # Number of ticks simulated
+final_tick 26876770500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 55932 # Simulator instruction rate (inst/s)
-host_op_rate 56334 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 16535050 # Simulator tick rate (ticks/s)
-host_mem_usage 421208 # Number of bytes of host memory used
-host_seconds 1619.64 # Real time elapsed on the host
+host_inst_rate 124105 # Simulator instruction rate (inst/s)
+host_op_rate 124996 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 36820237 # Simulator tick rate (ticks/s)
+host_mem_usage 379416 # Number of bytes of host memory used
+host_seconds 729.95 # Real time elapsed on the host
sim_insts 90589798 # Number of instructions simulated
sim_ops 91240351 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 44800 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory
-system.physmem.bytes_read::total 992640 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 44992 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 44992 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 703 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 992448 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 44800 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 44800 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 700 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15510 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1680003 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 35385219 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 37065223 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1680003 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1680003 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1680003 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 35385219 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 37065223 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15510 # Total number of read requests seen
+system.physmem.num_reads::total 15507 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1666867 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 35258998 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 36925865 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1666867 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1666867 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1666867 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 35258998 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 36925865 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15507 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 15513 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 992640 # Total number of bytes read from memory
+system.physmem.cpureqs 15509 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 992448 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 992640 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 992448 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 996 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 960 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 998 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 1012 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 996 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 1010 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 925 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 882 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 885 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 951 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 993 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 1001 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 966 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 968 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 968 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 999 # Track reads on a per bank basis
+system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 987 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 885 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 941 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 1028 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 1049 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 1105 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 1078 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 1078 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1024 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 957 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 935 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 899 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 904 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 865 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 876 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 896 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 26780729500 # Total gap between requests
+system.physmem.totGap 26876578500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 15510 # Categorize read packet sizes
+system.physmem.readPktSize::6 15507 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 10153 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 5074 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 253 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 11266 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 4119 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 101 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 54693250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 313977000 # Sum of mem lat for all requests
-system.physmem.totBusLat 77550000 # Total cycles spent in databus access
-system.physmem.totBankLat 181733750 # Total cycles spent in bank access
-system.physmem.avgQLat 3526.32 # Average queueing delay per request
-system.physmem.avgBankLat 11717.20 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 279 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 3465.175627 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 823.608896 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 3831.300006 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 68 24.37% 24.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 21 7.53% 31.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 17 6.09% 37.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 11 3.94% 41.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 11 3.94% 45.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 5 1.79% 47.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 1 0.36% 48.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 3 1.08% 49.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 2 0.72% 49.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 3 1.08% 50.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 1 0.36% 51.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 4 1.43% 52.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 1 0.36% 53.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 1 0.36% 53.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 1 0.36% 53.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 2 0.72% 54.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 1 0.36% 54.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 1 0.36% 55.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 2 0.72% 55.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 1 0.36% 56.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1473 1 0.36% 56.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 2 0.72% 57.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1665 1 0.36% 57.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2305 2 0.72% 58.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2369 2 0.72% 59.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3201 1 0.36% 59.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4033 1 0.36% 59.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4416-4417 1 0.36% 60.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4800-4801 1 0.36% 60.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4992-4993 1 0.36% 60.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5824-5825 1 0.36% 61.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 108 38.71% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 279 # Bytes accessed per row activation
+system.physmem.totQLat 33774250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 291406750 # Sum of mem lat for all requests
+system.physmem.totBusLat 77535000 # Total cycles spent in databus access
+system.physmem.totBankLat 180097500 # Total cycles spent in bank access
+system.physmem.avgQLat 2178.00 # Average queueing delay per request
+system.physmem.avgBankLat 11613.95 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 20243.52 # Average memory access latency
-system.physmem.avgRdBW 37.07 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 18791.95 # Average memory access latency
+system.physmem.avgRdBW 36.93 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 37.07 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 36.93 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.29 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 14776 # Number of row buffer hits during reads
+system.physmem.readRowHits 15228 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 95.27 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 98.20 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 1726675.02 # Average gap between requests
-system.cpu.branchPred.lookups 26686067 # Number of BP lookups
-system.cpu.branchPred.condPredicted 22003641 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 842721 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 11370784 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 11281397 # Number of BTB hits
+system.physmem.avgGap 1733190.08 # Average gap between requests
+system.membus.throughput 36925865 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 969 # Transaction distribution
+system.membus.trans_dist::ReadResp 969 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
+system.membus.trans_dist::ReadExReq 14538 # Transaction distribution
+system.membus.trans_dist::ReadExResp 14538 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 31018 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 31018 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 992448 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 992448 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 992448 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 19245500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer1.occupancy 145771998 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
+system.cpu.branchPred.lookups 26679971 # Number of BP lookups
+system.cpu.branchPred.condPredicted 21999923 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 841486 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 11361779 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 11280277 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.213889 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 70454 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 189 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 99.282665 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 69760 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 186 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
-system.cpu.numCycles 53561800 # number of cpu cycles simulated
+system.cpu.numCycles 53753542 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 14175164 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 127899633 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 26686067 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 11351851 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 24037657 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4765030 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 11217249 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 94 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.icacheStallCycles 14168054 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 127857393 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 26679971 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 11350037 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 24029267 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4759146 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 11320906 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 135 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 11 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13847383 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 331199 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 53336140 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.414591 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.216158 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 13839868 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 329939 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 53419540 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.409911 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.214764 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 29336778 55.00% 55.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3388806 6.35% 61.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2028790 3.80% 65.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1556293 2.92% 68.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1665637 3.12% 71.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2919109 5.47% 76.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1511505 2.83% 79.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1091219 2.05% 81.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9838003 18.45% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 29428601 55.09% 55.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 3388763 6.34% 61.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2027589 3.80% 65.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1554197 2.91% 68.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1665441 3.12% 71.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2919869 5.47% 76.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1510771 2.83% 79.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1090381 2.04% 81.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 9833928 18.41% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 53336140 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.498229 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.387889 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 16937190 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 9066542 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 22437695 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 997386 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3897327 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 4443416 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 8715 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 126080182 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 42547 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3897327 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 18717098 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 3539811 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 156330 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 21553550 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5472024 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 123163469 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 22 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 421860 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4589739 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 1294 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 143620029 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 536487458 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 536482847 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 4611 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 53419540 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.496339 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.378585 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 16932063 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 9167037 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 22428085 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 999775 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3892580 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 4442872 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 8651 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 126035469 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 42652 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3892580 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 18713289 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 3601391 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 176810 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 21544043 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 5491427 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 123129214 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 413620 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4613636 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 1365 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 143579054 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 536328979 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 536324233 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 4746 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 107414186 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 36205843 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 4601 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 4599 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12496499 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 29481175 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 5524207 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2105622 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1304065 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 118177785 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 8472 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 105170475 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 79267 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 26750487 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 65594281 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 254 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 53336140 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.971843 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.910853 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 36164868 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 4608 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 4606 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12537284 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 29472276 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 5518407 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 2148723 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 1268677 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 118148285 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 8477 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 105144607 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 78560 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 26719178 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 65548353 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 259 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 53419540 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.968280 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.909780 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 15308492 28.70% 28.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 11622242 21.79% 50.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 8283131 15.53% 66.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6774123 12.70% 78.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4939733 9.26% 87.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2964995 5.56% 93.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2471425 4.63% 98.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 528847 0.99% 99.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 443152 0.83% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 15372134 28.78% 28.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 11649287 21.81% 50.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 8266991 15.48% 66.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 6802353 12.73% 78.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 4948394 9.26% 88.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2939644 5.50% 93.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 2464571 4.61% 98.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 534271 1.00% 99.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 441895 0.83% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 53336140 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 53419540 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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-system.cpu.iq.fu_full::IntMult 27 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 340087 51.41% 58.31% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 275830 41.69% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 45832 6.94% 6.94% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 339714 51.41% 58.35% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 275235 41.65% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 74428958 70.77% 70.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 145 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 185 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.78% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 25611753 24.35% 95.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 5118456 4.87% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 74415665 70.77% 70.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 10973 0.01% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 126 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 171 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.79% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 25604813 24.35% 95.14% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 5112854 4.86% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 105170475 # Type of FU issued
-system.cpu.iq.rate 1.963535 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 661557 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006290 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 264417181 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 144941243 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 102695992 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 733 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1017 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 321 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 105831667 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 365 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 444874 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 105144607 # Type of FU issued
+system.cpu.iq.rate 1.956050 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 660808 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.006285 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 264447444 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 144880593 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 102675373 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 678 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 959 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 288 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 105805083 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 332 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 440146 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 6907209 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6633 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 6354 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 779363 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 6898310 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6801 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 6412 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 773563 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 31305 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 31426 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3897327 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 927642 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 126590 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 118198971 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 309734 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 29481175 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 5524207 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 4584 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 66006 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 6795 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 6354 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 446949 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 445983 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 892932 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 104193042 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25290857 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 977433 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3892580 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 959936 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 127408 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 118169460 # Number of instructions dispatched to IQ
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+system.cpu.iew.iewDispNonSpecInsts 4589 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 66175 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 6842 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 6412 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 445895 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 445553 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 891448 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 104166950 # Number of executed instructions
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+system.cpu.iew.iewExecSquashedInsts 977657 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 12714 # number of nop insts executed
-system.cpu.iew.exec_refs 30352506 # number of memory reference insts executed
-system.cpu.iew.exec_branches 21328586 # Number of branches executed
-system.cpu.iew.exec_stores 5061649 # Number of stores executed
-system.cpu.iew.exec_rate 1.945286 # Inst execution rate
-system.cpu.iew.wb_sent 102976105 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 102696313 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 62237913 # num instructions producing a value
-system.cpu.iew.wb_consumers 104299650 # num instructions consuming a value
+system.cpu.iew.exec_nop 12698 # number of nop insts executed
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+system.cpu.iew.wb_sent 102951696 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 102675661 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 62239721 # num instructions producing a value
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.917342 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.596722 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.910119 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.596849 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 26949111 # The number of squashed insts skipped by commit
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system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 834092 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 49438813 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.845776 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.541803 # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::mean 1.842491 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.540649 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 19950290 40.35% 40.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13144948 26.59% 66.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4163783 8.42% 75.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 3432949 6.94% 82.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1533470 3.10% 85.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 746046 1.51% 86.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 934782 1.89% 88.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 251563 0.51% 89.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5280982 10.68% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 20031869 40.45% 40.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13152738 26.56% 67.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4167621 8.41% 75.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 3431174 6.93% 82.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1533592 3.10% 85.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 731516 1.48% 86.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 947722 1.91% 88.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 252646 0.51% 89.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5278082 10.66% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 49438813 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 49526960 # Number of insts commited each cycle
system.cpu.commit.committedInsts 90602407 # Number of instructions committed
system.cpu.commit.committedOps 91252960 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
system.cpu.commit.int_insts 72525674 # Number of committed integer instructions.
system.cpu.commit.function_calls 56148 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5280982 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 5278082 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 162354168 # The number of ROB reads
-system.cpu.rob.rob_writes 240321058 # The number of ROB writes
-system.cpu.timesIdled 43778 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 225660 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 162415559 # The number of ROB reads
+system.cpu.rob.rob_writes 240257118 # The number of ROB writes
+system.cpu.timesIdled 46037 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 334002 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 90589798 # Number of Instructions Simulated
system.cpu.committedOps 91240351 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 90589798 # Number of Instructions Simulated
-system.cpu.cpi 0.591256 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.591256 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.691314 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.691314 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 495624515 # number of integer regfile reads
-system.cpu.int_regfile_writes 120561799 # number of integer regfile writes
-system.cpu.fp_regfile_reads 167 # number of floating regfile reads
-system.cpu.fp_regfile_writes 408 # number of floating regfile writes
-system.cpu.misc_regfile_reads 29097050 # number of misc regfile reads
+system.cpu.cpi 0.593373 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.593373 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.685281 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.685281 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 495496517 # number of integer regfile reads
+system.cpu.int_regfile_writes 120533542 # number of integer regfile writes
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system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
-system.cpu.icache.replacements 3 # number of replacements
-system.cpu.icache.tagsinuse 630.487158 # Cycle average of tags in use
-system.cpu.icache.total_refs 13846398 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 729 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 18993.687243 # Average number of references to valid blocks.
+system.cpu.toL2Bus.throughput 4503595847 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 904588 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 904588 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 942920 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 43775 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 43775 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1457 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2838192 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 2839649 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 46528 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120995392 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 121041920 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 121041920 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 192 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 1888563000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 7.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1095499 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 1421456489 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 5.3 # Layer utilization (%)
+system.cpu.icache.replacements 4 # number of replacements
+system.cpu.icache.tagsinuse 627.794494 # Cycle average of tags in use
+system.cpu.icache.total_refs 13838883 # Total number of references to valid blocks.
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+system.cpu.icache.avg_refs 19035.602476 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.icache.occ_percent::cpu.inst 0.307855 # Average percentage of cache occupancy
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-system.cpu.icache.overall_hits::total 13846398 # number of overall hits
+system.cpu.icache.occ_blocks::cpu.inst 627.794494 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.306540 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.306540 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_misses::cpu.inst 984 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 984 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 984 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 984 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::total 984 # number of overall misses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49900.405488 # average ReadReq miss latency
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-system.cpu.icache.overall_avg_miss_latency::cpu.inst 49900.405488 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 49900.405488 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67117.885163 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 67117.885163 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 67117.885163 # average overall miss latency
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 67117.885163 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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-system.cpu.icache.ReadReq_mshr_hits::total 251 # number of ReadReq MSHR hits
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-system.cpu.icache.demand_mshr_hits::total 251 # number of demand (read+write) MSHR hits
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-system.cpu.icache.overall_mshr_hits::total 251 # number of overall MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses::total 733 # number of ReadReq MSHR misses
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-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37481499 # number of overall MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total 49961500 # number of overall MSHR miss cycles
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+system.cpu.dcache.WriteReq_mshr_hits::total 158472 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 7 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 7 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 428331 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 428331 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 428331 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 428331 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903878 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 903878 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43758 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 43758 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 947636 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 947636 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 947636 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 947636 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9991782011 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 9991782011 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1252450464 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 1252450464 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11244232475 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 11244232475 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11244232475 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 11244232475 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036489 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036489 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009241 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009241 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032116 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.032116 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032116 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.032116 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11054.348055 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11054.348055 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28622.205402 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28622.205402 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11865.560695 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11865.560695 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11865.560695 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11865.560695 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 54240661000 # Number of ticks simulated
final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1585065 # Simulator instruction rate (inst/s)
-host_op_rate 1596445 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 948925064 # Simulator tick rate (ticks/s)
-host_mem_usage 411788 # Number of bytes of host memory used
-host_seconds 57.16 # Real time elapsed on the host
+host_inst_rate 2267620 # Simulator instruction rate (inst/s)
+host_op_rate 2283902 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1357548360 # Simulator tick rate (ticks/s)
+host_mem_usage 366572 # Number of bytes of host memory used
+host_seconds 39.95 # Real time elapsed on the host
sim_insts 90602407 # Number of instructions simulated
sim_ops 91252960 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7952024773 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2008174937 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9960199711 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 9960199711 # Throughput (bytes/s)
+system.membus.data_through_bus 540247816 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
sim_ticks 147135976000 # Number of ticks simulated
final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 836188 # Simulator instruction rate (inst/s)
-host_op_rate 842183 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1358330065 # Simulator tick rate (ticks/s)
-host_mem_usage 420368 # Number of bytes of host memory used
-host_seconds 108.32 # Real time elapsed on the host
+host_inst_rate 662214 # Simulator instruction rate (inst/s)
+host_op_rate 666963 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1075722156 # Simulator tick rate (ticks/s)
+host_mem_usage 375060 # Number of bytes of host memory used
+host_seconds 136.78 # Real time elapsed on the host
sim_insts 90576861 # Number of instructions simulated
sim_ops 91226312 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 251414 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 6421054 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6672467 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 6672467 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 792 # Transaction distribution
+system.membus.trans_dist::ReadResp 792 # Transaction distribution
+system.membus.trans_dist::ReadExReq 14548 # Transaction distribution
+system.membus.trans_dist::ReadExResp 14548 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 30680 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 30680 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 981760 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 981760 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 981760 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 15340000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 138060000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 821979690 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 900788 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 46609 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 46609 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1198 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2835930 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 2837128 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 38336 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 120904448 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 120942784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 120942784 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 898500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 1420197000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
sim_ticks 122215823500 # Number of ticks simulated
final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2097981 # Simulator instruction rate (inst/s)
-host_op_rate 2098068 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1051599524 # Simulator tick rate (ticks/s)
-host_mem_usage 405208 # Number of bytes of host memory used
-host_seconds 116.22 # Real time elapsed on the host
+host_inst_rate 2226348 # Simulator instruction rate (inst/s)
+host_op_rate 2226440 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1115942635 # Simulator tick rate (ticks/s)
+host_mem_usage 357000 # Number of bytes of host memory used
+host_seconds 109.52 # Real time elapsed on the host
sim_insts 243825150 # Number of instructions simulated
sim_ops 243835265 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7999667834 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3438835373 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11438503207 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 11438757576 # Throughput (bytes/s)
+system.membus.data_through_bus 1397997177 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.workload.num_syscalls 443 # Number of system calls
system.cpu.numCycles 244431648 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
sim_ticks 361488530000 # Number of ticks simulated
final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1027753 # Simulator instruction rate (inst/s)
-host_op_rate 1027796 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1523718944 # Simulator tick rate (ticks/s)
-host_mem_usage 413792 # Number of bytes of host memory used
-host_seconds 237.24 # Real time elapsed on the host
+host_inst_rate 653861 # Simulator instruction rate (inst/s)
+host_op_rate 653888 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 969395755 # Simulator tick rate (ticks/s)
+host_mem_usage 365508 # Number of bytes of host memory used
+host_seconds 372.90 # Real time elapsed on the host
sim_insts 243825150 # Number of instructions simulated
sim_ops 243835265 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 2762444 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 1036 # Transaction distribution
+system.membus.trans_dist::ReadResp 1036 # Transaction distribution
+system.membus.trans_dist::ReadExReq 14567 # Transaction distribution
+system.membus.trans_dist::ReadExResp 14567 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 31206 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 31206 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 998592 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 998592 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 998592 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.workload.num_syscalls 443 # Number of system calls
system.cpu.numCycles 722977060 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 332088036 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 893739 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 46714 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 46714 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1764 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 2814408 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 2816172 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 56448 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 119989568 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 120046016 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 120046016 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 1873125500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1323000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.064955 # Number of seconds simulated
-sim_ticks 64955437500 # Number of ticks simulated
-final_tick 64955437500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.065490 # Number of seconds simulated
+sim_ticks 65489948000 # Number of ticks simulated
+final_tick 65489948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 70718 # Simulator instruction rate (inst/s)
-host_op_rate 124523 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 29075113 # Simulator tick rate (ticks/s)
-host_mem_usage 434544 # Number of bytes of host memory used
-host_seconds 2234.06 # Real time elapsed on the host
+host_inst_rate 99083 # Simulator instruction rate (inst/s)
+host_op_rate 174470 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 41072394 # Simulator tick rate (ticks/s)
+host_mem_usage 386708 # Number of bytes of host memory used
+host_seconds 1594.50 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated
sim_ops 278192464 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 64064 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1882496 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1946560 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 64064 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 64064 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 10432 # Number of bytes written to this memory
-system.physmem.bytes_written::total 10432 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1001 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 29414 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 30415 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 163 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 163 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 986276 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 28981346 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 29967622 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 986276 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 986276 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 160602 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 160602 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 160602 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 986276 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 28981346 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 30128224 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 63872 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 1882624 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1946496 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 63872 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 63872 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 10112 # Number of bytes written to this memory
+system.physmem.bytes_written::total 10112 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 998 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 29416 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 30414 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 158 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 158 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 975295 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 28746763 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 29722057 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 975295 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 975295 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 154405 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 154405 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 154405 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 975295 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 28746763 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 29876463 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 30415 # Total number of read requests seen
-system.physmem.writeReqs 163 # Total number of write requests seen
-system.physmem.cpureqs 30578 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 1946560 # Total number of bytes read from memory
-system.physmem.bytesWritten 10432 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 1946560 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 10432 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 40 # Number of read reqs serviced by write Q
+system.physmem.writeReqs 158 # Total number of write requests seen
+system.physmem.cpureqs 30573 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 1946496 # Total number of bytes read from memory
+system.physmem.bytesWritten 10112 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 1946496 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 10112 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 47 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 1928 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 1903 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 1919 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 1928 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 1935 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 1899 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 1928 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 1949 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 1933 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 1946 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 1870 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 1874 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 1848 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 1890 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 1827 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 1798 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 7 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 63 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 50 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 2 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 4 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 3 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 11 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 6 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 6 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 4 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 7 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::0 1925 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 2071 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 2026 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 1927 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 2029 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 1901 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 1963 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 1864 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 1938 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1931 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1804 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 1797 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 1792 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 1800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 1821 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 1779 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 8 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 101 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 2 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 7 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 12 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 8 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 12 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 5 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 3 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 64955401000 # Total gap between requests
+system.physmem.totGap 65489931000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 163 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 29875 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 392 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 158 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 29911 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 366 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 71 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 11278750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 610070000 # Sum of mem lat for all requests
-system.physmem.totBusLat 151875000 # Total cycles spent in databus access
-system.physmem.totBankLat 446916250 # Total cycles spent in bank access
-system.physmem.avgQLat 371.32 # Average queueing delay per request
-system.physmem.avgBankLat 14713.29 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 551 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 3522.090744 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 829.782913 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 3844.695710 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 143 25.95% 25.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 46 8.35% 34.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 23 4.17% 38.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 15 2.72% 41.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 11 2.00% 43.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 10 1.81% 45.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 9 1.63% 46.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 5 0.91% 47.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 5 0.91% 48.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 10 1.81% 50.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 4 0.73% 51.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 6 1.09% 52.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 2 0.36% 52.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 1 0.18% 52.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 3 0.54% 53.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 1 0.18% 53.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 1 0.18% 53.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 9 1.63% 55.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 2 0.36% 55.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 1 0.18% 55.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 1 0.18% 55.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 3 0.54% 56.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 2 0.36% 56.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1793 1 0.18% 56.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1857 1 0.18% 57.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2113 1 0.18% 57.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2241 2 0.36% 57.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2433 1 0.18% 57.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2497 1 0.18% 58.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2625 1 0.18% 58.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2881 2 0.36% 58.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2945 1 0.18% 58.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3265 1 0.18% 58.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4033 2 0.36% 59.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4608-4609 1 0.18% 59.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5184-5185 1 0.18% 59.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5312-5313 1 0.18% 59.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5888-5889 1 0.18% 60.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6144-6145 2 0.36% 60.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7232-7233 1 0.18% 60.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8000-8001 1 0.18% 60.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 216 39.20% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 551 # Bytes accessed per row activation
+system.physmem.totQLat 7172750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 582609000 # Sum of mem lat for all requests
+system.physmem.totBusLat 151840000 # Total cycles spent in databus access
+system.physmem.totBankLat 423596250 # Total cycles spent in bank access
+system.physmem.avgQLat 236.19 # Average queueing delay per request
+system.physmem.avgBankLat 13948.77 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 20084.61 # Average memory access latency
-system.physmem.avgRdBW 29.97 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 29.97 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 0.16 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 19184.96 # Average memory access latency
+system.physmem.avgRdBW 29.72 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 29.72 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 0.15 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 0.24 # Data bus utilization in percentage
+system.physmem.busUtil 0.23 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 9.38 # Average write queue length over time
-system.physmem.readRowHits 29086 # Number of row buffer hits during reads
-system.physmem.writeRowHits 90 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 95.76 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 55.21 # Row buffer hit rate for writes
-system.physmem.avgGap 2124252.76 # Average gap between requests
-system.cpu.branchPred.lookups 33861369 # Number of BP lookups
-system.cpu.branchPred.condPredicted 33861369 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 775033 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 19294803 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 19205281 # Number of BTB hits
+system.physmem.avgWrQLen 0.64 # Average write queue length over time
+system.physmem.readRowHits 29867 # Number of row buffer hits during reads
+system.physmem.writeRowHits 88 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 98.35 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 55.70 # Row buffer hit rate for writes
+system.physmem.avgGap 2142083.90 # Average gap between requests
+system.membus.throughput 29875486 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 1414 # Transaction distribution
+system.membus.trans_dist::ReadResp 1412 # Transaction distribution
+system.membus.trans_dist::Writeback 158 # Transaction distribution
+system.membus.trans_dist::ReadExReq 29001 # Transaction distribution
+system.membus.trans_dist::ReadExResp 29001 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60986 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60986 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port 60986 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 60986 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1956544 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1956544 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.physmem.port 1956544 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 1956544 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 1956544 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 34719000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer1.occupancy 283984750 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
+system.cpu.branchPred.lookups 33857873 # Number of BP lookups
+system.cpu.branchPred.condPredicted 33857873 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 774323 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 19304335 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 19204317 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.536031 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 5016068 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 5449 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 99.481888 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 5017100 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 5401 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 444 # Number of system calls
-system.cpu.numCycles 129910880 # number of cpu cycles simulated
+system.cpu.numCycles 130979906 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 26135643 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 182272269 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 33861369 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 24221349 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 55463274 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5355481 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 43685508 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 41 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 275 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 25577909 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 166501 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 129829944 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.475075 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.321063 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 26132901 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 182254705 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 33857873 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 24221417 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 55457387 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5351238 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 44744671 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 61 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 388 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 6 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 25573947 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 166608 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 130876974 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.455077 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.315032 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 76844002 59.19% 59.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1961117 1.51% 60.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2942078 2.27% 62.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 3835155 2.95% 65.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 7767567 5.98% 71.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 4757667 3.66% 75.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2666355 2.05% 77.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1316617 1.01% 78.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 27739386 21.37% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 77895599 59.52% 59.52% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1961064 1.50% 61.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2941506 2.25% 63.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 3833280 2.93% 66.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 7768261 5.94% 72.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 4757709 3.64% 75.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2666396 2.04% 77.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1316117 1.01% 78.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 27737042 21.19% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 129829944 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.260651 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.403056 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 36820018 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 35912600 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 43886713 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 8665410 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 4545203 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 318850210 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 4545203 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 42299380 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 8565943 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 6540 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 46769687 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 27643191 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 315014600 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 177 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 37506 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 25780031 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 461 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 317193496 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 836529852 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 836528510 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1342 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 130876974 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.258497 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.391471 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 36825046 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 36962033 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 43884335 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 8664000 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 4541560 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 318828995 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 4541560 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 42312169 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 9511401 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 7346 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 46756594 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 27747904 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 314994654 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 172 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 26642 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 25895040 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 476 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 317170346 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 836475154 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 836474392 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 762 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 37980749 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 37957599 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 473 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 470 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 62475342 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 101554999 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 34779465 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 39658435 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 5856370 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 311474506 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1648 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 300268759 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 90582 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 32704656 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 46105854 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1203 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 129829944 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.312785 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.693578 # Number of insts issued each cycle
+system.cpu.rename.tempSerializingInsts 471 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 62618763 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 101546098 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 34776490 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 39628981 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 5872628 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 311460641 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1620 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 300263242 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 89194 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 32692736 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 46075932 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1175 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 130876974 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.294240 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.698248 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 23157142 17.84% 17.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 23146978 17.83% 35.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 25463277 19.61% 55.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 25807307 19.88% 75.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 18888431 14.55% 89.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 8277018 6.38% 96.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 3970528 3.06% 99.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 942780 0.73% 99.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 176483 0.14% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 24131864 18.44% 18.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 23200747 17.73% 36.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 25515846 19.50% 55.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 25800196 19.71% 75.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 18908821 14.45% 89.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 8226578 6.29% 96.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 3966533 3.03% 99.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 948269 0.72% 99.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 178120 0.14% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 129829944 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 130876974 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 31372 1.52% 1.52% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 31350 1.52% 1.52% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 1.52% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.52% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.52% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1915002 93.02% 94.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 112311 5.46% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1914118 93.02% 94.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 112203 5.45% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 31277 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 169830588 56.56% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 11175 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 333 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.57% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 97304104 32.41% 88.98% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 33091251 11.02% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 31269 0.01% 0.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 169831463 56.56% 56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 11173 0.00% 56.57% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 331 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 29 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.58% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 97296683 32.40% 88.98% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 33092294 11.02% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 300268759 # Type of FU issued
-system.cpu.iq.rate 2.311344 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2058685 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.006856 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 732516269 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 344212556 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 298017233 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 646 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 145 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 302295951 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 216 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 54147980 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 300263242 # Type of FU issued
+system.cpu.iq.rate 2.292437 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2057671 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.006853 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 733550061 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 344187115 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 298012847 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 262 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 328 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 104 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 302289511 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 54160833 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 10775614 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 30228 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 33222 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 3339713 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 10766713 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 30678 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 33261 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 3336738 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 3234 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 8606 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 3210 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 8599 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 4545203 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1761176 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 160180 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 311476154 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 195955 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 101554999 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 34779465 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 3219 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 73682 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 33222 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 393210 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 428039 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 821249 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 298868187 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 96891593 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1400572 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 4541560 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 2575832 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 162156 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 311462261 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 197211 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 101546098 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 34776490 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 463 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 2580 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 73528 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 33261 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 393064 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 427262 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 820326 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 298861022 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 96886540 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1402220 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 129818447 # number of memory reference insts executed
-system.cpu.iew.exec_branches 30819793 # Number of branches executed
-system.cpu.iew.exec_stores 32926854 # Number of stores executed
-system.cpu.iew.exec_rate 2.300563 # Inst execution rate
-system.cpu.iew.wb_sent 298386144 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 298017378 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 218312526 # num instructions producing a value
-system.cpu.iew.wb_consumers 296857185 # num instructions consuming a value
+system.cpu.iew.exec_refs 129814002 # number of memory reference insts executed
+system.cpu.iew.exec_branches 30818579 # Number of branches executed
+system.cpu.iew.exec_stores 32927462 # Number of stores executed
+system.cpu.iew.exec_rate 2.281732 # Inst execution rate
+system.cpu.iew.wb_sent 298381528 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 298012951 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 218258094 # num instructions producing a value
+system.cpu.iew.wb_consumers 296763752 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.294014 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.735413 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.275257 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.735461 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 33296720 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 33282582 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 775062 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 125284741 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.220482 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.978635 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 774373 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 126335414 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.202015 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.972310 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 57056182 45.54% 45.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 19092863 15.24% 60.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 11627505 9.28% 70.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 9458661 7.55% 77.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1851635 1.48% 79.09% # Number of insts commited each cycle
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system.cpu.committedInsts 157988547 # Number of Instructions Simulated
system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 157988547 # Number of Instructions Simulated
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-system.cpu.dcache.WriteReq_miss_latency::total 2106729496 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 33448316996 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 33448316996 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 33448316996 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 33448316996 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 42699344 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 42699344 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements 2072468 # number of replacements
+system.cpu.dcache.tagsinuse 4069.997432 # Cycle average of tags in use
+system.cpu.dcache.total_refs 71397556 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 2076564 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 34.382545 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 20655836000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4069.997432 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.993652 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.993652 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 40055849 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 40055849 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 31341707 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 31341707 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 71397556 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 71397556 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 71397556 # number of overall hits
+system.cpu.dcache.overall_hits::total 71397556 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 2625767 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 2625767 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 98045 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 98045 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 2723812 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2723812 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2723812 # number of overall misses
+system.cpu.dcache.overall_misses::total 2723812 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 31384094500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 31384094500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 2663792498 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 2663792498 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 34047886998 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 34047886998 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 34047886998 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 34047886998 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 42681616 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 42681616 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 74139096 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 74139096 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 74139096 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 74139096 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061521 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.061521 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 74121368 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 74121368 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 74121368 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 74121368 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061520 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.061520 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003119 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003119 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.036755 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.036755 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.036755 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.036755 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11930.903052 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11930.903052 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21486.715649 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 21486.715649 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12274.733363 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12274.733363 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12274.733363 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12274.733363 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 32679 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data 0.036748 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.036748 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.036748 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.036748 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11952.353160 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11952.353160 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.080504 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 27169.080504 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 12500.087010 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 12500.087010 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12500.087010 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 12500.087010 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 32905 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 9497 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 9507 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.440981 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 3.461134 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 2066867 # number of writebacks
-system.cpu.dcache.writebacks::total 2066867 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 632543 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 632543 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15848 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 15848 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 648391 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 648391 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 648391 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 648391 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994382 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1994382 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82200 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 82200 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2076582 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2076582 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2076582 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2076582 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21987816500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 21987816500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1833120496 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1833120496 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23820936996 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 23820936996 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23820936996 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 23820936996 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046708 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046708 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002615 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002615 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028009 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.028009 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028009 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.028009 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11024.877130 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11024.877130 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22300.735961 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22300.735961 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11471.223865 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11471.223865 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11471.223865 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11471.223865 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 2066544 # number of writebacks
+system.cpu.dcache.writebacks::total 2066544 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 631390 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 631390 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 15856 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 15856 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 647246 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 647246 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 647246 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 647246 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994377 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1994377 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82189 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 82189 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2076566 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2076566 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2076566 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2076566 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21994900501 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 21994900501 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2389827998 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2389827998 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24384728499 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 24384728499 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24384728499 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 24384728499 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046727 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046727 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002614 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002614 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028016 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.028016 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028016 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.028016 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11028.456757 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11028.456757 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29077.224422 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29077.224422 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11742.814097 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11742.814097 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11742.814097 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11742.814097 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 15992825110 # Throughput (bytes/s)
+system.membus.data_through_bus 2701988442 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 337900081 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 5272114 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 1025 # Transaction distribution
+system.membus.trans_dist::ReadResp 1025 # Transaction distribution
+system.membus.trans_dist::Writeback 100 # Transaction distribution
+system.membus.trans_dist::ReadExReq 29024 # Transaction distribution
+system.membus.trans_dist::ReadExResp 29024 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port 60198 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 1929536 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 30980000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 270472000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 731978130 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 722228529 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 106109 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 106109 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1616 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 6196142 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 6197758 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 51712 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 264276032 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 264327744 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 264327744 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1212000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.199986 # Number of seconds simulated
-sim_ticks 199986318000 # Number of ticks simulated
-final_tick 199986318000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.202265 # Number of seconds simulated
+sim_ticks 202264702500 # Number of ticks simulated
+final_tick 202264702500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 53828 # Simulator instruction rate (inst/s)
-host_op_rate 60688 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 21306693 # Simulator tick rate (ticks/s)
-host_mem_usage 292380 # Number of bytes of host memory used
-host_seconds 9386.08 # Real time elapsed on the host
+host_inst_rate 152154 # Simulator instruction rate (inst/s)
+host_op_rate 171544 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 60912686 # Simulator tick rate (ticks/s)
+host_mem_usage 250588 # Number of bytes of host memory used
+host_seconds 3320.57 # Real time elapsed on the host
sim_insts 505237723 # Number of instructions simulated
sim_ops 569624283 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 216704 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9268096 # Number of bytes read from this memory
-system.physmem.bytes_read::total 9484800 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 216704 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 216704 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6249408 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6249408 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3386 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 144814 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 148200 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 97647 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 97647 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1083594 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 46343650 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 47427244 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1083594 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1083594 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 31249178 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 31249178 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 31249178 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1083594 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 46343650 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 78676422 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 148200 # Total number of read requests seen
-system.physmem.writeReqs 97647 # Total number of write requests seen
-system.physmem.cpureqs 245864 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 9484800 # Total number of bytes read from memory
-system.physmem.bytesWritten 6249408 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 9484800 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6249408 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 78 # Number of read reqs serviced by write Q
+system.physmem.bytes_read::cpu.inst 216000 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9260928 # Number of bytes read from this memory
+system.physmem.bytes_read::total 9476928 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 216000 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 216000 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6246016 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6246016 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3375 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 144702 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 148077 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 97594 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 97594 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1067908 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 45786180 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 46854087 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1067908 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1067908 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 30880405 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 30880405 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 30880405 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1067908 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 45786180 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 77734493 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 148078 # Total number of read requests seen
+system.physmem.writeReqs 97594 # Total number of write requests seen
+system.physmem.cpureqs 245687 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 9476928 # Total number of bytes read from memory
+system.physmem.bytesWritten 6246016 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 9476928 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6246016 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 65 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 9 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 9181 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 9188 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 9616 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 9851 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 9533 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 9493 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 9413 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 9073 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 9057 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 9296 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 8842 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 9072 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 9240 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 9010 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 9027 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 9230 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 5960 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 5978 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 6283 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 6480 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 6185 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 6216 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 6227 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 6024 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 5968 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 6210 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 5897 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 6108 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 6001 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 5939 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 6059 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 6112 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::0 9583 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 9207 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 9281 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 8971 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 9774 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 9643 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 9100 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 8322 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 8802 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 8899 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 8932 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 9735 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 9616 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 9782 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 8932 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 9434 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 6260 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 6145 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 6098 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 5882 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 6246 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 6280 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 6041 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 5558 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 5810 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 5899 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 5989 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 6521 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 6350 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 6340 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 6045 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 6130 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry
-system.physmem.totGap 199986294500 # Total gap between requests
+system.physmem.numWrRetry 6 # Number of times wr buffer was full causing retry
+system.physmem.totGap 202264683000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 148200 # Categorize read packet sizes
+system.physmem.readPktSize::6 148078 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 97647 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 138069 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 9399 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 583 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 62 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 97594 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 138541 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 8888 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 4210 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 4229 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 4235 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 4237 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 4237 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 4237 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 4238 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 4238 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 4238 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 4246 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 4245 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 36 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 9 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 4223 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::4 4236 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 4235 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 4235 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 4237 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 4237 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 4243 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 4243 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 4243 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 4243 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 4243 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::15 4243 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 4243 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 4243 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 4243 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 4243 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 4243 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 4243 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 4243 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 21 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see
-system.physmem.totQLat 1719312500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 4989180000 # Sum of mem lat for all requests
-system.physmem.totBusLat 740610000 # Total cycles spent in databus access
-system.physmem.totBankLat 2529257500 # Total cycles spent in bank access
-system.physmem.avgQLat 11607.41 # Average queueing delay per request
-system.physmem.avgBankLat 17075.50 # Average bank access latency per request
+system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 55927 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 281.047508 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 134.123063 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 688.589570 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 27857 49.81% 49.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 10311 18.44% 68.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 4742 8.48% 76.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 2859 5.11% 81.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 1799 3.22% 85.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 1160 2.07% 87.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 842 1.51% 88.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 665 1.19% 89.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 468 0.84% 90.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 376 0.67% 91.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 271 0.48% 91.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 239 0.43% 92.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 201 0.36% 92.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 180 0.32% 92.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 171 0.31% 93.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 177 0.32% 93.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 169 0.30% 93.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 170 0.30% 94.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 147 0.26% 94.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 156 0.28% 94.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 167 0.30% 94.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 250 0.45% 95.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1473 974 1.74% 97.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 239 0.43% 97.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 147 0.26% 97.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1665 173 0.31% 98.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1729 101 0.18% 98.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1793 105 0.19% 98.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1857 71 0.13% 98.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1921 56 0.10% 98.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1985 36 0.06% 98.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2049 46 0.08% 98.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2113 27 0.05% 98.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2177 25 0.04% 99.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2241 21 0.04% 99.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2305 22 0.04% 99.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2369 17 0.03% 99.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2433 12 0.02% 99.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2497 14 0.03% 99.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2561 11 0.02% 99.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2625 12 0.02% 99.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2689 9 0.02% 99.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2753 11 0.02% 99.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2817 10 0.02% 99.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2881 4 0.01% 99.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2945 5 0.01% 99.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3009 8 0.01% 99.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3073 7 0.01% 99.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3137 3 0.01% 99.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3201 5 0.01% 99.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3265 3 0.01% 99.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3329 7 0.01% 99.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3393 4 0.01% 99.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3457 3 0.01% 99.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520-3521 2 0.00% 99.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3585 9 0.02% 99.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648-3649 6 0.01% 99.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3713 4 0.01% 99.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776-3777 1 0.00% 99.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840-3841 2 0.00% 99.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904-3905 2 0.00% 99.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3968-3969 1 0.00% 99.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4033 4 0.01% 99.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4096-4097 3 0.01% 99.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4160-4161 2 0.00% 99.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4224-4225 1 0.00% 99.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4288-4289 2 0.00% 99.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4416-4417 2 0.00% 99.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4480-4481 2 0.00% 99.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4736-4737 1 0.00% 99.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4800-4801 1 0.00% 99.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4928-4929 1 0.00% 99.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4992-4993 1 0.00% 99.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5056-5057 4 0.01% 99.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5120-5121 4 0.01% 99.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5184-5185 1 0.00% 99.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5248-5249 1 0.00% 99.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5376-5377 4 0.01% 99.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5440-5441 3 0.01% 99.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5568-5569 2 0.00% 99.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5696-5697 1 0.00% 99.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5760-5761 1 0.00% 99.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5952-5953 3 0.01% 99.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6144-6145 1 0.00% 99.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6272-6273 2 0.00% 99.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6336-6337 1 0.00% 99.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8128-8129 3 0.01% 99.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 256 0.46% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 55927 # Bytes accessed per row activation
+system.physmem.totQLat 1510568250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 4629837000 # Sum of mem lat for all requests
+system.physmem.totBusLat 740065000 # Total cycles spent in databus access
+system.physmem.totBankLat 2379203750 # Total cycles spent in bank access
+system.physmem.avgQLat 10205.65 # Average queueing delay per request
+system.physmem.avgBankLat 16074.29 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 33682.91 # Average memory access latency
-system.physmem.avgRdBW 47.43 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 31.25 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 47.43 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 31.25 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 31279.93 # Average memory access latency
+system.physmem.avgRdBW 46.85 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 30.88 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 46.85 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 30.88 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.61 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.02 # Average read queue length over time
-system.physmem.avgWrQLen 8.37 # Average write queue length over time
-system.physmem.readRowHits 125428 # Number of row buffer hits during reads
-system.physmem.writeRowHits 52865 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 84.68 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 54.14 # Row buffer hit rate for writes
-system.physmem.avgGap 813458.35 # Average gap between requests
-system.cpu.branchPred.lookups 182823475 # Number of BP lookups
-system.cpu.branchPred.condPredicted 143127293 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 7270205 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 92181207 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 87235258 # Number of BTB hits
+system.physmem.avgWrQLen 8.55 # Average write queue length over time
+system.physmem.readRowHits 130620 # Number of row buffer hits during reads
+system.physmem.writeRowHits 59055 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 88.25 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 60.51 # Row buffer hit rate for writes
+system.physmem.avgGap 823311.91 # Average gap between requests
+system.membus.throughput 77734493 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 46795 # Transaction distribution
+system.membus.trans_dist::ReadResp 46794 # Transaction distribution
+system.membus.trans_dist::Writeback 97594 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 9 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 9 # Transaction distribution
+system.membus.trans_dist::ReadExReq 101283 # Transaction distribution
+system.membus.trans_dist::ReadExResp 101283 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 393767 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 393767 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15722944 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 15722944 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 15722944 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 1079125750 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 1399666492 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
+system.cpu.branchPred.lookups 182795351 # Number of BP lookups
+system.cpu.branchPred.condPredicted 143107535 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 7264975 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 93466227 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 87209092 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 94.634537 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 12683949 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 116293 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 93.305459 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 12678830 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 116057 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
-system.cpu.numCycles 399972637 # number of cpu cycles simulated
+system.cpu.numCycles 404529406 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 119392306 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 761693904 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 182823475 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 99919207 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 170173986 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 35705843 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 75415774 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 31 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 554 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 37 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 114545284 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 2440918 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 392617380 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.175996 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.990505 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 119370904 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 761561247 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 182795351 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 99887922 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 170134463 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 35678521 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 77150212 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 98 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 455 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 48 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 114522843 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 2439505 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 394266586 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.166435 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.987414 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 222455990 56.66% 56.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 14183959 3.61% 60.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 22907819 5.83% 66.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 22738821 5.79% 71.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 20904503 5.32% 77.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 11594029 2.95% 80.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 13063211 3.33% 83.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 12002083 3.06% 86.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 52766965 13.44% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 224144737 56.85% 56.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 14179887 3.60% 60.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 22893161 5.81% 66.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 22745024 5.77% 72.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 20894474 5.30% 77.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 11598135 2.94% 80.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 13057002 3.31% 83.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 11992402 3.04% 86.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 52761764 13.38% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 392617380 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.457090 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.904365 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 129046079 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 70945312 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 158884174 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 6181299 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 27560516 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 26130325 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 76946 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 825690179 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 295591 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 27560516 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 135633063 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 9642191 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 46463188 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 158301033 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 15017389 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 800753920 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 1207 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 3038316 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 8776785 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 223 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 954449423 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3501232166 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3501230756 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1410 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 394266586 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.451872 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.882586 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 129061208 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 72641827 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 158799298 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 6227893 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 27536360 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 26125699 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 76608 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 825532349 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 291942 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 27536360 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 135656827 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 10155018 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 47441534 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 158249633 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 15227214 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 800580004 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 1401 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 3056484 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 8970861 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 208 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 954230970 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3500428728 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3500427418 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1310 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 288197132 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2293078 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2293075 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 41509096 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 170293066 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 73496638 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 28553519 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 15543647 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 755184516 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 3775403 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 665423791 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1392561 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 187499467 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 480050290 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 797771 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 392617380 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.694840 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.736370 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 287978679 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2292969 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2292967 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 41852604 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 170255884 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 73472812 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 28582851 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 15746500 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 755022174 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 3775311 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 665301102 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1380692 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 187339157 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 479760666 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 797679 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 394266586 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.687440 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.735091 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 137266683 34.96% 34.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 69764327 17.77% 52.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 71469341 18.20% 70.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 53405229 13.60% 84.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 31142767 7.93% 92.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 16033920 4.08% 96.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8799646 2.24% 98.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 2917185 0.74% 99.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1818282 0.46% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 138747020 35.19% 35.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 69982581 17.75% 52.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 71470863 18.13% 71.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 53423224 13.55% 84.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 31142023 7.90% 92.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 16022250 4.06% 96.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8747194 2.22% 98.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 2906831 0.74% 99.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1824600 0.46% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 392617380 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 394266586 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 479464 4.97% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 6557477 68.01% 72.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2605087 27.02% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 480987 5.01% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 6546208 68.16% 73.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 2577471 26.84% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 447824113 67.30% 67.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 383504 0.06% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 447771708 67.30% 67.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 383310 0.06% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 98 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 90 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 153397745 23.05% 90.41% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 63818328 9.59% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 153352638 23.05% 90.41% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 63793353 9.59% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 665423791 # Type of FU issued
-system.cpu.iq.rate 1.663673 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 9642028 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.014490 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1734499320 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 947266498 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 646124282 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 231 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 310 # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total 665301102 # Type of FU issued
+system.cpu.iq.rate 1.644630 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 9604666 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.014437 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1735853933 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 946943275 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 646028886 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 215 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 292 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 675065702 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 117 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 8583068 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses 674905659 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 109 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 8552862 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 44263511 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 42384 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 811218 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 16636161 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 44226329 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 41059 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 810522 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 16612335 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 19502 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 4251 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 19495 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 7104 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 27560516 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 5033845 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 374098 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 760518622 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1117950 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 170293066 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 73496638 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2286861 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 218393 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 11953 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 811218 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 4342934 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4001637 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 8344571 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 655982546 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 150110737 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 9441245 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 27536360 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 5290664 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 387489 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 760356154 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 1118953 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 170255884 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 73472812 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 2286769 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 219863 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 12400 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 810522 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 4337912 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 4002750 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 8340662 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 655875003 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 150077564 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 9426099 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1558703 # number of nop insts executed
-system.cpu.iew.exec_refs 212627196 # number of memory reference insts executed
-system.cpu.iew.exec_branches 138502657 # Number of branches executed
-system.cpu.iew.exec_stores 62516459 # Number of stores executed
-system.cpu.iew.exec_rate 1.640069 # Inst execution rate
-system.cpu.iew.wb_sent 651101010 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 646124298 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 374793054 # num instructions producing a value
-system.cpu.iew.wb_consumers 646490687 # num instructions consuming a value
+system.cpu.iew.exec_nop 1558669 # number of nop insts executed
+system.cpu.iew.exec_refs 212570616 # number of memory reference insts executed
+system.cpu.iew.exec_branches 138493352 # Number of branches executed
+system.cpu.iew.exec_stores 62493052 # Number of stores executed
+system.cpu.iew.exec_rate 1.621328 # Inst execution rate
+system.cpu.iew.wb_sent 650999754 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 646028902 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 374692861 # num instructions producing a value
+system.cpu.iew.wb_consumers 646290036 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.615421 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.579735 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.596989 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.579760 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 189577075 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 189414626 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 7196029 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 365056864 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.564053 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.233130 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 7190929 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 366730226 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.556916 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.230567 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 157408999 43.12% 43.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 98427012 26.96% 70.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 33819592 9.26% 79.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 18764553 5.14% 84.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 16211195 4.44% 88.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 7486266 2.05% 90.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 7003829 1.92% 92.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3174116 0.87% 93.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 22761302 6.24% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 159030510 43.36% 43.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 98471088 26.85% 70.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 33850160 9.23% 79.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 18801710 5.13% 84.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 16194042 4.42% 88.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 7449344 2.03% 91.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 6951093 1.90% 92.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3196049 0.87% 93.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 22786230 6.21% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 365056864 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 366730226 # Number of insts commited each cycle
system.cpu.commit.committedInsts 506581607 # Number of instructions committed
system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 470727693 # Number of committed integer instructions.
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 22761302 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 22786230 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1102833666 # The number of ROB reads
-system.cpu.rob.rob_writes 1548772691 # The number of ROB writes
-system.cpu.timesIdled 308172 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 7355257 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 1104319651 # The number of ROB reads
+system.cpu.rob.rob_writes 1548423446 # The number of ROB writes
+system.cpu.timesIdled 327931 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 10262820 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 505237723 # Number of Instructions Simulated
system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated
-system.cpu.cpi 0.791652 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.791652 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.263181 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.263181 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3059089015 # number of integer regfile reads
-system.cpu.int_regfile_writes 752056601 # number of integer regfile writes
+system.cpu.cpi 0.800671 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.800671 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.248952 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.248952 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3058568749 # number of integer regfile reads
+system.cpu.int_regfile_writes 751946172 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 210873671 # number of misc regfile reads
+system.cpu.misc_regfile_reads 210826056 # number of misc regfile reads
system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
-system.cpu.icache.replacements 14975 # number of replacements
-system.cpu.icache.tagsinuse 1101.758220 # Cycle average of tags in use
-system.cpu.icache.total_refs 114524199 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 16829 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 6805.169588 # Average number of references to valid blocks.
+system.cpu.toL2Bus.throughput 735267470 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 864400 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 864399 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 1110556 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 92 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 92 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 348774 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 348774 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 33891 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3503090 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 3536981 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1081088 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 147630784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 148711872 # Cumulative packet size per connected master and slave (bytes)
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-system.cpu.dcache.overall_hits::cpu.data 187201931 # number of overall hits
-system.cpu.dcache.overall_hits::total 187201931 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1698949 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1698949 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 3247674 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 3247674 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 4946623 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 4946623 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 4946623 # number of overall misses
-system.cpu.dcache.overall_misses::total 4946623 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 26713032500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 26713032500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 57280936446 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 57280936446 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 664500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 664500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 83993968946 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 83993968946 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 83993968946 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 83993968946 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 137909248 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 137909248 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data 187192750 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 187192750 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 187192750 # number of overall hits
+system.cpu.dcache.overall_hits::total 187192750 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1701442 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1701442 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 3251025 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 3251025 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 38 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 38 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 4952467 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 4952467 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 4952467 # number of overall misses
+system.cpu.dcache.overall_misses::total 4952467 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 29643398500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 29643398500 # number of ReadReq miss cycles
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+system.cpu.dcache.WriteReq_miss_latency::total 68982804444 # number of WriteReq miss cycles
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+system.cpu.dcache.LoadLockedReq_miss_latency::total 639500 # number of LoadLockedReq miss cycles
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+system.cpu.dcache.demand_miss_latency::total 98626202944 # number of demand (read+write) miss cycles
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+system.cpu.dcache.ReadReq_accesses::cpu.data 137905911 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 137905911 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488864 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 1488864 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488869 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 1488869 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 192148554 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 192148554 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 192148554 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 192148554 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012319 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.012319 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059877 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.059877 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.025744 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.025744 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.025744 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.025744 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15723.269209 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15723.269209 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17637.526564 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 17637.526564 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16207.317073 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16207.317073 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 16980.062751 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 16980.062751 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16980.062751 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16980.062751 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 15427 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 16116 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1677 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 607 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.199165 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 26.550247 # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 192145217 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 192145217 # number of demand (read+write) accesses
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+system.cpu.dcache.overall_accesses::total 192145217 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012338 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.012338 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059939 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.059939 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000026 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000026 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.025775 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.025775 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.025775 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.025775 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17422.514843 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17422.514843 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21218.786212 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 21218.786212 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16828.947368 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16828.947368 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 19914.560348 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 19914.560348 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 19914.560348 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 19914.560348 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 17857 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 40598 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 1694 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 662 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.541322 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 61.326284 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1110717 # number of writebacks
-system.cpu.dcache.writebacks::total 1110717 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 850753 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 850753 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2899322 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2899322 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3750075 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3750075 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3750075 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3750075 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848196 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 848196 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348352 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 348352 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1196548 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1196548 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1196548 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1196548 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11853689000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 11853689000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8094107996 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8094107996 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19947796996 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 19947796996 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19947796996 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 19947796996 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006150 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006150 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.006227 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.006227 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13975.176728 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13975.176728 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23235.428521 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23235.428521 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16671.121423 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 16671.121423 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16671.121423 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16671.121423 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 1110556 # number of writebacks
+system.cpu.dcache.writebacks::total 1110556 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 853509 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 853509 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902691 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2902691 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 38 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 38 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3756200 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3756200 # number of demand (read+write) MSHR hits
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+system.cpu.dcache.overall_mshr_hits::total 3756200 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 847933 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 847933 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348334 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 348334 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1196267 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1196267 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1196267 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1196267 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12570935024 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 12570935024 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9915738995 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 9915738995 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22486674019 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 22486674019 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22486674019 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 22486674019 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006149 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006149 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006422 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006422 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006226 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.006226 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006226 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.006226 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14825.387176 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14825.387176 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28466.181869 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28466.181869 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18797.370503 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 18797.370503 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18797.370503 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 18797.370503 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 290498967000 # Number of ticks simulated
final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1613323 # Simulator instruction rate (inst/s)
-host_op_rate 1818377 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 925159382 # Simulator tick rate (ticks/s)
-host_mem_usage 282068 # Number of bytes of host memory used
-host_seconds 314.00 # Real time elapsed on the host
+host_inst_rate 1591705 # Simulator instruction rate (inst/s)
+host_op_rate 1794011 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 912762441 # Simulator tick rate (ticks/s)
+host_mem_usage 237748 # Number of bytes of host memory used
+host_seconds 318.26 # Real time elapsed on the host
sim_insts 506581607 # Number of instructions simulated
sim_ops 570968167 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7113434933 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2199389318 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9312824252 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 9312824252 # Throughput (bytes/s)
+system.membus.data_through_bus 2705365825 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
sim_ticks 717366012000 # Number of ticks simulated
final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 858996 # Simulator instruction rate (inst/s)
-host_op_rate 967944 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1220258898 # Simulator tick rate (ticks/s)
-host_mem_usage 290524 # Number of bytes of host memory used
-host_seconds 587.88 # Real time elapsed on the host
+host_inst_rate 611042 # Simulator instruction rate (inst/s)
+host_op_rate 688541 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 868024183 # Simulator tick rate (ticks/s)
+host_mem_usage 246240 # Number of bytes of host memory used
+host_seconds 826.44 # Real time elapsed on the host
sim_insts 504986853 # Number of instructions simulated
sim_ops 569034839 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 247126 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 12479342 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 21286941 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 21286941 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 41855 # Transaction distribution
+system.membus.trans_dist::ReadResp 41855 # Transaction distribution
+system.membus.trans_dist::Writeback 95953 # Transaction distribution
+system.membus.trans_dist::ReadExReq 100794 # Transaction distribution
+system.membus.trans_dist::ReadExResp 100794 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 381251 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 381251 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15270528 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 15270528 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 15270528 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 1006226000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer1.occupancy 1283841000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 197642506 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 356260 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 356260 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 23042 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3342741 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 3365783 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 737344 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 141044672 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 141782016 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 141782016 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 17281500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 1708377000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.451833 # Number of seconds simulated
-sim_ticks 451832922000 # Number of ticks simulated
-final_tick 451832922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.458090 # Number of seconds simulated
+sim_ticks 458090415000 # Number of ticks simulated
+final_tick 458090415000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 67045 # Simulator instruction rate (inst/s)
-host_op_rate 123974 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 36635806 # Simulator tick rate (ticks/s)
-host_mem_usage 390776 # Number of bytes of host memory used
-host_seconds 12333.10 # Real time elapsed on the host
+host_inst_rate 96465 # Simulator instruction rate (inst/s)
+host_op_rate 178374 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 53441498 # Simulator tick rate (ticks/s)
+host_mem_usage 343040 # Number of bytes of host memory used
+host_seconds 8571.81 # Real time elapsed on the host
sim_insts 826877109 # Number of instructions simulated
sim_ops 1528988701 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 202816 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24482112 # Number of bytes read from this memory
-system.physmem.bytes_read::total 24684928 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 202816 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 202816 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 18794304 # Number of bytes written to this memory
-system.physmem.bytes_written::total 18794304 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3169 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 382533 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 385702 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 293661 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 293661 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 448874 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 54183993 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 54632867 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 448874 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 448874 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 41595694 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 41595694 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 41595694 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 448874 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 54183993 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 96228561 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 385702 # Total number of read requests seen
-system.physmem.writeReqs 293661 # Total number of write requests seen
-system.physmem.cpureqs 815428 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 24684928 # Total number of bytes read from memory
-system.physmem.bytesWritten 18794304 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 24684928 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 18794304 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 138 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 136028 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 23108 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 24460 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 23977 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 22639 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 23451 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 24452 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 24479 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 24189 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 24310 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 25055 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 24328 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 24340 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 24467 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 23420 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 24898 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 23991 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 17770 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 18792 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 18332 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 17557 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 18019 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 18441 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 18303 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 18298 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 18726 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 19016 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 18442 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 18563 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 18552 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 17871 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 18864 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 18115 # Track writes on a per bank basis
+system.physmem.bytes_read::cpu.inst 202496 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24476544 # Number of bytes read from this memory
+system.physmem.bytes_read::total 24679040 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 202496 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 202496 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 18790272 # Number of bytes written to this memory
+system.physmem.bytes_written::total 18790272 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3164 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 382446 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 385610 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 293598 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 293598 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 442044 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 53431688 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 53873731 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 442044 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 442044 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 41018697 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 41018697 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 41018697 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 442044 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 53431688 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 94892429 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 385610 # Total number of read requests seen
+system.physmem.writeReqs 293598 # Total number of write requests seen
+system.physmem.cpureqs 811581 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 24679040 # Total number of bytes read from memory
+system.physmem.bytesWritten 18790272 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 24679040 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 18790272 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 158 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 132366 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 24064 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 26444 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 24671 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 24517 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 23227 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 23669 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 24418 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 24212 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 23609 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 23834 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 24778 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 24050 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 23243 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 22960 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 23768 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 23988 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 18530 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 19820 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 18950 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 18922 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 18033 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 18412 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 18983 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 18945 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 18535 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 18118 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 18807 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 17707 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 17351 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 16952 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 17709 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 17824 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 37 # Number of times wr buffer was full causing retry
-system.physmem.totGap 451832896000 # Total gap between requests
+system.physmem.numWrRetry 7 # Number of times wr buffer was full causing retry
+system.physmem.totGap 458090389000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 385702 # Categorize read packet sizes
+system.physmem.readPktSize::6 385610 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 293661 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 380831 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4356 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 329 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 44 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 293598 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 380772 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 4340 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 300 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 12709 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 12717 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 12719 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 12722 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 12722 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 12723 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 12725 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 12728 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 12729 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 12768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 12767 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 59 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 51 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 49 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 46 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 46 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 45 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 43 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 40 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 39 # What write queue length does an incoming req see
-system.physmem.totQLat 3445991500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 12040169000 # Sum of mem lat for all requests
-system.physmem.totBusLat 1927820000 # Total cycles spent in databus access
-system.physmem.totBankLat 6666357500 # Total cycles spent in bank access
-system.physmem.avgQLat 8937.53 # Average queueing delay per request
-system.physmem.avgBankLat 17289.89 # Average bank access latency per request
+system.physmem.wrQLenPdf::0 12721 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 12730 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 12733 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 12738 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 12746 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 12748 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 12751 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 12755 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 12756 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 12765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 12765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 12765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 12765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 12765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 12765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 12765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 12765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 12765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 12765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 12765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 12765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 12765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 12765 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 45 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 36 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 33 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 27 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 19 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 126022 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 344.851534 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 161.962358 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 666.348366 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 54057 42.89% 42.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 23501 18.65% 61.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 10538 8.36% 69.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 6321 5.02% 74.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 4049 3.21% 78.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 2993 2.37% 80.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 2158 1.71% 82.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 1750 1.39% 83.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 1435 1.14% 84.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 1167 0.93% 85.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 1218 0.97% 86.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 1087 0.86% 87.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 749 0.59% 88.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 671 0.53% 88.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 595 0.47% 89.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 568 0.45% 89.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 568 0.45% 90.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 525 0.42% 90.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 573 0.45% 90.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 736 0.58% 91.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 592 0.47% 91.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 743 0.59% 92.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1473 6177 4.90% 97.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 481 0.38% 97.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 330 0.26% 98.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1665 288 0.23% 98.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1729 210 0.17% 98.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1793 190 0.15% 98.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1857 142 0.11% 98.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1921 147 0.12% 98.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1985 96 0.08% 98.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2049 92 0.07% 98.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2113 69 0.05% 99.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2177 52 0.04% 99.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2241 45 0.04% 99.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2305 44 0.03% 99.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2369 35 0.03% 99.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2433 33 0.03% 99.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2497 28 0.02% 99.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2561 24 0.02% 99.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2625 31 0.02% 99.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2689 21 0.02% 99.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2753 18 0.01% 99.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2817 25 0.02% 99.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2881 22 0.02% 99.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2945 20 0.02% 99.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3009 17 0.01% 99.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3073 13 0.01% 99.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3137 15 0.01% 99.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3201 13 0.01% 99.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3265 16 0.01% 99.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3329 17 0.01% 99.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3393 6 0.00% 99.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3457 9 0.01% 99.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520-3521 7 0.01% 99.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3585 17 0.01% 99.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648-3649 9 0.01% 99.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3713 10 0.01% 99.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776-3777 8 0.01% 99.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840-3841 13 0.01% 99.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904-3905 9 0.01% 99.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3968-3969 7 0.01% 99.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4033 5 0.00% 99.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4096-4097 13 0.01% 99.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4160-4161 4 0.00% 99.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4224-4225 7 0.01% 99.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4288-4289 8 0.01% 99.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4352-4353 7 0.01% 99.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4416-4417 6 0.00% 99.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4480-4481 5 0.00% 99.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4544-4545 4 0.00% 99.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4608-4609 4 0.00% 99.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4672-4673 8 0.01% 99.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4736-4737 2 0.00% 99.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4800-4801 4 0.00% 99.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4864-4865 2 0.00% 99.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4928-4929 6 0.00% 99.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4992-4993 6 0.00% 99.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5056-5057 7 0.01% 99.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5184-5185 9 0.01% 99.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5248-5249 3 0.00% 99.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5312-5313 8 0.01% 99.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5376-5377 11 0.01% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5440-5441 4 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5504-5505 5 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5568-5569 5 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5632-5633 3 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5696-5697 4 0.00% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5760-5761 3 0.00% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5824-5825 4 0.00% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5952-5953 3 0.00% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6080-6081 3 0.00% 99.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6144-6145 4 0.00% 99.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6208-6209 2 0.00% 99.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6400-6401 2 0.00% 99.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6464-6465 6 0.00% 99.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6528-6529 7 0.01% 99.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6656-6657 5 0.00% 99.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6720-6721 3 0.00% 99.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6784-6785 3 0.00% 99.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6912-6913 4 0.00% 99.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6976-6977 4 0.00% 99.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7232-7233 3 0.00% 99.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7296-7297 4 0.00% 99.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7552-7553 3 0.00% 99.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7808-7809 3 0.00% 99.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7936-7937 3 0.00% 99.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8000-8001 3 0.00% 99.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8064-8065 1 0.00% 99.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8128-8129 4 0.00% 99.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 373 0.30% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 126022 # Bytes accessed per row activation
+system.physmem.totQLat 3040953000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 11219526750 # Sum of mem lat for all requests
+system.physmem.totBusLat 1927260000 # Total cycles spent in databus access
+system.physmem.totBankLat 6251313750 # Total cycles spent in bank access
+system.physmem.avgQLat 7889.32 # Average queueing delay per request
+system.physmem.avgBankLat 16218.14 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 31227.42 # Average memory access latency
-system.physmem.avgRdBW 54.63 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 41.60 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 54.63 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 41.60 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 29107.46 # Average memory access latency
+system.physmem.avgRdBW 53.87 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 41.02 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 53.87 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 41.02 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 0.75 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.03 # Average read queue length over time
-system.physmem.avgWrQLen 8.94 # Average write queue length over time
-system.physmem.readRowHits 331871 # Number of row buffer hits during reads
-system.physmem.writeRowHits 191829 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 86.07 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 65.32 # Row buffer hit rate for writes
-system.physmem.avgGap 665083.17 # Average gap between requests
-system.cpu.branchPred.lookups 205621718 # Number of BP lookups
-system.cpu.branchPred.condPredicted 205621718 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 9907083 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 117077740 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 114695478 # Number of BTB hits
+system.physmem.busUtil 0.74 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.02 # Average read queue length over time
+system.physmem.avgWrQLen 10.25 # Average write queue length over time
+system.physmem.readRowHits 346179 # Number of row buffer hits during reads
+system.physmem.writeRowHits 206846 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 89.81 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 70.45 # Row buffer hit rate for writes
+system.physmem.avgGap 674447.87 # Average gap between requests
+system.membus.throughput 94892429 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 178764 # Transaction distribution
+system.membus.trans_dist::ReadResp 178764 # Transaction distribution
+system.membus.trans_dist::Writeback 293598 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 132366 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 132366 # Transaction distribution
+system.membus.trans_dist::ReadExReq 206846 # Transaction distribution
+system.membus.trans_dist::ReadExResp 206846 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1329550 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1329550 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port 1329550 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1329550 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43469312 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43469312 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.physmem.port 43469312 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 43469312 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 43469312 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 3305392000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
+system.membus.respLayer1.occupancy 3861844643 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.8 # Layer utilization (%)
+system.cpu.branchPred.lookups 205596082 # Number of BP lookups
+system.cpu.branchPred.condPredicted 205596082 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 9898225 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 117113450 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 114684719 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.965231 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 25073647 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1800250 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 97.926172 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 25065236 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1793499 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 551 # Number of system calls
-system.cpu.numCycles 903825131 # number of cpu cycles simulated
+system.cpu.numCycles 916341755 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 167418043 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1132282338 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 205621718 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 139769125 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 352430400 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 71153000 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 297148174 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 48797 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 255592 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 33 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 162064992 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 2572532 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 878293133 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.398381 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.331165 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 167380851 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1131684299 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 205596082 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 139749955 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 352238514 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 71080243 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 303608780 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 49221 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 257762 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 41 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 162013900 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 2533511 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 884463501 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.380571 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.325217 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 529920988 60.34% 60.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 23389932 2.66% 63.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 25306191 2.88% 65.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 27947555 3.18% 69.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 17765128 2.02% 71.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 22905202 2.61% 73.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 29375609 3.34% 77.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 26663527 3.04% 80.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 175019001 19.93% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 536297540 60.64% 60.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 23375974 2.64% 63.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 25249823 2.85% 66.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 27885460 3.15% 69.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 17746776 2.01% 71.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 22912915 2.59% 73.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 29432713 3.33% 77.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 26649868 3.01% 80.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 174912432 19.78% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 878293133 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.227502 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.252767 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 222360951 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 252528998 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 295744531 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 46666559 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 60992094 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2071948592 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 60992094 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 255743691 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 109858014 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 17204 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 306968990 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 144713140 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2035757004 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 14813 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 25048489 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 104458594 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 180 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 2138803025 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5151932301 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 5151817228 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 115073 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 884463501 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.224366 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.235002 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 222590662 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 258678079 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 295142458 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 47123970 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 60928332 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2071292159 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 60928332 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 256060013 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 114129471 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 17113 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 306672128 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 146656444 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2035150603 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 19208 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 24905685 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 106527720 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 191 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 2137983634 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5150411981 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 5150294631 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 117350 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 524762171 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1163 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1096 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 344343454 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 496005535 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 194479256 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 195803959 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 55147463 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1975947809 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 16072 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1772430246 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 489293 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 442088890 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 735772933 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 15520 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 878293133 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.018040 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.884895 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 523942780 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1169 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1101 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 347123881 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 495862419 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 194434977 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 195681210 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 55050050 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 1975391803 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 13688 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1772107860 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 473436 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 441529176 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 734849750 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 13136 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 884463501 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.003596 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.883133 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 263200988 29.97% 29.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 149900664 17.07% 47.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 137095286 15.61% 62.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 132054982 15.04% 77.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 91669420 10.44% 88.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 56193413 6.40% 94.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 34492530 3.93% 98.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 11912661 1.36% 99.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1773189 0.20% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 267821241 30.28% 30.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 151877147 17.17% 47.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 137227346 15.52% 62.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 131884953 14.91% 77.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 91607169 10.36% 88.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 55986805 6.33% 94.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 34422638 3.89% 98.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 11866983 1.34% 99.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1769219 0.20% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 878293133 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 884463501 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 4998230 32.74% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 7655755 50.14% 82.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2613853 17.12% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 4968361 32.63% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 7638299 50.16% 82.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 2620527 17.21% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 2627910 0.15% 0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1165981895 65.78% 65.93% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 352516 0.02% 65.95% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 3880818 0.22% 66.17% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 2623300 0.15% 0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1165765153 65.78% 65.93% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 352884 0.02% 65.95% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 3880872 0.22% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 429341212 24.22% 90.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 170245895 9.61% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 429256529 24.22% 90.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 170229122 9.61% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1772430246 # Type of FU issued
-system.cpu.iq.rate 1.961032 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 15267838 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.008614 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4438895750 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2418277528 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1745063548 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 15006 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 33162 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 3630 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1785062995 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 7179 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 172239839 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1772107860 # Type of FU issued
+system.cpu.iq.rate 1.933894 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 15227187 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.008593 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4444363529 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2417156929 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1744871940 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 16315 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 34548 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 3820 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1784704039 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 7708 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 172523009 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 111903378 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 383433 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 329474 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 45320259 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 111760262 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 384025 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 328721 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 45275855 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 14682 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 568 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 15305 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 564 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 60992094 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 64075051 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 7111223 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1975963881 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 801543 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 496005535 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 194480445 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 3509 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 4460880 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 83569 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 329474 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 5903386 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4417104 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 10320490 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1753197001 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 424204757 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 19233245 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 60928332 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 66654454 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 7158115 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 1975405491 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 788328 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 495862419 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 194436041 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 3451 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 4460839 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 82816 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 328721 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 5900080 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 4426535 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 10326615 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1752972690 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 424121378 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 19135170 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 591004689 # number of memory reference insts executed
-system.cpu.iew.exec_branches 167488871 # Number of branches executed
-system.cpu.iew.exec_stores 166799932 # Number of stores executed
-system.cpu.iew.exec_rate 1.939752 # Inst execution rate
-system.cpu.iew.wb_sent 1749947599 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1745067178 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1326505641 # num instructions producing a value
-system.cpu.iew.wb_consumers 1948512890 # num instructions consuming a value
+system.cpu.iew.exec_refs 590916604 # number of memory reference insts executed
+system.cpu.iew.exec_branches 167471832 # Number of branches executed
+system.cpu.iew.exec_stores 166795226 # Number of stores executed
+system.cpu.iew.exec_rate 1.913012 # Inst execution rate
+system.cpu.iew.wb_sent 1749734148 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1744875760 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1325266031 # num instructions producing a value
+system.cpu.iew.wb_consumers 1946145137 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.930758 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.680778 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.904176 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.680970 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 447002783 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 446445392 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 9936450 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 817301039 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.870778 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.444599 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 9927956 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 823535169 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.856616 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.436023 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 326881530 40.00% 40.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 191845418 23.47% 63.47% # Number of insts commited each cycle
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system.cpu.commit.committedInsts 826877109 # Number of instructions committed
system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
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system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
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system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.committedInsts 826877109 # Number of Instructions Simulated
system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated
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-system.cpu.cpi_total 1.093059 # CPI: Total CPI of All Threads
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-system.cpu.ipc_total 0.914864 # IPC: Total IPC of All Threads
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+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20416.820096 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20416.820096 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
system.physmem.bw_total::cpu.inst 9654872754 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13357308966 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 13357308966 # Throughput (bytes/s)
+system.membus.data_through_bus 11824281640 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 1770458657 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 26154600 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 174452 # Transaction distribution
+system.membus.trans_dist::ReadResp 174452 # Transaction distribution
+system.membus.trans_dist::Writeback 292286 # Transaction distribution
+system.membus.trans_dist::ReadExReq 206691 # Transaction distribution
+system.membus.trans_dist::ReadExResp 206691 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port 1054572 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 43099456 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 3011737000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
+system.membus.respLayer1.occupancy 3430300500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 3295745698 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 188161896 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 1730228 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 791044 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 791044 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 5628 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 7360439 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 7366067 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 180096 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 309886784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 310066880 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 310066880 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.139855 # Number of seconds simulated
-sim_ticks 139855372500 # Number of ticks simulated
-final_tick 139855372500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.139913 # Number of seconds simulated
+sim_ticks 139912878500 # Number of ticks simulated
+final_tick 139912878500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 118034 # Simulator instruction rate (inst/s)
-host_op_rate 118034 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 41407532 # Simulator tick rate (ticks/s)
-host_mem_usage 230404 # Number of bytes of host memory used
-host_seconds 3377.53 # Real time elapsed on the host
+host_inst_rate 81894 # Simulator instruction rate (inst/s)
+host_op_rate 81894 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 28740964 # Simulator tick rate (ticks/s)
+host_mem_usage 231128 # Number of bytes of host memory used
+host_seconds 4868.07 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1537131 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1816276 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3353407 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1537131 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1537131 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1537131 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1816276 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3353407 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1536499 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1815530 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3352029 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1536499 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1536499 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1536499 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1815530 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3352029 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7328 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 7328 # Reqs generatd by CPU via cache - shady
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 442 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 430 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 467 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 455 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 578 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 528 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 507 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 643 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 444 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 597 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 448 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 451 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 505 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 412 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 466 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 444 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 394 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 422 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 394 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 459 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 423 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 509 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 513 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 423 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 395 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 336 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 304 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 416 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 534 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 441 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 371 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 139855320500 # Total gap between requests
+system.physmem.totGap 139912806500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 4560 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1887 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 585 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 230 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 65 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 4704 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1856 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 185 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 47654000 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 197332750 # Sum of mem lat for all requests
+system.physmem.bytesPerActivate::samples 702 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 659.145299 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 261.737271 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 1246.496021 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 193 27.49% 27.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 99 14.10% 41.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 67 9.54% 51.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 56 7.98% 59.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 35 4.99% 64.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 20 2.85% 66.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 23 3.28% 70.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 21 2.99% 73.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 15 2.14% 75.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 12 1.71% 77.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 9 1.28% 78.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 4 0.57% 78.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 12 1.71% 80.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 8 1.14% 81.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 4 0.57% 82.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 5 0.71% 83.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 15 2.14% 85.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 5 0.71% 85.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 6 0.85% 86.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 1 0.14% 86.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 4 0.57% 87.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 4 0.57% 88.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1473 4 0.57% 88.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 3 0.43% 89.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 6 0.85% 89.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1665 6 0.85% 90.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1729 2 0.28% 91.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1793 3 0.43% 91.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1857 2 0.28% 91.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1921 1 0.14% 91.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1985 3 0.43% 92.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2049 2 0.28% 92.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2113 4 0.57% 93.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2177 2 0.28% 93.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2241 2 0.28% 93.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2305 1 0.14% 93.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2369 2 0.28% 94.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2497 3 0.43% 94.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2561 2 0.28% 94.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2689 3 0.43% 95.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2753 1 0.14% 95.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2817 1 0.14% 95.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2881 1 0.14% 95.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2945 1 0.14% 95.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3201 1 0.14% 96.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3265 2 0.28% 96.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3329 1 0.14% 96.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3585 1 0.14% 96.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4033 2 0.28% 96.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4160-4161 1 0.14% 97.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4224-4225 1 0.14% 97.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4480-4481 1 0.14% 97.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4544-4545 1 0.14% 97.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4608-4609 1 0.14% 97.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4992-4993 1 0.14% 97.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5312-5313 1 0.14% 97.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5632-5633 1 0.14% 98.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5888-5889 1 0.14% 98.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6208-6209 1 0.14% 98.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6400-6401 1 0.14% 98.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6464-6465 1 0.14% 98.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6592-6593 1 0.14% 98.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7232-7233 1 0.14% 98.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7296-7297 1 0.14% 99.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 7 1.00% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 702 # Bytes accessed per row activation
+system.physmem.totQLat 37727500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 172831250 # Sum of mem lat for all requests
system.physmem.totBusLat 36640000 # Total cycles spent in databus access
-system.physmem.totBankLat 113038750 # Total cycles spent in bank access
-system.physmem.avgQLat 6503.00 # Average queueing delay per request
-system.physmem.avgBankLat 15425.59 # Average bank access latency per request
+system.physmem.totBankLat 98463750 # Total cycles spent in bank access
+system.physmem.avgQLat 5148.40 # Average queueing delay per request
+system.physmem.avgBankLat 13436.65 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26928.60 # Average memory access latency
+system.physmem.avgMemAccLat 23585.05 # Average memory access latency
system.physmem.avgRdBW 3.35 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 3.35 # Average consumed read bandwidth in MB/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 6132 # Number of row buffer hits during reads
+system.physmem.readRowHits 6626 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.68 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 90.42 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 19085060.11 # Average gap between requests
-system.cpu.branchPred.lookups 53489671 # Number of BP lookups
-system.cpu.branchPred.condPredicted 30685392 # Number of conditional branches predicted
+system.physmem.avgGap 19092904.82 # Average gap between requests
+system.membus.throughput 3352029 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 4183 # Transaction distribution
+system.membus.trans_dist::ReadResp 4183 # Transaction distribution
+system.membus.trans_dist::ReadExReq 3145 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3145 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 14656 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 14656 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 468992 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 468992 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 468992 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 8784000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 68408750 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu.branchPred.lookups 53489761 # Number of BP lookups
+system.cpu.branchPred.condPredicted 30685482 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 32882352 # Number of BTB lookups
+system.cpu.branchPred.BTBLookups 32882438 # Number of BTB lookups
system.cpu.branchPred.BTBHits 15212539 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 46.263537 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 46.263416 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 94754610 # DTB read hits
+system.cpu.dtb.read_hits 94754611 # DTB read hits
system.cpu.dtb.read_misses 21 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 94754631 # DTB read accesses
-system.cpu.dtb.write_hits 73521101 # DTB write hits
+system.cpu.dtb.read_accesses 94754632 # DTB read accesses
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system.cpu.dtb.write_misses 35 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 73521136 # DTB write accesses
-system.cpu.dtb.data_hits 168275711 # DTB hits
+system.cpu.dtb.write_accesses 73521157 # DTB write accesses
+system.cpu.dtb.data_hits 168275733 # DTB hits
system.cpu.dtb.data_misses 56 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 168275767 # DTB accesses
-system.cpu.itb.fetch_hits 48611339 # ITB hits
+system.cpu.dtb.data_accesses 168275789 # DTB accesses
+system.cpu.itb.fetch_hits 48611325 # ITB hits
system.cpu.itb.fetch_misses 44520 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 48655859 # ITB accesses
+system.cpu.itb.fetch_accesses 48655845 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 29230506 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 24259165 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 280386586 # Number of Reads from Int. Register File
+system.cpu.branch_predictor.predictedNotTaken 24259255 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 439722445 # Total Accesses (Read+Write) to the Int. Register File
-system.cpu.regfile_manager.floatRegFileReads 119631954 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
-system.cpu.regfile_manager.floatRegFileAccesses 219828435 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 100484559 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 168485322 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 279400786 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 279401420 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 7707 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 13404116 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 266306630 # Number of cycles cpu stages are processed.
-system.cpu.activity 95.207865 # Percentage of cycles cpu is active
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+system.cpu.activity 95.168773 # Percentage of cycles cpu is active
system.cpu.comLoads 94754489 # Number of Load instructions committed
system.cpu.comStores 73520729 # Number of Store instructions committed
system.cpu.comBranches 44587532 # Number of Branches instructions committed
system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
-system.cpu.cpi 0.701619 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 0.701908 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 0.701619 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.425275 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 0.701908 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.424689 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 1.425275 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 77963056 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 201747690 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 72.127257 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 107059011 # Number of cycles 0 instructions are processed.
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-system.cpu.stage1.utilization 61.725099 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 102495582 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 177215164 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 63.356581 # Percentage of cycles stage was utilized (processing insts).
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+system.cpu.stage4.utilization 67.709245 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 1975 # number of replacements
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system.cpu.icache.sampled_refs 3903 # Sample count of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1831.214739 # Average occupied blocks per requestor
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45565.661047 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 45565.661047 # average ReadReq miss latency
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-system.cpu.icache.blocked_cycles::no_mshrs 206 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
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+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60172.303356 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 60172.303356 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60172.303356 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 60172.303356 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 3981449 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 4850 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 4850 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 3205 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 3205 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 7806 # Packet count per connected master and slave (bytes)
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+system.cpu.toL2Bus.pkt_count 16759 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 249792 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 307264 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 557056 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 557056 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 5854500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 6228499 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 3907.659379 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 3906.975758 # Cycle average of tags in use
system.cpu.l2cache.total_refs 753 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 4717 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.159635 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 370.655862 # Average occupied blocks per requestor
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-system.cpu.dcache.demand_mshr_miss_latency::total 211294500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 211294500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 211294500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61415001 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 61415001 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 217011500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 217011500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 278426501 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 278426501 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 278426501 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 278426501 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50737.368421 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50737.368421 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50935.040600 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50935.040600 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50889.812139 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 50889.812139 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50889.812139 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 50889.812139 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 64647.369474 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 64647.369474 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67773.735166 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67773.735166 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67058.405829 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 67058.405829 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67058.405829 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 67058.405829 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.077334 # Number of seconds simulated
-sim_ticks 77333664500 # Number of ticks simulated
-final_tick 77333664500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.077363 # Number of seconds simulated
+sim_ticks 77363103500 # Number of ticks simulated
+final_tick 77363103500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 71983 # Simulator instruction rate (inst/s)
-host_op_rate 71983 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 14821773 # Simulator tick rate (ticks/s)
-host_mem_usage 278592 # Number of bytes of host memory used
-host_seconds 5217.57 # Real time elapsed on the host
+host_inst_rate 219490 # Simulator instruction rate (inst/s)
+host_op_rate 219490 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 45211856 # Simulator tick rate (ticks/s)
+host_mem_usage 233160 # Number of bytes of host memory used
+host_seconds 1711.12 # Real time elapsed on the host
sim_insts 375574808 # Number of instructions simulated
sim_ops 375574808 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 221120 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 255552 # Number of bytes read from this memory
-system.physmem.bytes_read::total 476672 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 221120 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 221120 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3455 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 3993 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 7448 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2859298 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3304538 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 6163836 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2859298 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2859298 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2859298 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3304538 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6163836 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 7448 # Total number of read requests seen
+system.physmem.bytes_read::cpu.inst 220864 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 255360 # Number of bytes read from this memory
+system.physmem.bytes_read::total 476224 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 220864 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 220864 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 3451 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 3990 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 7441 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 2854901 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3300798 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 6155699 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 2854901 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 2854901 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 2854901 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3300798 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6155699 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 7441 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 7448 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 476672 # Total number of bytes read from memory
+system.physmem.cpureqs 7441 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 476224 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 476672 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 476224 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 449 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 440 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 474 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 462 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 590 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 533 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 518 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 418 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 475 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 455 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 401 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 425 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 391 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 465 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 433 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 519 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 524 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 654 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 449 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 599 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 447 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 455 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 516 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 524 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 435 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 405 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 339 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 305 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 414 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 543 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 453 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 379 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 77333596000 # Total gap between requests
+system.physmem.totGap 77363015000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 7448 # Categorize read packet sizes
+system.physmem.readPktSize::6 7441 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 4136 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 2084 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 806 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 306 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 111 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 4419 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 2033 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 692 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 234 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 53843750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 206982500 # Sum of mem lat for all requests
-system.physmem.totBusLat 37240000 # Total cycles spent in databus access
-system.physmem.totBankLat 115898750 # Total cycles spent in bank access
-system.physmem.avgQLat 7229.29 # Average queueing delay per request
-system.physmem.avgBankLat 15561.06 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 761 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 617.293035 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 239.548208 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 1200.351847 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 242 31.80% 31.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 107 14.06% 45.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 65 8.54% 54.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 58 7.62% 62.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 31 4.07% 66.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 22 2.89% 68.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 22 2.89% 71.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 17 2.23% 74.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 13 1.71% 75.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 18 2.37% 78.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 4 0.53% 78.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 12 1.58% 80.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 9 1.18% 81.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 10 1.31% 82.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 5 0.66% 83.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 5 0.66% 84.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 18 2.37% 86.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 4 0.53% 86.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 4 0.53% 87.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 2 0.26% 87.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 3 0.39% 88.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 7 0.92% 89.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1473 4 0.53% 89.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 4 0.53% 90.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 3 0.39% 90.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1665 5 0.66% 91.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1729 7 0.92% 92.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1793 1 0.13% 92.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1921 4 0.53% 92.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1985 3 0.39% 93.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2049 1 0.13% 93.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2113 4 0.53% 93.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2177 3 0.39% 94.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2241 2 0.26% 94.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2369 3 0.39% 94.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2433 1 0.13% 95.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2497 1 0.13% 95.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2561 1 0.13% 95.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2753 2 0.26% 95.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2817 3 0.39% 95.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3137 1 0.13% 96.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3201 2 0.26% 96.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3265 2 0.26% 96.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3329 1 0.13% 96.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3457 1 0.13% 96.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3585 1 0.13% 96.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4033 2 0.26% 97.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4160-4161 1 0.13% 97.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4224-4225 1 0.13% 97.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4416-4417 1 0.13% 97.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4480-4481 1 0.13% 97.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4608-4609 1 0.13% 97.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5312-5313 1 0.13% 98.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5632-5633 1 0.13% 98.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5888-5889 1 0.13% 98.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6144-6145 1 0.13% 98.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6400-6401 1 0.13% 98.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6464-6465 1 0.13% 98.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6592-6593 1 0.13% 98.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7232-7233 1 0.13% 98.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7296-7297 1 0.13% 99.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 7 0.92% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 761 # Bytes accessed per row activation
+system.physmem.totQLat 39473750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 177700000 # Sum of mem lat for all requests
+system.physmem.totBusLat 37205000 # Total cycles spent in databus access
+system.physmem.totBankLat 101021250 # Total cycles spent in bank access
+system.physmem.avgQLat 5304.90 # Average queueing delay per request
+system.physmem.avgBankLat 13576.30 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 27790.35 # Average memory access latency
+system.physmem.avgMemAccLat 23881.20 # Average memory access latency
system.physmem.avgRdBW 6.16 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 6.16 # Average consumed read bandwidth in MB/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 6188 # Number of row buffer hits during reads
+system.physmem.readRowHits 6680 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.08 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 89.77 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 10383135.88 # Average gap between requests
-system.cpu.branchPred.lookups 50250164 # Number of BP lookups
-system.cpu.branchPred.condPredicted 29237478 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1200857 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 25926393 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 23227731 # Number of BTB hits
+system.physmem.avgGap 10396857.28 # Average gap between requests
+system.membus.throughput 6155699 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 4309 # Transaction distribution
+system.membus.trans_dist::ReadResp 4309 # Transaction distribution
+system.membus.trans_dist::ReadExReq 3132 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3132 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 14882 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 14882 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 476224 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 476224 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 476224 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 9093000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 69496500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.cpu.branchPred.lookups 50225543 # Number of BP lookups
+system.cpu.branchPred.condPredicted 29217666 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1195897 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 25687498 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 23216118 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 89.591063 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 9011908 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1071 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 90.379055 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 9009525 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1024 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 101791407 # DTB read hits
-system.cpu.dtb.read_misses 78057 # DTB read misses
+system.cpu.dtb.read_hits 101778798 # DTB read hits
+system.cpu.dtb.read_misses 78056 # DTB read misses
system.cpu.dtb.read_acv 48605 # DTB read access violations
-system.cpu.dtb.read_accesses 101869464 # DTB read accesses
-system.cpu.dtb.write_hits 78427886 # DTB write hits
-system.cpu.dtb.write_misses 1487 # DTB write misses
-system.cpu.dtb.write_acv 4 # DTB write access violations
-system.cpu.dtb.write_accesses 78429373 # DTB write accesses
-system.cpu.dtb.data_hits 180219293 # DTB hits
-system.cpu.dtb.data_misses 79544 # DTB misses
-system.cpu.dtb.data_acv 48609 # DTB access violations
-system.cpu.dtb.data_accesses 180298837 # DTB accesses
-system.cpu.itb.fetch_hits 50219856 # ITB hits
-system.cpu.itb.fetch_misses 371 # ITB misses
+system.cpu.dtb.read_accesses 101856854 # DTB read accesses
+system.cpu.dtb.write_hits 78401927 # DTB write hits
+system.cpu.dtb.write_misses 1498 # DTB write misses
+system.cpu.dtb.write_acv 2 # DTB write access violations
+system.cpu.dtb.write_accesses 78403425 # DTB write accesses
+system.cpu.dtb.data_hits 180180725 # DTB hits
+system.cpu.dtb.data_misses 79554 # DTB misses
+system.cpu.dtb.data_acv 48607 # DTB access violations
+system.cpu.dtb.data_accesses 180260279 # DTB accesses
+system.cpu.itb.fetch_hits 50199009 # ITB hits
+system.cpu.itb.fetch_misses 367 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 50220227 # ITB accesses
+system.cpu.itb.fetch_accesses 50199376 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
-system.cpu.numCycles 154667331 # number of cpu cycles simulated
+system.cpu.numCycles 154726209 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 51106135 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 448668997 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 50250164 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 32239639 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 78764976 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6110488 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 19721558 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 9420 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 31 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 50219856 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 408750 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 154473494 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.904505 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.325354 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 51083952 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 448497930 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 50225543 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 32225643 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 78739470 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6093368 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 19754761 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 10148 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 20 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 50199009 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 408107 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 154447023 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.903895 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.325218 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 75708518 49.01% 49.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 4277779 2.77% 51.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 6877340 4.45% 56.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 5358744 3.47% 59.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 11737510 7.60% 67.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 7816086 5.06% 72.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 5610591 3.63% 75.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1829118 1.18% 77.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 35257808 22.82% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 75707553 49.02% 49.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 4276532 2.77% 51.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 6874422 4.45% 56.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 5367897 3.48% 59.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 11734775 7.60% 67.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 7804305 5.05% 72.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 5608156 3.63% 76.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1827762 1.18% 77.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 35245621 22.82% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 154473494 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.324892 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.900865 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 56459568 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 15066335 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 74129389 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3951215 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 4866987 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 9471000 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 4301 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 444763316 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 12199 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 4866987 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 59590781 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 4877606 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 403368 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 75043533 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 9691219 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 440325289 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 81 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 19776 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 8008631 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 287258502 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 578891140 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 306269617 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 272621523 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 154447023 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.324609 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.898655 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 56435005 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 15098519 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 74108370 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3950827 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 4854302 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 9469599 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 4266 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 444616188 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 12118 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 4854302 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 59563357 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 4893725 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 414604 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 75021983 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 9699052 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 440177556 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 167 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 18387 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 8017745 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 287187239 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 578692114 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 306192880 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 272499234 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 27726173 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 36829 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 293 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 27858969 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 104659356 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 80576509 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 8905764 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 6378561 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 408090089 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 285 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 401700569 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 966819 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 32383171 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 15203599 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 70 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 154473494 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.600450 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.995226 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 27654910 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 36841 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 298 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 27864767 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 104645789 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 80545124 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 8910343 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 6399312 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 408008914 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 286 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 401637302 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 964402 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 32300806 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 15167317 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 71 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 154447023 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.600486 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.995525 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 28241556 18.28% 18.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 25850500 16.73% 35.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 25557992 16.55% 51.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 24263581 15.71% 67.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 21289314 13.78% 81.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 15479662 10.02% 91.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8473784 5.49% 96.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3991768 2.58% 99.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1325337 0.86% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 28234595 18.28% 18.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 25848670 16.74% 35.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 25579083 16.56% 51.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 24239826 15.69% 67.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 21261159 13.77% 81.04% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 15485386 10.03% 91.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8478015 5.49% 96.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3990980 2.58% 99.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1329309 0.86% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 154473494 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 154447023 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 34111 0.29% 0.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 34190 0.29% 0.29% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 0.29% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.29% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 56920 0.48% 0.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 5994 0.05% 0.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 5359 0.05% 0.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 1948290 16.45% 17.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 1748478 14.77% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 5072340 42.83% 74.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2970257 25.08% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 57000 0.48% 0.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 5570 0.05% 0.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 5383 0.05% 0.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 1934681 16.39% 17.25% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 1747492 14.80% 32.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 32.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 32.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 5061407 42.87% 74.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 2960127 25.07% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 155713730 38.76% 38.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 2126194 0.53% 39.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 155697269 38.77% 38.77% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 2126268 0.53% 39.30% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 39.30% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 32798014 8.16% 47.47% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 7493329 1.87% 49.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 2792591 0.70% 50.03% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 16555292 4.12% 54.15% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 1575667 0.39% 54.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 32795718 8.17% 47.47% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 7492895 1.87% 49.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 2793275 0.70% 50.03% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 16555197 4.12% 54.15% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 1576539 0.39% 54.54% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.54% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 103367730 25.73% 80.27% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 79244441 19.73% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 103353833 25.73% 80.28% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 79212727 19.72% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 401700569 # Type of FU issued
-system.cpu.iq.rate 2.597191 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 11841749 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.029479 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 633918873 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 260111128 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 234694703 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 336764327 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 180411325 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 161341889 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 241419357 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 172089380 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 15066518 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 401637302 # Type of FU issued
+system.cpu.iq.rate 2.595794 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 11805850 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.029394 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 633814426 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 260039391 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 234669938 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 336677453 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 180319624 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 161314335 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 241373993 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 172035578 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 15061229 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 9904869 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 112431 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 48929 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 7055780 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 9891302 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 112335 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 49025 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 7024395 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 260879 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 2892 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 260907 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 3733 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 4866987 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 2513893 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 367538 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 432875839 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 130047 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 104659356 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 80576509 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 285 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 90 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 95 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 48929 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 945508 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 405299 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1350807 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 398189954 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 101918111 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 3510615 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 4854302 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 2516728 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 369298 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 432783708 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 121887 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 104645789 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 80545124 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 286 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 93 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 98 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 49025 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 940065 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 405593 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1345658 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 398139116 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 101905490 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 3498186 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 24785465 # number of nop insts executed
-system.cpu.iew.exec_refs 180347521 # number of memory reference insts executed
-system.cpu.iew.exec_branches 46544583 # Number of branches executed
-system.cpu.iew.exec_stores 78429410 # Number of stores executed
-system.cpu.iew.exec_rate 2.574493 # Inst execution rate
-system.cpu.iew.wb_sent 396666493 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 396036592 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 193534239 # num instructions producing a value
-system.cpu.iew.wb_consumers 271064266 # num instructions consuming a value
+system.cpu.iew.exec_nop 24774508 # number of nop insts executed
+system.cpu.iew.exec_refs 180308945 # number of memory reference insts executed
+system.cpu.iew.exec_branches 46542252 # Number of branches executed
+system.cpu.iew.exec_stores 78403455 # Number of stores executed
+system.cpu.iew.exec_rate 2.573185 # Inst execution rate
+system.cpu.iew.wb_sent 396614980 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 395984273 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 193530512 # num instructions producing a value
+system.cpu.iew.wb_consumers 271082574 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.560570 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.713979 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.559258 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.713917 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 34241399 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 34145749 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1196652 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 149606507 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.664754 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.996488 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1191710 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 149592721 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.665000 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.996623 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 55299800 36.96% 36.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 22506363 15.04% 52.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 13038979 8.72% 60.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 11456394 7.66% 68.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 8182423 5.47% 73.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 5460459 3.65% 77.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 5170598 3.46% 80.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3276423 2.19% 83.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 25215068 16.85% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 55286060 36.96% 36.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 22516991 15.05% 52.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 13020116 8.70% 60.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 11469174 7.67% 68.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 8183204 5.47% 73.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 5453733 3.65% 77.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 5164454 3.45% 80.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3280279 2.19% 83.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 25218710 16.86% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 149606507 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 149592721 # Number of insts commited each cycle
system.cpu.commit.committedInsts 398664583 # Number of instructions committed
system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions.
system.cpu.commit.int_insts 316365839 # Number of committed integer instructions.
system.cpu.commit.function_calls 8007752 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 25215068 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 25218710 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 557294444 # The number of ROB reads
-system.cpu.rob.rob_writes 870687583 # The number of ROB writes
-system.cpu.timesIdled 3434 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 193837 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 557181366 # The number of ROB reads
+system.cpu.rob.rob_writes 870483842 # The number of ROB writes
+system.cpu.timesIdled 3633 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 279186 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 375574808 # Number of Instructions Simulated
system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 375574808 # Number of Instructions Simulated
-system.cpu.cpi 0.411815 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.411815 # CPI: Total CPI of All Threads
-system.cpu.ipc 2.428275 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 2.428275 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 398027050 # number of integer regfile reads
-system.cpu.int_regfile_writes 170092717 # number of integer regfile writes
-system.cpu.fp_regfile_reads 156507210 # number of floating regfile reads
-system.cpu.fp_regfile_writes 104024348 # number of floating regfile writes
+system.cpu.cpi 0.411972 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.411972 # CPI: Total CPI of All Threads
+system.cpu.ipc 2.427351 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 2.427351 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 397971851 # number of integer regfile reads
+system.cpu.int_regfile_writes 170072905 # number of integer regfile writes
+system.cpu.fp_regfile_reads 156478965 # number of floating regfile reads
+system.cpu.fp_regfile_writes 104018276 # number of floating regfile writes
system.cpu.misc_regfile_reads 350572 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.icache.replacements 2144 # number of replacements
-system.cpu.icache.tagsinuse 1832.992784 # Cycle average of tags in use
-system.cpu.icache.total_refs 50214379 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 4071 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 12334.654630 # Average number of references to valid blocks.
+system.cpu.toL2Bus.throughput 7367647 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 5060 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 5060 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 655 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 3191 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 3191 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 8148 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 9009 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 17157 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 260736 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 309248 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 569984 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 569984 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 5108000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 6111000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 6265500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu.icache.replacements 2147 # number of replacements
+system.cpu.icache.tagsinuse 1831.625379 # Cycle average of tags in use
+system.cpu.icache.total_refs 50193388 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 4074 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 12320.419244 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1832.992784 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.895016 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.895016 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 50214379 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 50214379 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 50214379 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 50214379 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 50214379 # number of overall hits
-system.cpu.icache.overall_hits::total 50214379 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 5477 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 5477 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 5477 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 5477 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 5477 # number of overall misses
-system.cpu.icache.overall_misses::total 5477 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 242149500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 242149500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 242149500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 242149500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 242149500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 242149500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 50219856 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 50219856 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 50219856 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 50219856 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 50219856 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 50219856 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000109 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000109 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000109 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000109 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000109 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000109 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44212.068651 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 44212.068651 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 44212.068651 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 44212.068651 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 44212.068651 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 44212.068651 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 692 # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst 1831.625379 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.894348 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.894348 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 50193388 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 50193388 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 50193388 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 50193388 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 50193388 # number of overall hits
+system.cpu.icache.overall_hits::total 50193388 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 5621 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 5621 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 5621 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 5621 # number of demand (read+write) misses
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+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3191 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 3191 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 4177 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 4177 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 4177 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 4177 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 66792500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 66792500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 216966500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 216966500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 283759000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 283759000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 283759000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 283759000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000011 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000026 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000026 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000026 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54409.090909 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54409.090909 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52398.652882 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52398.652882 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52874.581540 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 52874.581540 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52874.581540 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 52874.581540 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67740.872211 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67740.872211 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67993.262300 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67993.262300 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67933.684463 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 67933.684463 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67933.684463 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 67933.684463 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 199332411500 # Number of ticks simulated
final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2294613 # Simulator instruction rate (inst/s)
-host_op_rate 2294613 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1147307033 # Simulator tick rate (ticks/s)
-host_mem_usage 269948 # Number of bytes of host memory used
-host_seconds 173.74 # Real time elapsed on the host
+host_inst_rate 1715563 # Simulator instruction rate (inst/s)
+host_op_rate 1715563 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 857781835 # Simulator tick rate (ticks/s)
+host_mem_usage 222488 # Number of bytes of host memory used
+host_seconds 232.38 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1594658604 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7999996548 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5793368275 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13793364824 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 13793364824 # Throughput (bytes/s)
+system.membus.data_through_bus 2749464673 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
sim_ticks 567335093000 # Number of ticks simulated
final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 853902 # Simulator instruction rate (inst/s)
-host_op_rate 853902 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1215178011 # Simulator tick rate (ticks/s)
-host_mem_usage 278532 # Number of bytes of host memory used
-host_seconds 466.87 # Real time elapsed on the host
+host_inst_rate 1715092 # Simulator instruction rate (inst/s)
+host_op_rate 1715091 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2440727076 # Simulator tick rate (ticks/s)
+host_mem_usage 230984 # Number of bytes of host memory used
+host_seconds 232.45 # Real time elapsed on the host
sim_insts 398664609 # Number of instructions simulated
sim_ops 398664609 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 361550 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 447735 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 809285 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 809285 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 4032 # Transaction distribution
+system.membus.trans_dist::ReadResp 4032 # Transaction distribution
+system.membus.trans_dist::ReadExReq 3142 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3142 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 14348 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 14348 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 459136 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 459136 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 459136 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 7174000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 64566000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 955936 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 4623 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 7346 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 8953 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 16299 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 235072 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 307264 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 542336 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 542336 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 4886000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 5509500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.068258 # Number of seconds simulated
-sim_ticks 68258363000 # Number of ticks simulated
-final_tick 68258363000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.068340 # Number of seconds simulated
+sim_ticks 68340072000 # Number of ticks simulated
+final_tick 68340072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 73419 # Simulator instruction rate (inst/s)
-host_op_rate 93863 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 18354583 # Simulator tick rate (ticks/s)
-host_mem_usage 296524 # Number of bytes of host memory used
-host_seconds 3718.87 # Real time elapsed on the host
+host_inst_rate 97727 # Simulator instruction rate (inst/s)
+host_op_rate 124939 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 24460648 # Simulator tick rate (ticks/s)
+host_mem_usage 254748 # Number of bytes of host memory used
+host_seconds 2793.88 # Real time elapsed on the host
sim_insts 273036725 # Number of instructions simulated
sim_ops 349064449 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 193792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 272192 # Number of bytes read from this memory
-system.physmem.bytes_read::total 465984 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 193792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 193792 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3028 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 4253 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 7281 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2839095 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3987673 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 6826768 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2839095 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2839095 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2839095 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3987673 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6826768 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 7281 # Total number of read requests seen
+system.physmem.bytes_read::cpu.inst 193856 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 272320 # Number of bytes read from this memory
+system.physmem.bytes_read::total 466176 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 193856 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 193856 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 3029 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 4255 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 7284 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 2836637 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3984778 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 6821415 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 2836637 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 2836637 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 2836637 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3984778 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6821415 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 7284 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 7284 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 465984 # Total number of bytes read from memory
+system.physmem.cpureqs 7289 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 466176 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 465984 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 466176 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 3 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 412 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 408 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 483 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 476 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 509 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 487 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 544 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 590 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 400 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 432 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 455 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 417 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 381 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 421 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 450 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 416 # Track reads on a per bank basis
+system.physmem.neitherReadNorWrite 5 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 605 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 803 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 607 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 525 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 442 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 354 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 161 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 219 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 210 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 288 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 325 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 414 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 530 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 686 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 611 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 504 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 68258164000 # Total gap between requests
+system.physmem.totGap 68339875000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 7281 # Categorize read packet sizes
+system.physmem.readPktSize::6 7284 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 4267 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 2163 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 597 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 187 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 67 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 4420 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 2077 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 561 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 165 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 45271500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 191126500 # Sum of mem lat for all requests
-system.physmem.totBusLat 36405000 # Total cycles spent in databus access
-system.physmem.totBankLat 109450000 # Total cycles spent in bank access
-system.physmem.avgQLat 6217.76 # Average queueing delay per request
-system.physmem.avgBankLat 15032.28 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 717 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 639.642957 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 236.501213 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 1328.325684 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 231 32.22% 32.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 96 13.39% 45.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 63 8.79% 54.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 56 7.81% 62.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 30 4.18% 66.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 30 4.18% 70.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 16 2.23% 72.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 21 2.93% 75.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 13 1.81% 77.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 17 2.37% 79.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 8 1.12% 81.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 12 1.67% 82.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 3 0.42% 83.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 9 1.26% 84.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 5 0.70% 85.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 7 0.98% 86.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 5 0.70% 86.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 5 0.70% 87.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 4 0.56% 88.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 4 0.56% 88.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 2 0.28% 88.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 4 0.56% 89.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1473 3 0.42% 89.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 4 0.56% 90.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1665 4 0.56% 90.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1729 2 0.28% 91.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1793 2 0.28% 91.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1857 2 0.28% 91.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1921 2 0.28% 92.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1985 2 0.28% 92.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2049 2 0.28% 92.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2113 3 0.42% 93.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2177 3 0.42% 93.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2241 1 0.14% 93.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2305 2 0.28% 93.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2369 2 0.28% 94.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2433 1 0.14% 94.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2561 2 0.28% 94.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2625 1 0.14% 94.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2689 2 0.28% 94.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2817 2 0.28% 95.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2881 1 0.14% 95.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3073 3 0.42% 95.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3137 1 0.14% 95.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3201 1 0.14% 96.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3265 1 0.14% 96.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3329 1 0.14% 96.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520-3521 1 0.14% 96.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3585 1 0.14% 96.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3713 1 0.14% 96.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776-3777 1 0.14% 96.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4608-4609 1 0.14% 97.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4800-4801 1 0.14% 97.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4864-4865 2 0.28% 97.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5632-5633 1 0.14% 97.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5952-5953 1 0.14% 97.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6080-6081 1 0.14% 97.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6656-6657 1 0.14% 98.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6912-6913 2 0.28% 98.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8128-8129 2 0.28% 98.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 10 1.39% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 717 # Bytes accessed per row activation
+system.physmem.totQLat 39275000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 171092500 # Sum of mem lat for all requests
+system.physmem.totBusLat 36420000 # Total cycles spent in databus access
+system.physmem.totBankLat 95397500 # Total cycles spent in bank access
+system.physmem.avgQLat 5391.95 # Average queueing delay per request
+system.physmem.avgBankLat 13096.86 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26250.03 # Average memory access latency
-system.physmem.avgRdBW 6.83 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 23488.81 # Average memory access latency
+system.physmem.avgRdBW 6.82 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 6.83 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 6.82 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 6071 # Number of row buffer hits during reads
+system.physmem.readRowHits 6567 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 90.16 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 9374833.68 # Average gap between requests
-system.cpu.branchPred.lookups 35375534 # Number of BP lookups
-system.cpu.branchPred.condPredicted 21203624 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1636565 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 18693932 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 16765511 # Number of BTB hits
+system.physmem.avgGap 9382190.42 # Average gap between requests
+system.membus.throughput 6821415 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 4461 # Transaction distribution
+system.membus.trans_dist::ReadResp 4461 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 5 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 5 # Transaction distribution
+system.membus.trans_dist::ReadExReq 2823 # Transaction distribution
+system.membus.trans_dist::ReadExResp 2823 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 14578 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 14578 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 466176 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 466176 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 466176 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 8863500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 67994996 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.cpu.branchPred.lookups 35386289 # Number of BP lookups
+system.cpu.branchPred.condPredicted 21204879 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1638532 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 19153921 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 16759106 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 89.684241 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 6786649 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 8328 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 87.496999 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 6781793 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 8488 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
-system.cpu.numCycles 136516727 # number of cpu cycles simulated
+system.cpu.numCycles 136680145 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 38896982 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 317376259 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 35375534 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 23552160 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 70779245 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6771648 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 21491054 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1891 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 27 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 37519444 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 509386 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 136293047 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.985311 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.454516 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 38911514 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 317585001 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 35386289 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 23540899 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 70801219 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6795871 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 21500027 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 100 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1484 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 37522622 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 503492 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 136360129 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.984944 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.454705 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 66138904 48.53% 48.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 6767660 4.97% 53.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 5699163 4.18% 57.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 6081886 4.46% 62.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 4905828 3.60% 65.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 4088301 3.00% 68.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 3176914 2.33% 71.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 4135950 3.03% 74.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 35298441 25.90% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 66188924 48.54% 48.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 6771554 4.97% 53.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 5692762 4.17% 57.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 6083969 4.46% 62.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 4907326 3.60% 65.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 4077145 2.99% 68.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 3184432 2.34% 71.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 4135342 3.03% 74.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 35318675 25.90% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 136293047 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.259130 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.324816 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 45396979 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 16650013 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 66644263 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 2546649 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 5055143 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 7329146 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 69002 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 400901285 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 213083 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 5055143 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 50932623 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 1928706 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 309700 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 63595700 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 14471175 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 393334802 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 54 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1658050 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 10199893 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 1072 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 431829381 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 2328856465 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1256465206 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1072391259 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 136360129 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.258899 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.323564 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 45414780 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 16659439 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 66663560 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 2545187 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 5077163 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 7331349 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 68935 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 401047467 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 212517 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 5077163 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 50947779 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 1931381 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 327570 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 63615860 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 14460376 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 393522571 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 45 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1660698 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 10177766 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 1066 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 432139045 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 2330040462 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1257112117 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1072928345 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 384566193 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 47263188 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 11836 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 11835 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 36477776 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 103434690 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 91236939 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 4267637 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 5260584 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 383959282 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 22788 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 373920129 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1206190 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 34165918 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 85628063 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 668 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 136293047 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.743501 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.023111 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 47572852 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 11802 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 11801 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 36468583 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 103474945 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 91276854 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 4259608 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 5261316 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 384098955 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 22768 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 373971213 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1208914 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 34303040 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 86231470 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 648 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 136360129 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.742526 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.023578 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 24835944 18.22% 18.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 19923821 14.62% 32.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 20538519 15.07% 47.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 18169219 13.33% 61.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 24028277 17.63% 78.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 15701712 11.52% 90.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8800214 6.46% 96.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 3374067 2.48% 99.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 921274 0.68% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 24894566 18.26% 18.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 19912259 14.60% 32.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 20562905 15.08% 47.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 18156426 13.32% 61.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 24028186 17.62% 78.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 15708589 11.52% 90.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8792760 6.45% 96.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 3383887 2.48% 99.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 920551 0.68% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 136293047 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 136360129 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 8902 0.05% 0.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 4689 0.03% 0.08% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 8941 0.05% 0.05% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 4699 0.03% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 46241 0.26% 0.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 46063 0.26% 0.34% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 7650 0.04% 0.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 432 0.00% 0.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 7630 0.04% 0.38% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 434 0.00% 0.38% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 2 0.00% 0.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 190629 1.08% 1.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 3972 0.02% 1.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 241372 1.36% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 190949 1.08% 1.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 4204 0.02% 1.48% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 241086 1.36% 2.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 9278872 52.34% 55.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 7944742 44.82% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 9286535 52.36% 55.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 7946359 44.80% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 126315653 33.78% 33.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 2175866 0.58% 34.36% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 3 0.00% 34.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 6776888 1.81% 36.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 126344065 33.78% 33.78% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 2175771 0.58% 34.37% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.37% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 2 0.00% 34.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 6778681 1.81% 36.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 8468895 2.26% 38.44% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 3427953 0.92% 39.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 1595639 0.43% 39.78% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 20851093 5.58% 45.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 7171347 1.92% 47.28% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 7126740 1.91% 49.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 49.23% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 101555976 27.16% 76.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 88278790 23.61% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 8473226 2.27% 38.44% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 3428816 0.92% 39.36% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 1595959 0.43% 39.79% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 20861053 5.58% 45.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 7172627 1.92% 47.28% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 7127553 1.91% 49.19% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.24% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 101561380 27.16% 76.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 88276793 23.61% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 373920129 # Type of FU issued
-system.cpu.iq.rate 2.739006 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 17727503 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.047410 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 653684952 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 287885544 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 249920404 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 249382046 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 130276634 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 118031995 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 263048449 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 128599183 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 11100195 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 373971213 # Type of FU issued
+system.cpu.iq.rate 2.736105 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 17736902 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.047429 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 653872242 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 288125780 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 249960786 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 249376129 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 130313231 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 118044740 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 263109864 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 128598251 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 11095244 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 8785942 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 109607 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14276 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 8861356 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 8826197 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 108953 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 14410 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 8901271 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 182774 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1441 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 178209 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1806 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 5055143 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 284926 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 36749 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 383983637 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 873190 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 103434690 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 91236939 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 11754 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 337 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 365 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 14276 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 1271835 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 367005 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1638840 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 369984044 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 100253903 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 3936085 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 5077163 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 281172 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 37033 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 384123288 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 853132 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 103474945 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 91276854 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 11734 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 343 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 352 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 14410 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 1275078 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 370888 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1645966 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 370028321 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 100269572 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 3942892 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1567 # number of nop insts executed
-system.cpu.iew.exec_refs 187478745 # number of memory reference insts executed
-system.cpu.iew.exec_branches 32002404 # Number of branches executed
-system.cpu.iew.exec_stores 87224842 # Number of stores executed
-system.cpu.iew.exec_rate 2.710174 # Inst execution rate
-system.cpu.iew.wb_sent 368608393 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 367952399 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 182920147 # num instructions producing a value
-system.cpu.iew.wb_consumers 363541669 # num instructions consuming a value
+system.cpu.iew.exec_nop 1565 # number of nop insts executed
+system.cpu.iew.exec_refs 187470029 # number of memory reference insts executed
+system.cpu.iew.exec_branches 32001457 # Number of branches executed
+system.cpu.iew.exec_stores 87200457 # Number of stores executed
+system.cpu.iew.exec_rate 2.707257 # Inst execution rate
+system.cpu.iew.wb_sent 368660932 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 368005526 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 182984682 # num instructions producing a value
+system.cpu.iew.wb_consumers 363667286 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.695292 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.503161 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.692458 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.503165 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 34918645 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 35058333 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1567905 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 131237904 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.659788 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.659697 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1569963 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 131282966 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.658875 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.659705 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 34480622 26.27% 26.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 28416799 21.65% 47.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 13301568 10.14% 58.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 11461353 8.73% 66.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 13768973 10.49% 77.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 7415781 5.65% 82.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 3872079 2.95% 85.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3892036 2.97% 88.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 14628693 11.15% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 34515611 26.29% 26.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 28430867 21.66% 47.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 13310132 10.14% 58.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 11454615 8.73% 66.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 13758236 10.48% 77.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 7411224 5.65% 82.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 3878786 2.95% 85.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3899655 2.97% 88.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 14623840 11.14% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 131237904 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 131282966 # Number of insts commited each cycle
system.cpu.commit.committedInsts 273037337 # Number of instructions committed
system.cpu.commit.committedOps 349065061 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
system.cpu.commit.int_insts 279584611 # Number of committed integer instructions.
system.cpu.commit.function_calls 6225112 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 14628693 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 14623840 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 500590394 # The number of ROB reads
-system.cpu.rob.rob_writes 773026490 # The number of ROB writes
-system.cpu.timesIdled 6380 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 223680 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 500779997 # The number of ROB reads
+system.cpu.rob.rob_writes 773327958 # The number of ROB writes
+system.cpu.timesIdled 6728 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 320016 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 273036725 # Number of Instructions Simulated
system.cpu.committedOps 349064449 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 273036725 # Number of Instructions Simulated
-system.cpu.cpi 0.499994 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.499994 # CPI: Total CPI of All Threads
-system.cpu.ipc 2.000024 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 2.000024 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1768667875 # number of integer regfile reads
-system.cpu.int_regfile_writes 232756138 # number of integer regfile writes
-system.cpu.fp_regfile_reads 188077365 # number of floating regfile reads
-system.cpu.fp_regfile_writes 132460015 # number of floating regfile writes
-system.cpu.misc_regfile_reads 566729148 # number of misc regfile reads
+system.cpu.cpi 0.500593 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.500593 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.997633 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.997633 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1768864956 # number of integer regfile reads
+system.cpu.int_regfile_writes 232856502 # number of integer regfile writes
+system.cpu.fp_regfile_reads 188105910 # number of floating regfile reads
+system.cpu.fp_regfile_writes 132495512 # number of floating regfile writes
+system.cpu.misc_regfile_reads 566780330 # number of misc regfile reads
system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes
-system.cpu.icache.replacements 13935 # number of replacements
-system.cpu.icache.tagsinuse 1853.031974 # Cycle average of tags in use
-system.cpu.icache.total_refs 37502330 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 15827 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 2369.516017 # Average number of references to valid blocks.
+system.cpu.toL2Bus.throughput 20129917 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 17615 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 17615 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 1040 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 2840 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 2840 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 31680 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 10272 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 41952 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1013504 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 361664 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 1375168 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 1375168 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 512 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 11790000 # Layer occupancy (ticks)
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-system.cpu.dcache.ReadReq_accesses::cpu.data 88790606 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 88790606 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 25434 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 25434 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 25434 # number of overall misses
+system.cpu.dcache.overall_misses::total 25434 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 218203000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 218203000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 1190820596 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 1190820596 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 155000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 1409023596 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 1409023596 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 1409023596 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 1409023596 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 88816484 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 88816484 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052665 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052665 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11007 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 11007 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11014 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 11014 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 170843271 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 170843271 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 170843271 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 170843271 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000258 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000258 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 170869149 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 170869149 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 170869149 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 170869149 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000261 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000261 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000182 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000182 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000148 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000148 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000148 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000148 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43735.830458 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 43735.830458 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41459.389647 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 41459.389647 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 58000 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58000 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 41825.518489 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 41825.518489 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 41825.518489 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 41825.518489 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 15191 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 833 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 436 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000149 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000149 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000149 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000149 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54619.023780 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 54619.023780 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55544.596110 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55544.596110 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77500 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77500 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55399.213494 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55399.213494 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55399.213494 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55399.213494 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 24937 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 1182 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 461 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.841743 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 64.076923 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 54.093275 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 90.923077 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1043 # number of writebacks
-system.cpu.dcache.writebacks::total 1043 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2254 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 2254 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18357 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 18357 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 1040 # number of writebacks
+system.cpu.dcache.writebacks::total 1040 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2223 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 2223 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18595 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 18595 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 20611 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 20611 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 20611 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 20611 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1804 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1804 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2816 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 2816 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 4620 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 4620 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 4620 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 4620 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86261000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 86261000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 138898000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 138898000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 225159000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 225159000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 225159000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 225159000 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data 20818 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 20818 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 20818 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 20818 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1772 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1772 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2844 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 2844 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 4616 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 4616 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 4616 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 4616 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 106478039 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 106478039 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 191753000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 191753000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298231039 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 298231039 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298231039 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 298231039 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000020 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000020 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000034 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000034 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47816.518847 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47816.518847 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49324.573864 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49324.573864 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48735.714286 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 48735.714286 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48735.714286 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 48735.714286 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60089.186795 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60089.186795 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67423.699015 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67423.699015 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64608.110702 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 64608.110702 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64608.110702 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 64608.110702 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 212344043000 # Number of ticks simulated
final_tick 212344043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1130367 # Simulator instruction rate (inst/s)
-host_op_rate 1445119 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 879097302 # Simulator tick rate (ticks/s)
-host_mem_usage 286212 # Number of bytes of host memory used
-host_seconds 241.55 # Real time elapsed on the host
+host_inst_rate 1381175 # Simulator instruction rate (inst/s)
+host_op_rate 1765765 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1074152891 # Simulator tick rate (ticks/s)
+host_mem_usage 241892 # Number of bytes of host memory used
+host_seconds 197.69 # Real time elapsed on the host
sim_insts 273037663 # Number of instructions simulated
sim_ops 349065399 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1394641404 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 6567838609 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4147783185 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10715621794 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 10715621794 # Throughput (bytes/s)
+system.membus.data_through_bus 2275398455 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
sim_ticks 525834342000 # Number of ticks simulated
final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 589682 # Simulator instruction rate (inst/s)
-host_op_rate 753887 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1136891744 # Simulator tick rate (ticks/s)
-host_mem_usage 294668 # Number of bytes of host memory used
-host_seconds 462.52 # Real time elapsed on the host
+host_inst_rate 442791 # Simulator instruction rate (inst/s)
+host_op_rate 566092 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 853689730 # Simulator tick rate (ticks/s)
+host_mem_usage 250392 # Number of bytes of host memory used
+host_seconds 615.96 # Real time elapsed on the host
sim_insts 272739283 # Number of instructions simulated
sim_ops 348687122 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 317545 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 513987 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 831532 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 831532 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 3976 # Transaction distribution
+system.membus.trans_dist::ReadResp 3976 # Transaction distribution
+system.membus.trans_dist::ReadExReq 2856 # Transaction distribution
+system.membus.trans_dist::ReadExResp 2856 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 13664 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 13664 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 437248 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 437248 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 437248 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 61488000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 2565553 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 31206 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 9954 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 41160 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 998592 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 350464 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 1349056 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 1349056 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.626015 # Number of seconds simulated
-sim_ticks 626014950000 # Number of ticks simulated
-final_tick 626014950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.631301 # Number of seconds simulated
+sim_ticks 631300530000 # Number of ticks simulated
+final_tick 631300530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 71515 # Simulator instruction rate (inst/s)
-host_op_rate 71515 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 24557485 # Simulator tick rate (ticks/s)
-host_mem_usage 282608 # Number of bytes of host memory used
-host_seconds 25491.82 # Real time elapsed on the host
+host_inst_rate 153163 # Simulator instruction rate (inst/s)
+host_op_rate 153163 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 53038574 # Simulator tick rate (ticks/s)
+host_mem_usage 237176 # Number of bytes of host memory used
+host_seconds 11902.67 # Real time elapsed on the host
sim_insts 1823043370 # Number of instructions simulated
sim_ops 1823043370 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 175936 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 30295808 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30471744 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 175936 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 175936 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 30295296 # Number of bytes read from this memory
+system.physmem.bytes_read::total 30472576 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 177280 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 177280 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory
system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2749 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 473372 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 476121 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 2770 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 473364 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 476134 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 281041 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 48394704 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 48675745 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 281041 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 281041 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 6840271 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6840271 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 6840271 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 281041 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 48394704 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 55516016 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 476121 # Total number of read requests seen
+system.physmem.bw_read::cpu.inst 280817 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 47988707 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 48269524 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 280817 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 280817 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 6783001 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6783001 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 6783001 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 280817 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 47988707 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 55052525 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 476134 # Total number of read requests seen
system.physmem.writeReqs 66908 # Total number of write requests seen
-system.physmem.cpureqs 543029 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 30471744 # Total number of bytes read from memory
+system.physmem.cpureqs 543042 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 30472576 # Total number of bytes read from memory
system.physmem.bytesWritten 4282112 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 30471744 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 30472576 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 4282112 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 90 # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ 95 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 29662 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 29736 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 29647 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 29658 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 29696 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 29714 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 29813 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 29814 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 29790 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 29811 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 29697 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 29776 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 29781 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 29762 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 29859 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 29815 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 4150 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 4168 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 4149 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 4131 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 4110 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 4146 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 4214 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 4228 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 4258 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 4213 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 4166 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 4191 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 4171 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 4198 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 4205 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 4210 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::0 29446 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 29796 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 29856 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 29790 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 29699 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 29772 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 29865 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 29863 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 29774 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 29887 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 29849 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 29919 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 29794 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 29585 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 29511 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 29633 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 4125 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 4164 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 4223 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 4160 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 4142 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 4099 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 4262 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 4226 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 4233 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 4335 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 4247 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 4241 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 4098 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 4100 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 4096 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 4157 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 626014887500 # Total gap between requests
+system.physmem.totGap 631300447500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 476121 # Categorize read packet sizes
+system.physmem.readPktSize::6 476134 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 66908 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 406557 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 66998 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 2282 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 164 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 26 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 408382 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 66876 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 628 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 130 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2898 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 2910 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 2909 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 2909 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 2909 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 2909 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 2909 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 2909 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3500552500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 21508187500 # Sum of mem lat for all requests
-system.physmem.totBusLat 2380155000 # Total cycles spent in databus access
-system.physmem.totBankLat 15627480000 # Total cycles spent in bank access
-system.physmem.avgQLat 7353.62 # Average queueing delay per request
-system.physmem.avgBankLat 32828.70 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 166615 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 208.530564 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 137.079554 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 536.352711 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 52781 31.68% 31.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 42583 25.56% 57.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 39981 24.00% 81.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 25354 15.22% 96.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 274 0.16% 96.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 129 0.08% 96.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 97 0.06% 96.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 83 0.05% 96.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 81 0.05% 96.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 95 0.06% 96.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 108 0.06% 96.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 114 0.07% 97.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 86 0.05% 97.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 90 0.05% 97.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 79 0.05% 97.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 79 0.05% 97.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 75 0.05% 97.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 70 0.04% 97.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 77 0.05% 97.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 76 0.05% 97.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 81 0.05% 97.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1473 3443 2.07% 99.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 36 0.02% 99.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 1 0.00% 99.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1665 1 0.00% 99.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1729 2 0.00% 99.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1857 2 0.00% 99.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1921 1 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1985 2 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2241 1 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2305 1 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2369 1 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2433 2 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2561 3 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2689 1 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3201 2 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3265 1 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3393 1 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3713 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4033 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4928-4929 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5120-5121 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5760-5761 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5824-5825 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6720-6721 3 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6784-6785 2 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6848-6849 3 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6976-6977 2 0.00% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7424-7425 2 0.00% 99.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7936-7937 2 0.00% 99.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8000-8001 4 0.00% 99.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8064-8065 1 0.00% 99.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8128-8129 1 0.00% 99.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 586 0.35% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 166615 # Bytes accessed per row activation
+system.physmem.totQLat 1512536000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 14445141000 # Sum of mem lat for all requests
+system.physmem.totBusLat 2380195000 # Total cycles spent in databus access
+system.physmem.totBankLat 10552410000 # Total cycles spent in bank access
+system.physmem.avgQLat 3177.34 # Average queueing delay per request
+system.physmem.avgBankLat 22167.11 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 45182.33 # Average memory access latency
-system.physmem.avgRdBW 48.68 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 6.84 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 48.68 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 6.84 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 30344.45 # Average memory access latency
+system.physmem.avgRdBW 48.27 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 6.78 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 48.27 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 6.78 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.43 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.03 # Average read queue length over time
-system.physmem.avgWrQLen 11.00 # Average write queue length over time
-system.physmem.readRowHits 143853 # Number of row buffer hits during reads
-system.physmem.writeRowHits 46182 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 30.22 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 69.02 # Row buffer hit rate for writes
-system.physmem.avgGap 1152820.36 # Average gap between requests
-system.cpu.branchPred.lookups 388875863 # Number of BP lookups
-system.cpu.branchPred.condPredicted 256999007 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 25264722 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 310547770 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 257563099 # Number of BTB hits
+system.physmem.avgRdQLen 0.02 # Average read queue length over time
+system.physmem.avgWrQLen 10.99 # Average write queue length over time
+system.physmem.readRowHits 326147 # Number of row buffer hits during reads
+system.physmem.writeRowHits 50184 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 68.51 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 75.00 # Row buffer hit rate for writes
+system.physmem.avgGap 1162526.01 # Average gap between requests
+system.membus.throughput 55052525 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 409284 # Transaction distribution
+system.membus.trans_dist::ReadResp 409284 # Transaction distribution
+system.membus.trans_dist::Writeback 66908 # Transaction distribution
+system.membus.trans_dist::ReadExReq 66850 # Transaction distribution
+system.membus.trans_dist::ReadExResp 66850 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 1019176 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 1019176 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34754688 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 34754688 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 34754688 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 1238262500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4532735250 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
+system.cpu.branchPred.lookups 388673605 # Number of BP lookups
+system.cpu.branchPred.condPredicted 255878326 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 25733265 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 278525299 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 258256723 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 82.938319 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 56744188 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 6782 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 92.722896 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 57195432 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 6738 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 519038391 # DTB read hits
-system.cpu.dtb.read_misses 606346 # DTB read misses
+system.cpu.dtb.read_hits 521844087 # DTB read hits
+system.cpu.dtb.read_misses 593644 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 519644737 # DTB read accesses
-system.cpu.dtb.write_hits 282491025 # DTB write hits
-system.cpu.dtb.write_misses 50159 # DTB write misses
+system.cpu.dtb.read_accesses 522437731 # DTB read accesses
+system.cpu.dtb.write_hits 282954606 # DTB write hits
+system.cpu.dtb.write_misses 50165 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 282541184 # DTB write accesses
-system.cpu.dtb.data_hits 801529416 # DTB hits
-system.cpu.dtb.data_misses 656505 # DTB misses
+system.cpu.dtb.write_accesses 283004771 # DTB write accesses
+system.cpu.dtb.data_hits 804798693 # DTB hits
+system.cpu.dtb.data_misses 643809 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 802185921 # DTB accesses
-system.cpu.itb.fetch_hits 390623308 # ITB hits
-system.cpu.itb.fetch_misses 546 # ITB misses
+system.cpu.dtb.data_accesses 805442502 # DTB accesses
+system.cpu.itb.fetch_hits 394528514 # ITB hits
+system.cpu.itb.fetch_misses 534 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 390623854 # ITB accesses
+system.cpu.itb.fetch_accesses 394529048 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 39 # Number of system calls
-system.cpu.numCycles 1252029901 # number of cpu cycles simulated
+system.cpu.numCycles 1262601061 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 405523870 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 3256215701 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 388875863 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 314307287 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 626203619 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 155794648 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 73991596 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 143 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 6471 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 390623308 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 10992432 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1235766511 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.634976 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.141364 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 409498007 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 3272810217 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 388673605 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 315452155 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 629699645 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 157846800 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 75851008 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 147 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 7336 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 49 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 394528514 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 11392908 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1246680714 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.625219 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.138755 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 609562892 49.33% 49.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 56929322 4.61% 53.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 42752934 3.46% 57.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 71333026 5.77% 63.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 128895698 10.43% 73.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 44916877 3.63% 77.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 41222080 3.34% 80.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 8947680 0.72% 81.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 231206002 18.71% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 616981069 49.49% 49.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 57198279 4.59% 54.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 43039078 3.45% 57.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 71977388 5.77% 63.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 129322230 10.37% 73.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 46258105 3.71% 77.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 41218514 3.31% 80.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 7777319 0.62% 81.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 232908732 18.68% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1235766511 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.310596 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.600749 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 434050234 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 59825791 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 602225660 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 9636107 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 130028719 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 31692009 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 12420 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3180730731 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 46427 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 130028719 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 463334620 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 24461750 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 27280 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 582229724 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 35684418 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 3082031269 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 93 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 15345 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 29415634 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2044995723 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3566316890 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3445638932 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 120677958 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1246680714 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.307836 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.592117 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 437789893 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 62140482 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 606005534 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 9132317 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 131612488 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 31510475 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 12424 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3192799837 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 46361 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 131612488 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 467284900 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 27231873 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 27253 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 585294370 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 35229830 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 3093290625 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 153 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 14758 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 28928557 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2053350484 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3577730264 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3457415406 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 120314858 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1384969070 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 660026653 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 4235 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 97 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 110158163 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 738560803 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 349770872 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 68005426 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 8800641 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2612267018 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 91 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2153832750 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 17944057 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 789157528 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 720017007 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 52 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1235766511 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.742912 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.802932 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 668381414 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 4231 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 93 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 109772702 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 743605283 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 351355021 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 69106055 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 8779755 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2622263880 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 88 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2159577480 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 17944946 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 799158217 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 726204094 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1246680714 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.732262 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.802997 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 442318037 35.79% 35.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 194738197 15.76% 51.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 250284254 20.25% 71.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 121277806 9.81% 81.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 105807762 8.56% 90.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 77171137 6.24% 96.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 25347258 2.05% 98.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 17054134 1.38% 99.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1767926 0.14% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 450451444 36.13% 36.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 196386892 15.75% 51.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 251435205 20.17% 72.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 120817476 9.69% 81.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 104827933 8.41% 90.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 79080340 6.34% 96.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 24383702 1.96% 98.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 17529670 1.41% 99.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1768052 0.14% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1235766511 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1246680714 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 1146289 3.17% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 25061435 69.20% 72.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 10007223 27.63% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 1146168 3.12% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 25530327 69.57% 72.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 10022787 27.31% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1231694482 57.19% 57.19% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 17093 0.00% 57.19% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 27851386 1.29% 58.48% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 8254692 0.38% 58.86% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 7204648 0.33% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.20% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 586233325 27.22% 86.42% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 292574368 13.58% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1233812197 57.13% 57.13% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 17092 0.00% 57.13% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 27851163 1.29% 58.42% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 8254698 0.38% 58.80% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 7204652 0.33% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.14% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 589396274 27.29% 86.43% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 293038648 13.57% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2153832750 # Type of FU issued
-system.cpu.iq.rate 1.720273 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 36214947 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.016814 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 5446489367 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3313484734 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1984683423 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 151101648 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 88013502 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 73610007 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2112595001 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 77449944 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 62149579 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2159577480 # Type of FU issued
+system.cpu.iq.rate 1.710420 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 36699282 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.016994 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 5469378913 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3334207188 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1989129090 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 151100989 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 87288283 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 73609749 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2118824418 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 77449592 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 62141857 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 227490777 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 22685 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 76128 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 138975976 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 232535257 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 18630 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 75784 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 140560125 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 4415 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 2362 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 4408 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 2802 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 130028719 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 10422536 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 524259 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2975772151 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 731348 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 738560803 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 349770872 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 91 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 195346 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 1466 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 76128 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 25258103 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 28541 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 25286644 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2060237153 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 519644898 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 93595597 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 131612488 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 13139012 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 539946 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2986122932 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 725503 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 743605283 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 351355021 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 88 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 196101 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 1503 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 75784 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 25727396 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 27151 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 25754547 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2065136857 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 522437892 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 94440623 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 363505042 # number of nop insts executed
-system.cpu.iew.exec_refs 802186536 # number of memory reference insts executed
-system.cpu.iew.exec_branches 277071948 # Number of branches executed
-system.cpu.iew.exec_stores 282541638 # Number of stores executed
-system.cpu.iew.exec_rate 1.645518 # Inst execution rate
-system.cpu.iew.wb_sent 2060115451 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2058293430 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1179460731 # num instructions producing a value
-system.cpu.iew.wb_consumers 1750814151 # num instructions consuming a value
+system.cpu.iew.exec_nop 363858964 # number of nop insts executed
+system.cpu.iew.exec_refs 805443124 # number of memory reference insts executed
+system.cpu.iew.exec_branches 277347977 # Number of branches executed
+system.cpu.iew.exec_stores 283005232 # Number of stores executed
+system.cpu.iew.exec_rate 1.635621 # Inst execution rate
+system.cpu.iew.wb_sent 2065019944 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2062738839 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1180752690 # num instructions producing a value
+system.cpu.iew.wb_consumers 1753366082 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.643965 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.673664 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.633722 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.673421 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 949829893 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 960178624 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 25252672 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1105737792 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.816875 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.519271 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 25721232 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1115068226 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.801672 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.508434 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 488711252 44.20% 44.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 226575390 20.49% 64.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 120398789 10.89% 75.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 59423757 5.37% 80.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 48998760 4.43% 85.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 24145631 2.18% 87.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 18552721 1.68% 89.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 16148092 1.46% 90.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 102783400 9.30% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 496151769 44.50% 44.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 228465229 20.49% 64.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 119927421 10.76% 75.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 58951874 5.29% 81.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 50411669 4.52% 85.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 24161138 2.17% 87.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 19007626 1.70% 89.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 16618211 1.49% 90.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 101373289 9.09% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1105737792 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1115068226 # Number of insts commited each cycle
system.cpu.commit.committedInsts 2008987604 # Number of instructions committed
system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 71824891 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1778941351 # Number of committed integer instructions.
system.cpu.commit.function_calls 39955347 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 102783400 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 101373289 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3956135479 # The number of ROB reads
-system.cpu.rob.rob_writes 6047665736 # The number of ROB writes
-system.cpu.timesIdled 331504 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 16263390 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3977224755 # The number of ROB reads
+system.cpu.rob.rob_writes 6069947076 # The number of ROB writes
+system.cpu.timesIdled 341189 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 15920347 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
-system.cpu.cpi 0.686780 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.686780 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.456070 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.456070 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 2621566555 # number of integer regfile reads
-system.cpu.int_regfile_writes 1491832809 # number of integer regfile writes
-system.cpu.fp_regfile_reads 78811406 # number of floating regfile reads
-system.cpu.fp_regfile_writes 52661103 # number of floating regfile writes
+system.cpu.cpi 0.692579 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.692579 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.443879 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.443879 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 2627113034 # number of integer regfile reads
+system.cpu.int_regfile_writes 1496009216 # number of integer regfile writes
+system.cpu.fp_regfile_reads 78810922 # number of floating regfile reads
+system.cpu.fp_regfile_writes 52660839 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.icache.replacements 8325 # number of replacements
-system.cpu.icache.tagsinuse 1657.564105 # Cycle average of tags in use
-system.cpu.icache.total_refs 390610507 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 10037 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 38917.057587 # Average number of references to valid blocks.
+system.cpu.toL2Bus.throughput 166051525 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 1470336 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 1470335 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 95971 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 71638 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 71638 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 20109 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3159809 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 3179918 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 643456 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104184960 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 104828416 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 104828416 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 914943500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 15081000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 2297878500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
+system.cpu.icache.replacements 8339 # number of replacements
+system.cpu.icache.tagsinuse 1660.409803 # Cycle average of tags in use
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-system.cpu.dcache.overall_avg_miss_latency::cpu.data 33916.205570 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 33916.205570 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 13719 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 113 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 382 # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 24 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 24 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 670490085 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 670490085 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 670490085 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 670490085 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004189 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.004189 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005038 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.005038 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.083333 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.083333 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.004456 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.004456 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.004456 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.004456 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39298.296685 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 39298.296685 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42472.937393 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 42472.937393 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 66750 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 66750 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 40426.646276 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 40426.646276 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 40426.646276 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 40426.646276 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 17832 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 107 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 375 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.913613 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 113 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.552000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 107 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 95989 # number of writebacks
-system.cpu.dcache.writebacks::total 95989 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465539 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 465539 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990134 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 990134 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1455673 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1455673 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1455673 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1455673 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460212 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1460212 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71642 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 71642 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1531854 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1531854 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1531854 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1531854 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40615263000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 40615263000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3896657000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3896657000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44511920000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 44511920000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44511920000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 44511920000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003196 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003196 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.writebacks::writebacks 95971 # number of writebacks
+system.cpu.dcache.writebacks::total 95971 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 465494 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 465494 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 990257 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 990257 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1455751 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1455751 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1455751 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1455751 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460280 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1460280 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71638 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 71638 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1531918 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1531918 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1531918 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1531918 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41822016500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 41822016500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5130364000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5130364000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 69500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 69500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46952380500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 46952380500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46952380500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 46952380500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003177 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003177 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000340 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000340 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002294 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.002294 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002294 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.002294 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27814.634450 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27814.634450 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54390.678652 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54390.678652 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29057.547260 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 29057.547260 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29057.547260 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 29057.547260 # average overall mshr miss latency
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041667 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041667 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002285 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.002285 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002285 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.002285 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28639.724231 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28639.724231 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71615.120467 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71615.120467 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 69500 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 69500 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30649.408454 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 30649.408454 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30649.408454 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 30649.408454 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 1004710587000 # Number of ticks simulated
final_tick 1004710587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2509174 # Simulator instruction rate (inst/s)
-host_op_rate 2509174 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1254857691 # Simulator tick rate (ticks/s)
-host_mem_usage 273968 # Number of bytes of host memory used
-host_seconds 800.66 # Real time elapsed on the host
+host_inst_rate 3493388 # Simulator instruction rate (inst/s)
+host_op_rate 3493388 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1747070946 # Simulator tick rate (ticks/s)
+host_mem_usage 225488 # Number of bytes of host memory used
+host_seconds 575.08 # Real time elapsed on the host
sim_insts 2008987605 # Number of instructions simulated
sim_ops 2008987605 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 8037684280 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7999999586 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5131370910 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13131370496 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 13131370496 # Throughput (bytes/s)
+system.membus.data_through_bus 13193226959 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
sim_ticks 2769739533000 # Number of ticks simulated
final_tick 2769739533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 964642 # Simulator instruction rate (inst/s)
-host_op_rate 964642 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1329927483 # Simulator tick rate (ticks/s)
-host_mem_usage 281524 # Number of bytes of host memory used
-host_seconds 2082.62 # Real time elapsed on the host
+host_inst_rate 1559352 # Simulator instruction rate (inst/s)
+host_op_rate 1559352 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2149839105 # Simulator tick rate (ticks/s)
+host_mem_usage 233980 # Number of bytes of host memory used
+host_seconds 1288.35 # Real time elapsed on the host
sim_insts 2008987605 # Number of instructions simulated
sim_ops 2008987605 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 49749 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 10934077 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12529860 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 12529860 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 408476 # Transaction distribution
+system.membus.trans_dist::ReadResp 408476 # Transaction distribution
+system.membus.trans_dist::Writeback 66908 # Transaction distribution
+system.membus.trans_dist::ReadExReq 66873 # Transaction distribution
+system.membus.trans_dist::ReadExResp 66873 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 1017606 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 1017606 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34704448 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 34704448 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 34704448 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 1077521000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4278141000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 37822912 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 1468788 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 1468788 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 96129 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 71952 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 71952 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 21192 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3156417 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 3177609 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 678144 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104081472 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 104759616 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 104759616 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 914563500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 15894000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 2295216000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.627426 # Number of seconds simulated
-sim_ticks 627426486000 # Number of ticks simulated
-final_tick 627426486000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.629145 # Number of seconds simulated
+sim_ticks 629144850500 # Number of ticks simulated
+final_tick 629144850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 65805 # Simulator instruction rate (inst/s)
-host_op_rate 89618 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 29824381 # Simulator tick rate (ticks/s)
-host_mem_usage 297136 # Number of bytes of host memory used
-host_seconds 21037.37 # Real time elapsed on the host
+host_inst_rate 104232 # Simulator instruction rate (inst/s)
+host_op_rate 141949 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 47369420 # Simulator tick rate (ticks/s)
+host_mem_usage 254336 # Number of bytes of host memory used
+host_seconds 13281.67 # Real time elapsed on the host
sim_insts 1384370590 # Number of instructions simulated
sim_ops 1885325342 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 154240 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 30242112 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30396352 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 154240 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 154240 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 155072 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 30241984 # Number of bytes read from this memory
+system.physmem.bytes_read::total 30397056 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 155072 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 155072 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2410 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 472533 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 474943 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 2423 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 472531 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 474954 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 245830 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 48200248 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 48446077 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 245830 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 245830 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 6742259 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6742259 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 6742259 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 245830 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 48200248 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 55188336 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 474944 # Total number of read requests seen
+system.physmem.bw_read::cpu.inst 246481 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 48068396 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 48314877 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 246481 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 246481 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 6723844 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6723844 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 6723844 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 246481 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 48068396 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 55038721 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 474954 # Total number of read requests seen
system.physmem.writeReqs 66098 # Total number of write requests seen
-system.physmem.cpureqs 545373 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 30396352 # Total number of bytes read from memory
+system.physmem.cpureqs 545348 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 30397056 # Total number of bytes read from memory
system.physmem.bytesWritten 4230272 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 30396352 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 30397056 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 152 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4331 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 29709 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 29700 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 29689 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 29766 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 29692 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 29719 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 29749 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 29652 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 29638 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 29679 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 29629 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 29599 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 29613 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 29623 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 29684 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 29651 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 4145 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 4146 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 4144 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 4159 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 4130 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 4128 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 4130 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 4131 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 4119 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 4145 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 4136 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 4104 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 4108 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 4104 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 4133 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 4136 # Track writes on a per bank basis
+system.physmem.servicedByWrQ 163 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4296 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 29873 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 29676 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 29740 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 29705 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 29805 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 29834 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 29631 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 29439 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 29482 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 29490 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 29536 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 29644 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 29703 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 29807 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 29631 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 29795 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 4174 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 4102 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 4138 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 4148 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 4226 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 4225 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 4174 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 4096 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 4096 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 4096 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 4096 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 4097 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 4098 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 4096 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 4096 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 4140 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 627426443000 # Total gap between requests
+system.physmem.totGap 629144781500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 474944 # Categorize read packet sizes
+system.physmem.readPktSize::6 474954 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 66098 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 405886 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 66680 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 2123 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 19 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 407688 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 66635 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 380 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 69 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3439648250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 21418222000 # Sum of mem lat for all requests
-system.physmem.totBusLat 2373960000 # Total cycles spent in databus access
-system.physmem.totBankLat 15604613750 # Total cycles spent in bank access
-system.physmem.avgQLat 7244.54 # Average queueing delay per request
-system.physmem.avgBankLat 32866.21 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 173211 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 199.837655 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 132.549683 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 508.405937 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 59600 34.41% 34.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 42691 24.65% 59.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 39909 23.04% 82.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 25367 14.65% 96.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 276 0.16% 96.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 104 0.06% 96.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 98 0.06% 97.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 91 0.05% 97.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 88 0.05% 97.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 83 0.05% 97.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 78 0.05% 97.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 81 0.05% 97.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 73 0.04% 97.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 74 0.04% 97.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 79 0.05% 97.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 80 0.05% 97.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 75 0.04% 97.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 70 0.04% 97.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 80 0.05% 97.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 73 0.04% 97.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 73 0.04% 97.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1473 3309 1.91% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 4 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 2 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1665 4 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1857 1 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1985 2 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2049 2 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2113 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2177 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2241 2 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2305 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2369 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2433 3 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2497 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2625 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2689 2 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2753 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2817 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3009 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3137 1 0.00% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3457 1 0.00% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648-3649 1 0.00% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776-3777 1 0.00% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3968-3969 1 0.00% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4160-4161 78 0.05% 99.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4224-4225 2 0.00% 99.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4352-4353 1 0.00% 99.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5120-5121 1 0.00% 99.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5376-5377 1 0.00% 99.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 558 0.32% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 173211 # Bytes accessed per row activation
+system.physmem.totQLat 2060605250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 15116660250 # Sum of mem lat for all requests
+system.physmem.totBusLat 2373955000 # Total cycles spent in databus access
+system.physmem.totBankLat 10682100000 # Total cycles spent in bank access
+system.physmem.avgQLat 4340.03 # Average queueing delay per request
+system.physmem.avgBankLat 22498.53 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 45110.75 # Average memory access latency
-system.physmem.avgRdBW 48.45 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 6.74 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 48.45 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 6.74 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 31838.56 # Average memory access latency
+system.physmem.avgRdBW 48.31 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 6.72 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 48.31 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 6.72 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.43 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.03 # Average read queue length over time
-system.physmem.avgWrQLen 17.42 # Average write queue length over time
-system.physmem.readRowHits 143318 # Number of row buffer hits during reads
-system.physmem.writeRowHits 45505 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 30.19 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 68.84 # Row buffer hit rate for writes
-system.physmem.avgGap 1159663.10 # Average gap between requests
-system.cpu.branchPred.lookups 441070019 # Number of BP lookups
-system.cpu.branchPred.condPredicted 353935839 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 30635394 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 253577570 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 230740155 # Number of BTB hits
+system.physmem.avgRdQLen 0.02 # Average read queue length over time
+system.physmem.avgWrQLen 17.41 # Average write queue length over time
+system.physmem.readRowHits 318020 # Number of row buffer hits during reads
+system.physmem.writeRowHits 49639 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 66.98 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 75.10 # Row buffer hit rate for writes
+system.physmem.avgGap 1162817.59 # Average gap between requests
+system.membus.throughput 55038619 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 408879 # Transaction distribution
+system.membus.trans_dist::ReadResp 408878 # Transaction distribution
+system.membus.trans_dist::Writeback 66098 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4296 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4296 # Transaction distribution
+system.membus.trans_dist::ReadExReq 66075 # Transaction distribution
+system.membus.trans_dist::ReadExResp 66075 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 1024597 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 1024597 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34627264 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 34627264 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 34627264 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 1206768500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4481136954 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
+system.cpu.branchPred.lookups 441633744 # Number of BP lookups
+system.cpu.branchPred.condPredicted 353245820 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 30626910 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 253291175 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 229518524 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 90.993914 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 51827244 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 2806499 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 90.614497 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 52707299 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 2806413 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1411 # Number of system calls
-system.cpu.numCycles 1254852973 # number of cpu cycles simulated
+system.cpu.numCycles 1258289702 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 354891147 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2286425176 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 441070019 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 282567399 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 601918215 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 156601137 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 130017521 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 563 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 11246 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 335797832 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 11972922 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1212752602 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.588148 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.180737 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 355059035 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2281679265 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 441633744 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 282225823 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 601500993 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 156584245 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 133257591 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 11034 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 167 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 335655020 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 11657170 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1215734936 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.578441 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.176596 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 610879185 50.37% 50.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 42915841 3.54% 53.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 96172627 7.93% 61.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 57091199 4.71% 66.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 71993232 5.94% 72.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 43518781 3.59% 76.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 30912276 2.55% 78.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 32947513 2.72% 81.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 226321948 18.66% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 614278728 50.53% 50.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 43031217 3.54% 54.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 96058050 7.90% 61.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 55653458 4.58% 66.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 73683625 6.06% 72.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 43835223 3.61% 76.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 31015132 2.55% 78.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 32844314 2.70% 81.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 225335189 18.53% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1212752602 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.351491 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.822066 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 405845320 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 102427093 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 561818768 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 16761536 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 125899885 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 44789430 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 14217 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3028082478 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 30107 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 125899885 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 441818256 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 34409054 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 439229 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 540562916 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 69623262 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2944183318 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 71 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 4821524 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 54501316 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 2929324563 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 14012451828 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 13441344414 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 571107414 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1215734936 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.350979 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.813318 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 405408112 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 105525155 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 562197495 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 16710779 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 125893395 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 45735070 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 12243 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3027450313 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 24999 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 125893395 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 441381944 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 37599884 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 466637 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 540742593 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 69650483 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2947282074 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 91 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 4813438 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 54199144 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2931640163 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 14025190740 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 13455020985 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 570169755 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 936184473 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 21713 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 19183 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 177423093 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 969808911 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 487407647 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 36223294 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 40155637 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2791556624 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 29091 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2432817301 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 13264046 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 893693392 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 2309057295 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 7707 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1212752602 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.006029 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.872054 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 938500073 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 22029 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 19516 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 179002715 # count of insts added to the skid buffer
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+system.cpu.memDep0.conflictingStores 41359268 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2792194659 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 28248 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2432796766 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 13281338 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 894337134 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 2316040320 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 6864 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1215734936 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.001091 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.872110 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::1 183745627 15.15% 46.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 204018800 16.82% 63.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 169675350 13.99% 77.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 132825359 10.95% 87.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 92323584 7.61% 95.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 37944626 3.13% 98.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 12438520 1.03% 99.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 3043909 0.25% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 379743334 31.24% 31.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 183587297 15.10% 46.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 204204940 16.80% 63.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 169567149 13.95% 77.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 132821991 10.93% 88.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 92473374 7.61% 95.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 37933065 3.12% 98.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 12385370 1.02% 99.75% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1212752602 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1215734936 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 715136 0.82% 0.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 24381 0.03% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 55109735 62.90% 63.74% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 31764891 36.26% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 717080 0.82% 0.82% # attempts to use FU when none available
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+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 55165781 62.93% 63.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 31749638 36.22% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1103878887 45.37% 45.37% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 11223380 0.46% 45.84% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1103940359 45.38% 45.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 11224025 0.46% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 45.84% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.84% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.89% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 6876473 0.28% 46.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 5503230 0.23% 46.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.90% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.28% 46.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 5502268 0.23% 46.40% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.40% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 23422628 0.96% 47.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 838195655 34.45% 81.82% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 442341757 18.18% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 23395329 0.96% 47.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.37% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.37% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 838660213 34.47% 81.84% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 441822804 18.16% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2432817301 # Type of FU issued
-system.cpu.iq.rate 1.938727 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 87614143 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.036013 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 6056711081 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3602481479 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 2248827251 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 122554312 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 82864717 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 56458852 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2457090579 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 63340865 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 84315452 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2432796766 # Type of FU issued
+system.cpu.iq.rate 1.933415 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 87656879 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.036031 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 6059775624 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3603986878 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 2248220965 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 122491061 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 82640163 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 56428970 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2457145320 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 63308325 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 84445856 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 338421730 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 8530 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 1429952 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 210412350 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 340236717 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 10068 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 1429873 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 210438994 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 257 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 345 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 125899885 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 12642453 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1559188 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2791598235 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1393439 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 969808911 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 487407647 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 19105 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1555218 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 2524 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 1429952 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 32462166 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1535020 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 33997186 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2358042615 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 792538170 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 74774686 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 125893395 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 15644195 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1562618 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2792235356 # Number of instructions dispatched to IQ
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+system.cpu.iew.iewIQFullEvents 1558827 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 2523 # Number of times the LSQ has become full, causing a stall
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+system.cpu.iew.predictedTakenIncorrect 32450935 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1518228 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 33969163 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2357455643 # Number of executed instructions
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system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 12520 # number of nop insts executed
-system.cpu.iew.exec_refs 1216339727 # number of memory reference insts executed
-system.cpu.iew.exec_branches 319851158 # Number of branches executed
-system.cpu.iew.exec_stores 423801557 # Number of stores executed
-system.cpu.iew.exec_rate 1.879139 # Inst execution rate
-system.cpu.iew.wb_sent 2331014082 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2305286103 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1347320139 # num instructions producing a value
-system.cpu.iew.wb_consumers 2523004414 # num instructions consuming a value
+system.cpu.iew.exec_nop 12449 # number of nop insts executed
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+system.cpu.iew.exec_stores 423176695 # Number of stores executed
+system.cpu.iew.exec_rate 1.873540 # Inst execution rate
+system.cpu.iew.wb_sent 2330413186 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2304649935 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1347862197 # num instructions producing a value
+system.cpu.iew.wb_consumers 2523443205 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.837097 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.534014 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.831573 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.534136 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 906262003 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 906899118 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 30621444 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1086852717 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.734675 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.398797 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 30614902 # The number of times a branch was mispredicted
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+system.cpu.commit.committed_per_cycle::mean 1.729918 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.397219 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 446522418 41.08% 41.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 288653852 26.56% 67.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 95098505 8.75% 76.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 70200543 6.46% 82.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 46464549 4.28% 87.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 22199454 2.04% 89.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 15846996 1.46% 90.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 10984775 1.01% 91.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 90881625 8.36% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 449517068 41.25% 41.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 288638854 26.48% 67.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 95107207 8.73% 76.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 70204085 6.44% 82.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 46459856 4.26% 87.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 22200640 2.04% 89.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 15848625 1.45% 90.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 10985187 1.01% 91.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 90880019 8.34% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1086852717 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1089841541 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions.
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 90881625 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 90880019 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3787551108 # The number of ROB reads
-system.cpu.rob.rob_writes 5709107671 # The number of ROB writes
-system.cpu.timesIdled 353124 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 42100371 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3791178653 # The number of ROB reads
+system.cpu.rob.rob_writes 5710375191 # The number of ROB writes
+system.cpu.timesIdled 353026 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 42554766 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated
-system.cpu.cpi 0.906443 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.906443 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.103213 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.103213 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 11756785732 # number of integer regfile reads
-system.cpu.int_regfile_writes 2218462767 # number of integer regfile writes
-system.cpu.fp_regfile_reads 68799116 # number of floating regfile reads
-system.cpu.fp_regfile_writes 49570496 # number of floating regfile writes
-system.cpu.misc_regfile_reads 1364149303 # number of misc regfile reads
+system.cpu.cpi 0.908925 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.908925 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.100200 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.100200 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 11755248902 # number of integer regfile reads
+system.cpu.int_regfile_writes 2218571084 # number of integer regfile writes
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+system.cpu.fp_regfile_writes 49541079 # number of floating regfile writes
+system.cpu.misc_regfile_reads 1363718123 # number of misc regfile reads
system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes
-system.cpu.icache.replacements 22544 # number of replacements
-system.cpu.icache.tagsinuse 1643.593682 # Cycle average of tags in use
-system.cpu.icache.total_refs 335759855 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 24228 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 13858.339731 # Average number of references to valid blocks.
+system.cpu.toL2Bus.throughput 169026080 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 1492742 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 1492741 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 96335 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 4299 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 4299 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 72516 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 72516 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 52382 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3178768 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 3231150 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1538688 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104528128 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 106066816 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 106066816 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 275072 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 929281000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 42510998 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 2307535978 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
+system.cpu.icache.replacements 22361 # number of replacements
+system.cpu.icache.tagsinuse 1639.588858 # Cycle average of tags in use
+system.cpu.icache.total_refs 335620121 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 24041 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 13960.322824 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1643.593682 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.802536 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.802536 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 335766423 # number of ReadReq hits
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-system.cpu.icache.demand_hits::cpu.inst 335766423 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 335766423 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 335766423 # number of overall hits
-system.cpu.icache.overall_hits::total 335766423 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 31408 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 31408 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 31408 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 31408 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 31408 # number of overall misses
-system.cpu.icache.overall_misses::total 31408 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 477378999 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 477378999 # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total 477378999 # number of demand (read+write) miss cycles
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-system.cpu.icache.overall_miss_latency::total 477378999 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 335797831 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.overall_accesses::total 335797831 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000094 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000094 # miss rate for ReadReq accesses
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-system.cpu.icache.demand_miss_rate::total 0.000094 # miss rate for demand accesses
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-system.cpu.icache.overall_miss_rate::total 0.000094 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15199.280406 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 15199.280406 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 15199.280406 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 15199.280406 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 15199.280406 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 15199.280406 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 872 # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst 1639.588858 # Average occupied blocks per requestor
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+system.cpu.icache.occ_percent::total 0.800580 # Average percentage of cache occupancy
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+system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses
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+system.cpu.icache.ReadReq_avg_miss_latency::total 17014.473885 # average ReadReq miss latency
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+system.cpu.icache.demand_avg_miss_latency::total 17014.473885 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 17014.473885 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 17014.473885 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 2055 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 35 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 33.538462 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 58.714286 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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-system.cpu.icache.demand_mshr_hits::total 2844 # number of demand (read+write) MSHR hits
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-system.cpu.icache.overall_mshr_hits::total 2844 # number of overall MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses::total 28564 # number of ReadReq MSHR misses
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-system.cpu.icache.demand_mshr_misses::total 28564 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 28564 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 28564 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 383349499 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 383349499 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 383349499 # number of demand (read+write) MSHR miss cycles
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-system.cpu.icache.overall_mshr_miss_latency::total 383349499 # number of overall MSHR miss cycles
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system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.writebacks::total 96322 # number of writebacks
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-system.cpu.dcache.ReadReq_mshr_hits::total 488793 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765175 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 765175 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 96335 # number of writebacks
+system.cpu.dcache.writebacks::total 96335 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488604 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 488604 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765599 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 765599 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1253968 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1253968 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1253968 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1253968 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464706 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1464706 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76852 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 76852 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1541558 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1541558 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1541558 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1541558 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 41088591000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 41088591000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3410048000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3410048000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44498639000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 44498639000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44498639000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 44498639000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.001585 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001585 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.001585 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28052.449434 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28052.449434 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44371.623380 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44371.623380 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28866.016718 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28866.016718 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28866.016718 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28866.016718 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_hits::cpu.data 1254203 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1254203 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1254203 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1254203 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464403 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1464403 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76814 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 76814 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1541217 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1541217 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1541217 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1541217 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42813858522 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 42813858522 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4818359000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4818359000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47632217522 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 47632217522 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47632217522 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 47632217522 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002104 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002104 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.001584 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.001584 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29236.390886 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29236.390886 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62727.614758 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62727.614758 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30905.587936 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 30905.587936 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30905.587936 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 30905.587936 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 945613126000 # Number of ticks simulated
final_tick 945613126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1270703 # Simulator instruction rate (inst/s)
-host_op_rate 1730522 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 867964073 # Simulator tick rate (ticks/s)
-host_mem_usage 286692 # Number of bytes of host memory used
-host_seconds 1089.46 # Real time elapsed on the host
+host_inst_rate 1181509 # Simulator instruction rate (inst/s)
+host_op_rate 1609052 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 807039161 # Simulator tick rate (ticks/s)
+host_mem_usage 242488 # Number of bytes of host memory used
+host_seconds 1171.71 # Real time elapsed on the host
sim_insts 1384381606 # Number of instructions simulated
sim_ops 1885336358 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 5561086004 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 5880931484 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3794748160 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9675679644 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 9675679644 # Throughput (bytes/s)
+system.membus.data_through_bus 9149449674 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
sim_ticks 2326118592000 # Number of ticks simulated
final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 664911 # Simulator instruction rate (inst/s)
-host_op_rate 901999 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1119467924 # Simulator tick rate (ticks/s)
-host_mem_usage 296296 # Number of bytes of host memory used
-host_seconds 2077.88 # Real time elapsed on the host
+host_inst_rate 575384 # Simulator instruction rate (inst/s)
+host_op_rate 780549 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 968736790 # Simulator tick rate (ticks/s)
+host_mem_usage 250996 # Number of bytes of host memory used
+host_seconds 2401.19 # Real time elapsed on the host
sim_insts 1381604339 # Number of instructions simulated
sim_ops 1874244941 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 113472 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 48782 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 12996978 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 14864384 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 14864384 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 408063 # Transaction distribution
+system.membus.trans_dist::ReadResp 408063 # Transaction distribution
+system.membus.trans_dist::Writeback 66099 # Transaction distribution
+system.membus.trans_dist::ReadExReq 66093 # Transaction distribution
+system.membus.trans_dist::ReadExResp 66093 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 1014411 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 1014411 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34576320 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 34576320 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 34576320 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 1069047000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4267404000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 45389617 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 1480676 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 1480676 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 96257 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 72780 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 72780 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 39606 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3163563 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 3203169 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1267392 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104314240 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 105581632 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 105581632 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 921113500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 29704500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 2300479500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.042726 # Number of seconds simulated
-sim_ticks 42725646500 # Number of ticks simulated
-final_tick 42725646500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.043732 # Number of seconds simulated
+sim_ticks 43731802500 # Number of ticks simulated
+final_tick 43731802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 44211 # Simulator instruction rate (inst/s)
-host_op_rate 44211 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 21382391 # Simulator tick rate (ticks/s)
-host_mem_usage 280712 # Number of bytes of host memory used
-host_seconds 1998.17 # Real time elapsed on the host
+host_inst_rate 69429 # Simulator instruction rate (inst/s)
+host_op_rate 69429 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 34369620 # Simulator tick rate (ticks/s)
+host_mem_usage 233240 # Number of bytes of host memory used
+host_seconds 1272.40 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 454528 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 454592 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10592896 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 454528 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 454528 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total 10592960 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 454592 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 454592 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory
system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 7102 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 7103 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 158412 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 165514 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 165515 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory
system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 10638294 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 237289985 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 247928279 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 10638294 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 10638294 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 170759452 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 170759452 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 170759452 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 10638294 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 237289985 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 418687731 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 165514 # Total number of read requests seen
+system.physmem.bw_read::cpu.inst 10394998 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 231830554 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 242225552 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 10394998 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 10394998 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 166830718 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 166830718 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 166830718 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 10394998 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 231830554 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 409056270 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 165515 # Total number of read requests seen
system.physmem.writeReqs 113997 # Total number of write requests seen
-system.physmem.cpureqs 279511 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 10592896 # Total number of bytes read from memory
+system.physmem.cpureqs 279512 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 10592960 # Total number of bytes read from memory
system.physmem.bytesWritten 7295808 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 10592896 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 10592960 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 7295808 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 10572 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 10465 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 10270 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 10169 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 10534 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 10768 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 10384 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 10283 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 10421 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 10442 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 10202 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 9934 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 10515 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 10344 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 10131 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 10080 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 7377 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7241 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 6946 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 6832 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7241 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 7386 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7023 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 7006 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 7262 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7155 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7040 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 6934 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 7274 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 7038 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 6992 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::0 10376 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 10439 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 10257 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 10013 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 10351 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 10363 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 9796 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 10275 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 10510 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 10590 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 10479 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 10187 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 10236 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 10581 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 10468 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 10594 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7081 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7259 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 7255 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 6998 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7125 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 7175 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 6769 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7226 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 6938 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7084 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 6989 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 6964 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 7284 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7283 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7472 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 42725626000 # Total gap between requests
+system.physmem.totGap 43731782000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 165514 # Categorize read packet sizes
+system.physmem.readPktSize::6 165515 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 113997 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 62488 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 76381 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 18709 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 7928 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 72899 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 71538 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 16211 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 4865 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2107 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 3879 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 4869 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 4907 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 4940 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 4955 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 3864 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 4588 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 4945 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 4953 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 4954 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 2850 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 1078 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 88 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 50 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 1093 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 369 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 7078163250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 9669555750 # Sum of mem lat for all requests
-system.physmem.totBusLat 827570000 # Total cycles spent in databus access
-system.physmem.totBankLat 1763822500 # Total cycles spent in bank access
-system.physmem.avgQLat 42764.74 # Average queueing delay per request
-system.physmem.avgBankLat 10656.64 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 48863 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 366.074289 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 172.394514 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 748.149039 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 19835 40.59% 40.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 7665 15.69% 56.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 4199 8.59% 64.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 2953 6.04% 70.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 2157 4.41% 75.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 1715 3.51% 78.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 1297 2.65% 81.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 1110 2.27% 83.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 804 1.65% 85.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 685 1.40% 86.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 483 0.99% 87.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 536 1.10% 88.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 409 0.84% 89.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 338 0.69% 90.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 255 0.52% 90.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 348 0.71% 91.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 228 0.47% 92.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 211 0.43% 92.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 159 0.33% 92.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 306 0.63% 93.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 209 0.43% 93.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 394 0.81% 94.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1473 305 0.62% 95.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 602 1.23% 96.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 201 0.41% 97.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1665 151 0.31% 97.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1729 39 0.08% 97.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1793 155 0.32% 97.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1857 66 0.14% 97.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1921 55 0.11% 97.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1985 29 0.06% 98.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2049 79 0.16% 98.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2113 42 0.09% 98.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2177 46 0.09% 98.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2241 24 0.05% 98.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2305 45 0.09% 98.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2369 30 0.06% 98.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2433 25 0.05% 98.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2497 9 0.02% 98.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2561 30 0.06% 98.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2625 23 0.05% 98.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2689 22 0.05% 98.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2753 9 0.02% 98.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2817 17 0.03% 98.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2881 10 0.02% 98.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2945 14 0.03% 98.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3009 14 0.03% 98.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3073 23 0.05% 98.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3137 11 0.02% 99.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3201 12 0.02% 99.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3265 11 0.02% 99.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3329 10 0.02% 99.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3393 6 0.01% 99.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3457 12 0.02% 99.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520-3521 5 0.01% 99.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3585 7 0.01% 99.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648-3649 6 0.01% 99.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3713 6 0.01% 99.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840-3841 8 0.02% 99.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904-3905 4 0.01% 99.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3968-3969 6 0.01% 99.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4033 6 0.01% 99.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4096-4097 7 0.01% 99.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4160-4161 7 0.01% 99.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4224-4225 7 0.01% 99.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4288-4289 8 0.02% 99.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4416-4417 4 0.01% 99.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4480-4481 3 0.01% 99.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4544-4545 2 0.00% 99.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4672-4673 9 0.02% 99.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4736-4737 6 0.01% 99.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4800-4801 5 0.01% 99.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4992-4993 3 0.01% 99.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5184-5185 6 0.01% 99.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5248-5249 6 0.01% 99.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5312-5313 1 0.00% 99.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5376-5377 5 0.01% 99.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5440-5441 2 0.00% 99.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5568-5569 4 0.01% 99.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5632-5633 4 0.01% 99.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5696-5697 4 0.01% 99.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5952-5953 1 0.00% 99.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6016-6017 6 0.01% 99.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6080-6081 5 0.01% 99.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6208-6209 12 0.02% 99.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6272-6273 1 0.00% 99.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6528-6529 4 0.01% 99.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6592-6593 4 0.01% 99.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6656-6657 1 0.00% 99.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6784-6785 2 0.00% 99.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6848-6849 3 0.01% 99.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6912-6913 1 0.00% 99.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6976-6977 5 0.01% 99.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7104-7105 6 0.01% 99.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7168-7169 11 0.02% 99.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7360-7361 4 0.01% 99.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7424-7425 3 0.01% 99.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7744-7745 3 0.01% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7808-7809 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8000-8001 3 0.01% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8064-8065 6 0.01% 99.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8128-8129 11 0.02% 99.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 164 0.34% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 48863 # Bytes accessed per row activation
+system.physmem.totQLat 6289978250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 8777494500 # Sum of mem lat for all requests
+system.physmem.totBusLat 827575000 # Total cycles spent in databus access
+system.physmem.totBankLat 1659941250 # Total cycles spent in bank access
+system.physmem.avgQLat 38002.47 # Average queueing delay per request
+system.physmem.avgBankLat 10028.95 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 58421.38 # Average memory access latency
-system.physmem.avgRdBW 247.93 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 170.76 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 247.93 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 170.76 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 53031.41 # Average memory access latency
+system.physmem.avgRdBW 242.23 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 166.83 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 242.23 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 166.83 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 3.27 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.23 # Average read queue length over time
-system.physmem.avgWrQLen 10.41 # Average write queue length over time
-system.physmem.readRowHits 148885 # Number of row buffer hits during reads
-system.physmem.writeRowHits 71702 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 89.95 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 62.90 # Row buffer hit rate for writes
-system.physmem.avgGap 152858.48 # Average gap between requests
-system.cpu.branchPred.lookups 18741806 # Number of BP lookups
-system.cpu.branchPred.condPredicted 12317440 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 4774691 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 15571063 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 4663219 # Number of BTB hits
+system.physmem.busUtil 3.20 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.20 # Average read queue length over time
+system.physmem.avgWrQLen 10.42 # Average write queue length over time
+system.physmem.readRowHits 153768 # Number of row buffer hits during reads
+system.physmem.writeRowHits 76872 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 92.90 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 67.43 # Row buffer hit rate for writes
+system.physmem.avgGap 156457.62 # Average gap between requests
+system.membus.throughput 409056270 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 34624 # Transaction distribution
+system.membus.trans_dist::ReadResp 34624 # Transaction distribution
+system.membus.trans_dist::Writeback 113997 # Transaction distribution
+system.membus.trans_dist::ReadExReq 130891 # Transaction distribution
+system.membus.trans_dist::ReadExResp 130891 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 445027 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 445027 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17888768 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 17888768 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 17888768 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 1215256500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
+system.membus.respLayer1.occupancy 1522914250 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 3.5 # Layer utilization (%)
+system.cpu.branchPred.lookups 18742056 # Number of BP lookups
+system.cpu.branchPred.condPredicted 12318265 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 4775163 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 15487144 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 4660091 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 29.947981 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1660960 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 30.090061 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1660966 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 20277542 # DTB read hits
+system.cpu.dtb.read_hits 20277593 # DTB read hits
system.cpu.dtb.read_misses 90148 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 20367690 # DTB read accesses
-system.cpu.dtb.write_hits 14728781 # DTB write hits
+system.cpu.dtb.read_accesses 20367741 # DTB read accesses
+system.cpu.dtb.write_hits 14728959 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 14736033 # DTB write accesses
-system.cpu.dtb.data_hits 35006323 # DTB hits
+system.cpu.dtb.write_accesses 14736211 # DTB write accesses
+system.cpu.dtb.data_hits 35006552 # DTB hits
system.cpu.dtb.data_misses 97400 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 35103723 # DTB accesses
-system.cpu.itb.fetch_hits 12368482 # ITB hits
-system.cpu.itb.fetch_misses 10998 # ITB misses
+system.cpu.dtb.data_accesses 35103952 # DTB accesses
+system.cpu.itb.fetch_hits 12367361 # ITB hits
+system.cpu.itb.fetch_misses 10891 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 12379480 # ITB accesses
+system.cpu.itb.fetch_accesses 12378252 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
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+system.cpu.numCycles 87463606 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.predictedTaken 8073687 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 10668119 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 74170009 # Number of Reads from Int. Register File
+system.cpu.branch_predictor.predictedTaken 8070350 # Number of Branches Predicted As Taken (True).
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system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 126489259 # Total Accesses (Read+Write) to the Int. Register File
-system.cpu.regfile_manager.floatRegFileReads 66071 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File
-system.cpu.regfile_manager.floatRegFileAccesses 293701 # Total Accesses (Read+Write) to the FP Register File
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-system.cpu.agen_unit.agens 35060353 # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect 4447581 # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect 216610 # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted 4664191 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted 9108383 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct 33.865790 # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions 44777788 # Number of Instructions Executed.
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+system.cpu.execution_unit.predicted 9107934 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct 33.869161 # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions 44778070 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 229187 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.comLoads 20276638 # Number of Load instructions committed
system.cpu.comStores 14613377 # Number of Store instructions committed
system.cpu.comBranches 13754477 # Number of Branches instructions committed
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system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total)
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system.cpu.smt_cpi nan # CPI: Total SMT-CPI
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system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 1.033813 # IPC: Total IPC of All Threads
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73234.664224 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72305.998405 # average overall mshr miss latency
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+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.569187 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082168 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.569187 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68591.405040 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60689.391737 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62310.463840 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92801.970724 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92801.970724 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68591.405040 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87223.035502 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 86423.467662 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68591.405040 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87223.035502 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86423.467662 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 200250 # number of replacements
-system.cpu.dcache.tagsinuse 4078.188542 # Cycle average of tags in use
-system.cpu.dcache.total_refs 33754850 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 204346 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 165.184785 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 253407000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4078.188542 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.995651 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.995651 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 20180240 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 20180240 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 13574610 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 13574610 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 33754850 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 33754850 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 33754850 # number of overall hits
-system.cpu.dcache.overall_hits::total 33754850 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 96398 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 96398 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1038767 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1038767 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 1135165 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1135165 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1135165 # number of overall misses
-system.cpu.dcache.overall_misses::total 1135165 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 3869387500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 3869387500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 76774000000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 76774000000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 80643387500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 80643387500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 80643387500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 80643387500 # number of overall miss cycles
+system.cpu.dcache.replacements 200251 # number of replacements
+system.cpu.dcache.tagsinuse 4076.684340 # Cycle average of tags in use
+system.cpu.dcache.total_refs 33754860 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 204347 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 165.184025 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 292193000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4076.684340 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.995284 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.995284 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 20180280 # number of ReadReq hits
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+system.cpu.dcache.overall_miss_latency::total 92178164500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004754 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.004754 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071083 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.071083 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.032536 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.032536 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.032536 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.032536 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40139.707255 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 40139.707255 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73908.778388 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73908.778388 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 71041.115168 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 71041.115168 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 71041.115168 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 71041.115168 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 5035459 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 519 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 116380 # number of cycles access was blocked
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+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51581.108989 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 51581.108989 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83950.870093 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 83950.870093 # average WriteReq miss latency
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+system.cpu.dcache.demand_avg_miss_latency::total 81203.152433 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 81203.152433 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 81203.152433 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 5824366 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 105 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 116607 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.267391 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 519 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.948682 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 105 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 168351 # number of writebacks
-system.cpu.dcache.writebacks::total 168351 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35632 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 35632 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895187 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 895187 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 930819 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 930819 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 930819 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 930819 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks 168352 # number of writebacks
+system.cpu.dcache.writebacks::total 168352 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35591 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 35591 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895217 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 895217 # number of WriteReq MSHR hits
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+system.cpu.dcache.overall_mshr_hits::total 930808 # number of overall MSHR hits
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+system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 204346 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 204346 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 204346 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 204346 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1910017000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 1910017000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12290144000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 12290144000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14200161000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 14200161000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14200161000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 14200161000 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data 204347 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses
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+system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses
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+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2407208517 # number of ReadReq MSHR miss cycles
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+system.cpu.dcache.WriteReq_mshr_miss_latency::total 14006251501 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16413460018 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 16413460018 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16413460018 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 16413460018 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31432.330580 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31432.330580 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85597.882713 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85597.882713 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69490.770556 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 69490.770556 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69490.770556 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 69490.770556 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39613.746227 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39613.746227 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97550.156714 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97550.156714 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80321.512026 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 80321.512026 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80321.512026 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 80321.512026 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.023932 # Number of seconds simulated
-sim_ticks 23931821000 # Number of ticks simulated
-final_tick 23931821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.024943 # Number of seconds simulated
+sim_ticks 24942850000 # Number of ticks simulated
+final_tick 24942850000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 61921 # Simulator instruction rate (inst/s)
-host_op_rate 61921 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 18618559 # Simulator tick rate (ticks/s)
-host_mem_usage 281736 # Number of bytes of host memory used
-host_seconds 1285.37 # Real time elapsed on the host
+host_inst_rate 187895 # Simulator instruction rate (inst/s)
+host_op_rate 187895 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 58883311 # Simulator tick rate (ticks/s)
+host_mem_usage 236320 # Number of bytes of host memory used
+host_seconds 423.60 # Real time elapsed on the host
sim_insts 79591756 # Number of instructions simulated
sim_ops 79591756 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 489984 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10154048 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10644032 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 489984 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 489984 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7296960 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7296960 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 7656 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 158657 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 166313 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 114015 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 114015 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 20474163 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 424290655 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 444764818 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 20474163 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 20474163 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 304906175 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 304906175 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 304906175 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 20474163 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 424290655 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 749670992 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 166313 # Total number of read requests seen
-system.physmem.writeReqs 114015 # Total number of write requests seen
-system.physmem.cpureqs 280328 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 10644032 # Total number of bytes read from memory
-system.physmem.bytesWritten 7296960 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 10644032 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7296960 # bytesWritten derated as per pkt->getSize()
+system.physmem.bytes_read::cpu.inst 490496 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10153472 # Number of bytes read from this memory
+system.physmem.bytes_read::total 10643968 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 490496 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 490496 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7296640 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7296640 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 7664 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 158648 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 166312 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 114010 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 114010 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 19664794 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 407069441 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 426734234 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 19664794 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 19664794 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 292534333 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 292534333 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 292534333 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 19664794 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 407069441 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 719268568 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 166312 # Total number of read requests seen
+system.physmem.writeReqs 114010 # Total number of write requests seen
+system.physmem.cpureqs 280322 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 10643968 # Total number of bytes read from memory
+system.physmem.bytesWritten 7296640 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 10643968 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7296640 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 10648 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 10525 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 10321 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 10258 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 10573 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 10797 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 10407 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 10349 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 10491 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 10476 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 10257 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 9976 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 10566 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 10401 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 10152 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 10114 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 7374 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7242 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 6949 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 6837 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7243 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 7385 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7024 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 7009 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 7264 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7155 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7041 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 6937 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 7276 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 7250 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 7040 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 6989 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::0 10433 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 10460 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 10315 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 10055 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 10429 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 10401 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 9845 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 10323 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 10623 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 10639 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 10547 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 10232 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 10278 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 10621 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 10486 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 10623 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7081 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7257 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 7255 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 6997 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7125 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 7176 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 6771 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 7095 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7228 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 6941 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7084 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 6990 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 6966 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 7287 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7285 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7472 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 23931788000 # Total gap between requests
+system.physmem.totGap 24942817000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 166313 # Categorize read packet sizes
+system.physmem.readPktSize::6 166312 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 114015 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 67890 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 63253 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 27479 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 7665 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 114010 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 73936 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 60757 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 25960 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 5644 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 3084 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 4387 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 4861 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 4929 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 4948 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 4956 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 4121 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 4676 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 4951 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 4957 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 4957 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 4957 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4957 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 4957 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 1874 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 571 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 97 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 29 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 4956 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 836 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 281 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 7245305500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 9792324250 # Sum of mem lat for all requests
-system.physmem.totBusLat 831555000 # Total cycles spent in databus access
-system.physmem.totBankLat 1715463750 # Total cycles spent in bank access
-system.physmem.avgQLat 43564.80 # Average queueing delay per request
-system.physmem.avgBankLat 10314.79 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 49789 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 360.286489 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 169.159256 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 741.433360 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 20689 41.55% 41.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 7785 15.64% 57.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 4196 8.43% 65.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 3037 6.10% 71.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 2069 4.16% 75.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 1703 3.42% 79.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 1326 2.66% 81.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 1152 2.31% 84.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 751 1.51% 85.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 622 1.25% 87.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 468 0.94% 87.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 538 1.08% 89.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 428 0.86% 89.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 311 0.62% 90.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 271 0.54% 91.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 335 0.67% 91.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 282 0.57% 92.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 173 0.35% 92.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 131 0.26% 92.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 297 0.60% 93.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 411 0.83% 94.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 172 0.35% 94.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1473 311 0.62% 95.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 639 1.28% 96.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 258 0.52% 97.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1665 81 0.16% 97.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1729 48 0.10% 97.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1793 163 0.33% 97.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1857 101 0.20% 97.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1921 35 0.07% 97.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1985 33 0.07% 98.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2049 83 0.17% 98.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2113 54 0.11% 98.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2177 28 0.06% 98.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2241 18 0.04% 98.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2305 37 0.07% 98.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2369 43 0.09% 98.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2433 20 0.04% 98.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2497 23 0.05% 98.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2561 32 0.06% 98.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2625 27 0.05% 98.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2689 20 0.04% 98.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2753 10 0.02% 98.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2817 21 0.04% 98.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2881 11 0.02% 98.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2945 8 0.02% 98.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3009 16 0.03% 98.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3073 24 0.05% 99.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3137 8 0.02% 99.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3201 7 0.01% 99.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3265 10 0.02% 99.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3329 17 0.03% 99.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3393 11 0.02% 99.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3457 7 0.01% 99.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520-3521 4 0.01% 99.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3585 11 0.02% 99.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648-3649 7 0.01% 99.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3713 5 0.01% 99.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776-3777 5 0.01% 99.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840-3841 10 0.02% 99.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904-3905 2 0.00% 99.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3968-3969 5 0.01% 99.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4033 7 0.01% 99.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4096-4097 8 0.02% 99.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4160-4161 7 0.01% 99.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4224-4225 5 0.01% 99.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4288-4289 4 0.01% 99.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4416-4417 7 0.01% 99.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4480-4481 2 0.00% 99.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4608-4609 4 0.01% 99.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4672-4673 8 0.02% 99.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4736-4737 5 0.01% 99.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4800-4801 1 0.00% 99.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4864-4865 2 0.00% 99.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4928-4929 5 0.01% 99.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4992-4993 3 0.01% 99.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5056-5057 2 0.00% 99.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5120-5121 5 0.01% 99.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5184-5185 1 0.00% 99.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5248-5249 4 0.01% 99.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5312-5313 3 0.01% 99.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5376-5377 3 0.01% 99.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5440-5441 3 0.01% 99.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5504-5505 2 0.00% 99.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5568-5569 2 0.00% 99.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5632-5633 3 0.01% 99.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5696-5697 6 0.01% 99.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5760-5761 3 0.01% 99.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5824-5825 3 0.01% 99.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6016-6017 3 0.01% 99.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6080-6081 8 0.02% 99.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6144-6145 2 0.00% 99.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6208-6209 13 0.03% 99.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6272-6273 5 0.01% 99.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6336-6337 3 0.01% 99.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6592-6593 1 0.00% 99.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6656-6657 6 0.01% 99.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6912-6913 2 0.00% 99.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6976-6977 4 0.01% 99.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7104-7105 9 0.02% 99.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7168-7169 11 0.02% 99.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7232-7233 3 0.01% 99.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7296-7297 4 0.01% 99.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7360-7361 5 0.01% 99.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7424-7425 2 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7552-7553 2 0.00% 99.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7616-7617 1 0.00% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7680-7681 2 0.00% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7744-7745 2 0.00% 99.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7808-7809 1 0.00% 99.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8000-8001 4 0.01% 99.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8064-8065 2 0.00% 99.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8128-8129 10 0.02% 99.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 165 0.33% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 49789 # Bytes accessed per row activation
+system.physmem.totQLat 6526905250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 8951626500 # Sum of mem lat for all requests
+system.physmem.totBusLat 831550000 # Total cycles spent in databus access
+system.physmem.totBankLat 1593171250 # Total cycles spent in bank access
+system.physmem.avgQLat 39245.42 # Average queueing delay per request
+system.physmem.avgBankLat 9579.53 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 58879.59 # Average memory access latency
-system.physmem.avgRdBW 444.76 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 304.91 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 444.76 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 304.91 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 53824.94 # Average memory access latency
+system.physmem.avgRdBW 426.73 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 292.53 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 426.73 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 292.53 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 5.86 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.41 # Average read queue length over time
-system.physmem.avgWrQLen 9.84 # Average write queue length over time
-system.physmem.readRowHits 149147 # Number of row buffer hits during reads
-system.physmem.writeRowHits 70867 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 62.16 # Row buffer hit rate for writes
-system.physmem.avgGap 85370.67 # Average gap between requests
-system.cpu.branchPred.lookups 16571170 # Number of BP lookups
-system.cpu.branchPred.condPredicted 10694499 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 427048 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 11996955 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7368452 # Number of BTB hits
+system.physmem.busUtil 5.62 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.36 # Average read queue length over time
+system.physmem.avgWrQLen 10.09 # Average write queue length over time
+system.physmem.readRowHits 154174 # Number of row buffer hits during reads
+system.physmem.writeRowHits 76335 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 92.70 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 66.95 # Row buffer hit rate for writes
+system.physmem.avgGap 88979.16 # Average gap between requests
+system.membus.throughput 719268568 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 35517 # Transaction distribution
+system.membus.trans_dist::ReadResp 35517 # Transaction distribution
+system.membus.trans_dist::Writeback 114010 # Transaction distribution
+system.membus.trans_dist::ReadExReq 130795 # Transaction distribution
+system.membus.trans_dist::ReadExResp 130795 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 446634 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 446634 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17940608 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 17940608 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 17940608 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 1221780000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 4.9 # Layer utilization (%)
+system.membus.respLayer1.occupancy 1527507000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 6.1 # Layer utilization (%)
+system.cpu.branchPred.lookups 16555988 # Number of BP lookups
+system.cpu.branchPred.condPredicted 10692092 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 419935 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 11595461 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7351910 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 61.419352 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1995064 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 41482 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 63.403344 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1990234 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 41425 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 22414538 # DTB read hits
-system.cpu.dtb.read_misses 219003 # DTB read misses
-system.cpu.dtb.read_acv 44 # DTB read access violations
-system.cpu.dtb.read_accesses 22633541 # DTB read accesses
-system.cpu.dtb.write_hits 15711620 # DTB write hits
-system.cpu.dtb.write_misses 41172 # DTB write misses
+system.cpu.dtb.read_hits 22410816 # DTB read hits
+system.cpu.dtb.read_misses 219473 # DTB read misses
+system.cpu.dtb.read_acv 42 # DTB read access violations
+system.cpu.dtb.read_accesses 22630289 # DTB read accesses
+system.cpu.dtb.write_hits 15705108 # DTB write hits
+system.cpu.dtb.write_misses 41065 # DTB write misses
system.cpu.dtb.write_acv 2 # DTB write access violations
-system.cpu.dtb.write_accesses 15752792 # DTB write accesses
-system.cpu.dtb.data_hits 38126158 # DTB hits
-system.cpu.dtb.data_misses 260175 # DTB misses
-system.cpu.dtb.data_acv 46 # DTB access violations
-system.cpu.dtb.data_accesses 38386333 # DTB accesses
-system.cpu.itb.fetch_hits 13959521 # ITB hits
-system.cpu.itb.fetch_misses 35718 # ITB misses
+system.cpu.dtb.write_accesses 15746173 # DTB write accesses
+system.cpu.dtb.data_hits 38115924 # DTB hits
+system.cpu.dtb.data_misses 260538 # DTB misses
+system.cpu.dtb.data_acv 44 # DTB access violations
+system.cpu.dtb.data_accesses 38376462 # DTB accesses
+system.cpu.itb.fetch_hits 13936543 # ITB hits
+system.cpu.itb.fetch_misses 35109 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 13995239 # ITB accesses
+system.cpu.itb.fetch_accesses 13971652 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
-system.cpu.numCycles 47863646 # number of cpu cycles simulated
+system.cpu.numCycles 49885704 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 15840434 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 105551509 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 16571170 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9363516 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 19590320 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2026285 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 6404003 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 7727 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 314524 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 62 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13959521 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 209834 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 43625903 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.419469 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.136822 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 15828757 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 105472202 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 16555988 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9342144 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 19569330 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2015634 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 7564714 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 7815 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 312127 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 89 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 13936543 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 209148 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 44745227 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.357172 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.120107 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 24035583 55.09% 55.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1538195 3.53% 58.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1379254 3.16% 61.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1510848 3.46% 65.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 4145444 9.50% 74.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1853786 4.25% 79.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 680324 1.56% 80.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1070140 2.45% 83.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 7412329 16.99% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 25175897 56.26% 56.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1533640 3.43% 59.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1372500 3.07% 62.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1510966 3.38% 66.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 4145174 9.26% 75.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1852523 4.14% 79.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 674526 1.51% 81.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1069811 2.39% 83.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 7410190 16.56% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 43625903 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.346216 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.205254 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 16922417 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 5946391 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 18583818 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 809277 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1364000 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3756330 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 107588 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 103803150 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 305479 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1364000 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 17385205 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 3661755 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 85469 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18882151 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 2247323 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 102504062 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 474 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 2634 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 2121433 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 61730148 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 123523109 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 123071072 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 452037 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 44745227 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.331878 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.114277 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 16915257 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 7099488 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 18565359 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 807394 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1357729 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3748109 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 107416 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 103728039 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 304294 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1357729 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 17378057 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 4787405 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 84706 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 18857243 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 2280087 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 102449322 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 562 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 2762 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 2150788 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 61699088 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 123470125 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 123020099 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 450026 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 9183267 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 5536 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 5533 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 4628434 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 23258454 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 16285736 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1194307 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 458239 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 90833658 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 5326 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 88506663 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 99992 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 10775029 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 4713260 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 743 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 43625903 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.028764 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.109591 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 9152207 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 5534 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 5532 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 4701242 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 23248702 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 16281518 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1196604 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 458974 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 90797694 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 5272 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 88473068 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 98121 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 10747304 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 4709427 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 689 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 44745227 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.977263 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.106527 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 15319091 35.11% 35.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 6943764 15.92% 51.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 5619916 12.88% 63.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 4753240 10.90% 74.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4687288 10.74% 85.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2648310 6.07% 91.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1927283 4.42% 96.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1307141 3.00% 99.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 419870 0.96% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 16442789 36.75% 36.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 6947095 15.53% 52.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 5617294 12.55% 64.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 4751397 10.62% 75.45% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 4688341 10.48% 85.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2649423 5.92% 91.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1924303 4.30% 96.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1305783 2.92% 99.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 418802 0.94% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 43625903 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 44745227 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 126036 6.75% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 786436 42.09% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 955888 51.16% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 126164 6.77% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 785807 42.18% 48.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 951202 51.05% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 49401565 55.82% 55.82% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 43900 0.05% 55.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 49382358 55.82% 55.82% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 43890 0.05% 55.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.87% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 121291 0.14% 56.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 56.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 121091 0.14% 56.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 53 0.00% 56.14% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 38958 0.04% 56.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 121219 0.14% 56.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 121003 0.14% 56.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.14% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 38951 0.04% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.18% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 22873159 25.84% 82.03% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 15906558 17.97% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 22865563 25.84% 82.03% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 15899938 17.97% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 88506663 # Type of FU issued
-system.cpu.iq.rate 1.849142 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1868360 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.021110 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 222003769 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 101216135 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 86588999 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 603812 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 415953 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 294156 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 90073048 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 301975 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1468681 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 88473068 # Type of FU issued
+system.cpu.iq.rate 1.773515 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1863173 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.021059 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 223048793 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 101154216 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 86567905 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 603864 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 414189 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 294216 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 90034241 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 302000 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1467603 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 2981816 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 4834 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 18324 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1672359 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 2972064 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 5071 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 18375 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1668141 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2816 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 91767 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2922 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 100269 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1364000 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 2689383 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 74209 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 100326423 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 230599 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 23258454 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 16285736 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 5326 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 60174 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 487 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 18324 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 205931 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 161115 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 367046 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 87639637 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 22636834 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 867026 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1357729 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 3744152 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 78814 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 100285943 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 219681 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 23248702 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 16281518 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 5272 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 60147 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 593 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 18375 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 199378 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 160408 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 359786 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 87617560 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 22633363 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 855508 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 9487439 # number of nop insts executed
-system.cpu.iew.exec_refs 38389952 # number of memory reference insts executed
-system.cpu.iew.exec_branches 15091410 # Number of branches executed
-system.cpu.iew.exec_stores 15753118 # Number of stores executed
-system.cpu.iew.exec_rate 1.831027 # Inst execution rate
-system.cpu.iew.wb_sent 87274889 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 86883155 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 33355142 # num instructions producing a value
-system.cpu.iew.wb_consumers 43763107 # num instructions consuming a value
+system.cpu.iew.exec_nop 9482977 # number of nop insts executed
+system.cpu.iew.exec_refs 38379854 # number of memory reference insts executed
+system.cpu.iew.exec_branches 15087965 # Number of branches executed
+system.cpu.iew.exec_stores 15746491 # Number of stores executed
+system.cpu.iew.exec_rate 1.756366 # Inst execution rate
+system.cpu.iew.wb_sent 87252732 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 86862121 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 33357056 # num instructions producing a value
+system.cpu.iew.wb_consumers 43763173 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.815222 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.762175 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.741223 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.762217 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 8976597 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 8947131 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 322215 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 42261903 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.090315 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.803165 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 315269 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 43387498 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.036086 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.786442 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 19374336 45.84% 45.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 7031479 16.64% 62.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3426891 8.11% 70.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2063946 4.88% 75.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2064090 4.88% 80.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1160431 2.75% 83.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1098411 2.60% 85.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 723960 1.71% 87.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5318359 12.58% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 20491808 47.23% 47.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 7040185 16.23% 63.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3430647 7.91% 71.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2065344 4.76% 76.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2060078 4.75% 80.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1160326 2.67% 83.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1096269 2.53% 86.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 719123 1.66% 87.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5323718 12.27% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 42261903 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 43387498 # Number of insts commited each cycle
system.cpu.commit.committedInsts 88340672 # Number of instructions committed
system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions.
system.cpu.commit.int_insts 77942044 # Number of committed integer instructions.
system.cpu.commit.function_calls 1661057 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5318359 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 5323718 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 132943471 # The number of ROB reads
-system.cpu.rob.rob_writes 196001226 # The number of ROB writes
-system.cpu.timesIdled 70501 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 4237743 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 134034241 # The number of ROB reads
+system.cpu.rob.rob_writes 195936054 # The number of ROB writes
+system.cpu.timesIdled 84426 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 5140477 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
-system.cpu.cpi 0.601364 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.601364 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.662885 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.662885 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 115989230 # number of integer regfile reads
-system.cpu.int_regfile_writes 57546941 # number of integer regfile writes
-system.cpu.fp_regfile_reads 249538 # number of floating regfile reads
-system.cpu.fp_regfile_writes 239891 # number of floating regfile writes
-system.cpu.misc_regfile_reads 38020 # number of misc regfile reads
+system.cpu.cpi 0.626770 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.626770 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.595482 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.595482 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 115957750 # number of integer regfile reads
+system.cpu.int_regfile_writes 57532597 # number of integer regfile writes
+system.cpu.fp_regfile_reads 249573 # number of floating regfile reads
+system.cpu.fp_regfile_writes 239887 # number of floating regfile writes
+system.cpu.misc_regfile_reads 38017 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.icache.replacements 91116 # number of replacements
-system.cpu.icache.tagsinuse 1928.908016 # Cycle average of tags in use
-system.cpu.icache.total_refs 13854125 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 93164 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 148.706850 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 19689670000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1928.908016 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.941850 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.941850 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 13854125 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 13854125 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 13854125 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 13854125 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 13854125 # number of overall hits
-system.cpu.icache.overall_hits::total 13854125 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 105395 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 105395 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 105395 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 105395 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 105395 # number of overall misses
-system.cpu.icache.overall_misses::total 105395 # number of overall misses
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-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071120 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.071120 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.036784 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.036784 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.036784 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.036784 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45045.363530 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 45045.363530 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76081.403874 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 76081.403874 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 69734.348986 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 69734.348986 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 69734.348986 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 69734.348986 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 4381626 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 119 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 112316 # number of cycles access was blocked
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 57 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 57 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 35510616 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 35510616 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 35510616 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 35510616 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012772 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.012772 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071119 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.071119 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.036783 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.036783 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.036783 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.036783 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58582.685441 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 58582.685441 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 86560.535625 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 86560.535625 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 80843.833387 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 80843.833387 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 80843.833387 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 80843.833387 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 5220473 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 159 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 112927 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.011592 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 119 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.228741 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 159 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 168939 # number of writebacks
-system.cpu.dcache.writebacks::total 168939 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 205002 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 205002 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895906 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 895906 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1100908 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1100908 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1100908 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1100908 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62184 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 62184 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143403 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 143403 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 205587 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 205587 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 205587 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 205587 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2020761500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2020761500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12440224991 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 12440224991 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14460986491 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 14460986491 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14460986491 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 14460986491 # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks 168941 # number of writebacks
+system.cpu.dcache.writebacks::total 168941 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 204728 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 204728 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 895877 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 895877 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1100605 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1100605 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1100605 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1100605 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62163 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 62163 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143411 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 143411 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 205574 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 205574 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 205574 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 205574 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2517427002 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2517427002 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14256184493 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 14256184493 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16773611495 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 16773611495 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16773611495 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 16773611495 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002975 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002975 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005788 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.005788 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005788 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.005788 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32496.486234 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 32496.486234 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86750.102794 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86750.102794 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70339.984975 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 70339.984975 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70339.984975 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 70339.984975 # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009814 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009814 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.005789 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005789 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.005789 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40497.192896 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40497.192896 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99407.887073 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99407.887073 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81594.031808 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 81594.031808 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81594.031808 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 81594.031808 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 44221003000 # Number of ticks simulated
final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2426632 # Simulator instruction rate (inst/s)
-host_op_rate 2426631 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1214706702 # Simulator tick rate (ticks/s)
-host_mem_usage 272072 # Number of bytes of host memory used
-host_seconds 36.40 # Real time elapsed on the host
+host_inst_rate 2564036 # Simulator instruction rate (inst/s)
+host_op_rate 2564035 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1283487470 # Simulator tick rate (ticks/s)
+host_mem_usage 224620 # Number of bytes of host memory used
+host_seconds 34.45 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 12937468537 # Throughput (bytes/s)
+system.membus.data_through_bus 572107835 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
sim_ticks 133634727000 # Number of ticks simulated
final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 996502 # Simulator instruction rate (inst/s)
-host_op_rate 996501 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1507427540 # Simulator tick rate (ticks/s)
-host_mem_usage 280652 # Number of bytes of host memory used
-host_seconds 88.65 # Real time elapsed on the host
+host_inst_rate 671194 # Simulator instruction rate (inst/s)
+host_op_rate 671194 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1015328507 # Simulator tick rate (ticks/s)
+host_mem_usage 233108 # Number of bytes of host memory used
+host_seconds 131.62 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 432896 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 3239397 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 75855253 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 133682617 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 133682617 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 34272 # Transaction distribution
+system.membus.trans_dist::ReadResp 34272 # Transaction distribution
+system.membus.trans_dist::Writeback 113982 # Transaction distribution
+system.membus.trans_dist::ReadExReq 130881 # Transaction distribution
+system.membus.trans_dist::ReadExResp 130881 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 444288 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 444288 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17864640 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 17864640 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 17864640 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 1190991000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
+system.membus.respLayer1.occupancy 1486377000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 215108158 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 137202 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 152872 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 577063 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 729935 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 4891904 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 23854016 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 28745920 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 28745920 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 392952500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.025535 # Number of seconds simulated
-sim_ticks 25534556000 # Number of ticks simulated
-final_tick 25534556000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.026649 # Number of seconds simulated
+sim_ticks 26649062500 # Number of ticks simulated
+final_tick 26649062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 124211 # Simulator instruction rate (inst/s)
-host_op_rate 176271 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 44729688 # Simulator tick rate (ticks/s)
-host_mem_usage 254184 # Number of bytes of host memory used
-host_seconds 570.86 # Real time elapsed on the host
+host_inst_rate 95593 # Simulator instruction rate (inst/s)
+host_op_rate 135659 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 35926621 # Simulator tick rate (ticks/s)
+host_mem_usage 255136 # Number of bytes of host memory used
+host_seconds 741.76 # Real time elapsed on the host
sim_insts 70907629 # Number of instructions simulated
sim_ops 100626876 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 297536 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 7943488 # Number of bytes read from this memory
-system.physmem.bytes_read::total 8241024 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 297536 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 297536 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 5372480 # Number of bytes written to this memory
-system.physmem.bytes_written::total 5372480 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 4649 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 124117 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 128766 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 83945 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 83945 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 11652288 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 311087767 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 322740055 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 11652288 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 11652288 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 210400369 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 210400369 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 210400369 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 11652288 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 311087767 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 533140424 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 128767 # Total number of read requests seen
-system.physmem.writeReqs 83945 # Total number of write requests seen
-system.physmem.cpureqs 213037 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 8241024 # Total number of bytes read from memory
-system.physmem.bytesWritten 5372480 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 8241024 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 5372480 # bytesWritten derated as per pkt->getSize()
+system.physmem.bytes_read::cpu.inst 298304 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 7942464 # Number of bytes read from this memory
+system.physmem.bytes_read::total 8240768 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 298304 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 298304 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 5372800 # Number of bytes written to this memory
+system.physmem.bytes_written::total 5372800 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 4661 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 124101 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 128762 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 83950 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 83950 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 11193790 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 298039152 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 309232942 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 11193790 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 11193790 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 201613096 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 201613096 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 201613096 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 11193790 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 298039152 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 510846038 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 128763 # Total number of read requests seen
+system.physmem.writeReqs 83950 # Total number of write requests seen
+system.physmem.cpureqs 213025 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 8240768 # Total number of bytes read from memory
+system.physmem.bytesWritten 5372800 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 8240768 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 5372800 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 325 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 7974 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 8181 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 8060 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 8163 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 8166 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 8116 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 8007 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 8045 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 8002 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 7985 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 7994 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 8125 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 8030 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 7980 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 7988 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 7949 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 5143 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 5260 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 5208 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 5207 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 5324 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 5374 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 5324 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 5328 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 5262 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 5276 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 5312 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 5351 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 5167 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 5124 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 5132 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 5153 # Track writes on a per bank basis
+system.physmem.neitherReadNorWrite 312 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 8141 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 8383 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 8250 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 8168 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 8300 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 8450 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 8090 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 7962 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 8062 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 7609 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 7789 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 7813 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 7880 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 7885 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 7974 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 8005 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 5180 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 5377 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 5289 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 5158 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 5268 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 5519 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 5208 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 5049 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 5031 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::10 5253 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::12 5343 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 5363 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 5451 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 5227 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 25534539500 # Total gap between requests
+system.physmem.totGap 26649044000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 128767 # Categorize read packet sizes
+system.physmem.readPktSize::6 128763 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 83945 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 70152 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 56460 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 2075 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 83950 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 75538 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 51656 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 1500 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 3544 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 3638 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 3572 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 106 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 12 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 3650 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 3650 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 3650 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 3650 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 3650 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 78 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3209361000 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 5253486000 # Sum of mem lat for all requests
-system.physmem.totBusLat 643825000 # Total cycles spent in databus access
-system.physmem.totBankLat 1400300000 # Total cycles spent in bank access
-system.physmem.avgQLat 24924.17 # Average queueing delay per request
-system.physmem.avgBankLat 10874.85 # Average bank access latency per request
-system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 40799.02 # Average memory access latency
-system.physmem.avgRdBW 322.74 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 210.40 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 322.74 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 210.40 # Average consumed write bandwidth in MB/s
+system.physmem.bytesPerActivate::samples 34891 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 390.104497 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 179.978164 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 858.430673 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 13421 38.47% 38.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 5383 15.43% 53.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 3065 8.78% 62.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 2226 6.38% 69.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 1625 4.66% 73.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 1388 3.98% 77.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 1071 3.07% 80.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 870 2.49% 83.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 590 1.69% 84.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 488 1.40% 86.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 448 1.28% 87.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 588 1.69% 89.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 296 0.85% 90.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 306 0.88% 91.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 186 0.53% 91.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 205 0.59% 92.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 126 0.36% 92.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 210 0.60% 93.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 103 0.30% 93.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 233 0.67% 94.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 114 0.33% 94.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 336 0.96% 95.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1473 140 0.40% 95.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 305 0.87% 96.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 63 0.18% 96.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1665 139 0.40% 97.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1729 46 0.13% 97.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1793 83 0.24% 97.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1857 24 0.07% 97.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1921 56 0.16% 97.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1985 22 0.06% 97.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2049 58 0.17% 98.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2113 11 0.03% 98.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2177 27 0.08% 98.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2241 19 0.05% 98.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2305 23 0.07% 98.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2369 10 0.03% 98.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2433 17 0.05% 98.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2497 8 0.02% 98.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2561 14 0.04% 98.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2625 16 0.05% 98.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2689 16 0.05% 98.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2753 9 0.03% 98.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2817 15 0.04% 98.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2881 9 0.03% 98.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2945 7 0.02% 98.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3009 7 0.02% 98.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3073 12 0.03% 98.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3137 4 0.01% 98.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3201 11 0.03% 98.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3265 7 0.02% 98.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3329 7 0.02% 98.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3393 3 0.01% 98.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3457 9 0.03% 98.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520-3521 3 0.01% 98.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3585 7 0.02% 98.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648-3649 3 0.01% 98.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3713 3 0.01% 98.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776-3777 2 0.01% 98.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840-3841 7 0.02% 98.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904-3905 2 0.01% 98.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3968-3969 5 0.01% 98.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4033 2 0.01% 98.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4096-4097 4 0.01% 98.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4160-4161 1 0.00% 98.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4224-4225 3 0.01% 98.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4288-4289 2 0.01% 98.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4352-4353 7 0.02% 98.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4416-4417 2 0.01% 98.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4480-4481 4 0.01% 98.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4544-4545 1 0.00% 98.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4608-4609 3 0.01% 98.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4672-4673 1 0.00% 98.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4736-4737 3 0.01% 98.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4864-4865 4 0.01% 99.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4992-4993 4 0.01% 99.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5056-5057 1 0.00% 99.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5184-5185 4 0.01% 99.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5248-5249 2 0.01% 99.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5312-5313 2 0.01% 99.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5376-5377 4 0.01% 99.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5568-5569 7 0.02% 99.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5696-5697 2 0.01% 99.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5760-5761 2 0.01% 99.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6016-6017 2 0.01% 99.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6080-6081 1 0.00% 99.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6144-6145 3 0.01% 99.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6272-6273 2 0.01% 99.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6336-6337 2 0.01% 99.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6400-6401 3 0.01% 99.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6464-6465 3 0.01% 99.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6528-6529 3 0.01% 99.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6592-6593 3 0.01% 99.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6656-6657 3 0.01% 99.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6784-6785 2 0.01% 99.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6912-6913 2 0.01% 99.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6976-6977 2 0.01% 99.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7296-7297 2 0.01% 99.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7488-7489 3 0.01% 99.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7552-7553 2 0.01% 99.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7616-7617 4 0.01% 99.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7808-7809 2 0.01% 99.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7872-7873 2 0.01% 99.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7936-7937 2 0.01% 99.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8128-8129 3 0.01% 99.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 238 0.68% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 34891 # Bytes accessed per row activation
+system.physmem.totQLat 2799338750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 4801886250 # Sum of mem lat for all requests
+system.physmem.totBusLat 643800000 # Total cycles spent in databus access
+system.physmem.totBankLat 1358747500 # Total cycles spent in bank access
+system.physmem.avgQLat 21740.58 # Average queueing delay per request
+system.physmem.avgBankLat 10552.48 # Average bank access latency per request
+system.physmem.avgBusLat 4999.96 # Average bus latency per request
+system.physmem.avgMemAccLat 37293.02 # Average memory access latency
+system.physmem.avgRdBW 309.23 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 201.61 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 309.23 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 201.61 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 4.17 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.21 # Average read queue length over time
-system.physmem.avgWrQLen 9.90 # Average write queue length over time
-system.physmem.readRowHits 116738 # Number of row buffer hits during reads
-system.physmem.writeRowHits 52892 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 90.66 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 63.01 # Row buffer hit rate for writes
-system.physmem.avgGap 120042.78 # Average gap between requests
-system.cpu.branchPred.lookups 16612549 # Number of BP lookups
-system.cpu.branchPred.condPredicted 12751503 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 599939 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 10534593 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7757405 # Number of BTB hits
+system.physmem.busUtil 3.99 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.18 # Average read queue length over time
+system.physmem.avgWrQLen 10.01 # Average write queue length over time
+system.physmem.readRowHits 120254 # Number of row buffer hits during reads
+system.physmem.writeRowHits 57565 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 93.39 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 68.57 # Row buffer hit rate for writes
+system.physmem.avgGap 125281.69 # Average gap between requests
+system.membus.throughput 510846038 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 26509 # Transaction distribution
+system.membus.trans_dist::ReadResp 26508 # Transaction distribution
+system.membus.trans_dist::Writeback 83950 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 312 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 312 # Transaction distribution
+system.membus.trans_dist::ReadExReq 102254 # Transaction distribution
+system.membus.trans_dist::ReadExResp 102254 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 342099 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 342099 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13613568 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 13613568 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 13613568 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 926784500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 3.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 1200135938 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 4.5 # Layer utilization (%)
+system.cpu.branchPred.lookups 16620839 # Number of BP lookups
+system.cpu.branchPred.condPredicted 12757336 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 602395 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 10635009 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7765773 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 73.637444 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1822464 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 113740 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 73.020841 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1824331 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 113161 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1946 # Number of system calls
-system.cpu.numCycles 51069113 # number of cpu cycles simulated
+system.cpu.numCycles 53298126 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 12514697 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 85141272 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 16612549 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9579869 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 21174766 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2353264 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 10532727 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 68 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 498 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 11663165 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 178973 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 45949088 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.594403 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.336122 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 12535190 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 85154971 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 16620839 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9590104 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 21184086 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2355794 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 10829442 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 84 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 551 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 11674707 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 181091 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 46276167 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.576733 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.331391 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 24794811 53.96% 53.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2137100 4.65% 58.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1960912 4.27% 62.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2040333 4.44% 67.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1467005 3.19% 70.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1375299 2.99% 73.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 957293 2.08% 75.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1188429 2.59% 78.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 10027906 21.82% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 25111993 54.27% 54.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2139332 4.62% 58.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1963886 4.24% 63.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2043329 4.42% 67.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1467358 3.17% 70.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1375070 2.97% 73.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 956833 2.07% 75.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1188482 2.57% 78.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 10029884 21.67% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 45949088 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.325295 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.667177 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 14598304 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 8880725 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19456140 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1390682 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1623237 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 3327841 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 105063 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 116768795 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 361627 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1623237 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 16304724 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 2541710 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 873068 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 19090805 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5515544 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 114897326 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 145 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 17204 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4661371 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 307 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 115217977 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 529361609 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 529355204 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 6405 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 46276167 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.311847 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.597710 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 14619512 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 9177970 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 19466340 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1388431 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1623914 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 3328977 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 104776 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 116789336 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 361687 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1623914 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 16330804 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 2680643 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 1000847 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 19093672 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 5546287 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 114905556 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 219 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 17136 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4693151 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 1312 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 115218637 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 529387920 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 529379803 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 8117 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 16085305 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 20097 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 20095 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13032825 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 29592002 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 22430174 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 3871274 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 4372916 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 111465960 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 35763 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 107205680 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 272682 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 10729594 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 25689497 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1977 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 45949088 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.333141 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.988541 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 16085965 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 20302 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 20297 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 13065620 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 29609265 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 22417131 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 3885027 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 4397806 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 111472584 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 35916 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 107208843 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 271699 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 10738438 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 25737967 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 2130 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 46276167 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.316718 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.989507 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10727082 23.35% 23.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 8071187 17.57% 40.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7423916 16.16% 57.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7121409 15.50% 72.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 5405071 11.76% 84.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3914661 8.52% 92.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1842461 4.01% 96.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 872329 1.90% 98.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 570972 1.24% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 11020528 23.81% 23.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 8094858 17.49% 41.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7429249 16.05% 57.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7154901 15.46% 72.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 5386733 11.64% 84.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 3906460 8.44% 92.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1842144 3.98% 96.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 871664 1.88% 98.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 569630 1.23% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 45949088 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 46276167 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 112030 4.53% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1365113 55.14% 59.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 998480 40.33% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 112593 4.57% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1348878 54.73% 59.30% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 1003122 40.70% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 56613296 52.81% 52.81% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 91558 0.09% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 56608598 52.80% 52.80% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 91438 0.09% 52.89% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 214 0.00% 52.89% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 251 0.00% 52.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 28880685 26.94% 79.83% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 21619920 20.17% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 28894537 26.95% 79.84% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 21614012 20.16% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 107205680 # Type of FU issued
-system.cpu.iq.rate 2.099227 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2475625 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.023092 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 263108167 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 122259769 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 105531182 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 588 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 948 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 171 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 109681012 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 293 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 2183832 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 107208843 # Type of FU issued
+system.cpu.iq.rate 2.011494 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2464595 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.022989 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 263429476 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 122274650 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 105524045 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 671 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1168 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 196 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 109673111 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 327 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 2189921 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 2284894 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6284 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 30581 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1874436 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 2302157 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6684 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 29801 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1861393 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 30 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 495 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 27 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 724 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1623237 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1048241 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 45255 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 111511491 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 294294 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 29592002 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 22430174 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 19843 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 6298 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 5233 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30581 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 389128 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 180293 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 569421 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 106181674 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 28584421 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1024006 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1623914 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1145014 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 48197 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 111518283 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 295309 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 29609265 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 22417131 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 19996 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 6449 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 5406 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 29801 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 392238 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 181031 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 573269 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 106181942 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 28595303 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1026901 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 9768 # number of nop insts executed
-system.cpu.iew.exec_refs 49919693 # number of memory reference insts executed
-system.cpu.iew.exec_branches 14596236 # Number of branches executed
-system.cpu.iew.exec_stores 21335272 # Number of stores executed
-system.cpu.iew.exec_rate 2.079176 # Inst execution rate
-system.cpu.iew.wb_sent 105750982 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 105531353 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 53247115 # num instructions producing a value
-system.cpu.iew.wb_consumers 103478594 # num instructions consuming a value
+system.cpu.iew.exec_nop 9783 # number of nop insts executed
+system.cpu.iew.exec_refs 49924361 # number of memory reference insts executed
+system.cpu.iew.exec_branches 14597950 # Number of branches executed
+system.cpu.iew.exec_stores 21329058 # Number of stores executed
+system.cpu.iew.exec_rate 1.992227 # Inst execution rate
+system.cpu.iew.wb_sent 105744224 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 105524241 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 53247487 # num instructions producing a value
+system.cpu.iew.wb_consumers 103444790 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.066442 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.514571 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.979887 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.514743 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 10879947 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 10886753 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 496884 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 44325851 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.270288 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.765576 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 499558 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 44652253 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.253692 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.763005 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 15270109 34.45% 34.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11622339 26.22% 60.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3461273 7.81% 68.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2876315 6.49% 74.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1875935 4.23% 79.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1955485 4.41% 83.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 687541 1.55% 85.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 562645 1.27% 86.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 6014209 13.57% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 15559873 34.85% 34.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11688259 26.18% 61.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3454288 7.74% 68.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2872185 6.43% 75.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1868727 4.19% 79.38% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1932277 4.33% 83.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 683931 1.53% 85.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 562545 1.26% 86.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 6030168 13.50% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 44325851 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 44652253 # Number of insts commited each cycle
system.cpu.commit.committedInsts 70913181 # Number of instructions committed
system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
system.cpu.commit.int_insts 91472779 # Number of committed integer instructions.
system.cpu.commit.function_calls 1679850 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 6014209 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 6030168 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 149798718 # The number of ROB reads
-system.cpu.rob.rob_writes 224657070 # The number of ROB writes
-system.cpu.timesIdled 74104 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 5120025 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 150115967 # The number of ROB reads
+system.cpu.rob.rob_writes 224671489 # The number of ROB writes
+system.cpu.timesIdled 79206 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 7021959 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 70907629 # Number of Instructions Simulated
system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated
-system.cpu.cpi 0.720220 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.720220 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.388464 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.388464 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 511419502 # number of integer regfile reads
-system.cpu.int_regfile_writes 103305182 # number of integer regfile writes
-system.cpu.fp_regfile_reads 846 # number of floating regfile reads
-system.cpu.fp_regfile_writes 738 # number of floating regfile writes
-system.cpu.misc_regfile_reads 49163804 # number of misc regfile reads
+system.cpu.cpi 0.751656 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.751656 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.330396 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.330396 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 511415343 # number of integer regfile reads
+system.cpu.int_regfile_writes 103300902 # number of integer regfile writes
+system.cpu.fp_regfile_reads 1012 # number of floating regfile reads
+system.cpu.fp_regfile_writes 876 # number of floating regfile writes
+system.cpu.misc_regfile_reads 49160884 # number of misc regfile reads
system.cpu.misc_regfile_writes 31840 # number of misc regfile writes
-system.cpu.icache.replacements 28595 # number of replacements
-system.cpu.icache.tagsinuse 1814.564534 # Cycle average of tags in use
-system.cpu.icache.total_refs 11628419 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 30629 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 379.653890 # Average number of references to valid blocks.
+system.cpu.toL2Bus.throughput 776266857 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 87116 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 87115 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 129077 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 326 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 326 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 107039 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 107039 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 62962 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 454559 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 517521 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1998208 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 18655488 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 20653696 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 20653696 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 33088 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 290859995 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 47617981 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 243817935 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
+system.cpu.icache.replacements 29381 # number of replacements
+system.cpu.icache.tagsinuse 1810.408207 # Cycle average of tags in use
+system.cpu.icache.total_refs 11639182 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 31418 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 370.462219 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1814.564534 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.886018 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.886018 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 11628429 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 11628429 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 11628429 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 11628429 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 11628429 # number of overall hits
-system.cpu.icache.overall_hits::total 11628429 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 34736 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 34736 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 34736 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 34736 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 34736 # number of overall misses
-system.cpu.icache.overall_misses::total 34736 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 739850999 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 739850999 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 739850999 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 739850999 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 739850999 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 739850999 # number of overall miss cycles
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-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 860000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 860000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 102647823481 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 102647823481 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 102647823481 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 102647823481 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 26169985 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 26169985 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_hits::cpu.data 44315241 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 44315241 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 44315241 # number of overall hits
+system.cpu.dcache.overall_hits::total 44315241 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 125407 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 125407 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1583213 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1583213 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 44 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 44 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 1708620 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1708620 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1708620 # number of overall misses
+system.cpu.dcache.overall_misses::total 1708620 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 5134620500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 5134620500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 123147327479 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 123147327479 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 951500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 951500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 128281947979 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 128281947979 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 128281947979 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 128281947979 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 26173960 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 26173960 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16027 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 16027 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16024 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 16024 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 46019886 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 46019886 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 46019886 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 46019886 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079741 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.079741 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002621 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002621 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.037104 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.037104 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.037104 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.037104 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34145.285743 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 34145.285743 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62160.665018 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 62160.665018 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20476.190476 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20476.190476 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 60115.116289 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 60115.116289 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 60115.116289 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 60115.116289 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 3743 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 661 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 131 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.572519 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 44.066667 # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 46023861 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 46023861 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 46023861 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 46023861 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004791 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.004791 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079759 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.079759 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002746 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002746 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.037125 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.037125 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.037125 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.037125 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40943.651471 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 40943.651471 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77783.170981 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 77783.170981 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21625 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21625 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 75079.273319 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 75079.273319 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 75079.273319 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 75079.273319 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 5184 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 1288 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 145 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.751724 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 80.500000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 129075 # number of writebacks
-system.cpu.dcache.writebacks::total 129075 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69278 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 69278 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475504 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1475504 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 42 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 42 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1544782 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1544782 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1544782 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1544782 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55397 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 55397 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107342 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 107342 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 162739 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 162739 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 162739 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 162739 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878555500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878555500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6809217490 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 6809217490 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8687772990 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 8687772990 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8687772990 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 8687772990 # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks 129077 # number of writebacks
+system.cpu.dcache.writebacks::total 129077 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69998 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 69998 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475881 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1475881 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 44 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 44 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1545879 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1545879 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1545879 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1545879 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55409 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 55409 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107332 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 107332 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 162741 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 162741 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 162741 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 162741 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2243387065 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2243387065 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8465944990 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8465944990 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10709332055 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10709332055 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10709332055 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10709332055 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33910.780367 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33910.780367 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63434.792439 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63434.792439 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53384.701823 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53384.701823 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53384.701823 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53384.701823 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40487.773918 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40487.773918 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78876.243711 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78876.243711 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65805.986537 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 65805.986537 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65805.986537 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 65805.986537 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 53932157000 # Number of ticks simulated
final_tick 53932157000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1242714 # Simulator instruction rate (inst/s)
-host_op_rate 1763527 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 945130731 # Simulator tick rate (ticks/s)
-host_mem_usage 286616 # Number of bytes of host memory used
-host_seconds 57.06 # Real time elapsed on the host
+host_inst_rate 2080365 # Simulator instruction rate (inst/s)
+host_op_rate 2952231 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1582195312 # Simulator tick rate (ticks/s)
+host_mem_usage 241268 # Number of bytes of host memory used
+host_seconds 34.09 # Real time elapsed on the host
sim_insts 70913181 # Number of instructions simulated
sim_ops 100632428 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 312580272 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 5795805126 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3434566060 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9230371187 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 9230371187 # Throughput (bytes/s)
+system.membus.data_through_bus 497813828 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
sim_ticks 132689045000 # Number of ticks simulated
final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 652363 # Simulator instruction rate (inst/s)
-host_op_rate 925068 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1230026759 # Simulator tick rate (ticks/s)
-host_mem_usage 295072 # Number of bytes of host memory used
-host_seconds 107.88 # Real time elapsed on the host
+host_inst_rate 438025 # Simulator instruction rate (inst/s)
+host_op_rate 621131 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 825892843 # Simulator tick rate (ticks/s)
+host_mem_usage 249772 # Number of bytes of host memory used
+host_seconds 160.66 # Real time elapsed on the host
sim_insts 70373628 # Number of instructions simulated
sim_ops 99791654 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 1925464 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 59722187 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 102119538 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 102119538 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 25532 # Transaction distribution
+system.membus.trans_dist::ReadResp 25532 # Transaction distribution
+system.membus.trans_dist::Writeback 83909 # Transaction distribution
+system.membus.trans_dist::ReadExReq 102280 # Transaction distribution
+system.membus.trans_dist::ReadExResp 102280 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 339533 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 339533 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13550144 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 13550144 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 13550144 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 882993000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
+system.membus.respLayer1.occupancy 1150308000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 148145463 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 37816 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 448235 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 486051 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1210112 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 18447168 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 19657280 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 19657280 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
---------- End Simulation Statistics ----------
sim_ticks 68148672000 # Number of ticks simulated
final_tick 68148672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2091817 # Simulator instruction rate (inst/s)
-host_op_rate 2118902 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1060681468 # Simulator tick rate (ticks/s)
-host_mem_usage 281256 # Number of bytes of host memory used
-host_seconds 64.25 # Real time elapsed on the host
+host_inst_rate 2813738 # Simulator instruction rate (inst/s)
+host_op_rate 2850169 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1426739476 # Simulator tick rate (ticks/s)
+host_mem_usage 233072 # Number of bytes of host memory used
+host_seconds 47.77 # Real time elapsed on the host
sim_insts 134398962 # Number of instructions simulated
sim_ops 136139190 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 538214280 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7897648835 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3484181027 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11381829862 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 11383698247 # Throughput (bytes/s)
+system.membus.data_through_bus 775783918 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 136297345 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
sim_ticks 202242260000 # Number of ticks simulated
final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1033030 # Simulator instruction rate (inst/s)
-host_op_rate 1046406 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1554493166 # Simulator tick rate (ticks/s)
-host_mem_usage 289840 # Number of bytes of host memory used
-host_seconds 130.10 # Real time elapsed on the host
+host_inst_rate 840510 # Simulator instruction rate (inst/s)
+host_op_rate 851393 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1264790801 # Simulator tick rate (ticks/s)
+host_mem_usage 241580 # Number of bytes of host memory used
+host_seconds 159.90 # Real time elapsed on the host
sim_insts 134398962 # Number of instructions simulated
sim_ops 136139190 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 591488 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 2924651 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 38699251 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 67847660 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 67847660 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 30277 # Transaction distribution
+system.membus.trans_dist::ReadResp 30277 # Transaction distribution
+system.membus.trans_dist::Writeback 82868 # Transaction distribution
+system.membus.trans_dist::ReadExReq 101256 # Transaction distribution
+system.membus.trans_dist::ReadExResp 101256 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 345934 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 345934 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13721664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 13721664 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 13721664 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 877345000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
+system.membus.respLayer1.occupancy 1183797000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
system.cpu.workload.num_syscalls 1946 # Number of system calls
system.cpu.numCycles 404484520 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 146097102 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 232523 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 123970 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 374048 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 425326 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 799374 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 11969536 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 17577472 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 29547008 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 29547008 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 354806000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 226017000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.993430 # Number of seconds simulated
-sim_ticks 993429839500 # Number of ticks simulated
-final_tick 993429839500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.015958 # Number of seconds simulated
+sim_ticks 1015958135500 # Number of ticks simulated
+final_tick 1015958135500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 61068 # Simulator instruction rate (inst/s)
-host_op_rate 61068 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 33337374 # Simulator tick rate (ticks/s)
-host_mem_usage 271484 # Number of bytes of host memory used
-host_seconds 29799.28 # Real time elapsed on the host
+host_inst_rate 102863 # Simulator instruction rate (inst/s)
+host_op_rate 102863 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 57427110 # Simulator tick rate (ticks/s)
+host_mem_usage 225152 # Number of bytes of host memory used
+host_seconds 17691.26 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 125365056 # Number of bytes read from this memory
-system.physmem.bytes_read::total 125420032 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 125365184 # Number of bytes read from this memory
+system.physmem.bytes_read::total 125420160 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 65155584 # Number of bytes written to this memory
-system.physmem.bytes_written::total 65155584 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 65155712 # Number of bytes written to this memory
+system.physmem.bytes_written::total 65155712 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1958829 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1959688 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1018056 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1018056 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 55340 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 126194172 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 126249512 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 55340 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 55340 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 65586498 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 65586498 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 65586498 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 55340 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 126194172 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 191836009 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1959688 # Total number of read requests seen
-system.physmem.writeReqs 1018056 # Total number of write requests seen
-system.physmem.cpureqs 2977747 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 125420032 # Total number of bytes read from memory
-system.physmem.bytesWritten 65155584 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 125420032 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 65155584 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 583 # Number of read reqs serviced by write Q
+system.physmem.num_reads::cpu.data 1958831 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1959690 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1018058 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1018058 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 54112 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 123396014 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 123450126 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 54112 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 54112 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 64132280 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 64132280 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 64132280 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 54112 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 123396014 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 187582407 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1959690 # Total number of read requests seen
+system.physmem.writeReqs 1018058 # Total number of write requests seen
+system.physmem.cpureqs 2977748 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 125420160 # Total number of bytes read from memory
+system.physmem.bytesWritten 65155712 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 125420160 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 65155712 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 578 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 122178 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 121799 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 121645 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 123762 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 123293 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 122178 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 120330 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 121053 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 121197 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 121887 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 121114 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 123048 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 125176 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 123788 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 122723 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 123934 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 63389 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 62256 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 62952 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 63764 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 64028 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 63763 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 63369 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 63367 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 63391 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 63723 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 63292 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 64137 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 64555 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 64147 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 63646 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 64277 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::0 118716 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 114074 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 116204 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 117698 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 117773 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 117508 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 119859 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 124486 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 126960 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 130063 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 128617 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 130264 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 125937 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 125207 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 122563 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 123183 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 61224 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 61467 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 60558 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 61216 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 61647 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 63085 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 64137 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 65614 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 65334 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 65770 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 65297 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 65611 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 64156 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 64203 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 64552 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 64187 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 3 # Number of times wr buffer was full causing retry
-system.physmem.totGap 993429787500 # Total gap between requests
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1015958077500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 1959688 # Categorize read packet sizes
+system.physmem.readPktSize::6 1959690 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 1018056 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 1630073 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 205372 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 87756 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 35903 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1018058 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 1654417 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 206034 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 74348 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 24313 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 41526 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 43761 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 44237 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 44257 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 44260 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 44261 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 44261 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 44260 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 44260 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 42719 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 44064 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 44251 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 44262 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 44264 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 44264 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 44264 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 44264 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 44264 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 44263 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 44263 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 2738 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 503 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 27 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see
-system.physmem.totQLat 35756114000 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 104195196500 # Sum of mem lat for all requests
-system.physmem.totBusLat 9795525000 # Total cycles spent in databus access
-system.physmem.totBankLat 58643557500 # Total cycles spent in bank access
-system.physmem.avgQLat 18251.25 # Average queueing delay per request
-system.physmem.avgBankLat 29933.85 # Average bank access latency per request
+system.physmem.wrQLenPdf::23 1545 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 200 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 13 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 1724238 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 110.484683 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 80.063313 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 303.326643 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 1380958 80.09% 80.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 190861 11.07% 91.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 56628 3.28% 94.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 27570 1.60% 96.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 15749 0.91% 96.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 10044 0.58% 97.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 6620 0.38% 97.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 6559 0.38% 98.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 3696 0.21% 98.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 2923 0.17% 98.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 2676 0.16% 98.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 2682 0.16% 99.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 1400 0.08% 99.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 1070 0.06% 99.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 1040 0.06% 99.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 917 0.05% 99.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 816 0.05% 99.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 821 0.05% 99.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 760 0.04% 99.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 561 0.03% 99.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 626 0.04% 99.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 841 0.05% 99.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1473 3634 0.21% 99.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 546 0.03% 99.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 235 0.01% 99.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1665 177 0.01% 99.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1729 137 0.01% 99.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1793 143 0.01% 99.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1857 117 0.01% 99.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1921 89 0.01% 99.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1985 86 0.00% 99.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2049 92 0.01% 99.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2113 72 0.00% 99.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2177 67 0.00% 99.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2241 71 0.00% 99.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2305 60 0.00% 99.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2369 59 0.00% 99.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2433 57 0.00% 99.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2497 45 0.00% 99.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2561 52 0.00% 99.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2625 34 0.00% 99.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2689 33 0.00% 99.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2753 29 0.00% 99.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2817 45 0.00% 99.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2881 36 0.00% 99.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2945 31 0.00% 99.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3009 19 0.00% 99.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3073 27 0.00% 99.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3137 23 0.00% 99.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3201 16 0.00% 99.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3265 31 0.00% 99.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3329 31 0.00% 99.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3393 24 0.00% 99.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3457 15 0.00% 99.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520-3521 13 0.00% 99.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3585 15 0.00% 99.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648-3649 19 0.00% 99.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3713 18 0.00% 99.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776-3777 13 0.00% 99.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840-3841 23 0.00% 99.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904-3905 24 0.00% 99.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3968-3969 19 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4033 13 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4096-4097 10 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4160-4161 8 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4224-4225 8 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4288-4289 20 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4352-4353 24 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4416-4417 11 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4480-4481 10 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4544-4545 18 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4608-4609 6 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4672-4673 6 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4736-4737 9 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4800-4801 16 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4864-4865 19 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4928-4929 19 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4992-4993 11 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5056-5057 2 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5120-5121 7 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5184-5185 15 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5248-5249 9 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5312-5313 20 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5376-5377 9 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5440-5441 8 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5504-5505 7 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5568-5569 6 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5632-5633 11 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5696-5697 6 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5760-5761 5 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5824-5825 8 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5888-5889 10 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5952-5953 13 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6016-6017 6 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6080-6081 8 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6144-6145 8 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6208-6209 6 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6272-6273 4 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6336-6337 14 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6400-6401 14 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6464-6465 3 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6528-6529 10 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6592-6593 4 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6656-6657 8 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6720-6721 6 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6848-6849 6 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6912-6913 7 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6976-6977 10 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7040-7041 4 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7104-7105 2 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7168-7169 12 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7232-7233 5 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7296-7297 3 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7360-7361 9 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7424-7425 18 0.00% 99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7488-7489 5 0.00% 99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7552-7553 6 0.00% 99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7616-7617 7 0.00% 99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7680-7681 115 0.01% 99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7744-7745 10 0.00% 99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7808-7809 6 0.00% 99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7872-7873 5 0.00% 99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7936-7937 5 0.00% 99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8000-8001 19 0.00% 99.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8064-8065 6 0.00% 99.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8128-8129 14 0.00% 99.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 1430 0.08% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1724238 # Bytes accessed per row activation
+system.physmem.totQLat 33987005500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 98689973000 # Sum of mem lat for all requests
+system.physmem.totBusLat 9795560000 # Total cycles spent in databus access
+system.physmem.totBankLat 54907407500 # Total cycles spent in bank access
+system.physmem.avgQLat 17348.17 # Average queueing delay per request
+system.physmem.avgBankLat 28026.68 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 53185.10 # Average memory access latency
-system.physmem.avgRdBW 126.25 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 65.59 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 126.25 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 65.59 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 50374.85 # Average memory access latency
+system.physmem.avgRdBW 123.45 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 64.13 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 123.45 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 64.13 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 1.50 # Data bus utilization in percentage
+system.physmem.busUtil 1.47 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.10 # Average read queue length over time
-system.physmem.avgWrQLen 10.25 # Average write queue length over time
-system.physmem.readRowHits 770910 # Number of row buffer hits during reads
-system.physmem.writeRowHits 285915 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 39.35 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 28.08 # Row buffer hit rate for writes
-system.physmem.avgGap 333618.27 # Average gap between requests
-system.cpu.branchPred.lookups 326686623 # Number of BP lookups
-system.cpu.branchPred.condPredicted 252728421 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 138236618 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 220072192 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 135769528 # Number of BTB hits
+system.physmem.avgWrQLen 10.57 # Average write queue length over time
+system.physmem.readRowHits 900967 # Number of row buffer hits during reads
+system.physmem.writeRowHits 351956 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 45.99 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 34.57 # Row buffer hit rate for writes
+system.physmem.avgGap 341183.36 # Average gap between requests
+system.membus.throughput 187582407 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 1178392 # Transaction distribution
+system.membus.trans_dist::ReadResp 1178392 # Transaction distribution
+system.membus.trans_dist::Writeback 1018058 # Transaction distribution
+system.membus.trans_dist::ReadExReq 781298 # Transaction distribution
+system.membus.trans_dist::ReadExResp 781298 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 4937438 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 4937438 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190575872 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 190575872 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 190575872 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 11748266000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 1.2 # Layer utilization (%)
+system.membus.respLayer1.occupancy 18466425750 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 1.8 # Layer utilization (%)
+system.cpu.branchPred.lookups 326521750 # Number of BP lookups
+system.cpu.branchPred.condPredicted 252556520 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 138229412 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 220084071 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 135399986 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 61.693177 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 61.521938 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 444795652 # DTB read hits
+system.cpu.dtb.read_hits 444838557 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 449692730 # DTB read accesses
-system.cpu.dtb.write_hits 160833314 # DTB write hits
+system.cpu.dtb.read_accesses 449735635 # DTB read accesses
+system.cpu.dtb.write_hits 160846849 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 162534618 # DTB write accesses
-system.cpu.dtb.data_hits 605628966 # DTB hits
+system.cpu.dtb.write_accesses 162548153 # DTB write accesses
+system.cpu.dtb.data_hits 605685406 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 612227348 # DTB accesses
-system.cpu.itb.fetch_hits 231949721 # ITB hits
+system.cpu.dtb.data_accesses 612283788 # DTB accesses
+system.cpu.itb.fetch_hits 231915406 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 231949743 # ITB accesses
+system.cpu.itb.fetch_accesses 231915428 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
-system.cpu.numCycles 1986859680 # number of cpu cycles simulated
+system.cpu.numCycles 2031916272 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.predictedTaken 172586758 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 154099865 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 1667601840 # Number of Reads from Int. Register File
+system.cpu.branch_predictor.predictedTaken 172213740 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken 154308010 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 1667655233 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 3043804457 # Total Accesses (Read+Write) to the Int. Register File
-system.cpu.regfile_manager.floatRegFileReads 229 # Number of Reads from FP Register File
+system.cpu.regfile_manager.intRegFileAccesses 3043857850 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads 232 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
-system.cpu.regfile_manager.floatRegFileAccesses 574 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 651738878 # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens 617884917 # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect 120537665 # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect 11100495 # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted 131638160 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted 83561944 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct 61.170119 # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions 1139346059 # Number of Instructions Executed.
+system.cpu.regfile_manager.floatRegFileAccesses 577 # Total Accesses (Read+Write) to the FP Register File
+system.cpu.regfile_manager.regForwards 651713796 # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens 617884761 # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect 120483996 # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect 11146958 # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted 131630954 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted 83569020 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct 61.166808 # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions 1139383608 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 1741702087 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 1742160374 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 7484450 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 415164157 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 1571695523 # Number of cycles cpu stages are processed.
-system.cpu.activity 79.104505 # Percentage of cycles cpu is active
+system.cpu.timesIdled 7533550 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 460194055 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 1571722217 # Number of cycles cpu stages are processed.
+system.cpu.activity 77.351722 # Percentage of cycles cpu is active
system.cpu.comLoads 444595663 # Number of Load instructions committed
system.cpu.comStores 160728502 # Number of Store instructions committed
system.cpu.comBranches 214632552 # Number of Branches instructions committed
system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total)
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-system.cpu.dcache.WriteReq_avg_miss_latency::total 45098.948181 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 31281.288029 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 31281.288029 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 31281.288029 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 31281.288029 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 13468960 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 4773919 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 372025 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 65739 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.204449 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 72.619282 # average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029236 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.029236 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.019867 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.019867 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.019867 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.019867 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25692.506344 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 25692.506344 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55512.657915 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55512.657915 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37344.601817 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37344.601817 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 37344.601817 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 37344.601817 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 15563445 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 7313446 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 432083 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 73150 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.019573 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 99.978756 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3693289 # number of writebacks
-system.cpu.dcache.writebacks::total 3693289 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104624 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 104624 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2595524 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2595524 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 2700148 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 2700148 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 2700148 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 2700148 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222280 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7222280 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889182 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1889182 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 9111462 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9111462 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 9111462 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9111462 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 150904604500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 150904604500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 79287604500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 79287604500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230192209000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 230192209000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230192209000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 230192209000 # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks 3693280 # number of writebacks
+system.cpu.dcache.writebacks::total 3693280 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104632 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 104632 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2809939 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2809939 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 2914571 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 2914571 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2914571 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 2914571 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222272 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 7222272 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889176 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1889176 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 9111448 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 9111448 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 9111448 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 9111448 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171613180000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 171613180000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92147472000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 92147472000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 263760652000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 263760652000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 263760652000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 263760652000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20894.316545 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20894.316545 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41969.277973 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41969.277973 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25264.025576 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25264.025576 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25264.025576 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25264.025576 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23761.661150 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23761.661150 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48776.541730 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48776.541730 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28948.269474 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28948.269474 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28948.269474 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28948.269474 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.665535 # Number of seconds simulated
-sim_ticks 665534636500 # Number of ticks simulated
-final_tick 665534636500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.693021 # Number of seconds simulated
+sim_ticks 693021015500 # Number of ticks simulated
+final_tick 693021015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 68112 # Simulator instruction rate (inst/s)
-host_op_rate 68112 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 26111525 # Simulator tick rate (ticks/s)
-host_mem_usage 272636 # Number of bytes of host memory used
-host_seconds 25488.16 # Real time elapsed on the host
+host_inst_rate 172458 # Simulator instruction rate (inst/s)
+host_op_rate 172458 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 68844519 # Simulator tick rate (ticks/s)
+host_mem_usage 228224 # Number of bytes of host memory used
+host_seconds 10066.47 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
sim_ops 1736043781 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 62080 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 125797184 # Number of bytes read from this memory
-system.physmem.bytes_read::total 125859264 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 62080 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 62080 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 65262656 # Number of bytes written to this memory
-system.physmem.bytes_written::total 65262656 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 970 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1965581 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1966551 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1019729 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1019729 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 93278 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 189016735 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 189110013 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 93278 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 93278 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 98060495 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 98060495 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 98060495 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 93278 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 189016735 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 287170509 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1966551 # Total number of read requests seen
-system.physmem.writeReqs 1019729 # Total number of write requests seen
-system.physmem.cpureqs 2986294 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 125859264 # Total number of bytes read from memory
-system.physmem.bytesWritten 65262656 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 125859264 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 65262656 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 565 # Number of read reqs serviced by write Q
+system.physmem.bytes_read::cpu.inst 61376 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 125798976 # Number of bytes read from this memory
+system.physmem.bytes_read::total 125860352 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 61376 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 61376 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 65263616 # Number of bytes written to this memory
+system.physmem.bytes_written::total 65263616 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 959 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1965609 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1966568 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1019744 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1019744 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 88563 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 181522599 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 181611162 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 88563 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 88563 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 94172636 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 94172636 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 94172636 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 88563 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 181522599 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 275783798 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1966568 # Total number of read requests seen
+system.physmem.writeReqs 1019744 # Total number of write requests seen
+system.physmem.cpureqs 2986322 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 125860352 # Total number of bytes read from memory
+system.physmem.bytesWritten 65263616 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 125860352 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 65263616 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 585 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 122670 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 122308 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 122187 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 124219 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 123641 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 122574 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 120687 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 121413 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 121604 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 122268 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 121464 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 123454 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 125591 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 124312 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 123151 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 124443 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 63482 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 62396 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 63113 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 63858 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 64137 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 63872 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 63465 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 63448 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 63476 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 63820 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 63370 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 64242 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 64662 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 64289 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 63740 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 64359 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::0 119008 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 114438 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 116555 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 118046 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 118149 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 117808 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 120225 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 124916 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 127564 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 130488 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 129072 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 130765 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 126644 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 125671 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 122973 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 123661 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 61280 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 61566 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 60655 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 61327 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 61759 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 63170 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 64220 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 65701 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 65486 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 65876 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 65409 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 65716 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 64323 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 64319 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 64636 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 64301 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 14 # Number of times wr buffer was full causing retry
-system.physmem.totGap 665534568000 # Total gap between requests
+system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry
+system.physmem.totGap 693020927000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 1966551 # Categorize read packet sizes
+system.physmem.readPktSize::6 1966568 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 1019729 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 1625924 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 234682 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 77512 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 27850 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1019744 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 1645883 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 229621 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 69862 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 20600 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 42282 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 43951 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 44243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 44297 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 44314 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 44319 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 44320 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 44321 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 44321 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 44336 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::2 44291 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::7 44327 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::10 44337 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::12 44337 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 44336 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 44336 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 44336 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 44336 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 44336 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 44336 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 2055 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 385 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 93 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 39 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 22 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see
-system.physmem.totQLat 34329674750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 102455589750 # Sum of mem lat for all requests
-system.physmem.totBusLat 9829930000 # Total cycles spent in databus access
-system.physmem.totBankLat 58295985000 # Total cycles spent in bank access
-system.physmem.avgQLat 17461.81 # Average queueing delay per request
-system.physmem.avgBankLat 29652.29 # Average bank access latency per request
+system.physmem.wrQLenPdf::23 925 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 185 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 46 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 17 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 1725071 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 110.744307 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 80.207489 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 303.283228 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 1378927 79.93% 79.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 191993 11.13% 91.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 57386 3.33% 94.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 28102 1.63% 96.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 15937 0.92% 96.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 9770 0.57% 97.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 6740 0.39% 97.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 6906 0.40% 98.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 3659 0.21% 98.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 3018 0.17% 98.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 2639 0.15% 98.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 2655 0.15% 98.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 1401 0.08% 99.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 1109 0.06% 99.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 1069 0.06% 99.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 819 0.05% 99.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 853 0.05% 99.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 845 0.05% 99.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 758 0.04% 99.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 637 0.04% 99.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 729 0.04% 99.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 683 0.04% 99.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1473 3600 0.21% 99.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 572 0.03% 99.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 238 0.01% 99.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1665 183 0.01% 99.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1729 143 0.01% 99.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1793 137 0.01% 99.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1857 117 0.01% 99.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1921 83 0.00% 99.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1985 102 0.01% 99.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2049 118 0.01% 99.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2113 69 0.00% 99.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2177 71 0.00% 99.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2241 61 0.00% 99.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2305 48 0.00% 99.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2369 55 0.00% 99.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2433 46 0.00% 99.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2497 41 0.00% 99.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2561 53 0.00% 99.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2625 35 0.00% 99.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2689 34 0.00% 99.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2753 36 0.00% 99.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2817 52 0.00% 99.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2881 44 0.00% 99.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2945 22 0.00% 99.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3009 36 0.00% 99.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3073 29 0.00% 99.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3137 20 0.00% 99.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3201 25 0.00% 99.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3265 30 0.00% 99.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3329 21 0.00% 99.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3393 16 0.00% 99.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3457 19 0.00% 99.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520-3521 21 0.00% 99.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3585 15 0.00% 99.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648-3649 13 0.00% 99.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3713 10 0.00% 99.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776-3777 20 0.00% 99.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3840-3841 21 0.00% 99.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904-3905 25 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3968-3969 12 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4033 15 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4096-4097 16 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4160-4161 13 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4224-4225 10 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4288-4289 23 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4352-4353 19 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4416-4417 8 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4480-4481 7 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4544-4545 9 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4608-4609 8 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4672-4673 7 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4736-4737 11 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4800-4801 5 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4864-4865 8 0.00% 99.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4928-4929 17 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4992-4993 14 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5056-5057 4 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5120-5121 9 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5184-5185 15 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5248-5249 8 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5312-5313 26 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5376-5377 18 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5440-5441 8 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5568-5569 8 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5632-5633 8 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5696-5697 8 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5760-5761 6 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5824-5825 6 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5888-5889 11 0.00% 99.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5952-5953 11 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6016-6017 5 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6080-6081 6 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6144-6145 12 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6208-6209 8 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6272-6273 3 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6336-6337 11 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6400-6401 11 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6464-6465 10 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6528-6529 8 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6656-6657 13 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6720-6721 7 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6784-6785 5 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6848-6849 6 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6976-6977 10 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7040-7041 7 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7104-7105 5 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7168-7169 11 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7232-7233 7 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7296-7297 4 0.00% 99.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7360-7361 15 0.00% 99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7424-7425 7 0.00% 99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7488-7489 4 0.00% 99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7552-7553 3 0.00% 99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7616-7617 4 0.00% 99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7680-7681 118 0.01% 99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7744-7745 6 0.00% 99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7808-7809 4 0.00% 99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7872-7873 7 0.00% 99.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::7936-7937 15 0.00% 99.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8000-8001 12 0.00% 99.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8064-8065 5 0.00% 99.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8128-8129 16 0.00% 99.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 1427 0.08% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1725071 # Bytes accessed per row activation
+system.physmem.totQLat 33871310750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 97989140750 # Sum of mem lat for all requests
+system.physmem.totBusLat 9829915000 # Total cycles spent in databus access
+system.physmem.totBankLat 54287915000 # Total cycles spent in bank access
+system.physmem.avgQLat 17228.69 # Average queueing delay per request
+system.physmem.avgBankLat 27613.62 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 52114.10 # Average memory access latency
-system.physmem.avgRdBW 189.11 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 98.06 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 189.11 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 98.06 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 49842.31 # Average memory access latency
+system.physmem.avgRdBW 181.61 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 94.17 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 181.61 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 94.17 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 2.24 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.15 # Average read queue length over time
-system.physmem.avgWrQLen 10.52 # Average write queue length over time
-system.physmem.readRowHits 776084 # Number of row buffer hits during reads
-system.physmem.writeRowHits 286116 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 39.48 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 28.06 # Row buffer hit rate for writes
-system.physmem.avgGap 222864.09 # Average gap between requests
-system.cpu.branchPred.lookups 381314788 # Number of BP lookups
-system.cpu.branchPred.condPredicted 296330051 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 16069549 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 262009169 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 259516575 # Number of BTB hits
+system.physmem.busUtil 2.15 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.14 # Average read queue length over time
+system.physmem.avgWrQLen 11.24 # Average write queue length over time
+system.physmem.readRowHits 907929 # Number of row buffer hits during reads
+system.physmem.writeRowHits 352711 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 46.18 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 34.59 # Row buffer hit rate for writes
+system.physmem.avgGap 232065.81 # Average gap between requests
+system.membus.throughput 275783798 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 1191455 # Transaction distribution
+system.membus.trans_dist::ReadResp 1191455 # Transaction distribution
+system.membus.trans_dist::Writeback 1019744 # Transaction distribution
+system.membus.trans_dist::ReadExReq 775113 # Transaction distribution
+system.membus.trans_dist::ReadExResp 775113 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 4952880 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 4952880 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 191123968 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 191123968 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 191123968 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 11815530000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 1.7 # Layer utilization (%)
+system.membus.respLayer1.occupancy 18578292500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 2.7 # Layer utilization (%)
+system.cpu.branchPred.lookups 381829258 # Number of BP lookups
+system.cpu.branchPred.condPredicted 296791594 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 16090940 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 262534664 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 259935463 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.048662 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 24704658 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 2987 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 99.009959 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 24706233 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 3077 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 613784934 # DTB read hits
-system.cpu.dtb.read_misses 11255491 # DTB read misses
+system.cpu.dtb.read_hits 613998993 # DTB read hits
+system.cpu.dtb.read_misses 11257757 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 625040425 # DTB read accesses
-system.cpu.dtb.write_hits 212268072 # DTB write hits
-system.cpu.dtb.write_misses 7147147 # DTB write misses
+system.cpu.dtb.read_accesses 625256750 # DTB read accesses
+system.cpu.dtb.write_hits 212346659 # DTB write hits
+system.cpu.dtb.write_misses 7132839 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 219415219 # DTB write accesses
-system.cpu.dtb.data_hits 826053006 # DTB hits
-system.cpu.dtb.data_misses 18402638 # DTB misses
+system.cpu.dtb.write_accesses 219479498 # DTB write accesses
+system.cpu.dtb.data_hits 826345652 # DTB hits
+system.cpu.dtb.data_misses 18390596 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 844455644 # DTB accesses
-system.cpu.itb.fetch_hits 390718533 # ITB hits
-system.cpu.itb.fetch_misses 44 # ITB misses
+system.cpu.dtb.data_accesses 844736248 # DTB accesses
+system.cpu.itb.fetch_hits 391092043 # ITB hits
+system.cpu.itb.fetch_misses 41 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 390718577 # ITB accesses
+system.cpu.itb.fetch_accesses 391092084 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
-system.cpu.numCycles 1331069274 # number of cpu cycles simulated
+system.cpu.numCycles 1386042032 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 402166078 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 3159376011 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 381314788 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 284221233 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 574162316 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 140275246 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 173581201 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1319 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 44 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 390718533 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 8058234 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1266376452 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.494816 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.152860 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 402569601 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 3162430835 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 381829258 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 284641696 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 574759222 # Number of cycles fetch has run and was not squashing or blocked
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+system.cpu.fetch.BlockedCycles 196436536 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 132 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1508 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 391092043 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 8064861 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1290645563 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 692214136 54.66% 54.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 42617572 3.37% 58.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 21747694 1.72% 59.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 39672890 3.13% 62.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 129244053 10.21% 73.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 61517613 4.86% 77.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 38549434 3.04% 80.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 28120980 2.22% 83.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 212692080 16.80% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 715886341 55.47% 55.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 42669337 3.31% 58.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 21804756 1.69% 60.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 39713212 3.08% 63.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 129418344 10.03% 73.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 61537126 4.77% 78.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 38572706 2.99% 81.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 28132820 2.18% 83.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 212910921 16.50% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1266376452 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.286473 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.373562 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 433844233 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 155093027 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 542385824 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 18588672 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 116464696 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 58295749 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 820 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3086840549 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2050 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 116464696 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 456708081 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 101341646 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 4855 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 535414758 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 56442416 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 3004830564 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 566431 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1735808 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 50354826 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2246618583 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3897053047 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3895813174 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1239873 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1290645563 # Number of instructions fetched each cycle (Total)
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+system.cpu.fetch.rate 2.281627 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 434522823 # Number of cycles decode is idle
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+system.cpu.decode.SquashCycles 116877726 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 58348631 # Number of times decode resolved a branch
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+system.cpu.decode.DecodedInsts 3089538872 # Number of instructions handled by decode
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system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
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-system.cpu.rename.serializingInsts 152 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 150 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 121369541 # count of insts added to the skid buffer
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-system.cpu.memDep0.conflictingStores 36895317 # Number of conflicting stores.
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-system.cpu.iq.iqInstsIssued 2508867042 # Number of instructions issued
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-system.cpu.iq.iqSquashedOperandsExamined 414978517 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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+system.cpu.iq.issued_per_cycle::total 1290645563 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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-system.cpu.iq.fu_full::IntMult 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 11915798 64.49% 76.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 4409146 23.86% 100.00% # attempts to use FU when none available
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+system.cpu.iq.fu_full::IntDiv 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 11907011 64.43% 76.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 4409853 23.86% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1643427997 65.50% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 106 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1643982989 65.50% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 103 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 257 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 16 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 155 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 24 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 270 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 15 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 158 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 28 0.00% 65.50% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.50% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.50% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 641412571 25.57% 91.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 224025892 8.93% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 641664411 25.57% 91.07% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 224088858 8.93% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2508867042 # Type of FU issued
-system.cpu.iq.rate 1.884851 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 18477589 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.007365 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 6303778600 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3700560143 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 2412458758 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 1899886 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1215836 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 851322 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2526405516 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 939115 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 62596425 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2509736857 # Type of FU issued
+system.cpu.iq.rate 1.810722 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 18480420 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.007363 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 6329888754 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3704398033 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 2413211688 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 1897658 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1216996 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 850977 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2527279284 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 937993 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 62596809 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 234731586 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 264011 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 109067 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 94602408 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 235126047 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 263685 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 108576 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 94784323 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 66 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1508918 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 179 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1583083 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 116464696 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 45220798 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1155063 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2865407567 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 8873020 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 679327249 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 255330910 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 116 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 297140 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 16951 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 109067 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 10347954 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 8554699 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 18902653 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2461486866 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 625041025 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 47380176 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 116877726 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 58990263 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1298967 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2867530467 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 8941640 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 679721710 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 255512825 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 131 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 325521 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 17838 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 108576 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 10366897 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 8557633 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 18924530 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2462313409 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 625257301 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 47423448 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 142001640 # number of nop insts executed
-system.cpu.iew.exec_refs 844456273 # number of memory reference insts executed
-system.cpu.iew.exec_branches 300755716 # Number of branches executed
-system.cpu.iew.exec_stores 219415248 # Number of stores executed
-system.cpu.iew.exec_rate 1.849255 # Inst execution rate
-system.cpu.iew.wb_sent 2441275432 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2413310080 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1388594213 # num instructions producing a value
-system.cpu.iew.wb_consumers 1764461796 # num instructions consuming a value
+system.cpu.iew.exec_nop 142153473 # number of nop insts executed
+system.cpu.iew.exec_refs 844736823 # number of memory reference insts executed
+system.cpu.iew.exec_branches 300880868 # Number of branches executed
+system.cpu.iew.exec_stores 219479522 # Number of stores executed
+system.cpu.iew.exec_rate 1.776507 # Inst execution rate
+system.cpu.iew.wb_sent 2442002538 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2414062665 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1388567182 # num instructions producing a value
+system.cpu.iew.wb_consumers 1764588303 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.813061 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.786979 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.741695 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.786907 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 824506637 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 827045847 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 16068781 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1149911756 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.582539 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.513361 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 16090137 # The number of times a branch was mispredicted
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+system.cpu.commit.committed_per_cycle::mean 1.550375 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.495661 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 636560643 55.36% 55.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 174447924 15.17% 70.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 86151555 7.49% 78.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 53744022 4.67% 82.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 34427444 2.99% 85.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 25274936 2.20% 87.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 21893247 1.90% 89.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 22942792 2.00% 91.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 94469193 8.22% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 659878599 56.22% 56.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 174801477 14.89% 71.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 86143733 7.34% 78.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 53556827 4.56% 83.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 34704625 2.96% 85.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 26036675 2.22% 88.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 21629651 1.84% 90.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 22889079 1.95% 91.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 94127171 8.02% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1149911756 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1173767837 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1819780126 # Number of instructions committed
system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions.
system.cpu.commit.function_calls 16767440 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 94469193 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 94127171 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3613950126 # The number of ROB reads
-system.cpu.rob.rob_writes 5405135678 # The number of ROB writes
-system.cpu.timesIdled 818095 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 64692822 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3640687439 # The number of ROB reads
+system.cpu.rob.rob_writes 5410628429 # The number of ROB writes
+system.cpu.timesIdled 939185 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 95396469 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
-system.cpu.cpi 0.766726 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.766726 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.304248 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.304248 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3317233936 # number of integer regfile reads
-system.cpu.int_regfile_writes 1931587557 # number of integer regfile writes
-system.cpu.fp_regfile_reads 30073 # number of floating regfile reads
-system.cpu.fp_regfile_writes 508 # number of floating regfile writes
+system.cpu.cpi 0.798391 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.798391 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.252519 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.252519 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3318270268 # number of integer regfile reads
+system.cpu.int_regfile_writes 1932125497 # number of integer regfile writes
+system.cpu.fp_regfile_reads 30353 # number of floating regfile reads
+system.cpu.fp_regfile_writes 534 # number of floating regfile writes
system.cpu.misc_regfile_reads 25 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
+system.cpu.toL2Bus.throughput 1191881478 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 7297634 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 7297634 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 3724968 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1883631 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1883631 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1918 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22085580 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 22087498 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 61376 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 825937536 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 825998912 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 825998912 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 10178169165 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1438500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 13770459000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%)
system.cpu.icache.replacements 1 # number of replacements
-system.cpu.icache.tagsinuse 775.031780 # Cycle average of tags in use
-system.cpu.icache.total_refs 390717051 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 970 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 402801.083505 # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse 768.731270 # Cycle average of tags in use
+system.cpu.icache.total_refs 391090558 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 959 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 407810.800834 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 775.031780 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.378433 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.378433 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 390717051 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 390717051 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 390717051 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 390717051 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 390717051 # number of overall hits
-system.cpu.icache.overall_hits::total 390717051 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1482 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1482 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1482 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1482 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1482 # number of overall misses
-system.cpu.icache.overall_misses::total 1482 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 88954499 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 88954499 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 88954499 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 88954499 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 88954499 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 88954499 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 390718533 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 390718533 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 390718533 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 390718533 # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total 390718533 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 768.731270 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.375357 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.375357 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 391090558 # number of ReadReq hits
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+system.cpu.icache.ReadReq_misses::cpu.inst 1484 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1484 # number of ReadReq misses
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+system.cpu.icache.demand_misses::total 1484 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1484 # number of overall misses
+system.cpu.icache.overall_misses::total 1484 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 114408499 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 114408499 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 114408499 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 114408499 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 114408499 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 114408499 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 391092042 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 391092042 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 391092042 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 391092042 # number of demand (read+write) accesses
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+system.cpu.icache.overall_accesses::total 391092042 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
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system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 9180488 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9180488 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 9180488 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9180488 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 159258474500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 159258474500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71462908450 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 71462908450 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 47500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 47500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230721382950 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 230721382950 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 230721382950 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 230721382950 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013268 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013268 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data 9180305 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 9180305 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 9180305 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 9180305 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180470424000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 180470424000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85065304522 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 85065304522 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 69500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 69500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 265535728522 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 265535728522 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 265535728522 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 265535728522 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013264 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013264 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011719 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011719 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.333333 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012918 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.012918 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012918 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.012918 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21825.422969 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21825.422969 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37940.280442 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37940.280442 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 47500 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 47500 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25131.712274 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25131.712274 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25131.712274 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 25131.712274 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.012915 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012915 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.012915 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24733.217646 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24733.217646 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45160.472410 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45160.472410 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 69500 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 69500 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28924.499624 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 28924.499624 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28924.499624 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 28924.499624 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 913189263000 # Number of ticks simulated
final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2288605 # Simulator instruction rate (inst/s)
-host_op_rate 2288605 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1148451794 # Simulator tick rate (ticks/s)
-host_mem_usage 263992 # Number of bytes of host memory used
-host_seconds 795.15 # Real time elapsed on the host
+host_inst_rate 4050769 # Simulator instruction rate (inst/s)
+host_op_rate 4050768 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2032728095 # Simulator tick rate (ticks/s)
+host_mem_usage 217548 # Number of bytes of host memory used
+host_seconds 449.24 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 7305514036 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7999999926 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3068994956 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11068994882 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 11068994882 # Throughput (bytes/s)
+system.membus.data_through_bus 10108087278 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
sim_ticks 2623386226000 # Number of ticks simulated
final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1056521 # Simulator instruction rate (inst/s)
-host_op_rate 1056521 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1523075909 # Simulator tick rate (ticks/s)
-host_mem_usage 272444 # Number of bytes of host memory used
-host_seconds 1722.43 # Real time elapsed on the host
+host_inst_rate 781919 # Simulator instruction rate (inst/s)
+host_op_rate 781919 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1127211275 # Simulator tick rate (ticks/s)
+host_mem_usage 225028 # Number of bytes of host memory used
+host_seconds 2327.32 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 19566 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 47788276 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 72644797 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 72644797 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 1178362 # Transaction distribution
+system.membus.trans_dist::ReadResp 1178362 # Transaction distribution
+system.membus.trans_dist::Writeback 1018077 # Transaction distribution
+system.membus.trans_dist::ReadExReq 781301 # Transaction distribution
+system.membus.trans_dist::ReadExResp 781301 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 4937403 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 4937403 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190575360 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 190575360 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 190575360 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 11122356000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
+system.membus.respLayer1.occupancy 17636967000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 312415345 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 7223216 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 3693497 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1604 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21916965 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 21918569 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 51328 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819534784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 819586112 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 819586112 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 10096513500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.517355 # Number of seconds simulated
-sim_ticks 517355353500 # Number of ticks simulated
-final_tick 517355353500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.540696 # Number of seconds simulated
+sim_ticks 540696400000 # Number of ticks simulated
+final_tick 540696400000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 80961 # Simulator instruction rate (inst/s)
-host_op_rate 90318 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 27118174 # Simulator tick rate (ticks/s)
-host_mem_usage 288124 # Number of bytes of host memory used
-host_seconds 19077.81 # Real time elapsed on the host
+host_inst_rate 169038 # Simulator instruction rate (inst/s)
+host_op_rate 188575 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 59174301 # Simulator tick rate (ticks/s)
+host_mem_usage 246336 # Number of bytes of host memory used
+host_seconds 9137.35 # Real time elapsed on the host
sim_insts 1544563023 # Number of instructions simulated
sim_ops 1723073835 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 47616 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 143726656 # Number of bytes read from this memory
-system.physmem.bytes_read::total 143774272 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 47616 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 47616 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 70431232 # Number of bytes written to this memory
-system.physmem.bytes_written::total 70431232 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 744 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2245729 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2246473 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1100488 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1100488 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 92037 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 277810319 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 277902357 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 92037 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 92037 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 136137051 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 136137051 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 136137051 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 92037 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 277810319 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 414039407 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 2246473 # Total number of read requests seen
-system.physmem.writeReqs 1100488 # Total number of write requests seen
-system.physmem.cpureqs 3346979 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 143774272 # Total number of bytes read from memory
-system.physmem.bytesWritten 70431232 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 143774272 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 70431232 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 670 # Number of read reqs serviced by write Q
+system.physmem.bytes_read::cpu.inst 48128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 143740608 # Number of bytes read from this memory
+system.physmem.bytes_read::total 143788736 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 48128 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 48128 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 70441600 # Number of bytes written to this memory
+system.physmem.bytes_written::total 70441600 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 752 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 2245947 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2246699 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1100650 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1100650 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 89011 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 265843471 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 265932483 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 89011 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 89011 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 130279395 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 130279395 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 130279395 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 89011 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 265843471 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 396211878 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 2246699 # Total number of read requests seen
+system.physmem.writeReqs 1100650 # Total number of write requests seen
+system.physmem.cpureqs 3347359 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 143788736 # Total number of bytes read from memory
+system.physmem.bytesWritten 70441600 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 143788736 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 70441600 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 675 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 141489 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 139656 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 141525 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 141936 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 142251 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 140152 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 141094 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 140745 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 138661 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 136342 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 140561 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 140724 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 141098 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 138976 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 138964 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 141629 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 69092 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 68439 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 69113 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 69523 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 69288 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 69039 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 68977 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 68383 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 67923 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 67021 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 69461 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 69311 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 69094 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 68543 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 68433 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 68848 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::0 139594 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 136159 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 133894 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 136244 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 134956 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 135313 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 136207 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 136262 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 143860 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 146526 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 144286 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 146187 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 145855 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 146147 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 142095 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 142439 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 69117 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 67412 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 65719 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 66245 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 66183 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 66419 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 67973 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 68813 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 70394 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 70993 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 70492 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 70984 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 70346 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 70810 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 69619 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 69131 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 18 # Number of times wr buffer was full causing retry
-system.physmem.totGap 517355284500 # Total gap between requests
+system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry
+system.physmem.totGap 540696152000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 2246473 # Categorize read packet sizes
+system.physmem.readPktSize::6 2246699 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 1100488 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 1563773 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 450876 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 162701 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 68433 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1100650 # Categorize write packet sizes
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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-system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see
-system.physmem.totQLat 51860326500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 131350914000 # Sum of mem lat for all requests
-system.physmem.totBusLat 11229015000 # Total cycles spent in databus access
-system.physmem.totBankLat 68261572500 # Total cycles spent in bank access
-system.physmem.avgQLat 23092.11 # Average queueing delay per request
-system.physmem.avgBankLat 30395.17 # Average bank access latency per request
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+system.physmem.bytesPerActivate::samples 1997676 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 107.204860 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 79.811800 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 283.656472 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 1593756 79.78% 79.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 230264 11.53% 91.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 68043 3.41% 94.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 32667 1.64% 96.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 17678 0.88% 97.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 10939 0.55% 97.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 7434 0.37% 98.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 7476 0.37% 98.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 4079 0.20% 98.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 3182 0.16% 98.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 2817 0.14% 99.03% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::896-897 1138 0.06% 99.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 999 0.05% 99.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 880 0.04% 99.39% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1408-1409 838 0.04% 99.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1473 3581 0.18% 99.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 454 0.02% 99.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 187 0.01% 99.81% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::total 1997676 # Bytes accessed per row activation
+system.physmem.totQLat 50306526000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 124453758500 # Sum of mem lat for all requests
+system.physmem.totBusLat 11230120000 # Total cycles spent in databus access
+system.physmem.totBankLat 62917112500 # Total cycles spent in bank access
+system.physmem.avgQLat 22398.04 # Average queueing delay per request
+system.physmem.avgBankLat 28012.66 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 58487.28 # Average memory access latency
-system.physmem.avgRdBW 277.90 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 136.14 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 277.90 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 136.14 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 55410.70 # Average memory access latency
+system.physmem.avgRdBW 265.93 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 130.28 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 265.93 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 130.28 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 3.23 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.25 # Average read queue length over time
-system.physmem.avgWrQLen 11.18 # Average write queue length over time
-system.physmem.readRowHits 827290 # Number of row buffer hits during reads
-system.physmem.writeRowHits 270800 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 36.84 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 24.61 # Row buffer hit rate for writes
-system.physmem.avgGap 154574.64 # Average gap between requests
-system.cpu.branchPred.lookups 303238356 # Number of BP lookups
-system.cpu.branchPred.condPredicted 249416285 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 15213179 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 173189005 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 161485027 # Number of BTB hits
+system.physmem.busUtil 3.10 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.23 # Average read queue length over time
+system.physmem.avgWrQLen 10.44 # Average write queue length over time
+system.physmem.readRowHits 1005962 # Number of row buffer hits during reads
+system.physmem.writeRowHits 343028 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 44.79 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 31.17 # Row buffer hit rate for writes
+system.physmem.avgGap 161529.66 # Average gap between requests
+system.membus.throughput 396211878 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 1420214 # Transaction distribution
+system.membus.trans_dist::ReadResp 1420214 # Transaction distribution
+system.membus.trans_dist::Writeback 1100650 # Transaction distribution
+system.membus.trans_dist::ReadExReq 826485 # Transaction distribution
+system.membus.trans_dist::ReadExResp 826485 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 5594048 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 5594048 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 214230336 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 214230336 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 214230336 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 12859707750 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
+system.membus.respLayer1.occupancy 21134071500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 3.9 # Layer utilization (%)
+system.cpu.branchPred.lookups 304230401 # Number of BP lookups
+system.cpu.branchPred.condPredicted 250450611 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 15192997 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 172575058 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 162497547 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 93.242078 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 17562220 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 189 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 94.160506 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 17547944 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 207 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 1034710708 # number of cpu cycles simulated
+system.cpu.numCycles 1081392801 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 298243506 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2186139129 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 303238356 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 179047247 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 435102558 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 87842368 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 155357657 # Number of cycles fetch has spent blocked
-system.cpu.fetch.PendingTrapStallCycles 150 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 288597285 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 5732219 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 958597013 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.523325 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.213142 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 300338229 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2194868023 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 304230401 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 180045491 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 436913465 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 88946702 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 165329116 # Number of cycles fetch has spent blocked
+system.cpu.fetch.PendingTrapStallCycles 33 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 290586210 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 6069176 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 973112936 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.494450 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.204820 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 523494535 54.61% 54.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 25506855 2.66% 57.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 39100627 4.08% 61.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 48361324 5.05% 66.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 43019358 4.49% 70.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 46453211 4.85% 75.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 38427133 4.01% 79.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 18718773 1.95% 81.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 175515197 18.31% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 536199557 55.10% 55.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 25797166 2.65% 57.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 39079992 4.02% 61.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 48369850 4.97% 66.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 43937617 4.52% 71.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 46464611 4.77% 76.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 38405061 3.95% 79.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 19061800 1.96% 81.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 175797282 18.07% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 958597013 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.293066 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.112802 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 329802987 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 133619813 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 405201175 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 20080558 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 69892480 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 46072656 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 693 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 2366906963 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2456 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 69892480 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 353335624 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 63410713 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 18651 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 400220631 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 71718914 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2304481635 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 133374 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 5031151 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 58581263 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 68 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 2279812946 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 10642278370 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 10642275398 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 2972 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 973112936 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.281332 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.029668 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 332624022 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 143219561 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 406441589 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 20296480 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 70531284 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 46039188 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 865 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 2374316328 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 2545 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 70531284 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 356409274 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 71650111 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 21139 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 401304268 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 73196860 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2310523412 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 156231 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 5060521 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 60179356 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 18 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 2286636992 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 10669420338 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 10669417166 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 3172 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 573493016 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 743 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 740 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 158758361 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 624481311 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 220974466 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 86299107 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 71333452 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2201408276 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 781 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2018173722 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 4013043 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 473803931 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1125355707 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 611 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 958597013 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.105341 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.906395 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 580317062 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 904 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 901 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 161063694 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 625481573 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 221078320 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 85817344 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 70539912 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2205002740 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 913 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2019903116 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 4041921 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 477338341 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1137890497 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 743 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 973112936 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.075713 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.906230 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 277575373 28.96% 28.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 151381497 15.79% 44.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 161170411 16.81% 61.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 119836935 12.50% 74.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 123952521 12.93% 86.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 73863494 7.71% 94.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 38468068 4.01% 98.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 9785076 1.02% 99.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 2563638 0.27% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 289817184 29.78% 29.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 153400597 15.76% 45.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 161373326 16.58% 62.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 120291643 12.36% 74.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 123812966 12.72% 87.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 73732869 7.58% 94.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 38377982 3.94% 98.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 9754115 1.00% 99.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 2552254 0.26% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 958597013 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 973112936 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 884210 3.70% 3.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 5702 0.02% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.72% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 18296872 76.51% 80.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 4728009 19.77% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 873823 3.65% 3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 5574 0.02% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 18262233 76.32% 80.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 4786578 20.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1236704914 61.28% 61.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 925192 0.05% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 4 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 587491999 29.11% 90.43% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 193051561 9.57% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1237523467 61.27% 61.27% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 925246 0.05% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 44 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 23 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.31% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 588384414 29.13% 90.44% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 193069911 9.56% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2018173722 # Type of FU issued
-system.cpu.iq.rate 1.950471 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 23914793 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.011850 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 5022872024 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2675402581 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1957467931 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 269 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 546 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 94 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2042088379 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 136 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 64652420 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2019903116 # Type of FU issued
+system.cpu.iq.rate 1.867872 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 23928208 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.011846 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 5040888987 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2682531512 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1957653574 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 310 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 612 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 122 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2043831169 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 155 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 64629118 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 138554542 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 270922 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 192724 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 46127421 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 139554804 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 275861 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 192692 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 46231275 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 4683320 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 5362990 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 69892480 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 28879520 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1498948 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2201409154 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 6144718 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 624481311 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 220974466 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 719 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 474123 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 89366 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 192724 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 8152988 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 9608721 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 17761709 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1988146149 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 573921356 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 30027573 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 70531284 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 34407025 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1609544 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2205003765 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 7646058 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 625481573 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 221078320 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 851 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 482587 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 96102 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 192692 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 8138129 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 9602458 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 17740587 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1988966025 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 574553789 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 30937091 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 97 # number of nop insts executed
-system.cpu.iew.exec_refs 764085836 # number of memory reference insts executed
-system.cpu.iew.exec_branches 238329441 # Number of branches executed
-system.cpu.iew.exec_stores 190164480 # Number of stores executed
-system.cpu.iew.exec_rate 1.921451 # Inst execution rate
-system.cpu.iew.wb_sent 1965914335 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1957468025 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1296382145 # num instructions producing a value
-system.cpu.iew.wb_consumers 2061123370 # num instructions consuming a value
+system.cpu.iew.exec_nop 112 # number of nop insts executed
+system.cpu.iew.exec_refs 764737764 # number of memory reference insts executed
+system.cpu.iew.exec_branches 238303653 # Number of branches executed
+system.cpu.iew.exec_stores 190183975 # Number of stores executed
+system.cpu.iew.exec_rate 1.839263 # Inst execution rate
+system.cpu.iew.wb_sent 1966073864 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1957653696 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1295701173 # num instructions producing a value
+system.cpu.iew.wb_consumers 2059307469 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.891802 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.628969 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.810308 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.629193 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 478433603 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 482029293 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 15212517 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 888704533 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.938860 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.728045 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 15192188 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 902581652 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.909050 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.715598 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 401292741 45.15% 45.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 192157168 21.62% 66.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 72538162 8.16% 74.94% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 35233922 3.96% 78.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 18967934 2.13% 81.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 30755514 3.46% 84.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 20061647 2.26% 86.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 11460153 1.29% 88.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 106237292 11.95% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 414112551 45.88% 45.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 193170118 21.40% 67.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 72777120 8.06% 75.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 35259342 3.91% 79.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 18942446 2.10% 81.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 30787152 3.41% 84.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 19991978 2.21% 86.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 11413503 1.26% 88.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 106127442 11.76% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 888704533 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 902581652 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1544563041 # Number of instructions committed
system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 106237292 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 106127442 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2983974098 # The number of ROB reads
-system.cpu.rob.rob_writes 4473052836 # The number of ROB writes
-system.cpu.timesIdled 1016894 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 76113695 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3001556757 # The number of ROB reads
+system.cpu.rob.rob_writes 4480884032 # The number of ROB writes
+system.cpu.timesIdled 1155619 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 108279865 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1544563023 # Number of Instructions Simulated
system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated
-system.cpu.cpi 0.669905 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.669905 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.492749 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.492749 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 9956441643 # number of integer regfile reads
-system.cpu.int_regfile_writes 1937434969 # number of integer regfile writes
-system.cpu.fp_regfile_reads 88 # number of floating regfile reads
-system.cpu.fp_regfile_writes 99 # number of floating regfile writes
-system.cpu.misc_regfile_reads 737571197 # number of misc regfile reads
+system.cpu.cpi 0.700129 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.700129 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.428309 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.428309 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 9959942925 # number of integer regfile reads
+system.cpu.int_regfile_writes 1937523681 # number of integer regfile writes
+system.cpu.fp_regfile_reads 126 # number of floating regfile reads
+system.cpu.fp_regfile_writes 125 # number of floating regfile writes
+system.cpu.misc_regfile_reads 737562736 # number of misc regfile reads
system.cpu.misc_regfile_writes 124 # number of misc regfile writes
-system.cpu.icache.replacements 21 # number of replacements
-system.cpu.icache.tagsinuse 624.513050 # Cycle average of tags in use
-system.cpu.icache.total_refs 288596120 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 772 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 373829.170984 # Average number of references to valid blocks.
+system.cpu.toL2Bus.throughput 1584099202 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 7708436 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 7708436 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 3781153 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1893485 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1893485 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1562 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 22983433 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 22984995 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 49984 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 856466752 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 856516736 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 856516736 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 10472863577 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1171999 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 14401713992 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 2.7 # Layer utilization (%)
+system.cpu.icache.replacements 22 # number of replacements
+system.cpu.icache.tagsinuse 627.830229 # Cycle average of tags in use
+system.cpu.icache.total_refs 290585017 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 781 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 372067.883483 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 624.513050 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.304938 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.304938 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 288596120 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 288596120 # number of ReadReq hits
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system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
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-system.cpu.dcache.demand_accesses::total 673090856 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 673090856 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 673090856 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022927 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.022927 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032092 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.032092 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044118 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044118 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.025277 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.025277 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.025277 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.025277 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28153.864927 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 28153.864927 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41432.948286 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 41432.948286 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 32476.729176 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 32476.729176 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 32476.729176 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 32476.729176 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 26385368 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 1054130 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1182490 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 64549 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.313396 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 16.330695 # average number of cycles each access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 673064785 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 673064785 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 673064785 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 673064785 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022989 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.022989 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032601 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.032601 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.025454 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.025454 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.025454 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.025454 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32983.517270 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 32983.517270 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54634.461169 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54634.461169 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 217000 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 217000 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 40093.967105 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 40093.967105 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 40093.967105 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 40093.967105 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 29400681 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 3494014 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 1217576 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 65132 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.146896 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 53.645121 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3781426 # number of writebacks
-system.cpu.dcache.writebacks::total 3781426 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3767868 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 3767868 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3645146 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 3645146 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 3781153 # number of writebacks
+system.cpu.dcache.writebacks::total 3781153 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3798054 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 3798054 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3732924 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 3732924 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 7413014 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 7413014 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 7413014 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 7413014 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707083 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7707083 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893425 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1893425 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 9600508 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9600508 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 9600508 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9600508 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 186133873500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 186133873500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83704359724 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 83704359724 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 269838233224 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 269838233224 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 269838233224 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 269838233224 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015399 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015399 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_hits::cpu.data 7530978 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 7530978 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 7530978 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 7530978 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7707655 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 7707655 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893485 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1893485 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 9601140 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 9601140 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 9601140 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 9601140 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 210632290508 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 210632290508 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97135590826 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 97135590826 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 307767881334 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 307767881334 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 307767881334 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 307767881334 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015401 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015401 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.014263 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24151.014528 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24151.014528 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44207.908802 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44207.908802 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28106.661983 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 28106.661983 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28106.661983 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 28106.661983 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27327.674955 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27327.674955 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51299.899828 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51299.899828 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32055.347733 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 32055.347733 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32055.347733 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 32055.347733 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 861538200000 # Number of ticks simulated
final_tick 861538200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1602478 # Simulator instruction rate (inst/s)
-host_op_rate 1787682 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 893842215 # Simulator tick rate (ticks/s)
-host_mem_usage 278712 # Number of bytes of host memory used
-host_seconds 963.86 # Real time elapsed on the host
+host_inst_rate 2812355 # Simulator instruction rate (inst/s)
+host_op_rate 3137389 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1568696760 # Simulator tick rate (ticks/s)
+host_mem_usage 234512 # Number of bytes of host memory used
+host_seconds 549.21 # Real time elapsed on the host
sim_insts 1544563041 # Number of instructions simulated
sim_ops 1723073853 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 6178262356 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7171199554 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2560009600 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9731209155 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 9731209155 # Throughput (bytes/s)
+system.membus.data_through_bus 8383808419 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
sim_ticks 2391205115000 # Number of ticks simulated
final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 809589 # Simulator instruction rate (inst/s)
-host_op_rate 903509 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1258086461 # Simulator tick rate (ticks/s)
-host_mem_usage 287292 # Number of bytes of host memory used
-host_seconds 1900.67 # Real time elapsed on the host
+host_inst_rate 1401168 # Simulator instruction rate (inst/s)
+host_op_rate 1563717 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2177389973 # Simulator tick rate (ticks/s)
+host_mem_usage 243008 # Number of bytes of host memory used
+host_seconds 1098.20 # Real time elapsed on the host
sim_insts 1538759601 # Number of instructions simulated
sim_ops 1717270334 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 16487 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 52409604 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 79651138 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 79651138 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 1177898 # Transaction distribution
+system.membus.trans_dist::ReadResp 1177898 # Transaction distribution
+system.membus.trans_dist::Writeback 1017198 # Transaction distribution
+system.membus.trans_dist::ReadExReq 780876 # Transaction distribution
+system.membus.trans_dist::ReadExResp 780876 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 4934746 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 4934746 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 190462208 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 190462208 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 190462208 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 11113556000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 17628966000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 342944519 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1276 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21927890 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 21929166 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 40832 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 820009856 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 820050688 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 820050688 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
---------- End Simulation Statistics ----------
system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 13588998587 # Throughput (bytes/s)
+system.membus.data_through_bus 38674388193 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 5692014456 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 32392097 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 1177614 # Transaction distribution
+system.membus.trans_dist::ReadResp 1177614 # Transaction distribution
+system.membus.trans_dist::Writeback 1018421 # Transaction distribution
+system.membus.trans_dist::ReadExReq 781295 # Transaction distribution
+system.membus.trans_dist::ReadExResp 781295 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port 4936239 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 190549120 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 11124698000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
+system.membus.respLayer1.occupancy 17630181000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 11765161052 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 139381638 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 7223525 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1889827 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1889827 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1350 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 21923310 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 21924660 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 43200 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 819880512 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 819923712 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 819923712 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1012500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.041622 # Number of seconds simulated
-sim_ticks 41622221000 # Number of ticks simulated
-final_tick 41622221000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.041671 # Number of seconds simulated
+sim_ticks 41671058000 # Number of ticks simulated
+final_tick 41671058000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 47594 # Simulator instruction rate (inst/s)
-host_op_rate 47594 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 21554846 # Simulator tick rate (ticks/s)
-host_mem_usage 275256 # Number of bytes of host memory used
-host_seconds 1930.99 # Real time elapsed on the host
+host_inst_rate 79080 # Simulator instruction rate (inst/s)
+host_op_rate 79080 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 35856814 # Simulator tick rate (ticks/s)
+host_mem_usage 228800 # Number of bytes of host memory used
+host_seconds 1162.15 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 4296167 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3296701 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 7592867 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 4296167 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 4296167 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 4296167 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3296701 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7592867 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 4291132 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3292837 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 7583969 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 4291132 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 4291132 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 4291132 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3292837 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 7583969 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 4938 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 4938 # Reqs generatd by CPU via cache - shady
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 311 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 344 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 302 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 293 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 259 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 224 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 279 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 294 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 290 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 273 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 301 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 345 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 351 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 357 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 333 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 382 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 443 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 270 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 295 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 499 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 209 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 212 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 207 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 265 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 219 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 249 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 238 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 236 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 379 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 325 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 469 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 423 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 41622168000 # Total gap between requests
+system.physmem.totGap 41670985500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 3236 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1195 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 440 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 3344 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1140 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 428 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 23362750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 122110250 # Sum of mem lat for all requests
+system.physmem.bytesPerActivate::samples 360 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 858.311111 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 328.631203 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 1420.533351 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 87 24.17% 24.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 46 12.78% 36.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 36 10.00% 46.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 14 3.89% 50.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 20 5.56% 56.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 14 3.89% 60.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 9 2.50% 62.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 7 1.94% 64.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 8 2.22% 66.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 3 0.83% 67.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 8 2.22% 70.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 5 1.39% 71.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 6 1.67% 73.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 7 1.94% 75.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 4 1.11% 76.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 2 0.56% 76.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 5 1.39% 78.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 1 0.28% 78.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 3 0.83% 79.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 5 1.39% 80.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 1 0.28% 80.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 3 0.83% 81.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1473 4 1.11% 82.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 2 0.56% 83.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 3 0.83% 84.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1665 3 0.83% 85.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1729 2 0.56% 85.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1793 4 1.11% 86.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1921 1 0.28% 86.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1985 4 1.11% 88.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2049 2 0.56% 88.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2113 3 0.83% 89.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2305 1 0.28% 89.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2369 1 0.28% 90.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2497 3 0.83% 90.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2625 2 0.56% 91.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2689 1 0.28% 91.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2881 2 0.56% 92.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2945 1 0.28% 92.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3073 2 0.56% 93.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3137 1 0.28% 93.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3201 1 0.28% 93.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3265 1 0.28% 93.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3393 2 0.56% 94.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3457 1 0.28% 94.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3585 1 0.28% 95.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3713 1 0.28% 95.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776-3777 1 0.28% 95.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904-3905 1 0.28% 95.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4033 2 0.56% 96.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4160-4161 1 0.28% 96.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4480-4481 1 0.28% 96.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4992-4993 1 0.28% 97.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5056-5057 1 0.28% 97.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5312-5313 1 0.28% 97.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5632-5633 1 0.28% 98.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6144-6145 1 0.28% 98.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8128-8129 2 0.56% 98.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 4 1.11% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 360 # Bytes accessed per row activation
+system.physmem.totQLat 21938250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 110827000 # Sum of mem lat for all requests
system.physmem.totBusLat 24690000 # Total cycles spent in databus access
-system.physmem.totBankLat 74057500 # Total cycles spent in bank access
-system.physmem.avgQLat 4731.22 # Average queueing delay per request
-system.physmem.avgBankLat 14997.47 # Average bank access latency per request
+system.physmem.totBankLat 64198750 # Total cycles spent in bank access
+system.physmem.avgQLat 4442.74 # Average queueing delay per request
+system.physmem.avgBankLat 13000.96 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 24728.69 # Average memory access latency
-system.physmem.avgRdBW 7.59 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 22443.70 # Average memory access latency
+system.physmem.avgRdBW 7.58 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 7.59 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 7.58 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 4243 # Number of row buffer hits during reads
+system.physmem.readRowHits 4578 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 85.93 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 92.71 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 8428952.61 # Average gap between requests
-system.cpu.branchPred.lookups 13412628 # Number of BP lookups
-system.cpu.branchPred.condPredicted 9650145 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 7424480 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 3768497 # Number of BTB hits
+system.physmem.avgGap 8438838.70 # Average gap between requests
+system.membus.throughput 7583969 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 3216 # Transaction distribution
+system.membus.trans_dist::ReadResp 3216 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 9876 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 9876 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 316032 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 316032 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 316032 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 5804000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 46092250 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.cpu.branchPred.lookups 13412467 # Number of BP lookups
+system.cpu.branchPred.condPredicted 9649930 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 4269365 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 7424694 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 3768519 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 50.757723 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 50.756556 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1029619 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 126 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 19996247 # DTB read hits
+system.cpu.dtb.read_hits 19996249 # DTB read hits
system.cpu.dtb.read_misses 10 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 19996257 # DTB read accesses
-system.cpu.dtb.write_hits 6501860 # DTB write hits
+system.cpu.dtb.read_accesses 19996259 # DTB read accesses
+system.cpu.dtb.write_hits 6501862 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 6501883 # DTB write accesses
-system.cpu.dtb.data_hits 26498107 # DTB hits
+system.cpu.dtb.write_accesses 6501885 # DTB write accesses
+system.cpu.dtb.data_hits 26498111 # DTB hits
system.cpu.dtb.data_misses 33 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 26498140 # DTB accesses
-system.cpu.itb.fetch_hits 9956943 # ITB hits
+system.cpu.dtb.data_accesses 26498144 # DTB accesses
+system.cpu.itb.fetch_hits 9957259 # ITB hits
system.cpu.itb.fetch_misses 49 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 9956992 # ITB accesses
+system.cpu.itb.fetch_accesses 9957308 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
-system.cpu.numCycles 83244443 # number of cpu cycles simulated
+system.cpu.numCycles 83342117 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.predictedTaken 5905664 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 7506964 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 73570548 # Number of Reads from Int. Register File
+system.cpu.branch_predictor.predictedTaken 5905707 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken 7506760 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 73570716 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 136146020 # Total Accesses (Read+Write) to the Int. Register File
-system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File
+system.cpu.regfile_manager.intRegFileAccesses 136146188 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.floatRegFileReads 2206130 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
-system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 38521871 # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens 26722393 # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted 4268356 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted 5972346 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct 41.680307 # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions 57404029 # Number of Instructions Executed.
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+system.cpu.execution_unit.mispredicted 4268507 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted 5972195 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct 41.681781 # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions 57404114 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.comLoads 19996198 # Number of Load instructions committed
system.cpu.comStores 6501103 # Number of Store instructions committed
system.cpu.comBranches 10240685 # Number of Branches instructions committed
system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total)
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system.cpu.smt_cpi nan # CPI: Total SMT-CPI
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system.cpu.smt_ipc nan # IPC: Total SMT-IPC
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+system.cpu.dcache.WriteReq_avg_miss_latency::total 56403.504502 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 57142.142370 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 57142.142370 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 57142.142370 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 57142.142370 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 21765 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 822 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 825 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.681265 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.381818 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
system.cpu.dcache.writebacks::total 107 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 100 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6353 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 6353 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 6453 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 6453 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 6453 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 6453 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 101 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6470 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 6470 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 6571 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 6571 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 6571 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 6571 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25078500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 25078500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86165500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 86165500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 111244000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 111244000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 111244000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 111244000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31213000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 31213000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116706500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 116706500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 147919500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 147919500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 147919500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 147919500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52796.842105 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52796.842105 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49293.764302 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49293.764302 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50042.285200 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 50042.285200 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50042.285200 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 50042.285200 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65711.578947 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65711.578947 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66765.732265 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66765.732265 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66540.485830 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 66540.485830 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66540.485830 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 66540.485830 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.023380 # Number of seconds simulated
-sim_ticks 23379948000 # Number of ticks simulated
-final_tick 23379948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.023497 # Number of seconds simulated
+sim_ticks 23497413000 # Number of ticks simulated
+final_tick 23497413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 61366 # Simulator instruction rate (inst/s)
-host_op_rate 61366 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 17043654 # Simulator tick rate (ticks/s)
-host_mem_usage 277304 # Number of bytes of host memory used
-host_seconds 1371.77 # Real time elapsed on the host
+host_inst_rate 127551 # Simulator instruction rate (inst/s)
+host_op_rate 127551 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 35603882 # Simulator tick rate (ticks/s)
+host_mem_usage 231880 # Number of bytes of host memory used
+host_seconds 659.97 # Real time elapsed on the host
sim_insts 84179709 # Number of instructions simulated
sim_ops 84179709 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 195840 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 138688 # Number of bytes read from this memory
-system.physmem.bytes_read::total 334528 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 195840 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 195840 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3060 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2167 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 5227 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 8376409 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 5931921 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 14308330 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 8376409 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 8376409 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 8376409 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 5931921 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 14308330 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 5227 # Total number of read requests seen
+system.physmem.bytes_read::cpu.inst 195392 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 138624 # Number of bytes read from this memory
+system.physmem.bytes_read::total 334016 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 195392 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 195392 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 3053 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 2166 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 5219 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 8315469 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 5899543 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 14215012 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 8315469 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 8315469 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 8315469 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 5899543 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 14215012 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 5219 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 5227 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 334528 # Total number of bytes read from memory
+system.physmem.cpureqs 5219 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 334016 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 334528 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 334016 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 327 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 362 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 327 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 311 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 286 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 244 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 297 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 308 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 299 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 281 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 315 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 365 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 374 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 377 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 354 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 400 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 469 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 291 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 302 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 519 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 221 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 224 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 218 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 288 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 237 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 278 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 248 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 252 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 398 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 337 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 491 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 446 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 23379842000 # Total gap between requests
+system.physmem.totGap 23497287000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 5227 # Categorize read packet sizes
+system.physmem.readPktSize::6 5219 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 3182 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1372 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 547 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 112 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 3287 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1338 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 507 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 29390250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 134711500 # Sum of mem lat for all requests
-system.physmem.totBusLat 26135000 # Total cycles spent in databus access
-system.physmem.totBankLat 79186250 # Total cycles spent in bank access
-system.physmem.avgQLat 5622.78 # Average queueing delay per request
-system.physmem.avgBankLat 15149.46 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 418 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 779.330144 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 283.808293 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 1370.086091 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 124 29.67% 29.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 51 12.20% 41.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 42 10.05% 51.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 20 4.78% 56.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 15 3.59% 60.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 19 4.55% 64.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 7 1.67% 66.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 9 2.15% 68.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 7 1.67% 70.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 3 0.72% 71.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 8 1.91% 72.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 7 1.67% 74.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 6 1.44% 76.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 5 1.20% 77.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 4 0.96% 78.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 1 0.24% 78.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 6 1.44% 79.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 3 0.72% 80.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 4 0.96% 81.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 3 0.72% 82.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 5 1.20% 83.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 3 0.72% 84.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 5 1.20% 85.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 3 0.72% 86.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1665 3 0.72% 86.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1729 3 0.72% 87.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1793 1 0.24% 87.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1857 3 0.72% 88.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1921 1 0.24% 88.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1985 3 0.72% 89.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2049 2 0.48% 89.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2113 2 0.48% 90.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2177 1 0.24% 90.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2305 2 0.48% 91.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2369 1 0.24% 91.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2433 2 0.48% 91.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2497 1 0.24% 92.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2689 1 0.24% 92.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2753 1 0.24% 92.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2817 1 0.24% 92.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2881 1 0.24% 93.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2945 1 0.24% 93.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3009 1 0.24% 93.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3073 1 0.24% 93.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3137 1 0.24% 94.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3393 2 0.48% 94.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3457 1 0.24% 94.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3585 2 0.48% 95.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3713 1 0.24% 95.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3776-3777 1 0.24% 95.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3904-3905 1 0.24% 95.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3968-3969 1 0.24% 96.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4033 2 0.48% 96.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4096-4097 1 0.24% 96.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4352-4353 1 0.24% 97.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4864-4865 1 0.24% 97.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4992-4993 1 0.24% 97.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5312-5313 1 0.24% 97.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5376-5377 1 0.24% 98.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5632-5633 1 0.24% 98.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6848-6849 1 0.24% 98.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8128-8129 2 0.48% 99.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 4 0.96% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 418 # Bytes accessed per row activation
+system.physmem.totQLat 22102000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 116465750 # Sum of mem lat for all requests
+system.physmem.totBusLat 26095000 # Total cycles spent in databus access
+system.physmem.totBankLat 68268750 # Total cycles spent in bank access
+system.physmem.avgQLat 4234.91 # Average queueing delay per request
+system.physmem.avgBankLat 13080.81 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 25772.24 # Average memory access latency
-system.physmem.avgRdBW 14.31 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 22315.72 # Average memory access latency
+system.physmem.avgRdBW 14.22 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 14.31 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 14.22 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.11 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.01 # Average read queue length over time
+system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 4448 # Number of row buffer hits during reads
+system.physmem.readRowHits 4801 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 85.10 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 91.99 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 4472898.79 # Average gap between requests
-system.cpu.branchPred.lookups 14842140 # Number of BP lookups
-system.cpu.branchPred.condPredicted 10766991 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 921197 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 8255704 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 6953438 # Number of BTB hits
+system.physmem.avgGap 4502258.48 # Average gap between requests
+system.membus.throughput 14215012 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 3511 # Transaction distribution
+system.membus.trans_dist::ReadResp 3511 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1708 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1708 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 10438 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 10438 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 334016 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 334016 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 334016 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 6341000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 48807250 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.cpu.branchPred.lookups 14862551 # Number of BP lookups
+system.cpu.branchPred.condPredicted 10783549 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 926034 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 8413875 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 6968843 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 84.225864 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1467825 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 3067 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 82.825607 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1469354 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 3121 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 23110097 # DTB read hits
-system.cpu.dtb.read_misses 194589 # DTB read misses
+system.cpu.dtb.read_hits 23132924 # DTB read hits
+system.cpu.dtb.read_misses 192093 # DTB read misses
system.cpu.dtb.read_acv 2 # DTB read access violations
-system.cpu.dtb.read_accesses 23304686 # DTB read accesses
-system.cpu.dtb.write_hits 7067053 # DTB write hits
-system.cpu.dtb.write_misses 1113 # DTB write misses
-system.cpu.dtb.write_acv 6 # DTB write access violations
-system.cpu.dtb.write_accesses 7068166 # DTB write accesses
-system.cpu.dtb.data_hits 30177150 # DTB hits
-system.cpu.dtb.data_misses 195702 # DTB misses
-system.cpu.dtb.data_acv 8 # DTB access violations
-system.cpu.dtb.data_accesses 30372852 # DTB accesses
-system.cpu.itb.fetch_hits 14723480 # ITB hits
-system.cpu.itb.fetch_misses 97 # ITB misses
+system.cpu.dtb.read_accesses 23325017 # DTB read accesses
+system.cpu.dtb.write_hits 7072345 # DTB write hits
+system.cpu.dtb.write_misses 1094 # DTB write misses
+system.cpu.dtb.write_acv 2 # DTB write access violations
+system.cpu.dtb.write_accesses 7073439 # DTB write accesses
+system.cpu.dtb.data_hits 30205269 # DTB hits
+system.cpu.dtb.data_misses 193187 # DTB misses
+system.cpu.dtb.data_acv 4 # DTB access violations
+system.cpu.dtb.data_accesses 30398456 # DTB accesses
+system.cpu.itb.fetch_hits 14755058 # ITB hits
+system.cpu.itb.fetch_misses 101 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 14723577 # ITB accesses
+system.cpu.itb.fetch_accesses 14755159 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
-system.cpu.numCycles 46759897 # number of cpu cycles simulated
+system.cpu.numCycles 46994827 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 15452025 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 126885771 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14842140 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 8421263 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 22118402 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4462593 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 5523983 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 69 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 2725 # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles 15489149 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 127098752 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14862551 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 8438197 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 22157137 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4490975 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 5583322 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 113 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 2356 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 14723480 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 324121 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 46604653 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.722599 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.376512 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 14755058 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 326188 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 46762472 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.717965 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.375306 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 24486251 52.54% 52.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2361565 5.07% 57.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1190149 2.55% 60.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1742976 3.74% 63.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2754417 5.91% 69.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1149365 2.47% 72.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1217917 2.61% 74.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 773119 1.66% 76.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 10928894 23.45% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 24605335 52.62% 52.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2364392 5.06% 57.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1192796 2.55% 60.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1746753 3.74% 63.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2761574 5.91% 69.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1153115 2.47% 72.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1218931 2.61% 74.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 773556 1.65% 76.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 10946020 23.41% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 46604653 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.317412 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.713560 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 17272805 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 4225851 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 20520611 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1089695 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3495691 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 2514029 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 12278 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 123910172 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 32104 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3495691 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 18413803 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 951839 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 7350 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 20446933 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 3289037 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 121090735 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 56 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 399536 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 2410998 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 88918567 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 157348562 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 147674536 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 9674026 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 46762472 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.316259 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.704526 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 17321703 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 4276623 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 20543509 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1101986 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3518651 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 2516350 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 12158 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 124100512 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 31524 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3518651 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 18468008 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 966877 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 7668 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 20476490 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 3324778 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 121264521 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 82 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 403236 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 2443262 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 89058236 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 157582364 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 147884300 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 9698064 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 20491206 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 720 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 712 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 8742624 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 25345876 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 8236695 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2569867 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 913943 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 105383195 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1656 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 96551560 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 178239 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 20729473 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 15559619 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1267 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 46604653 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.071715 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.877215 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 20630875 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 727 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 718 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 8817740 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 25385211 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 8251770 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 2611914 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 924495 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 105530247 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1715 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 96635335 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 178536 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 20879466 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 15657073 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1326 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 46762472 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.066515 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.875135 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 12094878 25.95% 25.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 9328666 20.02% 45.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 8376475 17.97% 63.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6286526 13.49% 77.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 4922367 10.56% 87.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2863469 6.14% 94.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1727619 3.71% 97.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 799385 1.72% 99.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 205268 0.44% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 12166038 26.02% 26.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 9374565 20.05% 46.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 8425963 18.02% 64.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 6292522 13.46% 77.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 4920709 10.52% 88.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2854864 6.11% 94.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1726414 3.69% 97.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 795538 1.70% 99.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 205859 0.44% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 46604653 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 46762472 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 187515 11.95% 11.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 11.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 11.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 174 0.01% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 7228 0.46% 12.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 5644 0.36% 12.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 843061 53.75% 66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 446254 28.45% 94.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 78748 5.02% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 190796 12.16% 12.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 12.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 12.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 179 0.01% 12.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 7128 0.45% 12.62% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 5650 0.36% 12.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 843178 53.72% 66.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 66.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 66.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 66.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 66.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 66.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 66.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 66.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 66.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 66.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.70% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 444699 28.33% 95.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 77939 4.97% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 58727382 60.82% 60.82% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 479803 0.50% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 58779410 60.83% 60.83% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 479944 0.50% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2798335 2.90% 64.22% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 115384 0.12% 64.34% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 2386573 2.47% 66.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 311072 0.32% 67.13% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 760041 0.79% 67.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2800605 2.90% 64.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 115340 0.12% 64.34% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 2387840 2.47% 66.81% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 311019 0.32% 67.13% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 760059 0.79% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 23822951 24.67% 92.59% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 7149693 7.41% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 23845244 24.68% 92.60% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 7155548 7.40% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 96551560 # Type of FU issued
-system.cpu.iq.rate 2.064837 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1568624 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.016246 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 226343159 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 117415886 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 87055232 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 15111477 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 8732806 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 7062055 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 90134309 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 7985868 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1517472 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 96635335 # Type of FU issued
+system.cpu.iq.rate 2.056297 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1569569 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.016242 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 226659120 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 117679968 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 87126809 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 15122127 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 8766253 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 7066480 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 90213613 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 7991284 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1520773 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 5349678 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 18734 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 34491 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1735592 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 5389013 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 18483 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 34901 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1750667 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 10525 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1599 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 10533 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1986 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3495691 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 132330 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 18056 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 115618245 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 370442 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 25345876 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 8236695 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1656 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 2792 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 32 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 34491 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 533607 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 495069 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1028676 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 95323071 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 23305173 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1228489 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3518651 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 134178 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 18459 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 115772618 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 373350 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 25385211 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 8251770 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1715 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 3175 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 37 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 34901 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 538953 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 495548 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1034501 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 95401130 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 23325510 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1234205 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 10233394 # number of nop insts executed
-system.cpu.iew.exec_refs 30373541 # number of memory reference insts executed
-system.cpu.iew.exec_branches 12020857 # Number of branches executed
-system.cpu.iew.exec_stores 7068368 # Number of stores executed
-system.cpu.iew.exec_rate 2.038565 # Inst execution rate
-system.cpu.iew.wb_sent 94638543 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 94117287 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 64469301 # num instructions producing a value
-system.cpu.iew.wb_consumers 89849772 # num instructions consuming a value
+system.cpu.iew.exec_nop 10240656 # number of nop insts executed
+system.cpu.iew.exec_refs 30399148 # number of memory reference insts executed
+system.cpu.iew.exec_branches 12029434 # Number of branches executed
+system.cpu.iew.exec_stores 7073638 # Number of stores executed
+system.cpu.iew.exec_rate 2.030035 # Inst execution rate
+system.cpu.iew.wb_sent 94712572 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 94193289 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 64506867 # num instructions producing a value
+system.cpu.iew.wb_consumers 89893282 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.012778 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.717523 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.004333 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.717594 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 23716139 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 23870674 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 909447 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 43108962 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.131878 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.747863 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 914298 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 43243821 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.125230 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.743207 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 16687185 38.71% 38.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 9891500 22.95% 61.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4481461 10.40% 72.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2260770 5.24% 77.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1601496 3.71% 81.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1124303 2.61% 83.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 719465 1.67% 85.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 820222 1.90% 87.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5522560 12.81% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 16770420 38.78% 38.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 9933071 22.97% 61.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4488153 10.38% 72.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2264318 5.24% 77.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1614513 3.73% 81.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1126501 2.60% 83.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 722210 1.67% 85.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 820173 1.90% 87.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5504462 12.73% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 43108962 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 43243821 # Number of insts commited each cycle
system.cpu.commit.committedInsts 91903055 # Number of instructions committed
system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions.
system.cpu.commit.int_insts 79581076 # Number of committed integer instructions.
system.cpu.commit.function_calls 1029620 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5522560 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 5504462 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 153204556 # The number of ROB reads
-system.cpu.rob.rob_writes 234757733 # The number of ROB writes
-system.cpu.timesIdled 5297 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 155244 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 153512048 # The number of ROB reads
+system.cpu.rob.rob_writes 235089898 # The number of ROB writes
+system.cpu.timesIdled 5458 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 232355 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
-system.cpu.cpi 0.555477 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.555477 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.800254 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.800254 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 129030140 # number of integer regfile reads
-system.cpu.int_regfile_writes 70506108 # number of integer regfile writes
-system.cpu.fp_regfile_reads 6188141 # number of floating regfile reads
-system.cpu.fp_regfile_writes 6043644 # number of floating regfile writes
-system.cpu.misc_regfile_reads 714512 # number of misc regfile reads
+system.cpu.cpi 0.558268 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.558268 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.791255 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.791255 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 129137938 # number of integer regfile reads
+system.cpu.int_regfile_writes 70566847 # number of integer regfile writes
+system.cpu.fp_regfile_reads 6190616 # number of floating regfile reads
+system.cpu.fp_regfile_writes 6048237 # number of floating regfile writes
+system.cpu.misc_regfile_reads 714522 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.icache.replacements 9682 # number of replacements
-system.cpu.icache.tagsinuse 1594.464074 # Cycle average of tags in use
-system.cpu.icache.total_refs 14709198 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 11615 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 1266.396728 # Average number of references to valid blocks.
+system.cpu.toL2Bus.throughput 38347030 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 12236 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 12236 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1734 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1734 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 23446 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4603 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 28049 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 750272 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 150784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 901056 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 901056 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 7148500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 17584500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 3370500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu.icache.replacements 9791 # number of replacements
+system.cpu.icache.tagsinuse 1591.709559 # Cycle average of tags in use
+system.cpu.icache.total_refs 14740526 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 11723 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 1257.402201 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1594.464074 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.778547 # Average percentage of cache occupancy
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+system.cpu.dcache.overall_accesses::cpu.data 28100781 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 28100781 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000045 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001265 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.001265 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.004566 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.004566 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000327 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000327 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000327 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000327 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61365.087539 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 61365.087539 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57837.907808 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 57837.907808 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92000 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92000 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 58210.462091 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 58210.462091 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 58210.462091 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 58210.462091 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 21885 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 330 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 353 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 42.924242 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 61.997167 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 109 # number of writebacks
system.cpu.dcache.writebacks::total 109 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 491 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 491 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6367 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 6367 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 6858 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 6858 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 6858 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 6858 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 516 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 516 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1731 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1731 # number of WriteReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 459 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 459 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6488 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 6488 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 6947 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 6947 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 6947 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 6947 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 512 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 512 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1734 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1734 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2247 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2247 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2247 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2247 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30419500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 30419500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88590998 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 88590998 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 70000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 70000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 119010498 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 119010498 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 119010498 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 119010498 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data 2246 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2246 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2246 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2246 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34660000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 34660000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116538997 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 116538997 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151198997 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 151198997 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151198997 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 151198997 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004237 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004237 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000267 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.004566 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.004566 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000080 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58952.519380 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58952.519380 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51179.086077 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51179.086077 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 70000 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 70000 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52964.173565 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 52964.173565 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52964.173565 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 52964.173565 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67695.312500 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67695.312500 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67208.187428 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67208.187428 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90000 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90000 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67319.232858 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 67319.232858 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67319.232858 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 67319.232858 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 45951567500 # Number of ticks simulated
final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1141309 # Simulator instruction rate (inst/s)
-host_op_rate 1141309 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 570654979 # Simulator tick rate (ticks/s)
-host_mem_usage 267644 # Number of bytes of host memory used
-host_seconds 80.52 # Real time elapsed on the host
+host_inst_rate 3944537 # Simulator instruction rate (inst/s)
+host_op_rate 3944535 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1972268010 # Simulator tick rate (ticks/s)
+host_mem_usage 220188 # Number of bytes of host memory used
+host_seconds 23.30 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 367612356 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 11030545389 # Throughput (bytes/s)
+system.membus.data_through_bus 506870851 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
sim_ticks 118729316000 # Number of ticks simulated
final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1044383 # Simulator instruction rate (inst/s)
-host_op_rate 1044383 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1349235521 # Simulator tick rate (ticks/s)
-host_mem_usage 276220 # Number of bytes of host memory used
-host_seconds 88.00 # Real time elapsed on the host
+host_inst_rate 852211 # Simulator instruction rate (inst/s)
+host_op_rate 852211 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1100968725 # Simulator tick rate (ticks/s)
+host_mem_usage 228676 # Number of bytes of host memory used
+host_seconds 107.84 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 2568532 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 3043 # Transaction distribution
+system.membus.trans_dist::ReadResp 3043 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 9530 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 9530 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 304960 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 304960 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 304960 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 42885000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 5843207 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 8985 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 17020 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4553 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 21573 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 544640 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 149120 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 693760 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 693760 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 5527000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 12765000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.074157 # Number of seconds simulated
-sim_ticks 74157495500 # Number of ticks simulated
-final_tick 74157495500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.074184 # Number of seconds simulated
+sim_ticks 74184344000 # Number of ticks simulated
+final_tick 74184344000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 51189 # Simulator instruction rate (inst/s)
-host_op_rate 56047 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 22031117 # Simulator tick rate (ticks/s)
-host_mem_usage 291420 # Number of bytes of host memory used
-host_seconds 3366.03 # Real time elapsed on the host
+host_inst_rate 120810 # Simulator instruction rate (inst/s)
+host_op_rate 132276 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 52014122 # Simulator tick rate (ticks/s)
+host_mem_usage 249648 # Number of bytes of host memory used
+host_seconds 1426.23 # Real time elapsed on the host
sim_insts 172303021 # Number of instructions simulated
sim_ops 188656503 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 131776 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 111936 # Number of bytes read from this memory
-system.physmem.bytes_read::total 243712 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 131776 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 131776 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 2059 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1749 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 3808 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1776975 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1509436 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3286411 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1776975 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1776975 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1776975 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1509436 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3286411 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 3809 # Total number of read requests seen
+system.physmem.bytes_read::cpu.inst 131136 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 111808 # Number of bytes read from this memory
+system.physmem.bytes_read::total 242944 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 131136 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 131136 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 2049 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1747 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 3796 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1767705 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1507164 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3274869 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1767705 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1767705 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1767705 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1507164 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3274869 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 3796 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 3811 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 243712 # Total number of bytes read from memory
+system.physmem.cpureqs 3798 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 242944 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 243712 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 242944 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 2 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 323 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 239 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 208 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 272 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 244 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 197 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 247 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 252 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 233 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 244 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 235 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 309 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 215 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 134 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 309 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 297 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 300 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 262 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 217 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 246 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 213 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 288 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 193 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 201 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 199 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 248 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 274 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 189 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 206 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 219 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 199 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 74157477000 # Total gap between requests
+system.physmem.totGap 74184191000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 3809 # Categorize read packet sizes
+system.physmem.readPktSize::6 3796 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 2784 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 808 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 160 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 48 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 2837 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 786 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 131 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 17510750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 103435750 # Sum of mem lat for all requests
-system.physmem.totBusLat 19045000 # Total cycles spent in databus access
-system.physmem.totBankLat 66880000 # Total cycles spent in bank access
-system.physmem.avgQLat 4597.20 # Average queueing delay per request
-system.physmem.avgBankLat 17558.41 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 376 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 621.446809 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 226.720612 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 1211.628472 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 135 35.90% 35.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 51 13.56% 49.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 26 6.91% 56.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 29 7.71% 64.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 14 3.72% 67.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 14 3.72% 71.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 6 1.60% 73.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 5 1.33% 74.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 7 1.86% 76.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 7 1.86% 78.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 5 1.33% 79.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 6 1.60% 81.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 1 0.27% 81.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 5 1.33% 82.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 3 0.80% 83.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 4 1.06% 84.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 2 0.53% 85.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 3 0.80% 85.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 3 0.80% 86.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 1 0.27% 86.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 1 0.27% 87.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 5 1.33% 88.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1473 2 0.53% 89.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 1 0.27% 89.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 3 0.80% 90.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1665 3 0.80% 90.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1729 1 0.27% 91.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1793 1 0.27% 91.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1857 1 0.27% 91.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1921 1 0.27% 92.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2113 2 0.53% 92.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2177 1 0.27% 92.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2241 1 0.27% 93.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2305 1 0.27% 93.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2369 1 0.27% 93.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2433 1 0.27% 93.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2497 1 0.27% 94.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2625 1 0.27% 94.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2689 1 0.27% 94.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2817 1 0.27% 94.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2945 1 0.27% 95.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3009 1 0.27% 95.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3201 1 0.27% 95.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3265 3 0.80% 96.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3712-3713 1 0.27% 96.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4032-4033 1 0.27% 97.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4416-4417 1 0.27% 97.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4480-4481 1 0.27% 97.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4800-4801 1 0.27% 97.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5120-5121 1 0.27% 98.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5312-5313 1 0.27% 98.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6272-6273 1 0.27% 98.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6720-6721 1 0.27% 98.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6848-6849 1 0.27% 99.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8128-8129 1 0.27% 99.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 2 0.53% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 376 # Bytes accessed per row activation
+system.physmem.totQLat 13471250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 86310000 # Sum of mem lat for all requests
+system.physmem.totBusLat 18980000 # Total cycles spent in databus access
+system.physmem.totBankLat 53858750 # Total cycles spent in bank access
+system.physmem.avgQLat 3548.80 # Average queueing delay per request
+system.physmem.avgBankLat 14188.29 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 27155.62 # Average memory access latency
-system.physmem.avgRdBW 3.29 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 22737.09 # Average memory access latency
+system.physmem.avgRdBW 3.27 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 3.29 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 3.27 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 3021 # Number of row buffer hits during reads
+system.physmem.readRowHits 3420 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 79.31 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 19469014.70 # Average gap between requests
-system.cpu.branchPred.lookups 94703867 # Number of BP lookups
-system.cpu.branchPred.condPredicted 74722053 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 6280216 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 44664544 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 43035053 # Number of BTB hits
+system.physmem.avgGap 19542726.82 # Average gap between requests
+system.membus.throughput 3274869 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 2721 # Transaction distribution
+system.membus.trans_dist::ReadResp 2721 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 2 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1075 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1075 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 7596 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 7596 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 242944 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 242944 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 242944 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 4823500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 35740248 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu.branchPred.lookups 94757540 # Number of BP lookups
+system.cpu.branchPred.condPredicted 74764818 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 6278340 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 44654246 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 43033777 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 96.351712 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 4359745 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 88611 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 96.371075 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 4354951 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 88346 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 148314992 # number of cpu cycles simulated
+system.cpu.numCycles 148368689 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 39662414 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 380030694 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 94703867 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 47394798 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 80357293 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 27270600 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 7200009 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 7 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 5243 # Number of stall cycles due to pending traps
+system.cpu.fetch.icacheStallCycles 39647823 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 380146219 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 94757540 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 47388728 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 80358140 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 27268312 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 7203967 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 12 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 5523 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 36857358 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1832427 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 148199476 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.801422 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.152732 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles 69 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 36843987 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1833209 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 148189615 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.802214 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.153150 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 68011684 45.89% 45.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 5276203 3.56% 49.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 10540688 7.11% 56.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 10280783 6.94% 63.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 8654302 5.84% 69.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 6554085 4.42% 73.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 6244651 4.21% 77.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 7982798 5.39% 83.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 24654282 16.64% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 68000764 45.89% 45.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 5268021 3.55% 49.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 10540392 7.11% 56.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 10285161 6.94% 63.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 8646262 5.83% 69.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 6545573 4.42% 73.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 6244018 4.21% 77.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 7997629 5.40% 83.36% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 24661795 16.64% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 148199476 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.638532 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.562322 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 45512613 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 5867522 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 74797201 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1201275 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 20820865 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 14305085 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 164111 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 392663870 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 738369 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 20820865 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 50901215 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 722150 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 593982 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 70547488 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 4613776 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 371203156 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 33 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 343152 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 3655877 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 29 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 631482556 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1581281661 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1563963855 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 17317806 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 148189615 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.638663 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.562173 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 45498061 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 5874830 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 74793705 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1202536 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 20820483 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 14321847 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 164416 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 392715815 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 749819 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 20820483 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 50886064 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 722985 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 600307 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 70546117 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 4613659 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 371260855 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 69 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 344235 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 3657023 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 27 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 631666093 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1581493948 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1564155420 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 17338528 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 298044139 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 333438417 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 25133 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 25129 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13026907 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 42996111 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 16422667 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 5676383 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 3667621 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 329112708 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 47143 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 249432965 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 790911 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 139431014 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 361763997 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1927 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 148199476 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.683089 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.761808 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 333621954 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 25182 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 25179 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 13028807 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 42981884 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 16417977 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 5680787 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 3667947 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 329134626 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 47203 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 249422621 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 787073 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 139456652 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 361881130 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1987 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 148189615 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.683132 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.761818 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 56042939 37.82% 37.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 22629719 15.27% 53.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 24820832 16.75% 69.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 20320046 13.71% 83.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12535804 8.46% 92.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 6521757 4.40% 96.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 4030887 2.72% 99.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 1115815 0.75% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 181677 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 56042296 37.82% 37.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 22626121 15.27% 53.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 24808060 16.74% 69.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 20320875 13.71% 83.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12548887 8.47% 92.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 6516147 4.40% 96.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 4031410 2.72% 99.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 1113540 0.75% 99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 182279 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 148199476 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 148189615 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 963057 38.38% 38.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 5596 0.22% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 101 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.60% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 51 0.00% 38.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 1167699 46.53% 85.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 372909 14.86% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 962595 38.42% 38.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 5594 0.22% 38.65% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatAdd 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 107 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 48 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 38.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 1164588 46.49% 85.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 372359 14.86% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 194880762 78.13% 78.13% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 980286 0.39% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 33071 0.01% 78.54% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 194884583 78.13% 78.13% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 979638 0.39% 78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 33073 0.01% 78.54% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 164429 0.07% 78.60% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 254305 0.10% 78.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 76429 0.03% 78.73% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 465674 0.19% 78.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 206396 0.08% 79.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 71854 0.03% 79.03% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 321 0.00% 79.03% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 38348799 15.37% 94.41% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 13950639 5.59% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 164452 0.07% 78.61% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 254844 0.10% 78.71% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 76427 0.03% 78.74% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 465912 0.19% 78.93% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 206449 0.08% 79.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 71875 0.03% 79.04% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 323 0.00% 79.04% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 38337954 15.37% 94.41% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 13947091 5.59% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 249432965 # Type of FU issued
-system.cpu.iq.rate 1.681779 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2509413 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010060 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 646629225 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 466421271 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 237868779 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 3736505 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 2188097 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 1840763 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 250067463 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 1874915 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 2006857 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 249422621 # Type of FU issued
+system.cpu.iq.rate 1.681100 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2505291 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.010044 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 646588556 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 466464832 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 237860517 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 3738665 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 2192143 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 1842020 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 250052019 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 1875893 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 2007355 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 13146627 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 11917 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 18980 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 3778033 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 13132400 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 11727 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 18993 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 3773343 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 10 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads 13 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 104 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 20820865 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 17088 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 846 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 329176829 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 784787 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 42996111 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 16422667 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 24735 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 188 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 265 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 18980 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 3891833 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 3757719 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 7649552 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 242934999 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 36843669 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 6497966 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 20820483 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 18849 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 902 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 329198829 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 786805 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 42981884 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 16417977 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 24795 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 191 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 274 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 18993 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 3888167 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 3760327 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 7648494 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 242926605 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 36835264 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 6496016 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 16978 # number of nop insts executed
-system.cpu.iew.exec_refs 50492106 # number of memory reference insts executed
-system.cpu.iew.exec_branches 53412943 # Number of branches executed
-system.cpu.iew.exec_stores 13648437 # Number of stores executed
-system.cpu.iew.exec_rate 1.637967 # Inst execution rate
-system.cpu.iew.wb_sent 240767037 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 239709542 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 148457899 # num instructions producing a value
-system.cpu.iew.wb_consumers 267241195 # num instructions consuming a value
+system.cpu.iew.exec_nop 17000 # number of nop insts executed
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+system.cpu.iew.exec_branches 53424163 # Number of branches executed
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+system.cpu.iew.exec_rate 1.637317 # Inst execution rate
+system.cpu.iew.wb_sent 240758455 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 239702537 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 148455856 # num instructions producing a value
+system.cpu.iew.wb_consumers 267256641 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.616219 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.555520 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.615587 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.555481 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 140505920 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 140527929 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 6126595 # The number of times a branch was mispredicted
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-system.cpu.commit.committed_per_cycle::mean 1.481182 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.186353 # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::stdev 2.186316 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 57698651 45.30% 45.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 31675595 24.87% 70.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 13783953 10.82% 80.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 7631475 5.99% 86.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 4374952 3.43% 90.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1321227 1.04% 91.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1703973 1.34% 92.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1307096 1.03% 93.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 7881689 6.19% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 57689921 45.29% 45.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 31670367 24.87% 70.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 13785643 10.82% 80.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 7636266 6.00% 86.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 4374586 3.43% 90.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1321093 1.04% 91.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1699680 1.33% 92.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 1314057 1.03% 93.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 7877519 6.18% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::total 127369132 # Number of insts commited each cycle
system.cpu.commit.committedInsts 172317409 # Number of instructions committed
system.cpu.commit.committedOps 188670891 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
system.cpu.commit.int_insts 150106217 # Number of committed integer instructions.
system.cpu.commit.function_calls 1848934 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 7881689 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 7877519 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 448668532 # The number of ROB reads
-system.cpu.rob.rob_writes 679284219 # The number of ROB writes
-system.cpu.timesIdled 2567 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 115516 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 448685232 # The number of ROB reads
+system.cpu.rob.rob_writes 679327064 # The number of ROB writes
+system.cpu.timesIdled 2810 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 179074 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 172303021 # Number of Instructions Simulated
system.cpu.committedOps 188656503 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 172303021 # Number of Instructions Simulated
-system.cpu.cpi 0.860780 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.860780 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.161737 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.161737 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1079304778 # number of integer regfile reads
-system.cpu.int_regfile_writes 384845307 # number of integer regfile writes
-system.cpu.fp_regfile_reads 2912671 # number of floating regfile reads
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-system.cpu.misc_regfile_reads 54492663 # number of misc regfile reads
+system.cpu.cpi 0.861092 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.861092 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.161317 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.161317 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1079239284 # number of integer regfile reads
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system.cpu.misc_regfile_writes 820036 # number of misc regfile writes
-system.cpu.icache.replacements 2376 # number of replacements
-system.cpu.icache.tagsinuse 1350.566241 # Cycle average of tags in use
-system.cpu.icache.total_refs 36852122 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 4106 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 8975.188018 # Average number of references to valid blocks.
+system.cpu.toL2Bus.throughput 5142648 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 4861 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 4861 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 17 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1083 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1083 # Transaction distribution
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+system.cpu.toL2Bus.pkt_count 11907 # Packet count per connected master and slave (bytes)
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+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 119680 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 381376 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 381376 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 128 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 2998500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 6138496 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.icache.blocked_cycles::no_mshrs 608 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45409.607143 # average ReadReq mshr miss latency
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+system.cpu.dcache.overall_mshr_misses::total 1855 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 49331013 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 49331013 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 69111498 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 69111498 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 118442511 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 118442511 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 118442511 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 118442511 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000040 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000040 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53070.967742 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53070.967742 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46441.282569 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46441.282569 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49196.245576 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 49196.245576 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49196.245576 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 49196.245576 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63900.275907 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63900.275907 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63814.864266 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63814.864266 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63850.410243 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 63850.410243 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63850.410243 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 63850.410243 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 103106766000 # Number of ticks simulated
final_tick 103106766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1465257 # Simulator instruction rate (inst/s)
-host_op_rate 1604314 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 876741604 # Simulator tick rate (ticks/s)
-host_mem_usage 282008 # Number of bytes of host memory used
-host_seconds 117.60 # Real time elapsed on the host
+host_inst_rate 2813934 # Simulator instruction rate (inst/s)
+host_op_rate 3080985 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1683727447 # Simulator tick rate (ticks/s)
+host_mem_usage 236772 # Number of bytes of host memory used
+host_seconds 61.24 # Real time elapsed on the host
sim_insts 172317409 # Number of instructions simulated
sim_ops 188670891 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 759440204 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7365570985 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1510925103 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 8876496088 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 8876496088 # Throughput (bytes/s)
+system.membus.data_through_bus 915226805 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
sim_ticks 232072304000 # Number of ticks simulated
final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 817822 # Simulator instruction rate (inst/s)
-host_op_rate 895603 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1104464333 # Simulator tick rate (ticks/s)
-host_mem_usage 290584 # Number of bytes of host memory used
-host_seconds 210.12 # Real time elapsed on the host
+host_inst_rate 1198657 # Simulator instruction rate (inst/s)
+host_op_rate 1312657 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1618778979 # Simulator tick rate (ticks/s)
+host_mem_usage 245268 # Number of bytes of host memory used
+host_seconds 143.36 # Real time elapsed on the host
sim_insts 171842483 # Number of instructions simulated
sim_ops 188185920 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 476817 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 475438 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 952255 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 952255 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 2361 # Transaction distribution
+system.membus.trans_dist::ReadResp 2361 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1092 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1092 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 6906 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 6906 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 220992 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 220992 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 220992 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 3453000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 31077000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 1339169 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 6102 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3594 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 9696 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 195264 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 115520 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 310784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 310784 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
sim_ticks 96722945000 # Number of ticks simulated
final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1868868 # Simulator instruction rate (inst/s)
-host_op_rate 1868870 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 934440193 # Simulator tick rate (ticks/s)
-host_mem_usage 277724 # Number of bytes of host memory used
-host_seconds 103.51 # Real time elapsed on the host
+host_inst_rate 3763101 # Simulator instruction rate (inst/s)
+host_op_rate 3763105 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1881563141 # Simulator tick rate (ticks/s)
+host_mem_usage 229516 # Number of bytes of host memory used
+host_seconds 51.41 # Real time elapsed on the host
sim_insts 193444518 # Number of instructions simulated
sim_ops 193444756 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 11057254439 # Throughput (bytes/s)
+system.membus.data_through_bus 1069490213 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.workload.num_syscalls 401 # Number of system calls
system.cpu.numCycles 193445891 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
sim_ticks 270563082000 # Number of ticks simulated
final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1012263 # Simulator instruction rate (inst/s)
-host_op_rate 1012264 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1415810765 # Simulator tick rate (ticks/s)
-host_mem_usage 286308 # Number of bytes of host memory used
-host_seconds 191.10 # Real time elapsed on the host
+host_inst_rate 942019 # Simulator instruction rate (inst/s)
+host_op_rate 942020 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1317563963 # Simulator tick rate (ticks/s)
+host_mem_usage 238020 # Number of bytes of host memory used
+host_seconds 205.35 # Real time elapsed on the host
sim_insts 193444518 # Number of instructions simulated
sim_ops 193444756 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 1223641 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 4095 # Transaction distribution
+system.membus.trans_dist::ReadResp 4095 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1078 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1078 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 10346 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 10346 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 331072 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 331072 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 331072 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 5173000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 46557000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.workload.num_syscalls 401 # Number of system calls
system.cpu.numCycles 541126164 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 3279915 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 12786 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 24576 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3154 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 27730 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 786432 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 100992 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 887424 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 887424 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 6935000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.144599 # Number of seconds simulated
-sim_ticks 144599413000 # Number of ticks simulated
-final_tick 144599413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.144456 # Number of seconds simulated
+sim_ticks 144456233500 # Number of ticks simulated
+final_tick 144456233500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 53694 # Simulator instruction rate (inst/s)
-host_op_rate 89995 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 58787129 # Simulator tick rate (ticks/s)
-host_mem_usage 325332 # Number of bytes of host memory used
-host_seconds 2459.71 # Real time elapsed on the host
+host_inst_rate 58579 # Simulator instruction rate (inst/s)
+host_op_rate 98184 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 64072469 # Simulator tick rate (ticks/s)
+host_mem_usage 278680 # Number of bytes of host memory used
+host_seconds 2254.58 # Real time elapsed on the host
sim_insts 132071192 # Number of instructions simulated
sim_ops 221362962 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 217792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 217280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 125312 # Number of bytes read from this memory
-system.physmem.bytes_read::total 343104 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 217792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 217792 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 3403 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 342592 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 217280 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 217280 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 3395 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1958 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 5361 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1506175 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 866615 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2372790 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1506175 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1506175 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1506175 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 866615 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2372790 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 5365 # Total number of read requests seen
+system.physmem.num_reads::total 5353 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1504123 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 867474 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2371597 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1504123 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1504123 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1504123 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 867474 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2371597 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 5356 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 5519 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 343104 # Total number of bytes read from memory
+system.physmem.cpureqs 5495 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 342592 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 343104 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 342592 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 154 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 279 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 290 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 322 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 281 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 310 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 374 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 370 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 382 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 374 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 377 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 361 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 349 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 366 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 337 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 344 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 249 # Track reads on a per bank basis
+system.physmem.neitherReadNorWrite 139 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 290 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 357 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 448 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 355 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 333 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 327 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 397 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 380 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 339 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 278 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 230 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 277 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 210 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 465 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 387 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 283 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 144599380000 # Total gap between requests
+system.physmem.totGap 144456205000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 5365 # Categorize read packet sizes
+system.physmem.readPktSize::6 5356 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 4242 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 901 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 182 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 35 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 4319 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 866 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 147 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 15365500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 134288000 # Sum of mem lat for all requests
-system.physmem.totBusLat 26825000 # Total cycles spent in databus access
-system.physmem.totBankLat 92097500 # Total cycles spent in bank access
-system.physmem.avgQLat 2864.03 # Average queueing delay per request
-system.physmem.avgBankLat 17166.36 # Average bank access latency per request
-system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 25030.38 # Average memory access latency
+system.physmem.bytesPerActivate::samples 510 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 662.337255 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 234.191565 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 1287.834177 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 176 34.51% 34.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-129 77 15.10% 49.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-193 39 7.65% 57.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-257 29 5.69% 62.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-321 22 4.31% 67.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-385 12 2.35% 69.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-449 18 3.53% 73.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-513 5 0.98% 74.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-577 13 2.55% 76.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-641 6 1.18% 77.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-705 3 0.59% 78.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-769 6 1.18% 79.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-833 3 0.59% 80.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-897 6 1.18% 81.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-961 7 1.37% 82.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1025 5 0.98% 83.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1089 1 0.20% 83.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1153 6 1.18% 85.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1217 2 0.39% 85.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1281 2 0.39% 85.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1345 2 0.39% 86.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1409 6 1.18% 87.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1473 1 0.20% 87.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1537 3 0.59% 88.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1601 3 0.59% 88.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1665 1 0.20% 89.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1729 2 0.39% 89.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1793 1 0.20% 89.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1857 2 0.39% 90.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1921 3 0.59% 90.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-1985 1 0.20% 90.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2049 3 0.59% 91.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2177 1 0.20% 91.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2241 4 0.78% 92.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2305 1 0.20% 92.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2433 3 0.59% 93.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2497 2 0.39% 93.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2625 1 0.20% 93.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2689 1 0.20% 93.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2817 4 0.78% 94.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2881 1 0.20% 94.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-2945 1 0.20% 95.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3393 2 0.39% 95.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3457 1 0.20% 95.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3520-3521 2 0.39% 96.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3584-3585 2 0.39% 96.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3648-3649 1 0.20% 96.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4096-4097 1 0.20% 96.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4160-4161 1 0.20% 97.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4288-4289 1 0.20% 97.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4352-4353 1 0.20% 97.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4480-4481 1 0.20% 97.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::4544-4545 1 0.20% 97.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5312-5313 1 0.20% 98.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::5888-5889 1 0.20% 98.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6272-6273 1 0.20% 98.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6592-6593 1 0.20% 98.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::6912-6913 1 0.20% 98.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8128-8129 1 0.20% 99.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 5 0.98% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 510 # Bytes accessed per row activation
+system.physmem.totQLat 13729500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 120235750 # Sum of mem lat for all requests
+system.physmem.totBusLat 26770000 # Total cycles spent in databus access
+system.physmem.totBankLat 79736250 # Total cycles spent in bank access
+system.physmem.avgQLat 2563.39 # Average queueing delay per request
+system.physmem.avgBankLat 14887.28 # Average bank access latency per request
+system.physmem.avgBusLat 4998.13 # Average bus latency per request
+system.physmem.avgMemAccLat 22448.80 # Average memory access latency
system.physmem.avgRdBW 2.37 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2.37 # Average consumed read bandwidth in MB/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 4467 # Number of row buffer hits during reads
+system.physmem.readRowHits 4844 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.26 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 90.44 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 26952354.15 # Average gap between requests
-system.cpu.branchPred.lookups 18673504 # Number of BP lookups
-system.cpu.branchPred.condPredicted 18673504 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1493262 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 11432454 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 10793701 # Number of BTB hits
+system.physmem.avgGap 26970912.06 # Average gap between requests
+system.membus.throughput 2371597 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 3826 # Transaction distribution
+system.membus.trans_dist::ReadResp 3823 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 139 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 139 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1530 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1530 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10987 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 10987 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port 10987 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 10987 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 342592 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 342592 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.physmem.port 342592 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 342592 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 342592 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 7029500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 50887361 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu.branchPred.lookups 18668412 # Number of BP lookups
+system.cpu.branchPred.condPredicted 18668412 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1491215 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 11464480 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 10808529 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 94.412809 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1324082 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 23521 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 94.278406 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1321942 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 23508 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 400 # Number of system calls
-system.cpu.numCycles 289482612 # number of cpu cycles simulated
+system.cpu.numCycles 289199941 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 23502455 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 207109778 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 18673504 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 12117783 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 54283022 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 15594841 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 178283916 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 1444 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 8051 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 37 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 22396392 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 221801 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 269918552 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.268498 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.756525 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 23489092 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 206857811 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 18668412 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 12130471 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 54260755 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 15560780 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 178047703 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 1375 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 7863 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 75 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 22383448 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 227467 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 269615649 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.269321 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.757232 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 217073469 80.42% 80.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 2850604 1.06% 81.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 2315423 0.86% 82.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2639736 0.98% 83.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 3229574 1.20% 84.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 3384900 1.25% 85.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 3844403 1.42% 87.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 2562175 0.95% 88.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 32018268 11.86% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 216795166 80.41% 80.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 2848237 1.06% 81.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 2316890 0.86% 82.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2640281 0.98% 83.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 3221568 1.19% 84.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 3391687 1.26% 85.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 3836150 1.42% 87.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 2560999 0.95% 88.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 32004671 11.87% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 269918552 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.064506 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.715448 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 36985977 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 167209662 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 41646466 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 10236820 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 13839627 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 336463810 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 13839627 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 45047343 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 116751427 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 32413 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 42745141 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 51502601 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 330086802 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 10951 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 26152362 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 22736681 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 256 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 382815435 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 919037508 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 910796649 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 8240859 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 269615649 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.064552 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.715276 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 36944387 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 167005183 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 41608261 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 10249032 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 13808786 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 336293429 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 13808786 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 45003701 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 116679127 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 28084 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 42750473 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 51345478 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 329924152 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 10957 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 26042658 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 22711387 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 324 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 382665072 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 918469595 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 910237815 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 8231780 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 259428606 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 123386829 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2258 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2296 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 105258591 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 84679198 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 30165066 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 58703856 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 19098571 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 323202869 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 4566 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 260671940 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 116724 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 101460757 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 211331898 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 3321 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 269918552 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.965743 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.342643 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 123236466 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2077 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2071 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 105014998 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 84558511 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 30136347 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 58291555 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 18982732 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 322974285 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 4304 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 260692143 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 115978 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 101227039 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 210564251 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 3059 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 269615649 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.966903 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.344359 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 143572602 53.19% 53.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 55645964 20.62% 73.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 34208859 12.67% 86.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 19077068 7.07% 93.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 10849323 4.02% 97.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 4139320 1.53% 99.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1825268 0.68% 99.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 469630 0.17% 99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 130518 0.05% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 143415763 53.19% 53.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 55488403 20.58% 73.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 34156757 12.67% 86.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 19088088 7.08% 93.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 10888681 4.04% 97.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 4144802 1.54% 99.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1820810 0.68% 99.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 476392 0.18% 99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 135953 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 269918552 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 269615649 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 131441 4.84% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 2279294 83.91% 88.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 305503 11.25% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 130533 4.80% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 4.80% # attempts to use FU when none available
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+system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 2283697 84.00% 88.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 304445 11.20% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 1210514 0.46% 0.46% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 162160673 62.21% 62.67% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 788045 0.30% 62.98% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 7035797 2.70% 65.67% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 1444934 0.55% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 65461399 25.11% 91.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 22570578 8.66% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 1210883 0.46% 0.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 162146963 62.20% 62.66% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 788849 0.30% 62.97% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 7035772 2.70% 65.66% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 1445624 0.55% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.22% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 65501773 25.13% 91.35% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 22562279 8.65% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 260671940 # Type of FU issued
-system.cpu.iq.rate 0.900475 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 2716238 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010420 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 789209442 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 421320217 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 255304788 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 4885952 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 3632838 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 2349442 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 259718878 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 2458786 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 18858463 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 260692143 # Type of FU issued
+system.cpu.iq.rate 0.901425 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 2718675 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.010429 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 788942081 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 420863494 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 255312010 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 4892507 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 3626050 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 2350305 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 259737433 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 2462502 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 18945833 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 28029611 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 25725 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 290431 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 9649349 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 27908924 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 26612 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 289609 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 9620630 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 49573 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 51419 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 13839627 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 84981347 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 5427028 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 323207435 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 136147 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 84679198 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 30165066 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2231 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 2677235 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 14355 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 290431 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 637937 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 905599 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1543536 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 258899576 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 64693791 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1772364 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 13808786 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 85007909 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 5442016 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 322978589 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 134528 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 84558511 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 30136347 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 2042 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 2673918 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 13520 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 289609 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 642268 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 899522 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1541790 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 258904579 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 64718726 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1787564 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 87060323 # number of memory reference insts executed
-system.cpu.iew.exec_branches 14273836 # Number of branches executed
-system.cpu.iew.exec_stores 22366532 # Number of stores executed
-system.cpu.iew.exec_rate 0.894353 # Inst execution rate
-system.cpu.iew.wb_sent 258261406 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 257654230 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 206076672 # num instructions producing a value
-system.cpu.iew.wb_consumers 369295783 # num instructions consuming a value
+system.cpu.iew.exec_refs 87077956 # number of memory reference insts executed
+system.cpu.iew.exec_branches 14272272 # Number of branches executed
+system.cpu.iew.exec_stores 22359230 # Number of stores executed
+system.cpu.iew.exec_rate 0.895244 # Inst execution rate
+system.cpu.iew.wb_sent 258260440 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 257662315 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 206077428 # num instructions producing a value
+system.cpu.iew.wb_consumers 369317966 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.890051 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.558026 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.890949 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.557995 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 101920014 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 101692643 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1494473 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 256078925 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.864433 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.651734 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1492367 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 255806863 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.865352 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.655114 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 156603135 61.15% 61.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 57289650 22.37% 83.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 14093127 5.50% 89.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 12068952 4.71% 93.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 4185763 1.63% 95.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 2969218 1.16% 96.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 905577 0.35% 96.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1050426 0.41% 97.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 6913077 2.70% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 156513813 61.18% 61.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 57168789 22.35% 83.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 14010033 5.48% 89.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 12060678 4.71% 93.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 4174757 1.63% 95.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 2964012 1.16% 96.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 898257 0.35% 96.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 1048749 0.41% 97.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 6967775 2.72% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 256078925 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 255806863 # Number of insts commited each cycle
system.cpu.commit.committedInsts 132071192 # Number of instructions committed
system.cpu.commit.committedOps 221362962 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
system.cpu.commit.int_insts 220339553 # Number of committed integer instructions.
system.cpu.commit.function_calls 797818 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 6913077 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 6967775 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 572448824 # The number of ROB reads
-system.cpu.rob.rob_writes 660431667 # The number of ROB writes
-system.cpu.timesIdled 5928357 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 19564060 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 571894693 # The number of ROB reads
+system.cpu.rob.rob_writes 659945778 # The number of ROB writes
+system.cpu.timesIdled 5917549 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 19584292 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 132071192 # Number of Instructions Simulated
system.cpu.committedOps 221362962 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 132071192 # Number of Instructions Simulated
-system.cpu.cpi 2.191868 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.191868 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.456232 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.456232 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 554310914 # number of integer regfile reads
-system.cpu.int_regfile_writes 293915019 # number of integer regfile writes
-system.cpu.fp_regfile_reads 3215317 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2009393 # number of floating regfile writes
-system.cpu.misc_regfile_reads 133439176 # number of misc regfile reads
+system.cpu.cpi 2.189728 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.189728 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.456678 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.456678 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 554359034 # number of integer regfile reads
+system.cpu.int_regfile_writes 293931276 # number of integer regfile writes
+system.cpu.fp_regfile_reads 3216619 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2010069 # number of floating regfile writes
+system.cpu.misc_regfile_reads 133442201 # number of misc regfile reads
system.cpu.misc_regfile_writes 845 # number of misc regfile writes
-system.cpu.icache.replacements 4633 # number of replacements
-system.cpu.icache.tagsinuse 1627.424900 # Cycle average of tags in use
-system.cpu.icache.total_refs 22387705 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 6601 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 3391.562642 # Average number of references to valid blocks.
+system.cpu.toL2Bus.throughput 3896100 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 7248 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 7244 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 13 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 139 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 139 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1537 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1537 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 13426 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 4292 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 17718 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 425152 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 128768 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 553920 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 553920 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 8896 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 4481500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 10173000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 3068000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu.icache.replacements 4678 # number of replacements
+system.cpu.icache.tagsinuse 1622.603356 # Cycle average of tags in use
+system.cpu.icache.total_refs 22374543 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 6643 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 3368.138341 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1627.424900 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.794641 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.794641 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 22387705 # number of ReadReq hits
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-system.cpu.icache.demand_hits::cpu.inst 22387705 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 22387705 # number of demand (read+write) hits
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-system.cpu.icache.overall_hits::total 22387705 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 8687 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 8687 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 8687 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 8687 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 8687 # number of overall misses
-system.cpu.icache.overall_misses::total 8687 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 264464000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 264464000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 264464000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 264464000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 264464000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 264464000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 22396392 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 22396392 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total 22396392 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 22396392 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 22396392 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000388 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000388 # miss rate for ReadReq accesses
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-system.cpu.icache.demand_miss_rate::total 0.000388 # miss rate for demand accesses
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-system.cpu.icache.overall_miss_rate::total 0.000388 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30443.651433 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 30443.651433 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 30443.651433 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 30443.651433 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 30443.651433 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 30443.651433 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 666 # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst 1622.603356 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.792287 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.792287 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 22374545 # number of ReadReq hits
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+system.cpu.icache.ReadReq_misses::cpu.inst 8903 # number of ReadReq misses
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+system.cpu.icache.ReadReq_accesses::cpu.inst 22383448 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.overall_miss_rate::total 0.000398 # miss rate for overall accesses
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 39308.210715 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 39308.210715 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 1033 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 41.625000 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 57.388889 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1931 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 1931 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 1931 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 1931 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 1931 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 1931 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6756 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 6756 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 6756 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 6756 # number of demand (read+write) MSHR misses
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-system.cpu.icache.overall_mshr_misses::total 6756 # number of overall MSHR misses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30132.252812 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 30132.252812 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30132.252812 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 30132.252812 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30132.252812 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 30132.252812 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2120 # number of ReadReq MSHR hits
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+system.cpu.icache.demand_mshr_misses::total 6783 # number of demand (read+write) MSHR misses
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+system.cpu.icache.demand_mshr_miss_latency::total 262758000 # number of demand (read+write) MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total 262758000 # number of overall MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_rate::total 0.000303 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38737.726670 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38737.726670 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38737.726670 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 38737.726670 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38737.726670 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 38737.726670 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 2558.702101 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 3231 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 3835 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.842503 # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 2546.215814 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 3285 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 3827 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.858375 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 1.875617 # Average occupied blocks per requestor
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35649.372414 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35963.591951 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35103.934727 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35649.372414 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50563.398693 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50563.398693 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53370.877503 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52627.740948 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53098.842636 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53370.877503 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52627.740948 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53098.842636 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 54 # number of replacements
-system.cpu.dcache.tagsinuse 1433.982512 # Cycle average of tags in use
-system.cpu.dcache.total_refs 66194680 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1993 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 33213.587556 # Average number of references to valid blocks.
+system.cpu.dcache.replacements 56 # number of replacements
+system.cpu.dcache.tagsinuse 1435.278677 # Cycle average of tags in use
+system.cpu.dcache.total_refs 66130970 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1999 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 33082.026013 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 1433.982512 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.350093 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.350093 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 45680422 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 45680422 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 20514038 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 20514038 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 66194460 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 66194460 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 66194460 # number of overall hits
-system.cpu.dcache.overall_hits::total 66194460 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 872 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 872 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1693 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1693 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2565 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2565 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2565 # number of overall misses
-system.cpu.dcache.overall_misses::total 2565 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 43604500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 43604500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 76098000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 76098000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 119702500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 119702500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 119702500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 119702500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 45681294 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 45681294 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.occ_blocks::cpu.data 1435.278677 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.350410 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.350410 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 45616715 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 45616715 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 20514054 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 20514054 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 66130769 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 66130769 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 66130769 # number of overall hits
+system.cpu.dcache.overall_hits::total 66130769 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 933 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 933 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1677 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1677 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 2610 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2610 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2610 # number of overall misses
+system.cpu.dcache.overall_misses::total 2610 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 56235500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 56235500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 104835500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 104835500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 161071000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 161071000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 161071000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 161071000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 45617648 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 45617648 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 66197025 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 66197025 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 66197025 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 66197025 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000083 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000083 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 66133379 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 66133379 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 66133379 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 66133379 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000082 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000082 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000039 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000039 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000039 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000039 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50005.160550 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 50005.160550 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44948.611931 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 44948.611931 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 46667.641326 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 46667.641326 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 46667.641326 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 46667.641326 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 170 # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60273.847803 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 60273.847803 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62513.714967 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 62513.714967 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 61713.026820 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 61713.026820 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 61713.026820 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 61713.026820 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 227 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 56.666667 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 75.666667 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 13 # number of writebacks
system.cpu.dcache.writebacks::total 13 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 414 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 414 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 415 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 415 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 415 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 415 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 458 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1692 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1692 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2150 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2150 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2150 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2150 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26607000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 26607000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 72678500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 72678500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 99285500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 99285500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 99285500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 99285500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 467 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 467 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 469 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 469 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 469 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 469 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 466 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 466 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1675 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1675 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2141 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2141 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2141 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2141 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32012500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 32012500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 101366000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 101366000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133378500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 133378500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133378500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 133378500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000082 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58093.886463 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58093.886463 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42954.196217 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42954.196217 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46179.302326 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 46179.302326 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46179.302326 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 46179.302326 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68696.351931 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68696.351931 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60517.014925 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60517.014925 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62297.290986 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 62297.290986 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62297.290986 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 62297.290986 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
system.physmem.bw_total::cpu.inst 10563380223 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3122279959 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13685660183 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 13685660183 # Throughput (bytes/s)
+system.membus.data_through_bus 1798200879 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 262786137 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 1207552 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 3160 # Transaction distribution
+system.membus.trans_dist::ReadResp 3160 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1575 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1575 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port 9470 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 303040 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 4753500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 42633500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 501907914 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 1684707 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 5021 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1578 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1578 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 9388 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3817 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 13205 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 300416 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 122368 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 422784 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 422784 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 7041000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
sim_ticks 1870325497500 # Number of ticks simulated
final_tick 1870325497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3609656 # Simulator instruction rate (inst/s)
-host_op_rate 3609654 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 106905838632 # Simulator tick rate (ticks/s)
-host_mem_usage 305660 # Number of bytes of host memory used
-host_seconds 17.50 # Real time elapsed on the host
+host_inst_rate 3096593 # Simulator instruction rate (inst/s)
+host_op_rate 3096591 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 91710635166 # Simulator tick rate (ticks/s)
+host_mem_usage 308248 # Number of bytes of host memory used
+host_seconds 20.39 # Real time elapsed on the host
sim_insts 63151114 # Number of instructions simulated
sim_ops 63151114 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 760896 # Number of bytes read from this memory
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation
system.physmem.totQLat 0 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
system.physmem.totBusLat 0 # Total cycles spent in databus access
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap nan # Average gap between requests
+system.membus.throughput 42148404 # Throughput (bytes/s)
+system.membus.data_through_bus 78831234 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.l2c.replacements 1000406 # number of replacements
system.l2c.tagsinuse 65381.817483 # Cycle average of tags in use
system.l2c.total_refs 2465980 # Total number of references to valid blocks.
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+system.toL2Bus.throughput 131960056 # Throughput (bytes/s)
+system.toL2Bus.data_through_bus 246797826 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 10432 # Total snoop data (bytes)
+system.iobus.throughput 1460513 # Throughput (bytes/s)
+system.iobus.data_through_bus 2731634 # Total data (bytes)
system.cpu0.icache.replacements 883989 # number of replacements
system.cpu0.icache.tagsinuse 511.244895 # Cycle average of tags in use
system.cpu0.icache.total_refs 56307893 # Total number of references to valid blocks.
sim_ticks 1829330593000 # Number of ticks simulated
final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3233953 # Simulator instruction rate (inst/s)
-host_op_rate 3233951 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 98537371937 # Simulator tick rate (ticks/s)
-host_mem_usage 303612 # Number of bytes of host memory used
-host_seconds 18.56 # Real time elapsed on the host
+host_inst_rate 1529223 # Simulator instruction rate (inst/s)
+host_op_rate 1529222 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 46594888750 # Simulator tick rate (ticks/s)
+host_mem_usage 306208 # Number of bytes of host memory used
+host_seconds 39.26 # Real time elapsed on the host
sim_insts 60037737 # Number of instructions simulated
sim_ops 60037737 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation
system.physmem.totQLat 0 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
system.physmem.totBusLat 0 # Total cycles spent in databus access
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap nan # Average gap between requests
+system.membus.throughput 42552299 # Throughput (bytes/s)
+system.membus.data_through_bus 77842222 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.iocache.replacements 41686 # number of replacements
system.iocache.tagsinuse 1.225558 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+system.iobus.throughput 1480182 # Throughput (bytes/s)
+system.iobus.data_through_bus 2707742 # Total data (bytes)
system.cpu.icache.replacements 919577 # number of replacements
system.cpu.icache.tagsinuse 511.215229 # Cycle average of tags in use
system.cpu.icache.total_refs 59129371 # Total number of references to valid blocks.
system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks
system.cpu.dcache.writebacks::total 833491 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 132867618 # Throughput (bytes/s)
+system.cpu.toL2Bus.data_through_bus 243048686 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 10112 # Total snoop data (bytes)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 1.955749 # Number of seconds simulated
-sim_ticks 1955749107000 # Number of ticks simulated
-final_tick 1955749107000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.959865 # Number of seconds simulated
+sim_ticks 1959865139500 # Number of ticks simulated
+final_tick 1959865139500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 473674 # Simulator instruction rate (inst/s)
-host_op_rate 473674 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 15599111797 # Simulator tick rate (ticks/s)
-host_mem_usage 350548 # Number of bytes of host memory used
-host_seconds 125.38 # Real time elapsed on the host
-sim_insts 59387196 # Number of instructions simulated
-sim_ops 59387196 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 829760 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24747584 # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 34368 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 397760 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28660288 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 829760 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 34368 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 864128 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7682240 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7682240 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 12965 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 386681 # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 537 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 6215 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 447817 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 120035 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 120035 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 424267 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 12653762 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1355397 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 17573 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 203380 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 14654379 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 424267 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 17573 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 441840 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3928029 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3928029 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3928029 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 424267 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 12653762 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1355397 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 17573 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 203380 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 18582408 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 447817 # Total number of read requests seen
-system.physmem.writeReqs 120035 # Total number of write requests seen
-system.physmem.cpureqs 571031 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 28660288 # Total number of bytes read from memory
-system.physmem.bytesWritten 7682240 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 28660288 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7682240 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 69 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 3170 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 28165 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 28096 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 28057 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 27780 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 28035 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 27969 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 27895 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 27905 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 28286 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 28089 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 28219 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 28029 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 27787 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 27999 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 27702 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 27735 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 7631 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7483 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 7551 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 7343 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7579 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 7442 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7393 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 7470 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 7849 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7658 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7804 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 7534 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 7353 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 7502 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 7171 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 7272 # Track writes on a per bank basis
+host_inst_rate 1047911 # Simulator instruction rate (inst/s)
+host_op_rate 1047910 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 33678986014 # Simulator tick rate (ticks/s)
+host_mem_usage 308256 # Number of bytes of host memory used
+host_seconds 58.19 # Real time elapsed on the host
+sim_insts 60980539 # Number of instructions simulated
+sim_ops 60980539 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 833408 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24886848 # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 31616 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 338688 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28741440 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 833408 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 31616 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7743232 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7743232 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 13022 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 388857 # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 494 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 5292 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 449085 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 120988 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 120988 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 425237 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 12698245 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1352583 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 16132 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 172812 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 14665009 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 425237 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 16132 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 441369 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3950900 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3950900 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3950900 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 425237 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 12698245 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1352583 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 16132 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 172812 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 18615909 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 449085 # Total number of read requests seen
+system.physmem.writeReqs 120988 # Total number of write requests seen
+system.physmem.cpureqs 577269 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 28741440 # Total number of bytes read from memory
+system.physmem.bytesWritten 7743232 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 28741440 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7743232 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 62 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 7195 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 28163 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 28468 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 28046 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 27665 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 27762 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 27794 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 28266 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 27878 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 28077 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 27763 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 27645 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 28133 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 28181 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 28495 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 28656 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 28031 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7932 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7895 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 7532 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 7157 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7275 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 7314 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 7754 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 7257 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7316 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 7137 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7066 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 7523 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7683 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 8132 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 8336 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7679 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 9 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1955741979500 # Total gap between requests
+system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1959858128500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 447817 # Categorize read packet sizes
+system.physmem.readPktSize::6 449085 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 120035 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 407051 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4718 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 3658 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 2202 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3124 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2939 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2694 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 2706 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 2651 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 2603 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1540 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 1456 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 1432 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1384 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 1357 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 1403 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 1635 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 1524 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 905 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 760 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 120988 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 408321 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 7066 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 5331 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 3258 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3264 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 3003 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1531 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 1505 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 1476 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 1451 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 1408 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 1429 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 1415 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 2044 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 2352 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 2212 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 1198 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 461 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 203 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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-system.physmem.totQLat 4786344500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 13401468250 # Sum of mem lat for all requests
-system.physmem.totBusLat 2238740000 # Total cycles spent in databus access
-system.physmem.totBankLat 6376383750 # Total cycles spent in bank access
-system.physmem.avgQLat 10689.82 # Average queueing delay per request
-system.physmem.avgBankLat 14241.01 # Average bank access latency per request
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+system.physmem.bytesPerActivate::samples 40092 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 909.867305 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 223.303664 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 2368.170282 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-67 14180 35.37% 35.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-131 6168 15.38% 50.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-195 3902 9.73% 60.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-259 2490 6.21% 66.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-323 1693 4.22% 70.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-387 1359 3.39% 74.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-451 1096 2.73% 77.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-515 872 2.17% 79.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-579 629 1.57% 80.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-643 634 1.58% 82.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-707 494 1.23% 83.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-771 427 1.07% 84.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-835 257 0.64% 85.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-899 230 0.57% 85.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-963 171 0.43% 86.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1027 248 0.62% 86.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1091 146 0.36% 87.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1155 121 0.30% 87.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1219 95 0.24% 87.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1283 102 0.25% 88.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1347 86 0.21% 88.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1411 112 0.28% 88.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1475 1028 2.56% 91.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1539 203 0.51% 91.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1603 118 0.29% 91.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1667 93 0.23% 92.17% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1792-1795 46 0.11% 92.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1859 38 0.09% 92.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1923 17 0.04% 92.59% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::2048-2051 32 0.08% 92.72% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::2304-2307 5 0.01% 92.81% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::total 40092 # Bytes accessed per row activation
+system.physmem.totQLat 3740449750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 12011516000 # Sum of mem lat for all requests
+system.physmem.totBusLat 2245115000 # Total cycles spent in databus access
+system.physmem.totBankLat 6025951250 # Total cycles spent in bank access
+system.physmem.avgQLat 8330.20 # Average queueing delay per request
+system.physmem.avgBankLat 13420.14 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 29930.83 # Average memory access latency
-system.physmem.avgRdBW 14.65 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 14.65 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 3.93 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 26750.34 # Average memory access latency
+system.physmem.avgRdBW 14.67 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 14.67 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 3.95 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.15 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 6.57 # Average write queue length over time
-system.physmem.readRowHits 419819 # Number of row buffer hits during reads
-system.physmem.writeRowHits 92219 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 93.76 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 76.83 # Row buffer hit rate for writes
-system.physmem.avgGap 3444105.12 # Average gap between requests
-system.l2c.replacements 340805 # number of replacements
-system.l2c.tagsinuse 65304.474621 # Cycle average of tags in use
-system.l2c.total_refs 2495359 # Total number of references to valid blocks.
-system.l2c.sampled_refs 405916 # Sample count of references to valid blocks.
-system.l2c.avg_refs 6.147476 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 6939667751 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 55622.298055 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 4855.652105 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 4698.077679 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 117.035866 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 11.410916 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.848729 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.074091 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.071687 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.001786 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.000174 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.996467 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst 903439 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 772649 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 86404 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 33735 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1796227 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 821961 # number of Writeback hits
-system.l2c.Writeback_hits::total 821961 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 54 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 223 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 21 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 42 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 172231 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 12736 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 184967 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst 903439 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 944880 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 86404 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 46471 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1981194 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst 903439 # number of overall hits
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
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system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
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-system.cpu0.kern.ipl_count::22 1976 1.10% 41.80% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 7 0.00% 41.80% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 104234 58.20% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 179099 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 71384 49.27% 49.27% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1976 1.36% 50.73% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 7 0.00% 50.73% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 71377 49.27% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 144875 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1898825619000 97.12% 97.12% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 94636000 0.00% 97.13% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 768885000 0.04% 97.17% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 5899500 0.00% 97.17% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 55387314500 2.83% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1955082354000 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.981210 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce 6830 # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei 164217 # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0 56358 40.22% 40.22% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21 131 0.09% 40.31% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22 1973 1.41% 41.72% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30 445 0.32% 42.04% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 81223 57.96% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 140130 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 55870 49.08% 49.08% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22 1973 1.73% 50.92% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30 445 0.39% 51.31% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31 55425 48.69% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total 113844 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0 1901694919500 97.03% 97.03% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 94927000 0.00% 97.04% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 766727000 0.04% 97.08% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30 329552000 0.02% 97.09% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 56978256500 2.91% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1959864382000 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.991341 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.684777 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.808910 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
-system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
-system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
-system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed
-system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed
-system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed
-system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed
-system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed
-system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed
-system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed
-system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed
-system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed
-system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed
-system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed
-system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed
-system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed
-system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed
-system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed
-system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed
-system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed
-system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed
-system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed
-system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed
-system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed
-system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed
-system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed
-system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed
-system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed
-system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total 222 # number of syscalls executed
+system.cpu0.kern.ipl_used::31 0.682381 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total 0.812417 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed
+system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed
+system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed
+system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed
+system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed
+system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed
+system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed
+system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed
+system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed
+system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed
+system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed
+system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed
+system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed
+system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed
+system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed
+system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed
+system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed
+system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed
+system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed
+system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed
+system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed
+system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed
+system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed
+system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed
+system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed
+system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed
+system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed
+system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed
+system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total 234 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir 89 0.05% 0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 3897 2.07% 2.12% # number of callpals executed
-system.cpu0.kern.callpal::tbi 51 0.03% 2.15% # number of callpals executed
-system.cpu0.kern.callpal::wrent 7 0.00% 2.15% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 172231 91.49% 93.64% # number of callpals executed
-system.cpu0.kern.callpal::rdps 6679 3.55% 97.19% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp 1 0.00% 97.19% # number of callpals executed
-system.cpu0.kern.callpal::wrusp 3 0.00% 97.19% # number of callpals executed
-system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed
-system.cpu0.kern.callpal::whami 2 0.00% 97.20% # number of callpals executed
-system.cpu0.kern.callpal::rti 4753 2.52% 99.73% # number of callpals executed
-system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed
-system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 188243 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 7307 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1284 # number of protection mode switches
+system.cpu0.kern.callpal::wripir 528 0.36% 0.36% # number of callpals executed
+system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed
+system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed
+system.cpu0.kern.callpal::swpctx 3061 2.06% 2.42% # number of callpals executed
+system.cpu0.kern.callpal::tbi 51 0.03% 2.45% # number of callpals executed
+system.cpu0.kern.callpal::wrent 7 0.00% 2.46% # number of callpals executed
+system.cpu0.kern.callpal::swpipl 133182 89.70% 92.16% # number of callpals executed
+system.cpu0.kern.callpal::rdps 6700 4.51% 96.67% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp 1 0.00% 96.67% # number of callpals executed
+system.cpu0.kern.callpal::wrusp 4 0.00% 96.67% # number of callpals executed
+system.cpu0.kern.callpal::rdusp 9 0.01% 96.68% # number of callpals executed
+system.cpu0.kern.callpal::whami 2 0.00% 96.68% # number of callpals executed
+system.cpu0.kern.callpal::rti 4398 2.96% 99.64% # number of callpals executed
+system.cpu0.kern.callpal::callsys 394 0.27% 99.91% # number of callpals executed
+system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed
+system.cpu0.kern.callpal::total 148480 # number of callpals executed
+system.cpu0.kern.mode_switch::kernel 6996 # number of protection mode switches
+system.cpu0.kern.mode_switch::user 1373 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1284
-system.cpu0.kern.mode_good::user 1284
+system.cpu0.kern.mode_good::kernel 1372
+system.cpu0.kern.mode_good::user 1373
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.175722 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.196112 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.298917 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1951356000500 99.82% 99.82% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 3486973000 0.18% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total 0.327996 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 1956039363000 99.80% 99.80% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 3825014500 0.20% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3898 # number of times the context was actually changed
+system.cpu0.kern.swap_context 3062 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu0.icache.replacements 915791 # number of replacements
-system.cpu0.icache.tagsinuse 509.170825 # Cycle average of tags in use
-system.cpu0.icache.total_refs 53217526 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 916303 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 58.078524 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 32591402000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 509.170825 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.994474 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.994474 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 53217526 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 53217526 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 53217526 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 53217526 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 53217526 # number of overall hits
-system.cpu0.icache.overall_hits::total 53217526 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 916424 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 916424 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 916424 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 916424 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 916424 # number of overall misses
-system.cpu0.icache.overall_misses::total 916424 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12661489500 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 12661489500 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 12661489500 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 12661489500 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 12661489500 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 12661489500 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 54133950 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 54133950 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 54133950 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 54133950 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 54133950 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 54133950 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016929 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.016929 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016929 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.016929 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016929 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.016929 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13816.191523 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13816.191523 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13816.191523 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13816.191523 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13816.191523 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13816.191523 # average overall miss latency
+system.toL2Bus.throughput 103923821 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 2101274 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2101259 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 14151 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 14151 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 790404 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 17004 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 11907 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 28911 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 338243 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 296693 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1383805 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3109039 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 647529 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 472865 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count 5613238 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 44281088 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 118941040 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 20720896 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 17326866 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size 201269890 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 201259586 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 2417088 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 4784493652 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 3113609997 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 5406966495 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 1456953977 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 808879499 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.throughput 1400220 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 7373 # Transaction distribution
+system.iobus.trans_dist::ReadResp 7373 # Transaction distribution
+system.iobus.trans_dist::WriteReq 55703 # Transaction distribution
+system.iobus.trans_dist::WriteResp 55703 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14090 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 42700 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
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+system.iobus.pkt_count::total 126152 # Packet count per connected master and slave (bytes)
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+system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.tot_pkt_size::total 2744242 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 2744242 # Total data (bytes)
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+system.iobus.reqLayer24.occupancy 2453000 # Layer occupancy (ticks)
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+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
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+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
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+system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
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+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14374.666324 # average overall miss latency
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system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
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-system.cpu0.icache.ReadReq_mshr_miss_latency::total 10828641500 # number of ReadReq MSHR miss cycles
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-system.cpu0.icache.demand_mshr_miss_latency::total 10828641500 # number of demand (read+write) MSHR miss cycles
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-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016929 # mshr miss rate for ReadReq accesses
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+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12374.664160 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12374.664160 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 1338546 # number of replacements
-system.cpu0.dcache.tagsinuse 506.515538 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 13360558 # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs 1338960 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 9.978310 # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 94365000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 506.515538 # Average occupied blocks per requestor
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-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193085 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 193085 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192118 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 192118 # number of StoreCondReq accesses(hits+misses)
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-system.cpu0.dcache.ReadReq_miss_rate::total 0.122461 # miss rate for ReadReq accesses
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-system.cpu0.dcache.WriteReq_miss_rate::total 0.049743 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084761 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084761 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002264 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002264 # miss rate for StoreCondReq accesses
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-system.cpu0.dcache.demand_miss_rate::total 0.092726 # miss rate for demand accesses
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-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21589.493287 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 21589.493287 # average ReadReq miss latency
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-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13082.671392 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13082.671392 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5865.517241 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5865.517241 # average StoreCondReq miss latency
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+system.cpu0.dcache.sampled_refs 1182037 # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs 9.654482 # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle 105721000 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::cpu0.data 505.231432 # Average occupied blocks per requestor
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+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30325.200067 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 30325.200067 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 791336 # number of writebacks
-system.cpu0.dcache.writebacks::total 791336 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1036642 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 1036642 # number of ReadReq MSHR misses
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-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16366 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 435 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 435 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 1327950 # number of demand (read+write) MSHR misses
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-system.cpu0.dcache.overall_mshr_misses::total 1327950 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 20307291500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 20307291500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7610535000 # number of WriteReq MSHR miss cycles
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 181379000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1681500 # number of StoreCondReq MSHR miss cycles
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-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122461 # mshr miss rate for ReadReq accesses
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.084761 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.084761 # mshr miss rate for LoadLockedReq accesses
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-system.cpu0.dcache.overall_mshr_miss_rate::total 0.092726 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 19589.493287 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19589.493287 # average ReadReq mshr miss latency
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-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26125.389622 # average WriteReq mshr miss latency
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-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11082.671392 # average LoadLockedReq mshr miss latency
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-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3865.517241 # average StoreCondReq mshr miss latency
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-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21023.251252 # average overall mshr miss latency
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+system.cpu0.dcache.writebacks::writebacks 678820 # number of writebacks
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+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465600500 # number of ReadReq MSHR uncacheable cycles
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+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088239 # mshr miss rate for LoadLockedReq accesses
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+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25982.536006 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25982.536006 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36908.457289 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36908.457289 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8875.370151 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8875.370151 # average LoadLockedReq mshr miss latency
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+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5674.481436 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28325.197974 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28325.197974 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28325.197974 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28325.197974 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 1047303 # DTB read hits
-system.cpu1.dtb.read_misses 2992 # DTB read misses
+system.cpu1.dtb.read_hits 2417907 # DTB read hits
+system.cpu1.dtb.read_misses 2620 # DTB read misses
system.cpu1.dtb.read_acv 0 # DTB read access violations
-system.cpu1.dtb.read_accesses 239363 # DTB read accesses
-system.cpu1.dtb.write_hits 650380 # DTB write hits
-system.cpu1.dtb.write_misses 341 # DTB write misses
-system.cpu1.dtb.write_acv 29 # DTB write access violations
-system.cpu1.dtb.write_accesses 105247 # DTB write accesses
-system.cpu1.dtb.data_hits 1697683 # DTB hits
-system.cpu1.dtb.data_misses 3333 # DTB misses
-system.cpu1.dtb.data_acv 29 # DTB access violations
-system.cpu1.dtb.data_accesses 344610 # DTB accesses
-system.cpu1.itb.fetch_hits 1487846 # ITB hits
-system.cpu1.itb.fetch_misses 1216 # ITB misses
+system.cpu1.dtb.read_accesses 205337 # DTB read accesses
+system.cpu1.dtb.write_hits 1735068 # DTB write hits
+system.cpu1.dtb.write_misses 235 # DTB write misses
+system.cpu1.dtb.write_acv 24 # DTB write access violations
+system.cpu1.dtb.write_accesses 89739 # DTB write accesses
+system.cpu1.dtb.data_hits 4152975 # DTB hits
+system.cpu1.dtb.data_misses 2855 # DTB misses
+system.cpu1.dtb.data_acv 24 # DTB access violations
+system.cpu1.dtb.data_accesses 295076 # DTB accesses
+system.cpu1.itb.fetch_hits 1826925 # ITB hits
+system.cpu1.itb.fetch_misses 1064 # ITB misses
system.cpu1.itb.fetch_acv 0 # ITB acv
-system.cpu1.itb.fetch_accesses 1489062 # ITB accesses
+system.cpu1.itb.fetch_accesses 1827989 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 3911498214 # number of cpu cycles simulated
+system.cpu1.numCycles 3917974909 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 5261846 # Number of instructions committed
-system.cpu1.committedOps 5261846 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 4930311 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses
-system.cpu1.num_func_calls 156775 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 508835 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 4930311 # number of integer instructions
-system.cpu1.num_fp_insts 34031 # number of float instructions
-system.cpu1.num_int_register_reads 6861337 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 3717514 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 22062 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 21862 # number of times the floating registers were written
-system.cpu1.num_mem_refs 1707139 # number of memory refs
-system.cpu1.num_load_insts 1053310 # Number of load instructions
-system.cpu1.num_store_insts 653829 # Number of store instructions
-system.cpu1.num_idle_cycles 3891938527.998010 # Number of idle cycles
-system.cpu1.num_busy_cycles 19559686.001990 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.005001 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.994999 # Percentage of idle cycles
+system.cpu1.committedInsts 13128564 # Number of instructions committed
+system.cpu1.committedOps 13128564 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 12090481 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 177902 # Number of float alu accesses
+system.cpu1.num_func_calls 416956 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 1297332 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 12090481 # number of integer instructions
+system.cpu1.num_fp_insts 177902 # number of float instructions
+system.cpu1.num_int_register_reads 16603924 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 8888139 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 92328 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 94344 # number of times the floating registers were written
+system.cpu1.num_mem_refs 4176284 # number of memory refs
+system.cpu1.num_load_insts 2431879 # Number of load instructions
+system.cpu1.num_store_insts 1744405 # Number of store instructions
+system.cpu1.num_idle_cycles 3867819461.141509 # Number of idle cycles
+system.cpu1.num_busy_cycles 50155447.858491 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.012801 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.987199 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2300 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 35556 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 8967 31.73% 31.73% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1970 6.97% 38.70% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 89 0.31% 39.02% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 17234 60.98% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 28260 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 8957 45.05% 45.05% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1970 9.91% 54.95% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 89 0.45% 55.40% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 8868 44.60% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 19884 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1918859770000 98.11% 98.11% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 708002500 0.04% 98.15% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 60314000 0.00% 98.15% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 36120248500 1.85% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1955748335000 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.998885 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce 2741 # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei 79425 # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0 27091 38.34% 38.34% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22 1969 2.79% 41.13% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30 528 0.75% 41.87% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31 41074 58.13% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total 70662 # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0 26202 48.19% 48.19% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22 1969 3.62% 51.81% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30 528 0.97% 52.78% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31 25675 47.22% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total 54374 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0 1908747944000 97.44% 97.44% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 700841000 0.04% 97.47% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 369371500 0.02% 97.49% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 49169268000 2.51% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1958987424500 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0 0.967185 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.514564 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total 0.703609 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
-system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
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-system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed
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-system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed
-system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed
-system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed
-system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed
-system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total 104 # number of syscalls executed
+system.cpu1.kern.ipl_used::31 0.625091 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total 0.769494 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed
+system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed
+system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed
+system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed
+system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed
+system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed
+system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed
+system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed
+system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed
+system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed
+system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed
+system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed
+system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total 92 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir 7 0.02% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::swpctx 337 1.17% 1.20% # number of callpals executed
-system.cpu1.kern.callpal::tbi 3 0.01% 1.21% # number of callpals executed
-system.cpu1.kern.callpal::wrent 7 0.02% 1.23% # number of callpals executed
-system.cpu1.kern.callpal::swpipl 23668 81.85% 83.08% # number of callpals executed
-system.cpu1.kern.callpal::rdps 2171 7.51% 90.59% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp 1 0.00% 90.59% # number of callpals executed
-system.cpu1.kern.callpal::wrusp 4 0.01% 90.61% # number of callpals executed
-system.cpu1.kern.callpal::whami 3 0.01% 90.62% # number of callpals executed
-system.cpu1.kern.callpal::rti 2532 8.76% 99.37% # number of callpals executed
-system.cpu1.kern.callpal::callsys 136 0.47% 99.84% # number of callpals executed
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+system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed
+system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed
+system.cpu1.kern.callpal::swpctx 2045 2.80% 3.42% # number of callpals executed
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+system.cpu1.kern.callpal::wrent 7 0.01% 3.43% # number of callpals executed
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+system.cpu1.kern.callpal::whami 3 0.00% 94.64% # number of callpals executed
+system.cpu1.kern.callpal::rti 3751 5.14% 99.78% # number of callpals executed
+system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed
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system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 28917 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 802 # number of protection mode switches
-system.cpu1.kern.mode_switch::user 464 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2068 # number of protection mode switches
-system.cpu1.kern.mode_good::kernel 477
-system.cpu1.kern.mode_good::user 464
-system.cpu1.kern.mode_good::idle 13
-system.cpu1.kern.mode_switch_good::kernel 0.594763 # fraction of useful protection mode switches
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+system.cpu1.kern.mode_switch::user 369 # number of protection mode switches
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+system.cpu1.kern.mode_good::kernel 821
+system.cpu1.kern.mode_good::user 369
+system.cpu1.kern.mode_good::idle 452
+system.cpu1.kern.mode_switch_good::kernel 0.411735 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
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-system.cpu1.kern.mode_switch_good::total 0.286143 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 3597793000 0.18% 0.18% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 1722339500 0.09% 0.27% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1950428198000 99.73% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 338 # number of times the context was actually changed
-system.cpu1.icache.replacements 86405 # number of replacements
-system.cpu1.icache.tagsinuse 422.462851 # Cycle average of tags in use
-system.cpu1.icache.total_refs 5178256 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 86917 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 59.577022 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 1939963886500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 422.462851 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.825123 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.825123 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 5178256 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 5178256 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 5178256 # number of demand (read+write) hits
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-system.cpu1.icache.overall_hits::total 5178256 # number of overall hits
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-system.cpu1.icache.ReadReq_misses::total 86953 # number of ReadReq misses
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-system.cpu1.icache.overall_misses::total 86953 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1177160000 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 1177160000 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 1177160000 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 1177160000 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 1177160000 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 1177160000 # number of overall miss cycles
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-system.cpu1.icache.ReadReq_accesses::total 5265209 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 5265209 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 5265209 # number of demand (read+write) accesses
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-system.cpu1.icache.overall_accesses::total 5265209 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016515 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.016515 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016515 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.016515 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016515 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.016515 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13537.888284 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13537.888284 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13537.888284 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13537.888284 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13537.888284 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13537.888284 # average overall miss latency
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+system.cpu1.kern.swap_context 2046 # number of times the context was actually changed
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+system.cpu1.icache.total_refs 12807678 # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs 323725 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 39.563450 # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 1958057375000 # Cycle when the warmup percentage was hit.
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+system.cpu1.icache.ReadReq_accesses::cpu1.inst 13131443 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 13131443 # number of ReadReq accesses(hits+misses)
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+system.cpu1.icache.overall_accesses::total 13131443 # number of overall (read+write) accesses
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+system.cpu1.icache.ReadReq_miss_rate::total 0.024656 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024656 # miss rate for demand accesses
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+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024656 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.024656 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13163.708245 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13163.708245 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13163.708245 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13163.708245 # average overall miss latency
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system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2734500 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2734500 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 892281000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 892281000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 892281000 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 892281000 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19387500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19387500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 530266500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 530266500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 549654000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 549654000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035651 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035651 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032049 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032049 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.079354 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.079354 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.043378 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.043378 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034282 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.034282 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034282 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.034282 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10498.635946 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10498.635946 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24675.412808 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24675.412808 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9000 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9000 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5382.874016 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5382.874016 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15536.574324 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15536.574324 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15536.574324 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15536.574324 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 111584 # number of writebacks
+system.cpu1.dcache.writebacks::total 111584 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118911 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 118911 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58093 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 58093 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9306 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9306 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6171 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 6171 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 177004 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 177004 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 177004 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 177004 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1203056001 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1203056001 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 925664000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 925664000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 65798500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 65798500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32557500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32557500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2128720001 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 2128720001 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2128720001 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 2128720001 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18768000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18768000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 722866000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 722866000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 741634000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 741634000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050156 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050156 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034594 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034594 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.159535 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.159535 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106691 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106691 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043703 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.043703 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043703 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.043703 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10117.281000 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10117.281000 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15934.174513 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15934.174513 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7070.545884 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7070.545884 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5275.887214 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5275.887214 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12026.394889 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12026.394889 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12026.394889 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12026.394889 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 1.913475 # Number of seconds simulated
-sim_ticks 1913474690000 # Number of ticks simulated
-final_tick 1913474690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.918467 # Number of seconds simulated
+sim_ticks 1918467182000 # Number of ticks simulated
+final_tick 1918467182000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 985591 # Simulator instruction rate (inst/s)
-host_op_rate 985591 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 33597920761 # Simulator tick rate (ticks/s)
-host_mem_usage 329492 # Number of bytes of host memory used
-host_seconds 56.95 # Real time elapsed on the host
-sim_insts 56131527 # Number of instructions simulated
-sim_ops 56131527 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24859456 # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 2652096 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28362112 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7404992 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7404992 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 388429 # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 41439 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 443158 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 115703 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 115703 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 444511 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 12991787 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1386010 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 14822308 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 444511 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 444511 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3869919 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3869919 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3869919 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 444511 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 12991787 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1386010 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 18692227 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 443158 # Total number of read requests seen
-system.physmem.writeReqs 115703 # Total number of write requests seen
-system.physmem.cpureqs 559001 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 28362112 # Total number of bytes read from memory
-system.physmem.bytesWritten 7404992 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 28362112 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7404992 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 61 # Number of read reqs serviced by write Q
+host_inst_rate 829809 # Simulator instruction rate (inst/s)
+host_op_rate 829809 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 28329510825 # Simulator tick rate (ticks/s)
+host_mem_usage 306208 # Number of bytes of host memory used
+host_seconds 67.72 # Real time elapsed on the host
+sim_insts 56194431 # Number of instructions simulated
+sim_ops 56194431 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24859200 # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28362304 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7404544 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7404544 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 388425 # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 443161 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 115696 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 115696 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 443454 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 12957845 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1382537 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 14783836 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 443454 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 443454 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3859615 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3859615 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3859615 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 443454 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 12957845 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1382537 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 18643451 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 443161 # Total number of read requests seen
+system.physmem.writeReqs 115696 # Total number of write requests seen
+system.physmem.cpureqs 558987 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 28362304 # Total number of bytes read from memory
+system.physmem.bytesWritten 7404544 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 28362304 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7404544 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 54 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 27906 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 27707 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 27556 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 27383 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 27676 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 27765 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 27828 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 27614 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 28005 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 27777 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 27792 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 27558 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 27591 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 27731 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 27648 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 27560 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 7488 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7264 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 7148 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 7040 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7173 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 7213 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7315 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 7181 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 7581 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7357 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7354 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 7063 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 7148 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 7186 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 7115 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 7077 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::0 27850 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 28128 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 28329 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 28032 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 27520 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 27540 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 26738 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 26867 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 27896 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 27091 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 27744 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 27474 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 27482 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 28202 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 28119 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 28095 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7621 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7634 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 7863 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 7544 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7117 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 6982 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 6321 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 6315 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7316 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 6513 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7108 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 6910 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7064 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 7822 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7859 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7707 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1913462790000 # Total gap between requests
+system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1918455311000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 443158 # Categorize read packet sizes
+system.physmem.readPktSize::6 443161 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 115703 # Categorize write packet sizes
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-system.physmem.rdQLenPdf::6 2701 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see
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-system.physmem.totQLat 4710239250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 13222743000 # Sum of mem lat for all requests
-system.physmem.totBusLat 2215485000 # Total cycles spent in databus access
-system.physmem.totBankLat 6297018750 # Total cycles spent in bank access
-system.physmem.avgQLat 10630.27 # Average queueing delay per request
-system.physmem.avgBankLat 14211.38 # Average bank access latency per request
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+system.physmem.bytesPerActivate::samples 37346 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 957.575108 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 229.677714 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 2441.521254 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-67 13136 35.17% 35.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-131 5703 15.27% 50.44% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::384-387 1358 3.64% 73.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-451 966 2.59% 76.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-515 781 2.09% 78.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-579 632 1.69% 79.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-643 563 1.51% 81.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-707 543 1.45% 82.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-771 430 1.15% 84.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-835 310 0.83% 84.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-899 236 0.63% 85.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-963 166 0.44% 85.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1027 218 0.58% 86.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1091 124 0.33% 86.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1155 90 0.24% 87.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1219 81 0.22% 87.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1283 99 0.27% 87.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1347 87 0.23% 87.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1411 95 0.25% 88.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1475 1075 2.88% 90.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1539 150 0.40% 91.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1603 90 0.24% 91.56% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::1856-1859 29 0.08% 91.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1923 22 0.06% 92.03% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::2048-2051 29 0.08% 92.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2115 17 0.05% 92.21% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::2240-2243 12 0.03% 92.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2307 7 0.02% 92.27% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::2496-2499 3 0.01% 92.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2627 6 0.02% 92.33% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::total 37346 # Bytes accessed per row activation
+system.physmem.totQLat 3689041500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 11833576500 # Sum of mem lat for all requests
+system.physmem.totBusLat 2215535000 # Total cycles spent in databus access
+system.physmem.totBankLat 5929000000 # Total cycles spent in bank access
+system.physmem.avgQLat 8325.40 # Average queueing delay per request
+system.physmem.avgBankLat 13380.52 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 29841.64 # Average memory access latency
-system.physmem.avgRdBW 14.82 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 3.87 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 14.82 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 3.87 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 26705.91 # Average memory access latency
+system.physmem.avgRdBW 14.78 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 14.78 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 3.86 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.15 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 9.64 # Average write queue length over time
-system.physmem.readRowHits 415747 # Number of row buffer hits during reads
-system.physmem.writeRowHits 89943 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 93.83 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 77.74 # Row buffer hit rate for writes
-system.physmem.avgGap 3423861.73 # Average gap between requests
+system.physmem.avgWrQLen 11.67 # Average write queue length over time
+system.physmem.readRowHits 427971 # Number of row buffer hits during reads
+system.physmem.writeRowHits 93480 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 96.58 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes
+system.physmem.avgGap 3432819.69 # Average gap between requests
+system.membus.throughput 18685123 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 292355 # Transaction distribution
+system.membus.trans_dist::ReadResp 292355 # Transaction distribution
+system.membus.trans_dist::WriteReq 9649 # Transaction distribution
+system.membus.trans_dist::WriteResp 9649 # Transaction distribution
+system.membus.trans_dist::Writeback 115696 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 132 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 132 # Transaction distribution
+system.membus.trans_dist::ReadExReq 158289 # Transaction distribution
+system.membus.trans_dist::ReadExResp 158289 # Transaction distribution
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+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911311 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes)
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+system.membus.pkt_count::system.bridge.slave 33158 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port 1002833 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1035991 # Packet count per connected master and slave (bytes)
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+system.membus.tot_pkt_size::system.physmem.port 35766848 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 35811404 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 35811404 # Total data (bytes)
+system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 32374500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
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+system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
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+system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
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system.iocache.replacements 41685 # number of replacements
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system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
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system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
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system.iocache.overall_misses::total 41725 # number of overall misses
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system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
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system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
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system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
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system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
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system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
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-system.iocache.demand_avg_mshr_miss_latency::total 203791.376777 # average overall mshr miss latency
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system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 9056964 # DTB read hits
-system.cpu.dtb.read_misses 10329 # DTB read misses
+system.cpu.dtb.read_hits 9066498 # DTB read hits
+system.cpu.dtb.read_misses 10324 # DTB read misses
system.cpu.dtb.read_acv 210 # DTB read access violations
-system.cpu.dtb.read_accesses 728856 # DTB read accesses
-system.cpu.dtb.write_hits 6352252 # DTB write hits
+system.cpu.dtb.read_accesses 728853 # DTB read accesses
+system.cpu.dtb.write_hits 6357377 # DTB write hits
system.cpu.dtb.write_misses 1142 # DTB write misses
system.cpu.dtb.write_acv 157 # DTB write access violations
system.cpu.dtb.write_accesses 291931 # DTB write accesses
-system.cpu.dtb.data_hits 15409216 # DTB hits
-system.cpu.dtb.data_misses 11471 # DTB misses
+system.cpu.dtb.data_hits 15423875 # DTB hits
+system.cpu.dtb.data_misses 11466 # DTB misses
system.cpu.dtb.data_acv 367 # DTB access violations
-system.cpu.dtb.data_accesses 1020787 # DTB accesses
-system.cpu.itb.fetch_hits 4974658 # ITB hits
-system.cpu.itb.fetch_misses 5006 # ITB misses
+system.cpu.dtb.data_accesses 1020784 # DTB accesses
+system.cpu.itb.fetch_hits 4974559 # ITB hits
+system.cpu.itb.fetch_misses 5010 # ITB misses
system.cpu.itb.fetch_acv 184 # ITB acv
-system.cpu.itb.fetch_accesses 4979664 # ITB accesses
+system.cpu.itb.fetch_accesses 4979569 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 3826949380 # number of cpu cycles simulated
+system.cpu.numCycles 3836934364 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 56131527 # Number of instructions committed
-system.cpu.committedOps 56131527 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 52005592 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 324259 # Number of float alu accesses
-system.cpu.num_func_calls 1482234 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 6464100 # number of instructions that are conditional controls
-system.cpu.num_int_insts 52005592 # number of integer instructions
-system.cpu.num_fp_insts 324259 # number of float instructions
-system.cpu.num_int_register_reads 71250465 # number of times the integer registers were read
-system.cpu.num_int_register_writes 38480970 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 163543 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 166418 # number of times the floating registers were written
-system.cpu.num_mem_refs 15461819 # number of memory refs
-system.cpu.num_load_insts 9093811 # Number of load instructions
-system.cpu.num_store_insts 6368008 # Number of store instructions
-system.cpu.num_idle_cycles 3593002703.998122 # Number of idle cycles
-system.cpu.num_busy_cycles 233946676.001878 # Number of busy cycles
-system.cpu.not_idle_fraction 0.061131 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.938869 # Percentage of idle cycles
+system.cpu.committedInsts 56194431 # Number of instructions committed
+system.cpu.committedOps 56194431 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 52065988 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 324527 # Number of float alu accesses
+system.cpu.num_func_calls 1483664 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 6469615 # number of instructions that are conditional controls
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+system.cpu.num_fp_insts 324527 # number of float instructions
+system.cpu.num_int_register_reads 71339773 # number of times the integer registers were read
+system.cpu.num_int_register_writes 38529890 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 163675 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 166554 # number of times the floating registers were written
+system.cpu.num_mem_refs 15476497 # number of memory refs
+system.cpu.num_load_insts 9103354 # Number of load instructions
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+system.cpu.num_idle_cycles 3587701469.998130 # Number of idle cycles
+system.cpu.num_busy_cycles 249232894.001870 # Number of busy cycles
+system.cpu.not_idle_fraction 0.064956 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.935044 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei 212010 # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0 74899 40.89% 40.89% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei 212005 # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0 74904 40.89% 40.89% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22 1933 1.06% 42.01% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31 106230 57.99% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total 183193 # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0 73532 49.31% 49.31% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31 106221 57.99% 100.00% # number of times we switched to this ipl
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+system.cpu.kern.ipl_good::0 73537 49.31% 49.31% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22 1933 1.30% 50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total 149128 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1858610730000 97.13% 97.13% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 91300500 0.00% 97.14% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 737276500 0.04% 97.18% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 54034649000 2.82% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1913473956000 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31 73537 49.31% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total 149136 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0 1857459158500 96.82% 96.82% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21 91312500 0.00% 96.82% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22 736664500 0.04% 96.86% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 60179312500 3.14% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1918466448000 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0 0.981750 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31 0.692196 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total 0.814049 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31 0.692302 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total 0.814119 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx 4174 2.16% 2.17% # number of callpals executed
-system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
+system.cpu.kern.callpal::swpctx 4178 2.17% 2.17% # number of callpals executed
+system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl 175970 91.22% 93.41% # number of callpals executed
-system.cpu.kern.callpal::rdps 6834 3.54% 96.96% # number of callpals executed
+system.cpu.kern.callpal::swpipl 175968 91.22% 93.42% # number of callpals executed
+system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
-system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
+system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed
-system.cpu.kern.callpal::rti 5158 2.67% 99.64% # number of callpals executed
+system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 192916 # number of callpals executed
-system.cpu.kern.mode_switch::kernel 5900 # number of protection mode switches
-system.cpu.kern.mode_switch::user 1742 # number of protection mode switches
-system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches
+system.cpu.kern.callpal::total 192914 # number of callpals executed
+system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches
+system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
+system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches
system.cpu.kern.mode_good::kernel 1911
-system.cpu.kern.mode_good::user 1742
-system.cpu.kern.mode_good::idle 169
-system.cpu.kern.mode_switch_good::kernel 0.323898 # fraction of useful protection mode switches
+system.cpu.kern.mode_good::user 1740
+system.cpu.kern.mode_good::idle 171
+system.cpu.kern.mode_switch_good::kernel 0.323679 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle 0.080553 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::idle 0.081584 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 45394332000 2.37% 2.37% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 5131699000 0.27% 2.64% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1862947923000 97.36% 100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context 4175 # number of times the context was actually changed
+system.cpu.kern.mode_ticks::kernel 46102035000 2.40% 2.40% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user 5243076000 0.27% 2.68% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle 1867121335000 97.32% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context 4179 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu.icache.replacements 927958 # number of replacements
-system.cpu.icache.tagsinuse 509.106403 # Cycle average of tags in use
-system.cpu.icache.total_refs 55214738 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 928469 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 59.468585 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 32313596000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 509.106403 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.994348 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.994348 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 55214738 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 55214738 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 55214738 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 55214738 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 55214738 # number of overall hits
-system.cpu.icache.overall_hits::total 55214738 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 928628 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 928628 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 928628 # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::total 928628 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 12770432000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 12770432000 # number of ReadReq miss cycles
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-system.cpu.icache.overall_miss_latency::cpu.inst 12770432000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 12770432000 # number of overall miss cycles
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-system.cpu.icache.ReadReq_accesses::total 56143366 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 56143366 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 56143366 # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total 56143366 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016540 # miss rate for ReadReq accesses
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-system.cpu.icache.overall_miss_rate::total 0.016540 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13751.935113 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13751.935113 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13751.935113 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13751.935113 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13751.935113 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13751.935113 # average overall miss latency
+system.iobus.throughput 1410587 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 7103 # Transaction distribution
+system.iobus.trans_dist::ReadResp 7103 # Transaction distribution
+system.iobus.trans_dist::WriteReq 51201 # Transaction distribution
+system.iobus.trans_dist::WriteResp 51201 # Transaction distribution
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+system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
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+system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
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+system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes)
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+system.iobus.pkt_count_system.bridge.master::total 33158 # Packet count per connected master and slave (bytes)
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+system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes)
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+system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.tot_pkt_size::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 2706164 # Total data (bytes)
+system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks)
+system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer29.occupancy 378256913 # Layer occupancy (ticks)
+system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer1.occupancy 42010000 # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu.icache.replacements 928573 # number of replacements
+system.cpu.icache.tagsinuse 508.447268 # Cycle average of tags in use
+system.cpu.icache.total_refs 55277021 # Total number of references to valid blocks.
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+system.cpu.icache.warmup_cycle 38501717000 # Cycle when the warmup percentage was hit.
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928628 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 928628 # number of ReadReq MSHR misses
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-system.cpu.icache.overall_mshr_miss_latency::total 10913176000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016540 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.016540 # mshr miss rate for demand accesses
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-system.cpu.icache.overall_mshr_miss_rate::total 0.016540 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11751.935113 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11751.935113 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11751.935113 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11751.935113 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11751.935113 # average overall mshr miss latency
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-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28507781000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 28507781000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011665000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011665000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435901000 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435901000 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120403 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120403 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049472 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049472 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086113 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086113 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091364 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.091364 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091364 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.091364 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19398.119410 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19398.119410 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25549.300726 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25549.300726 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11272.384598 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11272.384598 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20761.711143 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20761.711143 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20761.711143 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20761.711143 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 835526 # number of writebacks
+system.cpu.dcache.writebacks::total 835526 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069817 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1069817 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304458 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 304458 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17270 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 17270 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1374275 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1374275 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1374275 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1374275 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25921356500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 25921356500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9930655500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 9930655500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 195056000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 195056000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 35852012000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 35852012000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 35852012000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 35852012000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011219500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011219500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435454500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435454500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120399 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120399 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049443 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049443 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086234 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086234 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091354 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.091354 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091354 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.091354 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24229.710782 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24229.710782 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32617.489112 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32617.489112 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11294.499131 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11294.499131 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26087.946008 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26087.946008 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26087.946008 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26087.946008 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 105322456 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 2023434 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2023417 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 835526 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 345993 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 304442 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1858468 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3651931 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 5510399 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 59470336 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 142586060 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 202056396 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 202046348 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 11328 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 2426797500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1393866000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 2099055000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
sim_ticks 912096763500 # Number of ticks simulated
final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1025890 # Simulator instruction rate (inst/s)
-host_op_rate 1320831 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 15183699019 # Simulator tick rate (ticks/s)
-host_mem_usage 392232 # Number of bytes of host memory used
-host_seconds 60.07 # Real time elapsed on the host
+host_inst_rate 749434 # Simulator instruction rate (inst/s)
+host_op_rate 964895 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 11092016800 # Simulator tick rate (ticks/s)
+host_mem_usage 399496 # Number of bytes of host memory used
+host_seconds 82.23 # Real time elapsed on the host
sim_insts 61625970 # Number of instructions simulated
sim_ops 79343340 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation
system.physmem.totQLat 0 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
system.physmem.totBusLat 0 # Total cycles spent in databus access
system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 64986577 # Throughput (bytes/s)
+system.membus.data_through_bus 59274047 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.l2c.replacements 70658 # number of replacements
system.l2c.tagsinuse 51560.149653 # Cycle average of tags in use
system.l2c.total_refs 1623339 # Total number of references to valid blocks.
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.toL2Bus.throughput 154009014 # Throughput (bytes/s)
+system.toL2Bus.data_through_bus 140471123 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.iobus.throughput 45730949 # Throughput (bytes/s)
+system.iobus.data_through_bus 41711051 # Total data (bytes)
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 7975768 # DTB read hits
sim_ticks 2332810264000 # Number of ticks simulated
final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1712706 # Simulator instruction rate (inst/s)
-host_op_rate 2202434 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 66139785958 # Simulator tick rate (ticks/s)
-host_mem_usage 391204 # Number of bytes of host memory used
-host_seconds 35.27 # Real time elapsed on the host
+host_inst_rate 692273 # Simulator instruction rate (inst/s)
+host_op_rate 890221 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 26733610702 # Simulator tick rate (ticks/s)
+host_mem_usage 396420 # Number of bytes of host memory used
+host_seconds 87.26 # Real time elapsed on the host
sim_insts 60408639 # Number of instructions simulated
sim_ops 77681819 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation
system.physmem.totQLat 0 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
system.physmem.totBusLat 0 # Total cycles spent in databus access
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 55969585 # Throughput (bytes/s)
+system.membus.data_through_bus 130566422 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.iobus.throughput 48895252 # Throughput (bytes/s)
+system.iobus.data_through_bus 114063346 # Total data (bytes)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 14971214 # DTB read hits
system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks
system.cpu.dcache.writebacks::total 592643 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 59102649 # Throughput (bytes/s)
+system.cpu.toL2Bus.data_through_bus 137875266 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
---------- Begin Simulation Statistics ----------
-sim_seconds 1.183438 # Number of seconds simulated
-sim_ticks 1183437503500 # Number of ticks simulated
-final_tick 1183437503500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.194897 # Number of seconds simulated
+sim_ticks 1194896580500 # Number of ticks simulated
+final_tick 1194896580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 462248 # Simulator instruction rate (inst/s)
-host_op_rate 589061 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 8900686287 # Simulator tick rate (ticks/s)
-host_mem_usage 440324 # Number of bytes of host memory used
-host_seconds 132.96 # Real time elapsed on the host
-sim_insts 61460532 # Number of instructions simulated
-sim_ops 78321652 # Number of ops (including micro ops) simulated
+host_inst_rate 311660 # Simulator instruction rate (inst/s)
+host_op_rate 397163 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6068013925 # Simulator tick rate (ticks/s)
+host_mem_usage 403588 # Number of bytes of host memory used
+host_seconds 196.92 # Real time elapsed on the host
+sim_insts 61371297 # Number of instructions simulated
+sim_ops 78208202 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 393828 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4708980 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4819184 # Number of bytes read from this memory
-system.physmem.bytes_read::total 62150116 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 393828 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 716992 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4119552 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7146896 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.inst 463972 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 6626100 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 255836 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 2904240 # Number of bytes read from this memory
+system.physmem.bytes_read::total 62155108 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 463972 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 255836 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 719808 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4136192 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7163536 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 12372 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 73650 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 75326 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6654550 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 64368 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 821204 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 43859107 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 332783 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 3979069 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 273072 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 4072191 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 52516602 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 332783 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 273072 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 605855 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3481005 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 14365 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 2543729 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6039099 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3481005 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 43859107 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 332783 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3993434 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 273072 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 6615920 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 58555700 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 6654550 # Total number of read requests seen
-system.physmem.writeReqs 821204 # Total number of write requests seen
-system.physmem.cpureqs 235817 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 425891200 # Total number of bytes read from memory
-system.physmem.bytesWritten 52557056 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 62150116 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7146896 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 97 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 11788 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 422295 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 415695 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 415259 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 415928 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 415873 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 415149 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 415167 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 415977 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 415766 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 415145 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 415183 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 415709 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 415657 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 415044 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 414930 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 415676 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 51328 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 51156 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50890 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51482 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 51387 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 50754 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50751 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 51440 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51875 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51227 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 51302 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51806 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51729 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 51213 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51075 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51789 # Track writes on a per bank basis
+system.physmem.num_reads::cpu0.inst 13468 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 103605 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
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+system.physmem.num_reads::cpu1.data 45405 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 6654628 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 64628 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 821464 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 43438497 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_read::cpu0.data 5545333 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 214107 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 2430537 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 52017144 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 388295 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 214107 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 602402 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3461548 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 2533528 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 5995110 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3461548 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 43438497 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 388295 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 8078862 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::total 58012254 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 6654628 # Total number of read requests seen
+system.physmem.writeReqs 821464 # Total number of write requests seen
+system.physmem.cpureqs 235013 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 425896192 # Total number of bytes read from memory
+system.physmem.bytesWritten 52573696 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 62155108 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7163536 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 139 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 10646 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 415731 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 415559 # Track reads on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1183433014000 # Total gap between requests
+system.physmem.totGap 1194892168500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 6825 # Categorize read packet sizes
system.physmem.readPktSize::3 6488064 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 159661 # Categorize read packet sizes
+system.physmem.readPktSize::6 159739 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 756836 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 64368 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 571102 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 64628 # Categorize write packet sizes
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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-system.physmem.wrQLenPdf::22 35704 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::24 26 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 147040385750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 189361608250 # Sum of mem lat for all requests
-system.physmem.totBusLat 33272265000 # Total cycles spent in databus access
-system.physmem.totBankLat 9048957500 # Total cycles spent in bank access
-system.physmem.avgQLat 22096.54 # Average queueing delay per request
-system.physmem.avgBankLat 1359.83 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 34609 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 13824.665723 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 735.190153 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 27804.066503 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-127 7914 22.87% 22.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-191 4043 11.68% 34.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-255 2692 7.78% 42.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-319 1927 5.57% 47.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-383 1400 4.05% 51.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-447 1123 3.24% 55.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-511 878 2.54% 57.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-575 878 2.54% 60.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-639 638 1.84% 62.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-703 541 1.56% 63.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-767 480 1.39% 65.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-831 476 1.38% 66.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-895 262 0.76% 67.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-959 253 0.73% 67.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-1023 191 0.55% 68.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1087 292 0.84% 69.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1151 145 0.42% 69.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1215 146 0.42% 70.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1279 123 0.36% 70.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1343 107 0.31% 70.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1407 79 0.23% 71.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1471 170 0.49% 71.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1535 949 2.74% 74.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1599 246 0.71% 74.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1663 151 0.44% 75.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1727 129 0.37% 75.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1791 98 0.28% 76.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1855 72 0.21% 76.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1919 65 0.19% 76.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1983 51 0.15% 76.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-2047 51 0.15% 76.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2111 71 0.21% 76.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2175 44 0.13% 77.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2239 29 0.08% 77.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2303 19 0.05% 77.24% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::total 34609 # Bytes accessed per row activation
+system.physmem.totQLat 134116991750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 175932036750 # Sum of mem lat for all requests
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 3.16 # Data bus utilization in percentage
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-system.physmem.avgWrQLen 11.75 # Average write queue length over time
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-system.physmem.writeRowHits 800418 # Number of row buffer hits during writes
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system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
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system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
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system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.l2c.overall_mshr_misses::total 162175 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 345500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 97500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 401430000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data 565873249 # number of ReadReq MSHR miss cycles
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+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 233821750 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 130194500 # number of ReadReq MSHR miss cycles
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+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 39898978 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 33754347 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 73653325 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3848381 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4768474 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 8616855 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5004861313 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2258786863 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 7263648176 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 345500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 97500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst 401430000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data 5570734562 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 76250 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 233821750 # number of demand (read+write) MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::total 8595486925 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 340227750 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12648650244 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4863250 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154086171248 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 167079912492 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16271278232 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486203500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 16757481732 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 340227750 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28919928476 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4863250 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154572374748 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 183837394224 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001388 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013950 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038621 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010609 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016805 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.018070 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.753212 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.886459 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.808869 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.599064 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.827526 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.706996 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.592032 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.495550 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.557393 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001388 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013950 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.254314 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010609 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.229619 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.108651 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001388 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013950 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.254314 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010609 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.229619 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.108651 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 86375 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58731.528895 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 58235.386333 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58572.582665 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68885.978836 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 59348.458135 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10009.778726 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10031.009510 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.497347 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10021.825521 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10038.892632 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10031.263097 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 52609.097926 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50644.309836 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 51981.966994 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86375 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58731.528895 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53130.515613 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58572.582665 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51385.888946 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 53001.306767 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86375 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58731.528895 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53130.515613 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58572.582665 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51385.888946 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 53001.306767 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.toL2Bus.throughput 118409228 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 2504917 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2504917 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 767201 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 767201 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 576235 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 27028 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 16759 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 43787 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 262464 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 262464 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 993919 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2951089 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 5837 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 14921 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 753559 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 2879854 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 6195 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 11995 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count 7617369 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 31383352 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 53719796 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 5764 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 18112 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 24083148 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 27940806 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 7476 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 15128 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size 137173582 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 137173582 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 4313200 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 4765991701 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 2214801410 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 2446229482 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 10393499 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy 1696938433 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy 2203617971 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 4326998 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy 8213499 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.throughput 45438572 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 7671400 # Transaction distribution
+system.iobus.trans_dist::ReadResp 7671400 # Transaction distribution
+system.iobus.trans_dist::WriteReq 7946 # Transaction distribution
+system.iobus.trans_dist::WriteResp 7946 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8062 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2382564 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.realview_io.pio 8062 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 15358692 # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16124 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 2389882 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.realview_io.pio 16124 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 54294394 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 54294394 # Total data (bytes)
+system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 4037000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 376000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
+system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%)
+system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
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+system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
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+system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
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+system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
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+system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
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+system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
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+system.iobus.respLayer1.utilization 1.1 # Layer utilization (%)
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 7074446 # DTB read hits
-system.cpu0.dtb.read_misses 3765 # DTB read misses
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system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 1806 # Number of entries that have been flushed from TLB
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system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch
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system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 7078211 # DTB read accesses
-system.cpu0.dtb.write_accesses 5660472 # DTB write accesses
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system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 12734115 # DTB hits
-system.cpu0.dtb.misses 4568 # DTB misses
-system.cpu0.dtb.accesses 12738683 # DTB accesses
-system.cpu0.itb.inst_hits 29576941 # ITB inst hits
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+system.cpu0.dtb.accesses 17256467 # DTB accesses
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system.cpu0.itb.inst_misses 2205 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 29579146 # ITB inst accesses
-system.cpu0.itb.hits 29576941 # DTB hits
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system.cpu0.itb.misses 2205 # DTB misses
-system.cpu0.itb.accesses 29579146 # DTB accesses
-system.cpu0.numCycles 2366875007 # number of cpu cycles simulated
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 28878978 # Number of instructions committed
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system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
-system.cpu0.num_func_calls 1241874 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4373945 # number of instructions that are conditional controls
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system.cpu0.num_fp_insts 3860 # number of float instructions
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-system.cpu0.num_int_register_writes 36237784 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 272457591 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 52272439 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
-system.cpu0.num_mem_refs 13402466 # number of memory refs
-system.cpu0.num_load_insts 7412077 # Number of load instructions
-system.cpu0.num_store_insts 5990389 # Number of store instructions
-system.cpu0.num_idle_cycles 2224972760.370120 # Number of idle cycles
-system.cpu0.num_busy_cycles 141902246.629880 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.059953 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.940047 # Percentage of idle cycles
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+system.cpu0.not_idle_fraction 0.100200 # Percentage of non-idle cycles
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
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-system.cpu0.icache.replacements 425548 # number of replacements
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-system.cpu0.icache.avg_refs 68.419619 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 75070085000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 509.590371 # Average occupied blocks per requestor
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-system.cpu0.icache.occ_percent::total 0.995294 # Average percentage of cache occupancy
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-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5812849500 # number of ReadReq miss cycles
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-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13643.233011 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13643.233011 # average ReadReq miss latency
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-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13643.233011 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13643.233011 # average overall miss latency
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system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 306255 # number of writebacks
-system.cpu0.dcache.writebacks::total 306255 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227474 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 227474 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141720 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 141720 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9335 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9335 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7498 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 7498 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 369194 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 369194 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 369194 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 369194 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2686390000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2686390000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3877797500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3877797500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69967000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69967000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29358500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29358500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.writebacks::writebacks 376588 # number of writebacks
+system.cpu0.dcache.writebacks::total 376588 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263671 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 263671 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176701 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 176701 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9917 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9917 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7370 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 7370 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 440372 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 440372 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 440372 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 440372 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3343027009 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3343027009 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7158388504 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7158388504 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79292501 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79292501 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25539500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25539500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6564187500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 6564187500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6564187500 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 6564187500 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13562288000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13562288000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128633000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128633000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14690921000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14690921000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033295 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033295 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025785 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025785 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059350 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059350 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047695 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047695 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029947 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.029947 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029947 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.029947 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11809.657367 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11809.657367 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27362.387101 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27362.387101 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7495.125870 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7495.125870 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3915.510803 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3915.510803 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10501415513 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 10501415513 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10501415513 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 10501415513 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13765210500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13765210500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807067504 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807067504 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39572278004 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39572278004 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028046 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028046 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026485 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026485 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059581 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059581 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044294 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044294 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.027398 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.027398 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12678.781546 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12678.781546 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40511.307259 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40511.307259 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7995.613694 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7995.613694 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3465.332429 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3465.332429 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17779.778382 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17779.778382 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17779.778382 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17779.778382 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23846.692144 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23846.692144 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23846.692144 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23846.692144 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 8312224 # DTB read hits
-system.cpu1.dtb.read_misses 3649 # DTB read misses
-system.cpu1.dtb.write_hits 5828610 # DTB write hits
-system.cpu1.dtb.write_misses 1432 # DTB write misses
+system.cpu1.dtb.read_hits 5706432 # DTB read hits
+system.cpu1.dtb.read_misses 3576 # DTB read misses
+system.cpu1.dtb.write_hits 3873109 # DTB write hits
+system.cpu1.dtb.write_misses 645 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1964 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 8315873 # DTB read accesses
-system.cpu1.dtb.write_accesses 5830042 # DTB write accesses
+system.cpu1.dtb.read_accesses 5710008 # DTB read accesses
+system.cpu1.dtb.write_accesses 3873754 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 14140834 # DTB hits
-system.cpu1.dtb.misses 5081 # DTB misses
-system.cpu1.dtb.accesses 14145915 # DTB accesses
-system.cpu1.itb.inst_hits 33192056 # ITB inst hits
+system.cpu1.dtb.hits 9579541 # DTB hits
+system.cpu1.dtb.misses 4221 # DTB misses
+system.cpu1.dtb.accesses 9583762 # DTB accesses
+system.cpu1.itb.inst_hits 19379683 # ITB inst hits
system.cpu1.itb.inst_misses 2171 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 33194227 # ITB inst accesses
-system.cpu1.itb.hits 33192056 # DTB hits
+system.cpu1.itb.inst_accesses 19381854 # ITB inst accesses
+system.cpu1.itb.hits 19379683 # DTB hits
system.cpu1.itb.misses 2171 # DTB misses
-system.cpu1.itb.accesses 33194227 # DTB accesses
-system.cpu1.numCycles 2365415230 # number of cpu cycles simulated
+system.cpu1.itb.accesses 19381854 # DTB accesses
+system.cpu1.numCycles 2388360365 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 32581554 # Number of instructions committed
-system.cpu1.committedOps 41094791 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 37318858 # Number of integer alu accesses
+system.cpu1.committedInsts 18799110 # Number of instructions committed
+system.cpu1.committedOps 24903355 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 22267252 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
-system.cpu1.num_func_calls 962092 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 3732954 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 37318858 # number of integer instructions
+system.cpu1.num_func_calls 796685 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 2514656 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 22267252 # number of integer instructions
system.cpu1.num_fp_insts 6793 # number of float instructions
-system.cpu1.num_int_register_reads 213696952 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 39459665 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 130770555 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 23319815 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
-system.cpu1.num_mem_refs 14678596 # number of memory refs
-system.cpu1.num_load_insts 8634126 # Number of load instructions
-system.cpu1.num_store_insts 6044470 # Number of store instructions
-system.cpu1.num_idle_cycles 1868274479.951726 # Number of idle cycles
-system.cpu1.num_busy_cycles 497140750.048273 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.210171 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.789829 # Percentage of idle cycles
+system.cpu1.num_mem_refs 10014978 # number of memory refs
+system.cpu1.num_load_insts 5983060 # Number of load instructions
+system.cpu1.num_store_insts 4031918 # Number of store instructions
+system.cpu1.num_idle_cycles 1968746844.438183 # Number of idle cycles
+system.cpu1.num_busy_cycles 419613520.561817 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.175691 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.824309 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 43886 # number of quiesce instructions executed
-system.cpu1.icache.replacements 469169 # number of replacements
-system.cpu1.icache.tagsinuse 478.729775 # Cycle average of tags in use
-system.cpu1.icache.total_refs 32722371 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 469681 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 69.669352 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 92399174500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 478.729775 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.935019 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.935019 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 32722371 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 32722371 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 32722371 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 32722371 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 32722371 # number of overall hits
-system.cpu1.icache.overall_hits::total 32722371 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 469681 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 469681 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 469681 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 469681 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 469681 # number of overall misses
-system.cpu1.icache.overall_misses::total 469681 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6362521500 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 6362521500 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 6362521500 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 6362521500 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 6362521500 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 6362521500 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 33192052 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 33192052 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 33192052 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 33192052 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 33192052 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 33192052 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014150 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.014150 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014150 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.014150 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014150 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.014150 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13546.474096 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13546.474096 # average ReadReq miss latency
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-system.cpu1.icache.demand_avg_miss_latency::total 13546.474096 # average overall miss latency
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+system.cpu1.dcache.LoadLockedReq_accesses::total 83204 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83126 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 83126 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 8309209 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 8309209 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 8309209 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 8309209 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029593 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.029593 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029791 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.029791 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117122 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117122 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112985 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112985 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029683 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.029683 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029683 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.029683 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12347.059834 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12347.059834 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32832.229522 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 32832.229522 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 7996.664956 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 7996.664956 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5210.498296 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5210.498296 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21714.985972 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 21714.985972 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21714.985972 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 21714.985972 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 265193 # number of writebacks
-system.cpu1.dcache.writebacks::total 265193 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170592 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 170592 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149961 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 149961 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11053 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11053 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10042 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 10042 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 320553 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 320553 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 320553 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 320553 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1822921500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1822921500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4235901500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4235901500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70121500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70121500 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31910500 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31910500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.writebacks::writebacks 199647 # number of writebacks
+system.cpu1.dcache.writebacks::total 199647 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133853 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 133853 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112791 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 112791 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9745 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9745 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9391 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 9391 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 246644 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 246644 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 246644 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 246644 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1384976517 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1384976517 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3477593010 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3477593010 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58436502 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58436502 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30157000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30157000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6058823000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 6058823000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6058823000 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 6058823000 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168642031500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168642031500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17668268500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17668268500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186310300000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186310300000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023965 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023965 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030123 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030123 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119040 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119040 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108237 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108237 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026500 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.026500 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026500 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.026500 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10685.855726 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10685.855726 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28246.687472 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28246.687472 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6344.114720 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6344.114720 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3177.703645 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3177.703645 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4862569527 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 4862569527 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4862569527 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 4862569527 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168387734500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168387734500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531024500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531024500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168918759000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168918759000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029593 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029593 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029791 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029791 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117122 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117122 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112973 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112973 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029683 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.029683 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029683 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.029683 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10346.996459 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10346.996459 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30832.185281 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30832.185281 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 5996.562545 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 5996.562545 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3211.266106 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3211.266106 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18901.158311 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18901.158311 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18901.158311 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18901.158311 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19714.931346 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19714.931346 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19714.931346 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19714.931346 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509664351240 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 509664351240 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509664351240 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 509664351240 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 626235127001 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 626235127001 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 626235127001 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 626235127001 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 2.603674 # Number of seconds simulated
-sim_ticks 2603674284000 # Number of ticks simulated
-final_tick 2603674284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.615622 # Number of seconds simulated
+sim_ticks 2615622384000 # Number of ticks simulated
+final_tick 2615622384000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 271279 # Simulator instruction rate (inst/s)
-host_op_rate 345198 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 11733407598 # Simulator tick rate (ticks/s)
-host_mem_usage 403640 # Number of bytes of host memory used
-host_seconds 221.90 # Real time elapsed on the host
-sim_insts 60197457 # Number of instructions simulated
-sim_ops 76600355 # Number of ops (including micro ops) simulated
+host_inst_rate 264818 # Simulator instruction rate (inst/s)
+host_op_rate 336993 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 11506330329 # Simulator tick rate (ticks/s)
+host_mem_usage 396436 # Number of bytes of host memory used
+host_seconds 227.32 # Real time elapsed on the host
+sim_insts 60198587 # Number of instructions simulated
+sim_ops 76605405 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9050192 # Number of bytes read from this memory
-system.physmem.bytes_read::total 132439216 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3677632 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9093200 # Number of bytes read from this memory
+system.physmem.bytes_read::total 132481840 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3709760 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6693704 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6725832 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 141443 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15494095 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 57463 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142115 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15494761 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 57965 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 811481 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47119332 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 270817 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3475931 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50866276 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 270817 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 270817 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1412478 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1158391 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2570868 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1412478 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47119332 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 270817 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4634322 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53437145 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15494095 # Total number of read requests seen
-system.physmem.writeReqs 811481 # Total number of write requests seen
-system.physmem.cpureqs 213992 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 991622080 # Total number of bytes read from memory
-system.physmem.bytesWritten 51934784 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 132439216 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6693704 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 974844 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 967900 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 967764 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 968566 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 968387 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 967635 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 967737 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 968249 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 968100 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 967668 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 967710 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 968007 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 968101 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 967570 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 967434 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 968087 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50753 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50356 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50308 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51002 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 50784 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 50139 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50212 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 50710 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51142 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 50724 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51058 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51155 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 50650 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 50587 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51214 # Track writes on a per bank basis
+system.physmem.num_writes::total 811983 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 46904092 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 269458 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3476496 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 50650216 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 269458 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 269458 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1418309 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1153099 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2571408 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1418309 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 46904092 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 269458 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4629595 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53221624 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15494761 # Total number of read requests seen
+system.physmem.writeReqs 811983 # Total number of write requests seen
+system.physmem.cpureqs 215166 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 991664704 # Total number of bytes read from memory
+system.physmem.bytesWritten 51966912 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 132481840 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6725832 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 301 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4516 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 968108 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 967904 # Track reads on a per bank basis
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+system.physmem.perBankWrReqs::0 49152 # Track writes on a per bank basis
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+system.physmem.perBankWrReqs::14 50825 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 50676 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2603669924000 # Total gap between requests
+system.physmem.totGap 2615618000000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 6652 # Categorize read packet sizes
system.physmem.readPktSize::3 15335424 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 152019 # Categorize read packet sizes
+system.physmem.readPktSize::6 152685 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 754018 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 57463 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 1115862 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::16 93 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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+system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 341488215750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 436408620750 # Sum of mem lat for all requests
-system.physmem.totBusLat 77468795000 # Total cycles spent in databus access
-system.physmem.totBankLat 17451610000 # Total cycles spent in bank access
-system.physmem.avgQLat 22040.37 # Average queueing delay per request
-system.physmem.avgBankLat 1126.36 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 38567 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 27059.676926 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 2495.376643 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 33105.439598 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-127 5489 14.23% 14.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-191 3331 8.64% 22.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192-255 2176 5.64% 28.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-319 1697 4.40% 32.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320-383 1162 3.01% 35.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-447 1046 2.71% 38.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448-511 828 2.15% 40.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-575 748 1.94% 42.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576-639 582 1.51% 44.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-703 509 1.32% 45.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704-767 411 1.07% 46.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-831 479 1.24% 47.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832-895 285 0.74% 48.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-959 248 0.64% 49.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960-1023 187 0.48% 49.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1087 239 0.62% 50.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088-1151 141 0.37% 50.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152-1215 137 0.36% 51.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216-1279 106 0.27% 51.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280-1343 105 0.27% 51.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344-1407 92 0.24% 51.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1408-1471 151 0.39% 52.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472-1535 970 2.52% 54.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536-1599 203 0.53% 55.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600-1663 135 0.35% 55.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664-1727 110 0.29% 55.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728-1791 91 0.24% 56.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1792-1855 77 0.20% 56.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856-1919 66 0.17% 56.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920-1983 47 0.12% 56.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984-2047 51 0.13% 56.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048-2111 64 0.17% 56.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112-2175 37 0.10% 57.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176-2239 25 0.06% 57.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240-2303 18 0.05% 57.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304-2367 25 0.06% 57.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368-2431 26 0.07% 57.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432-2495 13 0.03% 57.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496-2559 25 0.06% 57.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2560-2623 11 0.03% 57.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2624-2687 14 0.04% 57.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2688-2751 8 0.02% 57.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2752-2815 18 0.05% 57.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2816-2879 9 0.02% 57.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880-2943 8 0.02% 57.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2944-3007 14 0.04% 57.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008-3071 7 0.02% 57.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3072-3135 17 0.04% 57.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3136-3199 7 0.02% 57.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3200-3263 8 0.02% 57.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3264-3327 12 0.03% 57.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3328-3391 12 0.03% 57.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3455 3 0.01% 57.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3456-3519 9 0.02% 57.79% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::total 38567 # Bytes accessed per row activation
+system.physmem.totQLat 306544443250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 400266823250 # Sum of mem lat for all requests
+system.physmem.totBusLat 77472300000 # Total cycles spent in databus access
+system.physmem.totBankLat 16250080000 # Total cycles spent in bank access
+system.physmem.avgQLat 19784.13 # Average queueing delay per request
+system.physmem.avgBankLat 1048.77 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 28166.74 # Average memory access latency
-system.physmem.avgRdBW 380.85 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s
+system.physmem.avgMemAccLat 25832.90 # Average memory access latency
+system.physmem.avgRdBW 379.13 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 19.87 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 50.65 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 3.13 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.17 # Average read queue length over time
-system.physmem.avgWrQLen 12.40 # Average write queue length over time
-system.physmem.readRowHits 15418728 # Number of row buffer hits during reads
-system.physmem.writeRowHits 794030 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes
-system.physmem.avgGap 159679.73 # Average gap between requests
+system.physmem.busUtil 3.12 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.15 # Average read queue length over time
+system.physmem.avgWrQLen 10.80 # Average write queue length over time
+system.physmem.readRowHits 15469403 # Number of row buffer hits during reads
+system.physmem.writeRowHits 798459 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 98.33 # Row buffer hit rate for writes
+system.physmem.avgGap 160401.00 # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 54138467 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 16546589 # Transaction distribution
+system.membus.trans_dist::ReadResp 16546589 # Transaction distribution
+system.membus.trans_dist::WriteReq 763368 # Transaction distribution
+system.membus.trans_dist::WriteResp 763368 # Transaction distribution
+system.membus.trans_dist::Writeback 57965 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution
+system.membus.trans_dist::ReadExReq 132246 # Transaction distribution
+system.membus.trans_dist::ReadExResp 132246 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893707 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280555 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port 32564555 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 34951403 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16524280 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18922393 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.physmem.port 139207672 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 141605785 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 141605785 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 1206150500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 17904777500 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.7 # Layer utilization (%)
+system.membus.reqLayer3.occupancy 3613000 # Layer occupancy (ticks)
+system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4945376509 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
+system.membus.respLayer2.occupancy 34635651750 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.iobus.throughput 47817981 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 16518751 # Transaction distribution
+system.iobus.trans_dist::ReadResp 16518751 # Transaction distribution
+system.iobus.trans_dist::WriteReq 8166 # Transaction distribution
+system.iobus.trans_dist::WriteResp 8166 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 33053834 # Packet count per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.tot_pkt_size::total 125073781 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.data_through_bus 125073781 # Total data (bytes)
+system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
+system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 2374820000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.iobus.respLayer1.occupancy 30670848000 # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization 1.2 # Layer utilization (%)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 14995645 # DTB read hits
-system.cpu.dtb.read_misses 7332 # DTB read misses
-system.cpu.dtb.write_hits 11230857 # DTB write hits
-system.cpu.dtb.write_misses 2203 # DTB write misses
+system.cpu.dtb.read_hits 14996055 # DTB read hits
+system.cpu.dtb.read_misses 7342 # DTB read misses
+system.cpu.dtb.write_hits 11230429 # DTB write hits
+system.cpu.dtb.write_misses 2216 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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-system.cpu.dcache.overall_avg_miss_latency::total 21421.980536 # average overall miss latency
+system.cpu.dcache.replacements 626656 # number of replacements
+system.cpu.dcache.tagsinuse 511.879114 # Cycle average of tags in use
+system.cpu.dcache.total_refs 23655617 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 627168 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 37.718150 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 650249000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 511.879114 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999764 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999764 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 13195840 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 13195840 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 9972724 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 9972724 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 236345 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 236345 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 247797 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 247797 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 23168564 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 23168564 # number of demand (read+write) hits
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+system.cpu.dcache.overall_hits::total 23168564 # number of overall hits
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+system.cpu.dcache.ReadReq_misses::total 368347 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 250279 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 250279 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 11453 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 11453 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 618626 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 618626 # number of demand (read+write) misses
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+system.cpu.dcache.overall_misses::total 618626 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 5378545500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 5378545500 # number of ReadReq miss cycles
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+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158860000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 158860000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 15910456000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 15910456000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 15910456000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 15910456000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 13564187 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 13564187 # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.WriteReq_accesses::total 10223003 # number of WriteReq accesses(hits+misses)
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+system.cpu.dcache.LoadLockedReq_accesses::total 247798 # number of LoadLockedReq accesses(hits+misses)
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+system.cpu.dcache.StoreCondReq_accesses::total 247797 # number of StoreCondReq accesses(hits+misses)
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+system.cpu.dcache.demand_accesses::total 23787190 # number of demand (read+write) accesses
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+system.cpu.dcache.overall_accesses::total 23787190 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027156 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.027156 # miss rate for ReadReq accesses
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+system.cpu.dcache.WriteReq_miss_rate::total 0.024482 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046219 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046219 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.026007 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.026007 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.026007 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.026007 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14601.844185 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14601.844185 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42080.679961 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 42080.679961 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13870.601589 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13870.601589 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 25719.022479 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 25719.022479 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 25719.022479 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 25719.022479 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 596040 # number of writebacks
-system.cpu.dcache.writebacks::total 596040 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368785 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 368785 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250522 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 250522 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11402 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 11402 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 619307 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 619307 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 619307 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 619307 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4486508000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4486508000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7541660500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 7541660500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 132907000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 132907000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12028168500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 12028168500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12028168500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 12028168500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182082624500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182082624500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18709226000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18709226000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200791850500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 200791850500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027189 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027189 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024504 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024504 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046035 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046035 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12165.646650 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12165.646650 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30103.785296 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30103.785296 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11656.463778 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11656.463778 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19421.980536 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 19421.980536 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19421.980536 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 19421.980536 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 595512 # number of writebacks
+system.cpu.dcache.writebacks::total 595512 # number of writebacks
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+system.cpu.dcache.LoadLockedReq_mshr_misses::total 11453 # number of LoadLockedReq MSHR misses
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+system.cpu.dcache.overall_mshr_misses::total 618626 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4641851500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4641851500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10031352500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 10031352500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135954000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135954000 # number of LoadLockedReq MSHR miss cycles
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+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14673204000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 14673204000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050723500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050723500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234076500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234076500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284800000 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284800000 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027156 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027156 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024482 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024482 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046219 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046219 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.026007 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.026007 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12601.844185 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12601.844185 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40080.679961 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40080.679961 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11870.601589 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11870.601589 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23719.022479 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23719.022479 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23719.022479 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23719.022479 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 53002965 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 2454953 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2454953 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 595512 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2911 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2911 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 247368 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 247368 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1725126 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5750616 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 12461 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 27468 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 7515671 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54754292 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 83665829 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 14140 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 34916 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 138469177 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 138469177 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 166564 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 3009252000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1291764000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 2507996500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer3.occupancy 18739000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199377224257 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1199377224257 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199377224257 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1199377224257 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1470128900250 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1470128900250 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1470128900250 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1470128900250 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
sim_ticks 2332810264000 # Number of ticks simulated
final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1307768 # Simulator instruction rate (inst/s)
-host_op_rate 1681709 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 50502250863 # Simulator tick rate (ticks/s)
-host_mem_usage 395644 # Number of bytes of host memory used
-host_seconds 46.19 # Real time elapsed on the host
+host_inst_rate 662335 # Simulator instruction rate (inst/s)
+host_op_rate 851722 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 25577480180 # Simulator tick rate (ticks/s)
+host_mem_usage 396424 # Number of bytes of host memory used
+host_seconds 91.21 # Real time elapsed on the host
sim_insts 60408639 # Number of instructions simulated
sim_ops 77681819 # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation
system.physmem.totQLat 0 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
system.physmem.totBusLat 0 # Total cycles spent in databus access
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap nan # Average gap between requests
+system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 55969561 # Throughput (bytes/s)
+system.membus.data_through_bus 130566366 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.l2c.replacements 62242 # number of replacements
system.l2c.tagsinuse 50006.300222 # Cycle average of tags in use
system.l2c.total_refs 1678485 # Total number of references to valid blocks.
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.toL2Bus.throughput 59119250 # Throughput (bytes/s)
+system.toL2Bus.data_through_bus 137913994 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.iobus.throughput 48895252 # Throughput (bytes/s)
+system.iobus.data_through_bus 114063346 # Total data (bytes)
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 7929205 # DTB read hits
sim_ticks 5112099860500 # Number of ticks simulated
final_tick 5112099860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1019592 # Simulator instruction rate (inst/s)
-host_op_rate 2087576 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 26073588986 # Simulator tick rate (ticks/s)
-host_mem_usage 631672 # Number of bytes of host memory used
-host_seconds 196.06 # Real time elapsed on the host
+host_inst_rate 794426 # Simulator instruction rate (inst/s)
+host_op_rate 1626557 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 20315509625 # Simulator tick rate (ticks/s)
+host_mem_usage 586244 # Number of bytes of host memory used
+host_seconds 251.64 # Real time elapsed on the host
sim_insts 199905607 # Number of instructions simulated
sim_ops 409299132 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2420928 # Number of bytes read from this memory
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation
system.physmem.totQLat 0 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 0 # Sum of mem lat for all requests
system.physmem.totBusLat 0 # Total cycles spent in databus access
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap nan # Average gap between requests
+system.membus.throughput 9632717 # Throughput (bytes/s)
+system.membus.data_through_bus 49243411 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.iocache.replacements 47568 # number of replacements
system.iocache.tagsinuse 0.042441 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
+system.iobus.throughput 2555194 # Throughput (bytes/s)
+system.iobus.data_through_bus 13062406 # Total data (bytes)
system.cpu.numCycles 10224199744 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dcache.writebacks::writebacks 1535700 # number of writebacks
system.cpu.dcache.writebacks::total 1535700 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 54622198 # Throughput (bytes/s)
+system.cpu.toL2Bus.data_through_bus 279208723 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 25408 # Total snoop data (bytes)
system.cpu.l2cache.replacements 105930 # number of replacements
system.cpu.l2cache.tagsinuse 64819.953901 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3456506 # Total number of references to valid blocks.
---------- Begin Simulation Statistics ----------
-sim_seconds 5.187336 # Number of seconds simulated
-sim_ticks 5187335906000 # Number of ticks simulated
-final_tick 5187335906000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.196145 # Number of seconds simulated
+sim_ticks 5196144770000 # Number of ticks simulated
+final_tick 5196144770000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 633010 # Simulator instruction rate (inst/s)
-host_op_rate 1220249 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 25590316667 # Simulator tick rate (ticks/s)
-host_mem_usage 632708 # Number of bytes of host memory used
-host_seconds 202.71 # Real time elapsed on the host
-sim_insts 128315489 # Number of instructions simulated
-sim_ops 247353048 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide 2850304 # Number of bytes read from this memory
+host_inst_rate 471788 # Simulator instruction rate (inst/s)
+host_op_rate 909467 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 19106715414 # Simulator tick rate (ticks/s)
+host_mem_usage 586268 # Number of bytes of host memory used
+host_seconds 271.95 # Real time elapsed on the host
+sim_insts 128304418 # Number of instructions simulated
+sim_ops 247333117 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide 2891776 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 824512 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9026304 # Number of bytes read from this memory
-system.physmem.bytes_read::total 12701440 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 824512 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 824512 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8120576 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8120576 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 44536 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst 823744 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 8961408 # Number of bytes read from this memory
+system.physmem.bytes_read::total 12677312 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 823744 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 823744 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8105792 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8105792 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 45184 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12883 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 141036 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 198460 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 126884 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 126884 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 549474 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu.inst 12871 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 140022 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 198083 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 126653 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 126653 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 556523 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 158947 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1740065 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2448548 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 158947 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 158947 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1565462 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1565462 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1565462 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 549474 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 158530 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1724626 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2439753 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 158530 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 158530 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1559963 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1559963 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1559963 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 556523 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 158947 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1740065 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4014010 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 198460 # Total number of read requests seen
-system.physmem.writeReqs 126884 # Total number of write requests seen
-system.physmem.cpureqs 326965 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 12701440 # Total number of bytes read from memory
-system.physmem.bytesWritten 8120576 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 12701440 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 8120576 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 110 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 1615 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 12387 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 12046 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 12118 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 12449 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 12193 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 12119 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 12473 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 12536 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 12592 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 12290 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 12456 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 12641 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 12408 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 12254 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 12740 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 12648 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 7793 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7533 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 7699 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 7988 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7862 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 7739 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7964 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 8103 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 8131 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7898 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7933 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 8107 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 7973 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 7879 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 8152 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 8130 # Track writes on a per bank basis
+system.physmem.bw_total::cpu.inst 158530 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1724626 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3999716 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 198083 # Total number of read requests seen
+system.physmem.writeReqs 126653 # Total number of write requests seen
+system.physmem.cpureqs 326336 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 12677312 # Total number of bytes read from memory
+system.physmem.bytesWritten 8105792 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 12677312 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 8105792 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 70 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 1597 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 12388 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 12465 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 13064 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 12742 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 12822 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 12061 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 12170 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 12418 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 11780 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 11808 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 12169 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 12505 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 12558 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 12789 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 12227 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 12047 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7920 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 8110 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 8533 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 8387 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 8388 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 7744 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 7664 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 7959 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7196 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 7383 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7714 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 7959 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 8157 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 8159 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7876 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7504 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 6 # Number of times wr buffer was full causing retry
-system.physmem.totGap 5187335842500 # Total gap between requests
+system.physmem.numWrRetry 3 # Number of times wr buffer was full causing retry
+system.physmem.totGap 5196144706500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 198460 # Categorize read packet sizes
+system.physmem.readPktSize::6 198083 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 126884 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 155340 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 8720 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 6686 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3417 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3378 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2810 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2218 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 2141 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 2080 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 2004 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1276 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 1172 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 1102 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1032 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 958 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 968 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 1114 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 1055 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 518 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 325 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 126653 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 154572 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 13375 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 7517 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 3048 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2915 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2517 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1489 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 1349 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 1265 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 1181 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 1109 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 1086 # What read queue length does an incoming req see
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-system.physmem.totQLat 4133329999 # Total cycles spent in queuing delays
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-system.physmem.totBusLat 991750000 # Total cycles spent in databus access
-system.physmem.totBankLat 2845603750 # Total cycles spent in bank access
-system.physmem.avgQLat 20838.57 # Average queueing delay per request
-system.physmem.avgBankLat 14346.38 # Average bank access latency per request
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+system.physmem.bytesPerActivate::mean 458.910923 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 168.789921 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 1568.289191 # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::total 45242 # Bytes accessed per row activation
+system.physmem.totQLat 3435518998 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 7067756498 # Sum of mem lat for all requests
+system.physmem.totBusLat 990065000 # Total cycles spent in databus access
+system.physmem.totBankLat 2642172500 # Total cycles spent in bank access
+system.physmem.avgQLat 17349.97 # Average queueing delay per request
+system.physmem.avgBankLat 13343.43 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 40184.94 # Average memory access latency
-system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 1.57 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 35693.40 # Average memory access latency
+system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 12.90 # Average write queue length over time
-system.physmem.readRowHits 174211 # Number of row buffer hits during reads
-system.physmem.writeRowHits 94671 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 87.83 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 74.61 # Row buffer hit rate for writes
-system.physmem.avgGap 15944157.08 # Average gap between requests
-system.iocache.replacements 47504 # number of replacements
-system.iocache.tagsinuse 0.157150 # Cycle average of tags in use
+system.physmem.avgWrQLen 9.35 # Average write queue length over time
+system.physmem.readRowHits 181015 # Number of row buffer hits during reads
+system.physmem.writeRowHits 98394 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 91.42 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 77.69 # Row buffer hit rate for writes
+system.physmem.avgGap 16001135.40 # Average gap between requests
+system.membus.throughput 4358895 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 623371 # Transaction distribution
+system.membus.trans_dist::ReadResp 623371 # Transaction distribution
+system.membus.trans_dist::WriteReq 13727 # Transaction distribution
+system.membus.trans_dist::WriteResp 13727 # Transaction distribution
+system.membus.trans_dist::Writeback 126653 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 2147 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 1615 # Transaction distribution
+system.membus.trans_dist::ReadExReq 159120 # Transaction distribution
+system.membus.trans_dist::ReadExResp 159120 # Transaction distribution
+system.membus.trans_dist::MessageReq 1656 # Transaction distribution
+system.membus.trans_dist::MessageResp 1656 # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3312 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total 3312 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 390174 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480118 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710116 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1580408 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139407 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 139407 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port 529581 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.bridge.slave 480118 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.cpu.interrupts.pio 710116 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.cpu.interrupts.int_slave 3312 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1723127 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.apicbridge.master::total 6624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14904512 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246342 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420229 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16571083 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5878592 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.iocache.mem_side::total 5878592 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.physmem.port 20783104 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.bridge.slave 246342 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.cpu.interrupts.pio 1420229 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 22456299 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 22456299 # Total data (bytes)
+system.membus.snoop_data_through_bus 193152 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 1348670998 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 256617500 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 359320000 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer3.occupancy 3312000 # Layer occupancy (ticks)
+system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer0.occupancy 1656000 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 2607874799 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer4.occupancy 428809000 # Layer occupancy (ticks)
+system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.iocache.replacements 47501 # number of replacements
+system.iocache.tagsinuse 0.169264 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 47520 # Sample count of references to valid blocks.
+system.iocache.sampled_refs 47517 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 5044705088000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide 0.157150 # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide 0.009822 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.009822 # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide 837 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 837 # number of ReadReq misses
+system.iocache.warmup_cycle 5049524013000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::pc.south_bridge.ide 0.169264 # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide 0.010579 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.010579 # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::pc.south_bridge.ide 834 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 834 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 47557 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47557 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 47557 # number of overall misses
-system.iocache.overall_misses::total 47557 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 139731143 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 139731143 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10765565415 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10765565415 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 10905296558 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10905296558 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 10905296558 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10905296558 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 837 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 837 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide 47554 # number of demand (read+write) misses
+system.iocache.demand_misses::total 47554 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 47554 # number of overall misses
+system.iocache.overall_misses::total 47554 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142703185 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 142703185 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10862337325 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 10862337325 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 11005040510 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 11005040510 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 11005040510 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 11005040510 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 834 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 834 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 47557 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47557 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 47557 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47557 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 47554 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 47554 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 47554 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 47554 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166942.823178 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 166942.823178 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 230427.341931 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 230427.341931 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 229310.018672 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 229310.018672 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 229310.018672 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 229310.018672 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 177808 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 171106.936451 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 171106.936451 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 232498.658497 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 232498.658497 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 231421.973125 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 231421.973125 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 231421.973125 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 231421.973125 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 174194 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 16153 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 16040 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 11.007739 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 10.859975 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46669 # number of writebacks
system.iocache.writebacks::total 46669 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 837 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 837 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 834 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 834 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 47557 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 47557 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 47557 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 47557 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96185423 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 96185423 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8334760316 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 8334760316 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8430945739 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 8430945739 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8430945739 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 8430945739 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 47554 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 47554 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 47554 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 47554 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99319185 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 99319185 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8432090325 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 8432090325 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8531409510 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 8531409510 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8531409510 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 8531409510 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114916.873357 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 114916.873357 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 178398.123202 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 178398.123202 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 177280.857476 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 177280.857476 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 177280.857476 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 177280.857476 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 119087.751799 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 119087.751799 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 180481.385381 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 180481.385381 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 179404.666484 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 179404.666484 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 179404.666484 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 179404.666484 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.numCycles 10374671812 # number of cpu cycles simulated
+system.iobus.throughput 631272 # Throughput (bytes/s)
+system.iobus.trans_dist::ReadReq 230083 # Transaction distribution
+system.iobus.trans_dist::ReadResp 230083 # Transaction distribution
+system.iobus.trans_dist::WriteReq 57530 # Transaction distribution
+system.iobus.trans_dist::WriteResp 57530 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1656 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1656 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 480118 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95108 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95108 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3312 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3312 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.apicbridge.slave 3312 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
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+system.iobus.pkt_count::total 578538 # Packet count per connected master and slave (bytes)
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+system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027216 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.data_through_bus 3280182 # Total data (bytes)
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358810 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000161 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001781 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.086886 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.063482 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000161 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001781 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016254 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.086886 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.063482 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66168.098042 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62664.695921 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63761.308163 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10696.720060 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10696.720060 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55606.615572 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55606.615572 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66168.098042 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57022.207658 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57787.918707 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66168.098042 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57022.207658 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57787.918707 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
---------- Begin Simulation Statistics ----------
sim_seconds 0.200409 # Number of seconds simulated
-sim_ticks 200409293000 # Number of ticks simulated
-final_tick 4321201686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 200409284500 # Number of ticks simulated
+final_tick 4321214250500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 11931696 # Simulator instruction rate (inst/s)
-host_op_rate 11931689 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4547176905 # Simulator tick rate (ticks/s)
-host_mem_usage 472520 # Number of bytes of host memory used
-host_seconds 44.07 # Real time elapsed on the host
-sim_insts 525869186 # Number of instructions simulated
-sim_ops 525869186 # Number of ops (including micro ops) simulated
-testsys.physmem.bytes_read::cpu.inst 81048564 # Number of bytes read from this memory
-testsys.physmem.bytes_read::cpu.data 27826180 # Number of bytes read from this memory
-testsys.physmem.bytes_read::tsunami.ethernet 51169128 # Number of bytes read from this memory
-testsys.physmem.bytes_read::total 160043872 # Number of bytes read from this memory
-testsys.physmem.bytes_inst_read::cpu.inst 81048564 # Number of instructions bytes read from this memory
-testsys.physmem.bytes_inst_read::total 81048564 # Number of instructions bytes read from this memory
-testsys.physmem.bytes_written::cpu.data 16606324 # Number of bytes written to this memory
+host_inst_rate 10833540 # Simulator instruction rate (inst/s)
+host_op_rate 10833535 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4145057481 # Simulator tick rate (ticks/s)
+host_mem_usage 475668 # Number of bytes of host memory used
+host_seconds 48.35 # Real time elapsed on the host
+sim_insts 523790075 # Number of instructions simulated
+sim_ops 523790075 # Number of ops (including micro ops) simulated
+testsys.physmem.bytes_read::cpu.inst 81046720 # Number of bytes read from this memory
+testsys.physmem.bytes_read::cpu.data 27826276 # Number of bytes read from this memory
+testsys.physmem.bytes_read::tsunami.ethernet 57260496 # Number of bytes read from this memory
+testsys.physmem.bytes_read::total 166133492 # Number of bytes read from this memory
+testsys.physmem.bytes_inst_read::cpu.inst 81046720 # Number of instructions bytes read from this memory
+testsys.physmem.bytes_inst_read::total 81046720 # Number of instructions bytes read from this memory
+testsys.physmem.bytes_written::cpu.data 16606680 # Number of bytes written to this memory
testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory
-testsys.physmem.bytes_written::total 16607226 # Number of bytes written to this memory
-testsys.physmem.num_reads::cpu.inst 20262141 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::cpu.data 3842564 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::tsunami.ethernet 2132029 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::total 26236734 # Number of read requests responded to by this memory
-testsys.physmem.num_writes::cpu.data 2258349 # Number of write requests responded to by this memory
+testsys.physmem.bytes_written::total 16607582 # Number of bytes written to this memory
+testsys.physmem.num_reads::cpu.inst 20261680 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::cpu.data 3842559 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::tsunami.ethernet 2385836 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::total 26490075 # Number of read requests responded to by this memory
+testsys.physmem.num_writes::cpu.data 2258392 # Number of write requests responded to by this memory
testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory
-testsys.physmem.num_writes::total 2258380 # Number of write requests responded to by this memory
-testsys.physmem.bw_read::cpu.inst 404415198 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::cpu.data 138846755 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::tsunami.ethernet 255323130 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::total 798585084 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::cpu.inst 404415198 # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::total 404415198 # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::cpu.data 82862046 # Write bandwidth from this memory (bytes/s)
+testsys.physmem.num_writes::total 2258423 # Number of write requests responded to by this memory
+testsys.physmem.bw_read::cpu.inst 404406014 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::cpu.data 138847240 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::tsunami.ethernet 285717781 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::total 828971035 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read::cpu.inst 404406014 # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read::total 404406014 # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_write::cpu.data 82863826 # Write bandwidth from this memory (bytes/s)
testsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::total 82866547 # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.inst 404415198 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.data 221708801 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::tsunami.ethernet 255327631 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::total 881451630 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.readReqs 0 # Total number of read requests seen
-testsys.physmem.writeReqs 0 # Total number of write requests seen
-testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
-testsys.physmem.bytesRead 0 # Total number of bytes read from memory
-testsys.physmem.bytesWritten 0 # Total number of bytes written to memory
-testsys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
-testsys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-testsys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-testsys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-testsys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
-testsys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
-testsys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-testsys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-testsys.physmem.totGap 0 # Total gap between requests
-testsys.physmem.readPktSize::0 0 # Categorize read packet sizes
-testsys.physmem.readPktSize::1 0 # Categorize read packet sizes
-testsys.physmem.readPktSize::2 0 # Categorize read packet sizes
-testsys.physmem.readPktSize::3 0 # Categorize read packet sizes
-testsys.physmem.readPktSize::4 0 # Categorize read packet sizes
-testsys.physmem.readPktSize::5 0 # Categorize read packet sizes
-testsys.physmem.readPktSize::6 0 # Categorize read packet sizes
-testsys.physmem.writePktSize::0 0 # Categorize write packet sizes
-testsys.physmem.writePktSize::1 0 # Categorize write packet sizes
-testsys.physmem.writePktSize::2 0 # Categorize write packet sizes
-testsys.physmem.writePktSize::3 0 # Categorize write packet sizes
-testsys.physmem.writePktSize::4 0 # Categorize write packet sizes
-testsys.physmem.writePktSize::5 0 # Categorize write packet sizes
-testsys.physmem.writePktSize::6 0 # Categorize write packet sizes
-testsys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-testsys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-testsys.physmem.totQLat 0 # Total cycles spent in queuing delays
-testsys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
-testsys.physmem.totBusLat 0 # Total cycles spent in databus access
-testsys.physmem.totBankLat 0 # Total cycles spent in bank access
-testsys.physmem.avgQLat nan # Average queueing delay per request
-testsys.physmem.avgBankLat nan # Average bank access latency per request
-testsys.physmem.avgBusLat nan # Average bus latency per request
-testsys.physmem.avgMemAccLat nan # Average memory access latency
-testsys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
-testsys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-testsys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
-testsys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
-testsys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-testsys.physmem.busUtil 0.00 # Data bus utilization in percentage
-testsys.physmem.avgRdQLen 0.00 # Average read queue length over time
-testsys.physmem.avgWrQLen 0.00 # Average write queue length over time
-testsys.physmem.readRowHits 0 # Number of row buffer hits during reads
-testsys.physmem.writeRowHits 0 # Number of row buffer hits during writes
-testsys.physmem.readRowHitRate nan # Row buffer hit rate for reads
-testsys.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-testsys.physmem.avgGap nan # Average gap between requests
+testsys.physmem.bw_write::total 82868326 # Write bandwidth from this memory (bytes/s)
+testsys.physmem.bw_total::cpu.inst 404406014 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::cpu.data 221711065 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::tsunami.ethernet 285722281 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::total 911839361 # Total bandwidth to/from this memory (bytes/s)
+testsys.membus.throughput 916540501 # Throughput (bytes/s)
+testsys.membus.data_through_bus 183683226 # Total data (bytes)
+testsys.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
testsys.cpu.dtb.fetch_misses 0 # ITB misses
testsys.cpu.dtb.fetch_acv 0 # ITB acv
testsys.cpu.dtb.fetch_accesses 0 # ITB accesses
-testsys.cpu.dtb.read_hits 3916928 # DTB read hits
+testsys.cpu.dtb.read_hits 3916918 # DTB read hits
testsys.cpu.dtb.read_misses 3287 # DTB read misses
testsys.cpu.dtb.read_acv 80 # DTB read access violations
testsys.cpu.dtb.read_accesses 225414 # DTB read accesses
-testsys.cpu.dtb.write_hits 2316846 # DTB write hits
+testsys.cpu.dtb.write_hits 2316885 # DTB write hits
testsys.cpu.dtb.write_misses 528 # DTB write misses
testsys.cpu.dtb.write_acv 81 # DTB write access violations
testsys.cpu.dtb.write_accesses 109988 # DTB write accesses
-testsys.cpu.dtb.data_hits 6233774 # DTB hits
+testsys.cpu.dtb.data_hits 6233803 # DTB hits
testsys.cpu.dtb.data_misses 3815 # DTB misses
testsys.cpu.dtb.data_acv 161 # DTB access violations
testsys.cpu.dtb.data_accesses 335402 # DTB accesses
-testsys.cpu.itb.fetch_hits 4052272 # ITB hits
+testsys.cpu.itb.fetch_hits 4052211 # ITB hits
testsys.cpu.itb.fetch_misses 1497 # ITB misses
testsys.cpu.itb.fetch_acv 69 # ITB acv
-testsys.cpu.itb.fetch_accesses 4053769 # ITB accesses
+testsys.cpu.itb.fetch_accesses 4053708 # ITB accesses
testsys.cpu.itb.read_hits 0 # DTB read hits
testsys.cpu.itb.read_misses 0 # DTB read misses
testsys.cpu.itb.read_acv 0 # DTB read access violations
testsys.cpu.itb.data_misses 0 # DTB misses
testsys.cpu.itb.data_acv 0 # DTB access violations
testsys.cpu.itb.data_accesses 0 # DTB accesses
-testsys.cpu.numCycles 400815936 # number of cpu cycles simulated
+testsys.cpu.numCycles 400804755 # number of cpu cycles simulated
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-testsys.cpu.committedInsts 20258165 # Number of instructions committed
-testsys.cpu.committedOps 20258165 # Number of ops (including micro ops) committed
-testsys.cpu.num_int_alu_accesses 18837392 # Number of integer alu accesses
-testsys.cpu.num_fp_alu_accesses 17313 # Number of float alu accesses
-testsys.cpu.num_func_calls 1221260 # number of times a function call or return occured
-testsys.cpu.num_conditional_control_insts 1442190 # number of instructions that are conditional controls
-testsys.cpu.num_int_insts 18837392 # number of integer instructions
-testsys.cpu.num_fp_insts 17313 # number of float instructions
-testsys.cpu.num_int_register_reads 24787608 # number of times the integer registers were read
-testsys.cpu.num_int_register_writes 14694255 # number of times the integer registers were written
-testsys.cpu.num_fp_register_reads 11133 # number of times the floating registers were read
-testsys.cpu.num_fp_register_writes 10789 # number of times the floating registers were written
-testsys.cpu.num_mem_refs 6263009 # number of memory refs
-testsys.cpu.num_load_insts 3944038 # Number of load instructions
-testsys.cpu.num_store_insts 2318971 # Number of store instructions
-testsys.cpu.num_idle_cycles 380552362.972989 # Number of idle cycles
-testsys.cpu.num_busy_cycles 20263573.027011 # Number of busy cycles
-testsys.cpu.not_idle_fraction 0.050556 # Percentage of non-idle cycles
-testsys.cpu.idle_fraction 0.949444 # Percentage of idle cycles
+testsys.cpu.committedInsts 20257704 # Number of instructions committed
+testsys.cpu.committedOps 20257704 # Number of ops (including micro ops) committed
+testsys.cpu.num_int_alu_accesses 18837017 # Number of integer alu accesses
+testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses
+testsys.cpu.num_func_calls 1221180 # number of times a function call or return occured
+testsys.cpu.num_conditional_control_insts 1442148 # number of instructions that are conditional controls
+testsys.cpu.num_int_insts 18837017 # number of integer instructions
+testsys.cpu.num_fp_insts 17380 # number of float instructions
+testsys.cpu.num_int_register_reads 24787248 # number of times the integer registers were read
+testsys.cpu.num_int_register_writes 14693875 # number of times the integer registers were written
+testsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read
+testsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written
+testsys.cpu.num_mem_refs 6263046 # number of memory refs
+testsys.cpu.num_load_insts 3944033 # Number of load instructions
+testsys.cpu.num_store_insts 2319013 # Number of store instructions
+testsys.cpu.num_idle_cycles 380542207.362158 # Number of idle cycles
+testsys.cpu.num_busy_cycles 20262547.637842 # Number of busy cycles
+testsys.cpu.not_idle_fraction 0.050555 # Percentage of non-idle cycles
+testsys.cpu.idle_fraction 0.949445 # Percentage of idle cycles
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
-testsys.cpu.kern.inst.quiesce 19598 # number of quiesce instructions executed
-testsys.cpu.kern.inst.hwrei 153677 # number of hwrei instructions executed
-testsys.cpu.kern.ipl_count::0 62790 42.68% 42.68% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::21 19620 13.34% 56.01% # number of times we switched to this ipl
+testsys.cpu.kern.inst.quiesce 19580 # number of quiesce instructions executed
+testsys.cpu.kern.inst.hwrei 153667 # number of hwrei instructions executed
+testsys.cpu.kern.ipl_count::0 62779 42.67% 42.67% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::21 19625 13.34% 56.01% # number of times we switched to this ipl
testsys.cpu.kern.ipl_count::22 205 0.14% 56.15% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::31 64514 43.85% 100.00% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::total 147129 # number of times we switched to this ipl
-testsys.cpu.kern.ipl_good::0 62784 43.18% 43.18% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::21 19620 13.49% 56.67% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::22 205 0.14% 56.81% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::31 62791 43.19% 100.00% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::total 145400 # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_ticks::0 194352160500 96.98% 96.98% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::21 1588908500 0.79% 97.77% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_count::31 64509 43.85% 100.00% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::total 147118 # number of times we switched to this ipl
+testsys.cpu.kern.ipl_good::0 62773 43.18% 43.18% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::21 19625 13.50% 56.67% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::22 205 0.14% 56.82% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::31 62785 43.18% 100.00% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::total 145388 # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_ticks::0 194346512500 96.98% 96.98% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::21 1588986000 0.79% 97.77% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 97.78% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::31 4458302500 2.22% 100.00% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::total 200408186500 # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::31 4458282500 2.22% 100.00% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::total 200402596000 # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_used::0 0.999904 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::31 0.973293 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::total 0.988248 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::31 0.973275 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::total 0.988241 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed
testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed
testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed
testsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed
testsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed
testsys.cpu.kern.syscall::total 83 # number of syscalls executed
-testsys.cpu.kern.callpal::swpctx 437 0.34% 0.34% # number of callpals executed
+testsys.cpu.kern.callpal::swpctx 438 0.34% 0.34% # number of callpals executed
testsys.cpu.kern.callpal::tbi 20 0.02% 0.36% # number of callpals executed
-testsys.cpu.kern.callpal::swpipl 106841 83.26% 83.62% # number of callpals executed
+testsys.cpu.kern.callpal::swpipl 106830 83.26% 83.62% # number of callpals executed
testsys.cpu.kern.callpal::rdps 359 0.28% 83.90% # number of callpals executed
testsys.cpu.kern.callpal::wrusp 3 0.00% 83.90% # number of callpals executed
testsys.cpu.kern.callpal::rdusp 3 0.00% 83.90% # number of callpals executed
testsys.cpu.kern.callpal::rti 20470 15.95% 99.86% # number of callpals executed
testsys.cpu.kern.callpal::callsys 140 0.11% 99.97% # number of callpals executed
testsys.cpu.kern.callpal::imb 44 0.03% 100.00% # number of callpals executed
-testsys.cpu.kern.callpal::total 128317 # number of callpals executed
-testsys.cpu.kern.mode_switch::kernel 1281 # number of protection mode switches
-testsys.cpu.kern.mode_switch::user 703 # number of protection mode switches
-testsys.cpu.kern.mode_switch::idle 19627 # number of protection mode switches
+testsys.cpu.kern.callpal::total 128307 # number of callpals executed
+testsys.cpu.kern.mode_switch::kernel 1280 # number of protection mode switches
+testsys.cpu.kern.mode_switch::user 702 # number of protection mode switches
+testsys.cpu.kern.mode_switch::idle 19629 # number of protection mode switches
testsys.cpu.kern.mode_good::kernel 707
-testsys.cpu.kern.mode_good::user 703
-testsys.cpu.kern.mode_good::idle 4
-testsys.cpu.kern.mode_switch_good::kernel 0.551913 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_good::user 702
+testsys.cpu.kern.mode_good::idle 5
+testsys.cpu.kern.mode_switch_good::kernel 0.552344 # fraction of useful protection mode switches
testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_switch_good::idle 0.000204 # fraction of useful protection mode switches
+testsys.cpu.kern.mode_switch_good::idle 0.000255 # fraction of useful protection mode switches
testsys.cpu.kern.mode_switch_good::total 0.065430 # fraction of useful protection mode switches
-testsys.cpu.kern.mode_ticks::kernel 1002766500 60.53% 60.53% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::user 533073000 32.18% 92.70% # number of ticks spent at the given mode
-testsys.cpu.kern.mode_ticks::idle 120928500 7.30% 100.00% # number of ticks spent at the given mode
-testsys.cpu.kern.swap_context 437 # number of times the context was actually changed
+testsys.cpu.kern.mode_ticks::kernel 994603000 60.01% 60.01% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks::user 533068000 32.16% 92.17% # number of ticks spent at the given mode
+testsys.cpu.kern.mode_ticks::idle 129740500 7.83% 100.00% # number of ticks spent at the given mode
+testsys.cpu.kern.swap_context 438 # number of times the context was actually changed
testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted
testsys.tsunami.ethernet.rxBytes 798 # Bytes Received
testsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted
testsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device
testsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
testsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
-testsys.tsunami.ethernet.descDMAReads 2131994 # Number of descriptors the device read w/ DMA
+testsys.tsunami.ethernet.descDMAReads 2385801 # Number of descriptors the device read w/ DMA
testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
-testsys.tsunami.ethernet.descDmaReadBytes 51167856 # number of descriptor bytes read w/ DMA
+testsys.tsunami.ethernet.descDmaReadBytes 57259224 # number of descriptor bytes read w/ DMA
testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
testsys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s)
testsys.tsunami.ethernet.totPackets 13 # Total Packets
testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
testsys.tsunami.ethernet.postedTxIdle 19571 # number of TxIdle interrupts posted to CPU
testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
-testsys.tsunami.ethernet.totalTxIdle 2131994 # total number of TxIdle written to ISR
+testsys.tsunami.ethernet.totalTxIdle 2385801 # total number of TxIdle written to ISR
testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
-testsys.tsunami.ethernet.postedInterrupts 2132012 # number of posts to CPU
+testsys.tsunami.ethernet.postedInterrupts 2385819 # number of posts to CPU
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-drivesys.physmem.bytes_read::cpu.inst 76288612 # Number of bytes read from this memory
-drivesys.physmem.bytes_read::cpu.data 26312880 # Number of bytes read from this memory
-drivesys.physmem.bytes_read::tsunami.ethernet 51169134 # Number of bytes read from this memory
-drivesys.physmem.bytes_read::total 153770626 # Number of bytes read from this memory
-drivesys.physmem.bytes_inst_read::cpu.inst 76288612 # Number of instructions bytes read from this memory
-drivesys.physmem.bytes_inst_read::total 76288612 # Number of instructions bytes read from this memory
-drivesys.physmem.bytes_written::cpu.data 14635456 # Number of bytes written to this memory
+testsys.iobus.throughput 290423421 # Throughput (bytes/s)
+testsys.iobus.data_through_bus 58203550 # Total data (bytes)
+drivesys.physmem.bytes_read::cpu.inst 76205572 # Number of bytes read from this memory
+drivesys.physmem.bytes_read::cpu.data 26284292 # Number of bytes read from this memory
+drivesys.physmem.bytes_read::tsunami.ethernet 57260526 # Number of bytes read from this memory
+drivesys.physmem.bytes_read::total 159750390 # Number of bytes read from this memory
+drivesys.physmem.bytes_inst_read::cpu.inst 76205572 # Number of instructions bytes read from this memory
+drivesys.physmem.bytes_inst_read::total 76205572 # Number of instructions bytes read from this memory
+drivesys.physmem.bytes_written::cpu.data 14619632 # Number of bytes written to this memory
drivesys.physmem.bytes_written::tsunami.ethernet 1064 # Number of bytes written to this memory
-drivesys.physmem.bytes_written::total 14636520 # Number of bytes written to this memory
-drivesys.physmem.num_reads::cpu.inst 19072153 # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::cpu.data 3651006 # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::tsunami.ethernet 2132030 # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::total 24855189 # Number of read requests responded to by this memory
-drivesys.physmem.num_writes::cpu.data 2026958 # Number of write requests responded to by this memory
+drivesys.physmem.bytes_written::total 14620696 # Number of bytes written to this memory
+drivesys.physmem.num_reads::cpu.inst 19051393 # Number of read requests responded to by this memory
+drivesys.physmem.num_reads::cpu.data 3647049 # Number of read requests responded to by this memory
+drivesys.physmem.num_reads::tsunami.ethernet 2385838 # Number of read requests responded to by this memory
+drivesys.physmem.num_reads::total 25084280 # Number of read requests responded to by this memory
+drivesys.physmem.num_writes::cpu.data 2024776 # Number of write requests responded to by this memory
drivesys.physmem.num_writes::tsunami.ethernet 37 # Number of write requests responded to by this memory
-drivesys.physmem.num_writes::total 2026995 # Number of write requests responded to by this memory
-drivesys.physmem.bw_read::cpu.inst 380664044 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::cpu.data 131295708 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::tsunami.ethernet 255323160 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::total 767282912 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::cpu.inst 380664044 # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::total 380664044 # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::cpu.data 73027831 # Write bandwidth from this memory (bytes/s)
+drivesys.physmem.num_writes::total 2024813 # Number of write requests responded to by this memory
+drivesys.physmem.bw_read::cpu.inst 380249708 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::cpu.data 131153065 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::tsunami.ethernet 285717930 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::total 797120704 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_inst_read::cpu.inst 380249708 # Instruction read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_inst_read::total 380249708 # Instruction read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_write::cpu.data 72948876 # Write bandwidth from this memory (bytes/s)
drivesys.physmem.bw_write::tsunami.ethernet 5309 # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::total 73033140 # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.inst 380664044 # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.data 204323539 # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::tsunami.ethernet 255328469 # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::total 840316053 # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.readReqs 0 # Total number of read requests seen
-drivesys.physmem.writeReqs 0 # Total number of write requests seen
-drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
-drivesys.physmem.bytesRead 0 # Total number of bytes read from memory
-drivesys.physmem.bytesWritten 0 # Total number of bytes written to memory
-drivesys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
-drivesys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-drivesys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-drivesys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-drivesys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
-drivesys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
-drivesys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-drivesys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-drivesys.physmem.totGap 0 # Total gap between requests
-drivesys.physmem.readPktSize::0 0 # Categorize read packet sizes
-drivesys.physmem.readPktSize::1 0 # Categorize read packet sizes
-drivesys.physmem.readPktSize::2 0 # Categorize read packet sizes
-drivesys.physmem.readPktSize::3 0 # Categorize read packet sizes
-drivesys.physmem.readPktSize::4 0 # Categorize read packet sizes
-drivesys.physmem.readPktSize::5 0 # Categorize read packet sizes
-drivesys.physmem.readPktSize::6 0 # Categorize read packet sizes
-drivesys.physmem.writePktSize::0 0 # Categorize write packet sizes
-drivesys.physmem.writePktSize::1 0 # Categorize write packet sizes
-drivesys.physmem.writePktSize::2 0 # Categorize write packet sizes
-drivesys.physmem.writePktSize::3 0 # Categorize write packet sizes
-drivesys.physmem.writePktSize::4 0 # Categorize write packet sizes
-drivesys.physmem.writePktSize::5 0 # Categorize write packet sizes
-drivesys.physmem.writePktSize::6 0 # Categorize write packet sizes
-drivesys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-drivesys.physmem.totQLat 0 # Total cycles spent in queuing delays
-drivesys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
-drivesys.physmem.totBusLat 0 # Total cycles spent in databus access
-drivesys.physmem.totBankLat 0 # Total cycles spent in bank access
-drivesys.physmem.avgQLat nan # Average queueing delay per request
-drivesys.physmem.avgBankLat nan # Average bank access latency per request
-drivesys.physmem.avgBusLat nan # Average bus latency per request
-drivesys.physmem.avgMemAccLat nan # Average memory access latency
-drivesys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
-drivesys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-drivesys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
-drivesys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
-drivesys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-drivesys.physmem.busUtil 0.00 # Data bus utilization in percentage
-drivesys.physmem.avgRdQLen 0.00 # Average read queue length over time
-drivesys.physmem.avgWrQLen 0.00 # Average write queue length over time
-drivesys.physmem.readRowHits 0 # Number of row buffer hits during reads
-drivesys.physmem.writeRowHits 0 # Number of row buffer hits during writes
-drivesys.physmem.readRowHitRate nan # Row buffer hit rate for reads
-drivesys.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-drivesys.physmem.avgGap nan # Average gap between requests
+drivesys.physmem.bw_write::total 72954185 # Write bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_total::cpu.inst 380249708 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::cpu.data 204101941 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::tsunami.ethernet 285723240 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::total 870074889 # Total bandwidth to/from this memory (bytes/s)
+drivesys.membus.throughput 874808223 # Throughput (bytes/s)
+drivesys.membus.data_through_bus 175319690 # Total data (bytes)
+drivesys.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
drivesys.cpu.dtb.fetch_misses 0 # ITB misses
drivesys.cpu.dtb.fetch_acv 0 # ITB acv
drivesys.cpu.dtb.fetch_accesses 0 # ITB accesses
-drivesys.cpu.dtb.read_hits 3729326 # DTB read hits
+drivesys.cpu.dtb.read_hits 3725273 # DTB read hits
drivesys.cpu.dtb.read_misses 487 # DTB read misses
drivesys.cpu.dtb.read_acv 30 # DTB read access violations
drivesys.cpu.dtb.read_accesses 267991 # DTB read accesses
-drivesys.cpu.dtb.write_hits 2086333 # DTB write hits
+drivesys.cpu.dtb.write_hits 2084079 # DTB write hits
drivesys.cpu.dtb.write_misses 82 # DTB write misses
drivesys.cpu.dtb.write_acv 10 # DTB write access violations
drivesys.cpu.dtb.write_accesses 133239 # DTB write accesses
-drivesys.cpu.dtb.data_hits 5815659 # DTB hits
+drivesys.cpu.dtb.data_hits 5809352 # DTB hits
drivesys.cpu.dtb.data_misses 569 # DTB misses
drivesys.cpu.dtb.data_acv 40 # DTB access violations
drivesys.cpu.dtb.data_accesses 401230 # DTB accesses
-drivesys.cpu.itb.fetch_hits 4201097 # ITB hits
+drivesys.cpu.itb.fetch_hits 4197628 # ITB hits
drivesys.cpu.itb.fetch_misses 194 # ITB misses
drivesys.cpu.itb.fetch_acv 22 # ITB acv
-drivesys.cpu.itb.fetch_accesses 4201291 # ITB accesses
+drivesys.cpu.itb.fetch_accesses 4197822 # ITB accesses
drivesys.cpu.itb.read_hits 0 # DTB read hits
drivesys.cpu.itb.read_misses 0 # DTB read misses
drivesys.cpu.itb.read_acv 0 # DTB read access violations
drivesys.cpu.itb.data_misses 0 # DTB misses
drivesys.cpu.itb.data_acv 0 # DTB access violations
drivesys.cpu.itb.data_accesses 0 # DTB accesses
-drivesys.cpu.numCycles 801619128 # number of cpu cycles simulated
+drivesys.cpu.numCycles 801631448 # number of cpu cycles simulated
drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-drivesys.cpu.committedInsts 19071544 # Number of instructions committed
-drivesys.cpu.committedOps 19071544 # Number of ops (including micro ops) committed
-drivesys.cpu.num_int_alu_accesses 17759891 # Number of integer alu accesses
+drivesys.cpu.committedInsts 19050784 # Number of instructions committed
+drivesys.cpu.committedOps 19050784 # Number of ops (including micro ops) committed
+drivesys.cpu.num_int_alu_accesses 17740632 # Number of integer alu accesses
drivesys.cpu.num_fp_alu_accesses 1412 # Number of float alu accesses
-drivesys.cpu.num_func_calls 1266408 # number of times a function call or return occured
-drivesys.cpu.num_conditional_control_insts 1266328 # number of instructions that are conditional controls
-drivesys.cpu.num_int_insts 17759891 # number of integer instructions
+drivesys.cpu.num_func_calls 1265024 # number of times a function call or return occured
+drivesys.cpu.num_conditional_control_insts 1264985 # number of instructions that are conditional controls
+drivesys.cpu.num_int_insts 17740632 # number of integer instructions
drivesys.cpu.num_fp_insts 1412 # number of float instructions
-drivesys.cpu.num_int_register_reads 23097438 # number of times the integer registers were read
-drivesys.cpu.num_int_register_writes 13996340 # number of times the integer registers were written
+drivesys.cpu.num_int_register_reads 23072330 # number of times the integer registers were read
+drivesys.cpu.num_int_register_writes 13981107 # number of times the integer registers were written
drivesys.cpu.num_fp_register_reads 760 # number of times the floating registers were read
drivesys.cpu.num_fp_register_writes 766 # number of times the floating registers were written
-drivesys.cpu.num_mem_refs 5837119 # number of memory refs
-drivesys.cpu.num_load_insts 3750273 # Number of load instructions
-drivesys.cpu.num_store_insts 2086846 # Number of store instructions
-drivesys.cpu.num_idle_cycles 782547188.298833 # Number of idle cycles
-drivesys.cpu.num_busy_cycles 19071939.701167 # Number of busy cycles
-drivesys.cpu.not_idle_fraction 0.023792 # Percentage of non-idle cycles
-drivesys.cpu.idle_fraction 0.976208 # Percentage of idle cycles
+drivesys.cpu.num_mem_refs 5830788 # number of memory refs
+drivesys.cpu.num_load_insts 3746196 # Number of load instructions
+drivesys.cpu.num_store_insts 2084592 # Number of store instructions
+drivesys.cpu.num_idle_cycles 782579974.227931 # Number of idle cycles
+drivesys.cpu.num_busy_cycles 19051473.772069 # Number of busy cycles
+drivesys.cpu.not_idle_fraction 0.023766 # Percentage of non-idle cycles
+drivesys.cpu.idle_fraction 0.976234 # Percentage of idle cycles
drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed
-drivesys.cpu.kern.inst.quiesce 19898 # number of quiesce instructions executed
-drivesys.cpu.kern.inst.hwrei 143758 # number of hwrei instructions executed
-drivesys.cpu.kern.ipl_count::0 60430 42.42% 42.42% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::21 19752 13.86% 56.28% # number of times we switched to this ipl
+drivesys.cpu.kern.inst.quiesce 19876 # number of quiesce instructions executed
+drivesys.cpu.kern.inst.hwrei 143591 # number of hwrei instructions executed
+drivesys.cpu.kern.ipl_count::0 60359 42.42% 42.42% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::21 19727 13.86% 56.28% # number of times we switched to this ipl
drivesys.cpu.kern.ipl_count::22 205 0.14% 56.42% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::31 62082 43.58% 100.00% # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_count::total 142469 # number of times we switched to this ipl
-drivesys.cpu.kern.ipl_good::0 60430 42.91% 42.91% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::21 19752 14.03% 56.94% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_count::31 62011 43.58% 100.00% # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_count::total 142302 # number of times we switched to this ipl
+drivesys.cpu.kern.ipl_good::0 60359 42.91% 42.91% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::21 19727 14.03% 56.94% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good::22 205 0.15% 57.09% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::31 60432 42.91% 100.00% # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_good::total 140819 # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_ticks::0 197392680000 98.50% 98.50% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::21 799890500 0.40% 98.90% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_good::31 60360 42.91% 100.00% # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_good::total 140651 # number of times we switched to this ipl from a different ipl
+drivesys.cpu.kern.ipl_ticks::0 197399332500 98.50% 98.50% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::21 798910750 0.40% 98.90% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks::22 4407500 0.00% 98.90% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::31 2207804000 1.10% 100.00% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::total 200404782000 # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::31 2205211250 1.10% 100.00% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::total 200407862000 # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::31 0.973422 # fraction of swpipl calls that actually changed the ipl
-drivesys.cpu.kern.ipl_used::total 0.988419 # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.ipl_used::31 0.973376 # fraction of swpipl calls that actually changed the ipl
+drivesys.cpu.kern.ipl_used::total 0.988398 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.syscall::2 1 4.55% 4.55% # number of syscalls executed
drivesys.cpu.kern.syscall::6 3 13.64% 18.18% # number of syscalls executed
drivesys.cpu.kern.syscall::17 2 9.09% 27.27% # number of syscalls executed
drivesys.cpu.kern.syscall::total 22 # number of syscalls executed
drivesys.cpu.kern.callpal::swpctx 72 0.06% 0.06% # number of callpals executed
drivesys.cpu.kern.callpal::tbi 5 0.00% 0.06% # number of callpals executed
-drivesys.cpu.kern.callpal::swpipl 102452 83.31% 83.37% # number of callpals executed
+drivesys.cpu.kern.callpal::swpipl 102333 83.31% 83.37% # number of callpals executed
drivesys.cpu.kern.callpal::rdps 354 0.29% 83.66% # number of callpals executed
drivesys.cpu.kern.callpal::rdusp 1 0.00% 83.66% # number of callpals executed
-drivesys.cpu.kern.callpal::rti 20062 16.31% 99.97% # number of callpals executed
+drivesys.cpu.kern.callpal::rti 20038 16.31% 99.97% # number of callpals executed
drivesys.cpu.kern.callpal::callsys 25 0.02% 99.99% # number of callpals executed
drivesys.cpu.kern.callpal::imb 7 0.01% 100.00% # number of callpals executed
-drivesys.cpu.kern.callpal::total 122978 # number of callpals executed
+drivesys.cpu.kern.callpal::total 122835 # number of callpals executed
drivesys.cpu.kern.mode_switch::kernel 214 # number of protection mode switches
-drivesys.cpu.kern.mode_switch::user 139 # number of protection mode switches
-drivesys.cpu.kern.mode_switch::idle 19920 # number of protection mode switches
-drivesys.cpu.kern.mode_good::kernel 143
-drivesys.cpu.kern.mode_good::user 139
+drivesys.cpu.kern.mode_switch::user 140 # number of protection mode switches
+drivesys.cpu.kern.mode_switch::idle 19896 # number of protection mode switches
+drivesys.cpu.kern.mode_good::kernel 144
+drivesys.cpu.kern.mode_good::user 140
drivesys.cpu.kern.mode_good::idle 4
-drivesys.cpu.kern.mode_switch_good::kernel 0.668224 # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_switch_good::kernel 0.672897 # fraction of useful protection mode switches
drivesys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
drivesys.cpu.kern.mode_switch_good::idle 0.000201 # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_switch_good::total 0.014107 # fraction of useful protection mode switches
-drivesys.cpu.kern.mode_ticks::kernel 78132750 2.64% 2.64% # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::user 319665750 10.79% 13.43% # number of ticks spent at the given mode
-drivesys.cpu.kern.mode_ticks::idle 2564974000 86.57% 100.00% # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_switch_good::total 0.014222 # fraction of useful protection mode switches
+drivesys.cpu.kern.mode_ticks::kernel 78134250 2.63% 2.63% # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_ticks::user 319668250 10.78% 13.41% # number of ticks spent at the given mode
+drivesys.cpu.kern.mode_ticks::idle 2567942000 86.59% 100.00% # number of ticks spent at the given mode
drivesys.cpu.kern.swap_context 72 # number of times the context was actually changed
drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted
drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received
drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device
drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device
-drivesys.tsunami.ethernet.descDMAReads 2132001 # Number of descriptors the device read w/ DMA
+drivesys.tsunami.ethernet.descDMAReads 2385809 # Number of descriptors the device read w/ DMA
drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA
-drivesys.tsunami.ethernet.descDmaReadBytes 51168024 # number of descriptor bytes read w/ DMA
+drivesys.tsunami.ethernet.descDmaReadBytes 57259416 # number of descriptor bytes read w/ DMA
drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA
drivesys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s)
drivesys.tsunami.ethernet.totPackets 13 # Total Packets
drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-drivesys.tsunami.ethernet.postedTxIdle 19750 # number of TxIdle interrupts posted to CPU
+drivesys.tsunami.ethernet.postedTxIdle 19726 # number of TxIdle interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
-drivesys.tsunami.ethernet.totalTxIdle 2132001 # total number of TxIdle written to ISR
+drivesys.tsunami.ethernet.totalTxIdle 2385809 # total number of TxIdle written to ISR
drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
-drivesys.tsunami.ethernet.postedInterrupts 2132022 # number of posts to CPU
+drivesys.tsunami.ethernet.postedInterrupts 2385830 # number of posts to CPU
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+drivesys.iobus.throughput 290456573 # Throughput (bytes/s)
+drivesys.iobus.data_through_bus 58210194 # Total data (bytes)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
sim_seconds 0.000407 # Number of seconds simulated
-sim_ticks 407365500 # Number of ticks simulated
-final_tick 4321609052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 407341500 # Number of ticks simulated
+final_tick 4321621592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 6212406894 # Simulator instruction rate (inst/s)
-host_op_rate 6210790807 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4809282801 # Simulator tick rate (ticks/s)
-host_mem_usage 472520 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
-sim_insts 525940622 # Number of instructions simulated
-sim_ops 525940622 # Number of ops (including micro ops) simulated
-testsys.physmem.bytes_read::cpu.inst 141136 # Number of bytes read from this memory
-testsys.physmem.bytes_read::cpu.data 48760 # Number of bytes read from this memory
-testsys.physmem.bytes_read::tsunami.ethernet 103992 # Number of bytes read from this memory
-testsys.physmem.bytes_read::total 293888 # Number of bytes read from this memory
-testsys.physmem.bytes_inst_read::cpu.inst 141136 # Number of instructions bytes read from this memory
-testsys.physmem.bytes_inst_read::total 141136 # Number of instructions bytes read from this memory
-testsys.physmem.bytes_written::cpu.data 27028 # Number of bytes written to this memory
-testsys.physmem.bytes_written::total 27028 # Number of bytes written to this memory
-testsys.physmem.num_reads::cpu.inst 35284 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::cpu.data 6744 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::tsunami.ethernet 4333 # Number of read requests responded to by this memory
-testsys.physmem.num_reads::total 46361 # Number of read requests responded to by this memory
-testsys.physmem.num_writes::cpu.data 3721 # Number of write requests responded to by this memory
-testsys.physmem.num_writes::total 3721 # Number of write requests responded to by this memory
-testsys.physmem.bw_read::cpu.inst 346460365 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::cpu.data 119695949 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::tsunami.ethernet 255279350 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_read::total 721435664 # Total read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::cpu.inst 346460365 # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_inst_read::total 346460365 # Instruction read bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::cpu.data 66348279 # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_write::total 66348279 # Write bandwidth from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.inst 346460365 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::cpu.data 186044228 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::tsunami.ethernet 255279350 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.bw_total::total 787783943 # Total bandwidth to/from this memory (bytes/s)
-testsys.physmem.readReqs 0 # Total number of read requests seen
-testsys.physmem.writeReqs 0 # Total number of write requests seen
-testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
-testsys.physmem.bytesRead 0 # Total number of bytes read from memory
-testsys.physmem.bytesWritten 0 # Total number of bytes written to memory
-testsys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
-testsys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-testsys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-testsys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-testsys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
-testsys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
-testsys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
-testsys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
-testsys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-testsys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-testsys.physmem.totGap 0 # Total gap between requests
-testsys.physmem.readPktSize::0 0 # Categorize read packet sizes
-testsys.physmem.readPktSize::1 0 # Categorize read packet sizes
-testsys.physmem.readPktSize::2 0 # Categorize read packet sizes
-testsys.physmem.readPktSize::3 0 # Categorize read packet sizes
-testsys.physmem.readPktSize::4 0 # Categorize read packet sizes
-testsys.physmem.readPktSize::5 0 # Categorize read packet sizes
-testsys.physmem.readPktSize::6 0 # Categorize read packet sizes
-testsys.physmem.writePktSize::0 0 # Categorize write packet sizes
-testsys.physmem.writePktSize::1 0 # Categorize write packet sizes
-testsys.physmem.writePktSize::2 0 # Categorize write packet sizes
-testsys.physmem.writePktSize::3 0 # Categorize write packet sizes
-testsys.physmem.writePktSize::4 0 # Categorize write packet sizes
-testsys.physmem.writePktSize::5 0 # Categorize write packet sizes
-testsys.physmem.writePktSize::6 0 # Categorize write packet sizes
-testsys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-testsys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-testsys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-testsys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-testsys.physmem.totQLat 0 # Total cycles spent in queuing delays
-testsys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
-testsys.physmem.totBusLat 0 # Total cycles spent in databus access
-testsys.physmem.totBankLat 0 # Total cycles spent in bank access
-testsys.physmem.avgQLat nan # Average queueing delay per request
-testsys.physmem.avgBankLat nan # Average bank access latency per request
-testsys.physmem.avgBusLat nan # Average bus latency per request
-testsys.physmem.avgMemAccLat nan # Average memory access latency
-testsys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
-testsys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-testsys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
-testsys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
-testsys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-testsys.physmem.busUtil 0.00 # Data bus utilization in percentage
-testsys.physmem.avgRdQLen 0.00 # Average read queue length over time
-testsys.physmem.avgWrQLen 0.00 # Average write queue length over time
-testsys.physmem.readRowHits 0 # Number of row buffer hits during reads
-testsys.physmem.writeRowHits 0 # Number of row buffer hits during writes
-testsys.physmem.readRowHitRate nan # Row buffer hit rate for reads
-testsys.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-testsys.physmem.avgGap nan # Average gap between requests
+host_inst_rate 5619093232 # Simulator instruction rate (inst/s)
+host_op_rate 5617709608 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4367114686 # Simulator tick rate (ticks/s)
+host_mem_usage 475668 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
+sim_insts 523862353 # Number of instructions simulated
+sim_ops 523862353 # Number of ops (including micro ops) simulated
+testsys.physmem.bytes_read::cpu.inst 144504 # Number of bytes read from this memory
+testsys.physmem.bytes_read::cpu.data 49936 # Number of bytes read from this memory
+testsys.physmem.bytes_read::tsunami.ethernet 116376 # Number of bytes read from this memory
+testsys.physmem.bytes_read::total 310816 # Number of bytes read from this memory
+testsys.physmem.bytes_inst_read::cpu.inst 144504 # Number of instructions bytes read from this memory
+testsys.physmem.bytes_inst_read::total 144504 # Number of instructions bytes read from this memory
+testsys.physmem.bytes_written::cpu.data 27704 # Number of bytes written to this memory
+testsys.physmem.bytes_written::total 27704 # Number of bytes written to this memory
+testsys.physmem.num_reads::cpu.inst 36126 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::cpu.data 6905 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::tsunami.ethernet 4849 # Number of read requests responded to by this memory
+testsys.physmem.num_reads::total 47880 # Number of read requests responded to by this memory
+testsys.physmem.num_writes::cpu.data 3814 # Number of write requests responded to by this memory
+testsys.physmem.num_writes::total 3814 # Number of write requests responded to by this memory
+testsys.physmem.bw_read::cpu.inst 354749025 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::cpu.data 122590014 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::tsunami.ethernet 285696400 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_read::total 763035438 # Total read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read::cpu.inst 354749025 # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_inst_read::total 354749025 # Instruction read bandwidth from this memory (bytes/s)
+testsys.physmem.bw_write::cpu.data 68011730 # Write bandwidth from this memory (bytes/s)
+testsys.physmem.bw_write::total 68011730 # Write bandwidth from this memory (bytes/s)
+testsys.physmem.bw_total::cpu.inst 354749025 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::tsunami.ethernet 285696400 # Total bandwidth to/from this memory (bytes/s)
+testsys.physmem.bw_total::total 831047168 # Total bandwidth to/from this memory (bytes/s)
+testsys.membus.throughput 835780297 # Throughput (bytes/s)
+testsys.membus.data_through_bus 340448 # Total data (bytes)
+testsys.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
testsys.cpu.dtb.fetch_misses 0 # ITB misses
testsys.cpu.dtb.fetch_acv 0 # ITB acv
testsys.cpu.dtb.fetch_accesses 0 # ITB accesses
-testsys.cpu.dtb.read_hits 6900 # DTB read hits
+testsys.cpu.dtb.read_hits 7065 # DTB read hits
testsys.cpu.dtb.read_misses 0 # DTB read misses
testsys.cpu.dtb.read_acv 0 # DTB read access violations
testsys.cpu.dtb.read_accesses 0 # DTB read accesses
-testsys.cpu.dtb.write_hits 3839 # DTB write hits
+testsys.cpu.dtb.write_hits 3935 # DTB write hits
testsys.cpu.dtb.write_misses 0 # DTB write misses
testsys.cpu.dtb.write_acv 0 # DTB write access violations
testsys.cpu.dtb.write_accesses 0 # DTB write accesses
-testsys.cpu.dtb.data_hits 10739 # DTB hits
+testsys.cpu.dtb.data_hits 11000 # DTB hits
testsys.cpu.dtb.data_misses 0 # DTB misses
testsys.cpu.dtb.data_acv 0 # DTB access violations
testsys.cpu.dtb.data_accesses 0 # DTB accesses
-testsys.cpu.itb.fetch_hits 5847 # ITB hits
+testsys.cpu.itb.fetch_hits 5992 # ITB hits
testsys.cpu.itb.fetch_misses 0 # ITB misses
testsys.cpu.itb.fetch_acv 0 # ITB acv
-testsys.cpu.itb.fetch_accesses 5847 # ITB accesses
+testsys.cpu.itb.fetch_accesses 5992 # ITB accesses
testsys.cpu.itb.read_hits 0 # DTB read hits
testsys.cpu.itb.read_misses 0 # DTB read misses
testsys.cpu.itb.read_acv 0 # DTB read access violations
testsys.cpu.itb.data_misses 0 # DTB misses
testsys.cpu.itb.data_acv 0 # DTB access violations
testsys.cpu.itb.data_accesses 0 # DTB accesses
-testsys.cpu.numCycles 799188 # number of cpu cycles simulated
+testsys.cpu.numCycles 821016 # number of cpu cycles simulated
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-testsys.cpu.committedInsts 35284 # Number of instructions committed
-testsys.cpu.committedOps 35284 # Number of ops (including micro ops) committed
-testsys.cpu.num_int_alu_accesses 32710 # Number of integer alu accesses
+testsys.cpu.committedInsts 36126 # Number of instructions committed
+testsys.cpu.committedOps 36126 # Number of ops (including micro ops) committed
+testsys.cpu.num_int_alu_accesses 33492 # Number of integer alu accesses
testsys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-testsys.cpu.num_func_calls 2330 # number of times a function call or return occured
-testsys.cpu.num_conditional_control_insts 2292 # number of instructions that are conditional controls
-testsys.cpu.num_int_insts 32710 # number of integer instructions
+testsys.cpu.num_func_calls 2384 # number of times a function call or return occured
+testsys.cpu.num_conditional_control_insts 2346 # number of instructions that are conditional controls
+testsys.cpu.num_int_insts 33492 # number of integer instructions
testsys.cpu.num_fp_insts 0 # number of float instructions
-testsys.cpu.num_int_register_reads 42720 # number of times the integer registers were read
-testsys.cpu.num_int_register_writes 25860 # number of times the integer registers were written
+testsys.cpu.num_int_register_reads 43747 # number of times the integer registers were read
+testsys.cpu.num_int_register_writes 26476 # number of times the integer registers were written
testsys.cpu.num_fp_register_reads 0 # number of times the floating registers were read
testsys.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-testsys.cpu.num_mem_refs 10779 # number of memory refs
-testsys.cpu.num_load_insts 6939 # Number of load instructions
-testsys.cpu.num_store_insts 3840 # Number of store instructions
-testsys.cpu.num_idle_cycles 764577.129267 # Number of idle cycles
-testsys.cpu.num_busy_cycles 34610.870733 # Number of busy cycles
-testsys.cpu.not_idle_fraction 0.043308 # Percentage of non-idle cycles
-testsys.cpu.idle_fraction 0.956692 # Percentage of idle cycles
+testsys.cpu.num_mem_refs 11041 # number of memory refs
+testsys.cpu.num_load_insts 7105 # Number of load instructions
+testsys.cpu.num_store_insts 3936 # Number of store instructions
+testsys.cpu.num_idle_cycles 784609.171892 # Number of idle cycles
+testsys.cpu.num_busy_cycles 36406.828108 # Number of busy cycles
+testsys.cpu.not_idle_fraction 0.044344 # Percentage of non-idle cycles
+testsys.cpu.idle_fraction 0.955656 # Percentage of idle cycles
testsys.cpu.kern.inst.arm 0 # number of arm instructions executed
testsys.cpu.kern.inst.quiesce 40 # number of quiesce instructions executed
-testsys.cpu.kern.inst.hwrei 288 # number of hwrei instructions executed
-testsys.cpu.kern.ipl_count::0 120 41.81% 41.81% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::21 39 13.59% 55.40% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::22 1 0.35% 55.75% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::31 127 44.25% 100.00% # number of times we switched to this ipl
-testsys.cpu.kern.ipl_count::total 287 # number of times we switched to this ipl
-testsys.cpu.kern.ipl_good::0 120 42.86% 42.86% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::21 39 13.93% 56.79% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::22 1 0.36% 57.14% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::31 120 42.86% 100.00% # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_good::total 280 # number of times we switched to this ipl from a different ipl
-testsys.cpu.kern.ipl_ticks::0 387349500 96.94% 96.94% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::21 3159000 0.79% 97.73% # number of cycles we spent at this ipl
+testsys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed
+testsys.cpu.kern.ipl_count::0 123 41.84% 41.84% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::21 40 13.61% 55.44% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::22 1 0.34% 55.78% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::31 130 44.22% 100.00% # number of times we switched to this ipl
+testsys.cpu.kern.ipl_count::total 294 # number of times we switched to this ipl
+testsys.cpu.kern.ipl_good::0 123 42.86% 42.86% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::21 40 13.94% 56.79% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl
+testsys.cpu.kern.ipl_ticks::0 397967000 96.95% 96.95% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::21 3240000 0.79% 97.73% # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_ticks::22 43000 0.01% 97.74% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::31 9042500 2.26% 100.00% # number of cycles we spent at this ipl
-testsys.cpu.kern.ipl_ticks::total 399594000 # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::31 9258000 2.26% 100.00% # number of cycles we spent at this ipl
+testsys.cpu.kern.ipl_ticks::total 410508000 # number of cycles we spent at this ipl
testsys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::31 0.944882 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.ipl_used::total 0.975610 # fraction of swpipl calls that actually changed the ipl
-testsys.cpu.kern.callpal::swpipl 207 83.47% 83.47% # number of callpals executed
-testsys.cpu.kern.callpal::rdps 1 0.40% 83.87% # number of callpals executed
-testsys.cpu.kern.callpal::rti 40 16.13% 100.00% # number of callpals executed
-testsys.cpu.kern.callpal::total 248 # number of callpals executed
+testsys.cpu.kern.ipl_used::31 0.946154 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.ipl_used::total 0.976190 # fraction of swpipl calls that actually changed the ipl
+testsys.cpu.kern.callpal::swpipl 212 83.46% 83.46% # number of callpals executed
+testsys.cpu.kern.callpal::rdps 1 0.39% 83.86% # number of callpals executed
+testsys.cpu.kern.callpal::rti 41 16.14% 100.00% # number of callpals executed
+testsys.cpu.kern.callpal::total 254 # number of callpals executed
testsys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches
testsys.cpu.kern.mode_switch::user 0 # number of protection mode switches
-testsys.cpu.kern.mode_switch::idle 40 # number of protection mode switches
+testsys.cpu.kern.mode_switch::idle 41 # number of protection mode switches
testsys.cpu.kern.mode_good::kernel 0
testsys.cpu.kern.mode_good::user 0
testsys.cpu.kern.mode_good::idle 0
testsys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode
testsys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
testsys.cpu.kern.swap_context 0 # number of times the context was actually changed
-testsys.tsunami.ethernet.descDMAReads 4333 # Number of descriptors the device read w/ DMA
+testsys.tsunami.ethernet.descDMAReads 4849 # Number of descriptors the device read w/ DMA
testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-testsys.tsunami.ethernet.descDmaReadBytes 103992 # number of descriptor bytes read w/ DMA
+testsys.tsunami.ethernet.descDmaReadBytes 116376 # number of descriptor bytes read w/ DMA
testsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-testsys.tsunami.ethernet.postedTxIdle 39 # number of TxIdle interrupts posted to CPU
+testsys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU
testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
-testsys.tsunami.ethernet.totalTxIdle 4333 # total number of TxIdle written to ISR
+testsys.tsunami.ethernet.totalTxIdle 4849 # total number of TxIdle written to ISR
testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
-testsys.tsunami.ethernet.postedInterrupts 4333 # number of posts to CPU
+testsys.tsunami.ethernet.postedInterrupts 4849 # number of posts to CPU
testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+testsys.iobus.throughput 290429529 # Throughput (bytes/s)
+testsys.iobus.data_through_bus 118304 # Total data (bytes)
drivesys.physmem.bytes_read::cpu.inst 144608 # Number of bytes read from this memory
drivesys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory
-drivesys.physmem.bytes_read::tsunami.ethernet 104016 # Number of bytes read from this memory
-drivesys.physmem.bytes_read::total 298576 # Number of bytes read from this memory
+drivesys.physmem.bytes_read::tsunami.ethernet 116400 # Number of bytes read from this memory
+drivesys.physmem.bytes_read::total 310960 # Number of bytes read from this memory
drivesys.physmem.bytes_inst_read::cpu.inst 144608 # Number of instructions bytes read from this memory
drivesys.physmem.bytes_inst_read::total 144608 # Number of instructions bytes read from this memory
drivesys.physmem.bytes_written::cpu.data 27688 # Number of bytes written to this memory
drivesys.physmem.bytes_written::total 27688 # Number of bytes written to this memory
drivesys.physmem.num_reads::cpu.inst 36152 # Number of read requests responded to by this memory
drivesys.physmem.num_reads::cpu.data 6909 # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::tsunami.ethernet 4334 # Number of read requests responded to by this memory
-drivesys.physmem.num_reads::total 47395 # Number of read requests responded to by this memory
+drivesys.physmem.num_reads::tsunami.ethernet 4850 # Number of read requests responded to by this memory
+drivesys.physmem.num_reads::total 47911 # Number of read requests responded to by this memory
drivesys.physmem.num_writes::cpu.data 3812 # Number of write requests responded to by this memory
drivesys.physmem.num_writes::total 3812 # Number of write requests responded to by this memory
-drivesys.physmem.bw_read::cpu.inst 354983424 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::cpu.data 122622068 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::tsunami.ethernet 255338265 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_read::total 732943757 # Total read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::cpu.inst 354983424 # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_inst_read::total 354983424 # Instruction read bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::cpu.data 67968446 # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_write::total 67968446 # Write bandwidth from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.inst 354983424 # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::cpu.data 190590514 # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::tsunami.ethernet 255338265 # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.bw_total::total 800912203 # Total bandwidth to/from this memory (bytes/s)
-drivesys.physmem.readReqs 0 # Total number of read requests seen
-drivesys.physmem.writeReqs 0 # Total number of write requests seen
-drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
-drivesys.physmem.bytesRead 0 # Total number of bytes read from memory
-drivesys.physmem.bytesWritten 0 # Total number of bytes written to memory
-drivesys.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
-drivesys.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
-drivesys.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-drivesys.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-drivesys.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
-drivesys.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
-drivesys.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
-drivesys.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
-drivesys.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-drivesys.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-drivesys.physmem.totGap 0 # Total gap between requests
-drivesys.physmem.readPktSize::0 0 # Categorize read packet sizes
-drivesys.physmem.readPktSize::1 0 # Categorize read packet sizes
-drivesys.physmem.readPktSize::2 0 # Categorize read packet sizes
-drivesys.physmem.readPktSize::3 0 # Categorize read packet sizes
-drivesys.physmem.readPktSize::4 0 # Categorize read packet sizes
-drivesys.physmem.readPktSize::5 0 # Categorize read packet sizes
-drivesys.physmem.readPktSize::6 0 # Categorize read packet sizes
-drivesys.physmem.writePktSize::0 0 # Categorize write packet sizes
-drivesys.physmem.writePktSize::1 0 # Categorize write packet sizes
-drivesys.physmem.writePktSize::2 0 # Categorize write packet sizes
-drivesys.physmem.writePktSize::3 0 # Categorize write packet sizes
-drivesys.physmem.writePktSize::4 0 # Categorize write packet sizes
-drivesys.physmem.writePktSize::5 0 # Categorize write packet sizes
-drivesys.physmem.writePktSize::6 0 # Categorize write packet sizes
-drivesys.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-drivesys.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-drivesys.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-drivesys.physmem.totQLat 0 # Total cycles spent in queuing delays
-drivesys.physmem.totMemAccLat 0 # Sum of mem lat for all requests
-drivesys.physmem.totBusLat 0 # Total cycles spent in databus access
-drivesys.physmem.totBankLat 0 # Total cycles spent in bank access
-drivesys.physmem.avgQLat nan # Average queueing delay per request
-drivesys.physmem.avgBankLat nan # Average bank access latency per request
-drivesys.physmem.avgBusLat nan # Average bus latency per request
-drivesys.physmem.avgMemAccLat nan # Average memory access latency
-drivesys.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s
-drivesys.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-drivesys.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s
-drivesys.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
-drivesys.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-drivesys.physmem.busUtil 0.00 # Data bus utilization in percentage
-drivesys.physmem.avgRdQLen 0.00 # Average read queue length over time
-drivesys.physmem.avgWrQLen 0.00 # Average write queue length over time
-drivesys.physmem.readRowHits 0 # Number of row buffer hits during reads
-drivesys.physmem.writeRowHits 0 # Number of row buffer hits during writes
-drivesys.physmem.readRowHitRate nan # Row buffer hit rate for reads
-drivesys.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-drivesys.physmem.avgGap nan # Average gap between requests
+drivesys.physmem.bw_read::cpu.inst 355004339 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::cpu.data 122629293 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::tsunami.ethernet 285755318 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_read::total 763388950 # Total read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_inst_read::cpu.inst 355004339 # Instruction read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_inst_read::total 355004339 # Instruction read bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_write::cpu.data 67972451 # Write bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_write::total 67972451 # Write bandwidth from this memory (bytes/s)
+drivesys.physmem.bw_total::cpu.inst 355004339 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::tsunami.ethernet 285755318 # Total bandwidth to/from this memory (bytes/s)
+drivesys.physmem.bw_total::total 831361401 # Total bandwidth to/from this memory (bytes/s)
+drivesys.membus.throughput 836094530 # Throughput (bytes/s)
+drivesys.membus.data_through_bus 340576 # Total data (bytes)
+drivesys.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
drivesys.cpu.itb.data_misses 0 # DTB misses
drivesys.cpu.itb.data_acv 0 # DTB access violations
drivesys.cpu.itb.data_accesses 0 # DTB accesses
-drivesys.cpu.numCycles 1624320 # number of cpu cycles simulated
+drivesys.cpu.numCycles 1626240 # number of cpu cycles simulated
drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
drivesys.cpu.committedInsts 36152 # Number of instructions committed
drivesys.cpu.num_mem_refs 11043 # number of memory refs
drivesys.cpu.num_load_insts 7109 # Number of load instructions
drivesys.cpu.num_store_insts 3934 # Number of store instructions
-drivesys.cpu.num_idle_cycles 1588282.082886 # Number of idle cycles
-drivesys.cpu.num_busy_cycles 36037.917114 # Number of busy cycles
-drivesys.cpu.not_idle_fraction 0.022186 # Percentage of non-idle cycles
-drivesys.cpu.idle_fraction 0.977814 # Percentage of idle cycles
+drivesys.cpu.num_idle_cycles 1590157.359061 # Number of idle cycles
+drivesys.cpu.num_busy_cycles 36082.640939 # Number of busy cycles
+drivesys.cpu.not_idle_fraction 0.022188 # Percentage of non-idle cycles
+drivesys.cpu.idle_fraction 0.977812 # Percentage of idle cycles
drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed
drivesys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed
drivesys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed
drivesys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl
drivesys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl
-drivesys.cpu.kern.ipl_ticks::0 399809000 98.46% 98.46% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::21 1620000 0.40% 98.85% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::0 400289000 98.46% 98.46% # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::21 1620000 0.40% 98.86% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks::22 21500 0.01% 98.86% # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_ticks::31 4629500 1.14% 100.00% # number of cycles we spent at this ipl
-drivesys.cpu.kern.ipl_ticks::total 406080000 # number of cycles we spent at this ipl
+drivesys.cpu.kern.ipl_ticks::total 406560000 # number of cycles we spent at this ipl
drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
drivesys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode
drivesys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed
-drivesys.tsunami.ethernet.descDMAReads 4334 # Number of descriptors the device read w/ DMA
+drivesys.tsunami.ethernet.descDMAReads 4850 # Number of descriptors the device read w/ DMA
drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-drivesys.tsunami.ethernet.descDmaReadBytes 104016 # number of descriptor bytes read w/ DMA
+drivesys.tsunami.ethernet.descDmaReadBytes 116400 # number of descriptor bytes read w/ DMA
drivesys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
drivesys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post
-drivesys.tsunami.ethernet.totalTxIdle 4334 # total number of TxIdle written to ISR
+drivesys.tsunami.ethernet.totalTxIdle 4850 # total number of TxIdle written to ISR
drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post
-drivesys.tsunami.ethernet.postedInterrupts 4334 # number of posts to CPU
+drivesys.tsunami.ethernet.postedInterrupts 4850 # number of posts to CPU
drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped
+drivesys.iobus.throughput 290488448 # Throughput (bytes/s)
+drivesys.iobus.data_through_bus 118328 # Total data (bytes)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000019 # Number of seconds simulated
-sim_ticks 19476000 # Number of ticks simulated
-final_tick 19476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000025 # Number of seconds simulated
+sim_ticks 24560000 # Number of ticks simulated
+final_tick 24560000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1322 # Simulator instruction rate (inst/s)
-host_op_rate 1322 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4028719 # Simulator tick rate (ticks/s)
-host_mem_usage 223696 # Number of bytes of host memory used
-host_seconds 4.83 # Real time elapsed on the host
+host_inst_rate 1785 # Simulator instruction rate (inst/s)
+host_op_rate 1785 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6860090 # Simulator tick rate (ticks/s)
+host_mem_usage 225432 # Number of bytes of host memory used
+host_seconds 3.58 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
system.physmem.num_reads::total 468 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 985828712 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 552064079 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1537892791 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 985828712 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 985828712 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 985828712 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 552064079 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1537892791 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 781758958 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 437785016 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1219543974 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 781758958 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 781758958 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 781758958 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 437785016 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1219543974 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 469 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 23 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 28 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 26 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 43 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 49 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 29 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 41 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 17 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 6 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 7 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 3 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 47 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 27 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 47 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 19 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 1 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 3 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 19 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 25 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 119 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 46 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 12 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 19461500 # Total gap between requests
+system.physmem.totGap 24545500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 301 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 317 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2627750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 13374000 # Sum of mem lat for all requests
+system.physmem.bytesPerActivate::samples 67 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 285.611940 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 145.316634 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 484.514157 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64 33 49.25% 49.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128 8 11.94% 61.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192 5 7.46% 68.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256 5 7.46% 76.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320 4 5.97% 82.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384 3 4.48% 86.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448 1 1.49% 88.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512 1 1.49% 89.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704 1 1.49% 91.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768 1 1.49% 92.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832 1 1.49% 94.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344 1 1.49% 95.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856 1 1.49% 97.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368 1 1.49% 98.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496 1 1.49% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 67 # Bytes accessed per row activation
+system.physmem.totQLat 1607750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 11529000 # Sum of mem lat for all requests
system.physmem.totBusLat 2345000 # Total cycles spent in databus access
-system.physmem.totBankLat 8401250 # Total cycles spent in bank access
-system.physmem.avgQLat 5602.88 # Average queueing delay per request
-system.physmem.avgBankLat 17913.11 # Average bank access latency per request
+system.physmem.totBankLat 7576250 # Total cycles spent in bank access
+system.physmem.avgQLat 3428.04 # Average queueing delay per request
+system.physmem.avgBankLat 16154.05 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 28515.99 # Average memory access latency
-system.physmem.avgRdBW 1537.89 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 24582.09 # Average memory access latency
+system.physmem.avgRdBW 1219.54 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1537.89 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1219.54 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 12.01 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.69 # Average read queue length over time
+system.physmem.busUtil 9.53 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.47 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 377 # Number of row buffer hits during reads
+system.physmem.readRowHits 402 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 80.38 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 85.71 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 41495.74 # Average gap between requests
+system.physmem.avgGap 52335.82 # Average gap between requests
+system.membus.throughput 1219543974 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 396 # Transaction distribution
+system.membus.trans_dist::ReadResp 395 # Transaction distribution
+system.membus.trans_dist::ReadExReq 73 # Transaction distribution
+system.membus.trans_dist::ReadExResp 73 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 937 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 937 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29952 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 29952 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 29952 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 563500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4381500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 17.8 # Layer utilization (%)
system.cpu.branchPred.lookups 1632 # Number of BP lookups
system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 1183 # DTB read hits
+system.cpu.dtb.read_hits 1184 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 1190 # DTB read accesses
-system.cpu.dtb.write_hits 866 # DTB write hits
+system.cpu.dtb.read_accesses 1191 # DTB read accesses
+system.cpu.dtb.write_hits 893 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 869 # DTB write accesses
-system.cpu.dtb.data_hits 2049 # DTB hits
+system.cpu.dtb.write_accesses 896 # DTB write accesses
+system.cpu.dtb.data_hits 2077 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 2059 # DTB accesses
+system.cpu.dtb.data_accesses 2087 # DTB accesses
system.cpu.itb.fetch_hits 915 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 38953 # number of cpu cycles simulated
+system.cpu.numCycles 49121 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 1130 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 5201 # Number of Reads from Int. Register File
+system.cpu.regfile_manager.intRegFileReads 5174 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 4567 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 9768 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses 9741 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 2949 # Number of Registers Read Through Forwarding Logic
+system.cpu.regfile_manager.regForwards 2976 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 2152 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 325 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 11544 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 11658 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 503 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 31578 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 7375 # Number of cycles cpu stages are processed.
-system.cpu.activity 18.933073 # Percentage of cycles cpu is active
+system.cpu.timesIdled 510 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 41745 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 7376 # Number of cycles cpu stages are processed.
+system.cpu.activity 15.015981 # Percentage of cycles cpu is active
system.cpu.comLoads 1183 # Number of Load instructions committed
system.cpu.comStores 865 # Number of Store instructions committed
system.cpu.comBranches 1050 # Number of Branches instructions committed
system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total)
-system.cpu.cpi 6.095931 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 7.687167 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 6.095931 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.164044 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 7.687167 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.130087 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 0.164044 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 34029 # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total 0.130087 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 44197 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 12.640875 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 35060 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.utilization 10.024226 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 45228 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 9.994095 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 34792 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.utilization 7.925327 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 44960 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 4161 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 10.682104 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 37647 # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 1306 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 3.352758 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 34441 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 4512 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 11.583190 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.utilization 8.470919 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 47787 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 1334 # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 2.715743 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 44663 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 9.075548 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 142.957443 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 140.779037 # Cycle average of tags in use
system.cpu.icache.total_refs 560 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1.860465 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 142.957443 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.069803 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.069803 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst 140.779037 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.068740 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.068740 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits
system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses
system.cpu.icache.overall_misses::total 355 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 18504000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 18504000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 18504000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 18504000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 18504000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 18504000 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 24103000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 24103000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 24103000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 24103000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 24103000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 24103000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses
system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52123.943662 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 52123.943662 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 52123.943662 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 52123.943662 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 52123.943662 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 52123.943662 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67895.774648 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 67895.774648 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 67895.774648 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 67895.774648 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 67895.774648 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 67895.774648 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 88 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 48 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 88 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15862500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 15862500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15862500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 15862500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15862500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 15862500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20462500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 20462500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20462500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 20462500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20462500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 20462500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses
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system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57326.315789 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57326.315789 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49808.219178 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49808.219178 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 54059.523810 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 54059.523810 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 54059.523810 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 54059.523810 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74042.105263 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74042.105263 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67876.712329 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67876.712329 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71363.095238 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 71363.095238 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71363.095238 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 71363.095238 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000016 # Number of seconds simulated
-sim_ticks 16032500 # Number of ticks simulated
-final_tick 16032500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000021 # Number of seconds simulated
+sim_ticks 20632000 # Number of ticks simulated
+final_tick 20632000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 34765 # Simulator instruction rate (inst/s)
-host_op_rate 34761 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 87452252 # Simulator tick rate (ticks/s)
-host_mem_usage 269696 # Number of bytes of host memory used
-host_seconds 0.18 # Real time elapsed on the host
+host_inst_rate 1782 # Simulator instruction rate (inst/s)
+host_op_rate 1782 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5769044 # Simulator tick rate (ticks/s)
+host_mem_usage 227476 # Number of bytes of host memory used
+host_seconds 3.58 # Real time elapsed on the host
sim_insts 6372 # Number of instructions simulated
sim_ops 6372 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory
-system.physmem.bytes_read::total 31104 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 31168 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 486 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1245470139 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 694589116 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1940059255 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1245470139 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1245470139 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1245470139 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 694589116 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1940059255 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 486 # Total number of read requests seen
+system.physmem.num_reads::total 487 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 970918961 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 539744087 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1510663048 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 970918961 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 970918961 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 970918961 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 539744087 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1510663048 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 488 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 31104 # Total number of bytes read from memory
+system.physmem.cpureqs 488 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 31168 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 31104 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 24 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 26 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 47 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 50 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 31 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 44 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 20 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 6 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 8 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 3 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 45 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 34 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 32 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 47 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 43 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 21 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 1 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 3 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 24 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 14 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 119 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 45 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 12 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 15819000 # Total gap between requests
+system.physmem.totGap 20599000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 486 # Categorize read packet sizes
+system.physmem.readPktSize::6 488 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 247 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 285 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 139 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2907500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 13642500 # Sum of mem lat for all requests
-system.physmem.totBusLat 2430000 # Total cycles spent in databus access
-system.physmem.totBankLat 8305000 # Total cycles spent in bank access
-system.physmem.avgQLat 5982.51 # Average queueing delay per request
-system.physmem.avgBankLat 17088.48 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 69 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 293.101449 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 146.944081 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 525.630997 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64 33 47.83% 47.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128 7 10.14% 57.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192 9 13.04% 71.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256 5 7.25% 78.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320 2 2.90% 81.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384 3 4.35% 85.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448 2 2.90% 88.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512 2 2.90% 91.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576 1 1.45% 92.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960 1 1.45% 94.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1664 1 1.45% 95.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920 1 1.45% 97.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2496 1 1.45% 98.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880 1 1.45% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation
+system.physmem.totQLat 2633750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 12636250 # Sum of mem lat for all requests
+system.physmem.totBusLat 2440000 # Total cycles spent in databus access
+system.physmem.totBankLat 7562500 # Total cycles spent in bank access
+system.physmem.avgQLat 5397.03 # Average queueing delay per request
+system.physmem.avgBankLat 15496.93 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 28070.99 # Average memory access latency
-system.physmem.avgRdBW 1940.06 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 25893.95 # Average memory access latency
+system.physmem.avgRdBW 1510.66 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1940.06 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1510.66 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 15.16 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.85 # Average read queue length over time
+system.physmem.busUtil 11.80 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.61 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 396 # Number of row buffer hits during reads
+system.physmem.readRowHits 419 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.48 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 85.86 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 32549.38 # Average gap between requests
-system.cpu.branchPred.lookups 2896 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 513 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 2200 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 746 # Number of BTB hits
+system.physmem.avgGap 42211.07 # Average gap between requests
+system.membus.throughput 1510663048 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 415 # Transaction distribution
+system.membus.trans_dist::ReadResp 414 # Transaction distribution
+system.membus.trans_dist::ReadExReq 73 # Transaction distribution
+system.membus.trans_dist::ReadExResp 73 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 975 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 975 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 31168 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 31168 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 31168 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 600000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4550500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 22.1 # Layer utilization (%)
+system.cpu.branchPred.lookups 2906 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1709 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 511 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 2211 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 759 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 33.909091 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 416 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 34.328358 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 420 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 2071 # DTB read hits
-system.cpu.dtb.read_misses 50 # DTB read misses
+system.cpu.dtb.read_hits 2097 # DTB read hits
+system.cpu.dtb.read_misses 47 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 2121 # DTB read accesses
-system.cpu.dtb.write_hits 1069 # DTB write hits
-system.cpu.dtb.write_misses 30 # DTB write misses
+system.cpu.dtb.read_accesses 2144 # DTB read accesses
+system.cpu.dtb.write_hits 1063 # DTB write hits
+system.cpu.dtb.write_misses 31 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 1099 # DTB write accesses
-system.cpu.dtb.data_hits 3140 # DTB hits
-system.cpu.dtb.data_misses 80 # DTB misses
+system.cpu.dtb.write_accesses 1094 # DTB write accesses
+system.cpu.dtb.data_hits 3160 # DTB hits
+system.cpu.dtb.data_misses 78 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 3220 # DTB accesses
-system.cpu.itb.fetch_hits 2349 # ITB hits
-system.cpu.itb.fetch_misses 38 # ITB misses
+system.cpu.dtb.data_accesses 3238 # DTB accesses
+system.cpu.itb.fetch_hits 2393 # ITB hits
+system.cpu.itb.fetch_misses 39 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 2387 # ITB accesses
+system.cpu.itb.fetch_accesses 2432 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 32066 # number of cpu cycles simulated
+system.cpu.numCycles 41265 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 8354 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 16527 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2896 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1162 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2951 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1883 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 1142 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 2349 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 363 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 14511 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.138929 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.535970 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 8511 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 16675 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2906 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2982 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1908 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 1525 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 759 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 2393 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 379 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 15107 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.103793 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.501598 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 11560 79.66% 79.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 317 2.18% 81.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 230 1.59% 83.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 219 1.51% 84.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 255 1.76% 86.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 218 1.50% 88.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 264 1.82% 90.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 185 1.27% 91.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1263 8.70% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 12125 80.26% 80.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 320 2.12% 82.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 234 1.55% 83.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 215 1.42% 85.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 256 1.69% 87.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 241 1.60% 88.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 264 1.75% 90.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 187 1.24% 91.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1265 8.37% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 14511 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.090314 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.515406 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 9311 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 1148 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2752 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1212 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 252 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 15357 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 231 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1212 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 9520 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 459 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 372 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2630 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 318 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 14673 # Number of instructions processed by rename
+system.cpu.fetch.rateDist::total 15107 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.070423 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.404095 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 9355 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 1672 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2793 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 63 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1224 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 242 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 15419 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1224 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 9566 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 693 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 555 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2621 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 448 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 14692 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 286 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 11018 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 18307 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 18290 # Number of integer rename lookups
+system.cpu.rename.LSQFullEvents 388 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 11020 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 18321 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 18304 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6448 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 6450 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 30 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 757 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2761 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1357 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts 976 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2777 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1360 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 13018 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 10806 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 50 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 6314 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 3579 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 14511 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.744676 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.388965 # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded 12985 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 10814 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 6280 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 3603 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 15107 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.715827 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.359683 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10031 69.13% 69.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1602 11.04% 80.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 1157 7.97% 88.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 759 5.23% 93.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 471 3.25% 96.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 281 1.94% 98.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 159 1.10% 99.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 38 0.26% 99.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 10552 69.85% 69.85% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1715 11.35% 81.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 1107 7.33% 88.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 773 5.12% 93.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 494 3.27% 96.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 269 1.78% 98.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 148 0.98% 99.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 35 0.23% 99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 14511 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 15107 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 16 13.56% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 63 53.39% 66.95% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 39 33.05% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 14 12.61% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 59 53.15% 65.77% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 38 34.23% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 7299 67.55% 67.56% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.57% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.57% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.59% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2362 21.86% 89.45% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1140 10.55% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 7260 67.14% 67.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.16% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.16% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.18% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2415 22.33% 89.51% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1134 10.49% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 10806 # Type of FU issued
-system.cpu.iq.rate 0.336992 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 118 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.010920 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 36270 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 19365 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 9699 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 10814 # Type of FU issued
+system.cpu.iq.rate 0.262062 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 111 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.010264 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 36878 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 19300 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 9631 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 10911 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 10912 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 72 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1578 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1594 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 492 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 495 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 87 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 136 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1212 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 151 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 13132 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 147 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2761 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1357 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewSquashCycles 1224 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 218 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 13104 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 177 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2777 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1360 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 126 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 519 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 10153 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2132 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 653 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 124 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 385 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 509 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 10116 # Number of executed instructions
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+system.cpu.iew.iewExecSquashedInsts 698 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 86 # number of nop insts executed
-system.cpu.iew.exec_refs 3233 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1613 # Number of branches executed
-system.cpu.iew.exec_stores 1101 # Number of stores executed
-system.cpu.iew.exec_rate 0.316628 # Inst execution rate
-system.cpu.iew.wb_sent 9856 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 9709 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 5133 # num instructions producing a value
-system.cpu.iew.wb_consumers 6918 # num instructions consuming a value
+system.cpu.iew.exec_nop 89 # number of nop insts executed
+system.cpu.iew.exec_refs 3251 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1595 # Number of branches executed
+system.cpu.iew.exec_stores 1096 # Number of stores executed
+system.cpu.iew.exec_rate 0.245147 # Inst execution rate
+system.cpu.iew.wb_sent 9787 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 9641 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 5053 # num instructions producing a value
+system.cpu.iew.wb_consumers 6805 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.302782 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.741977 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.233636 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.742542 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 6741 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 6713 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 13299 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.480412 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.303409 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 430 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 13883 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.460203 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.266435 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 10550 79.33% 79.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1447 10.88% 90.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 514 3.86% 94.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 246 1.85% 95.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 153 1.15% 97.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 103 0.77% 97.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 101 0.76% 98.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 37 0.28% 98.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 148 1.11% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 11056 79.64% 79.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1544 11.12% 90.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 511 3.68% 94.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 249 1.79% 96.23% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 151 1.09% 97.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 81 0.58% 97.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 113 0.81% 98.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 35 0.25% 98.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 143 1.03% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 13299 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 13883 # Number of insts commited each cycle
system.cpu.commit.committedInsts 6389 # Number of instructions committed
system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 10 # Number of committed floating point instructions.
system.cpu.commit.int_insts 6307 # Number of committed integer instructions.
system.cpu.commit.function_calls 127 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 148 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 25930 # The number of ROB reads
-system.cpu.rob.rob_writes 27481 # The number of ROB writes
-system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 17555 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 26491 # The number of ROB reads
+system.cpu.rob.rob_writes 27437 # The number of ROB writes
+system.cpu.timesIdled 274 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 26158 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 6372 # Number of Instructions Simulated
system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 6372 # Number of Instructions Simulated
-system.cpu.cpi 5.032329 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 5.032329 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.198715 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.198715 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 12887 # number of integer regfile reads
-system.cpu.int_regfile_writes 7342 # number of integer regfile writes
+system.cpu.cpi 6.475989 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 6.475989 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.154417 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.154417 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 12831 # number of integer regfile reads
+system.cpu.int_regfile_writes 7294 # number of integer regfile writes
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
+system.cpu.toL2Bus.throughput 1513765025 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 629 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 348 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 977 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 20096 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 31232 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 471000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 261000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 159.192462 # Cycle average of tags in use
-system.cpu.icache.total_refs 1869 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 5.971246 # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse 159.617277 # Cycle average of tags in use
+system.cpu.icache.total_refs 1903 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 6.060510 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 159.192462 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.077731 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.077731 # Average percentage of cache occupancy
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-system.cpu.icache.overall_hits::total 1869 # number of overall hits
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-system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::total 480 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 22201500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 22201500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 22201500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 22201500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 22201500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 22201500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 2349 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 2349 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total 2349 # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total 2349 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204342 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.204342 # miss rate for ReadReq accesses
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-system.cpu.icache.demand_miss_rate::total 0.204342 # miss rate for demand accesses
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-system.cpu.icache.overall_miss_rate::total 0.204342 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46253.125000 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 46253.125000 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 46253.125000 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 46253.125000 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 46253.125000 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 46253.125000 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 159.617277 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.077938 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.077938 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 1903 # number of ReadReq hits
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+system.cpu.icache.overall_misses::total 490 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 30064500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 30064500 # number of ReadReq miss cycles
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+system.cpu.icache.overall_miss_rate::total 0.204764 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61356.122449 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 61356.122449 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 61356.122449 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 61356.122449 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 61356.122449 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 61356.122449 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits
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-system.cpu.icache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits
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-system.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses
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-system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16101000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 16101000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16101000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 16101000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16101000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 16101000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133248 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.133248 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.133248 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51440.894569 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51440.894569 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51440.894569 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 51440.894569 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51440.894569 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 51440.894569 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 175 # number of ReadReq MSHR hits
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-system.cpu.dcache.demand_hits::total 2262 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2262 # number of overall hits
-system.cpu.dcache.overall_hits::total 2262 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data 2246 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2246 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2246 # number of overall hits
+system.cpu.dcache.overall_hits::total 2246 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 528 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 528 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 528 # number of overall misses
-system.cpu.dcache.overall_misses::total 528 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 9128000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 9128000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 15893487 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 15893487 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 25021487 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 25021487 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 25021487 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 25021487 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1925 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1925 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 529 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 529 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 529 # number of overall misses
+system.cpu.dcache.overall_misses::total 529 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 11698500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 11698500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 21723478 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 21723478 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 33421978 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 33421978 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 33421978 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 33421978 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1910 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1910 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2790 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2790 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2790 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2790 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087792 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.087792 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2775 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2775 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2775 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2775 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.089005 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.089005 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.189247 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.189247 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.189247 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.189247 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54011.834320 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 54011.834320 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44271.551532 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 44271.551532 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 47389.179924 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 47389.179924 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 47389.179924 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 47389.179924 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 862 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data 0.190631 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.190631 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.190631 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.190631 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68814.705882 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 68814.705882 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60511.080780 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 60511.080780 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 63179.542533 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 63179.542533 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 63179.542533 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63179.542533 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 1568 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.478261 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.515152 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 68 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 354 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 354 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 354 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 354 # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6189000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 6189000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3763500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3763500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9952500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 9952500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9952500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 9952500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052468 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052468 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8145500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 8145500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5182500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5182500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13328000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 13328000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13328000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 13328000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052880 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052880 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062366 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.062366 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062366 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.062366 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61277.227723 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61277.227723 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51554.794521 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51554.794521 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57198.275862 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 57198.275862 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57198.275862 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 57198.275862 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062703 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.062703 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062703 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.062703 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80648.514851 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80648.514851 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70993.150685 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70993.150685 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76597.701149 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 76597.701149 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76597.701149 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 76597.701149 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 3208000 # Number of ticks simulated
final_tick 3208000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 84722 # Simulator instruction rate (inst/s)
-host_op_rate 84702 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 42507676 # Simulator tick rate (ticks/s)
-host_mem_usage 261184 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 2502 # Simulator instruction rate (inst/s)
+host_op_rate 2502 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1255935 # Simulator tick rate (ticks/s)
+host_mem_usage 215792 # Number of bytes of host memory used
+host_seconds 2.55 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7980049875 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4826683292 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12806733167 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 12806733167 # Throughput (bytes/s)
+system.membus.data_through_bus 41084 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
sim_ticks 32544000 # Number of ticks simulated
final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 97330 # Simulator instruction rate (inst/s)
-host_op_rate 97300 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 495402774 # Simulator tick rate (ticks/s)
-host_mem_usage 269640 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
+host_inst_rate 19861 # Simulator instruction rate (inst/s)
+host_op_rate 19860 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 101141711 # Simulator tick rate (ticks/s)
+host_mem_usage 224276 # Number of bytes of host memory used
+host_seconds 0.32 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 877089479 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 373 # Transaction distribution
+system.membus.trans_dist::ReadResp 373 # Transaction distribution
+system.membus.trans_dist::ReadExReq 73 # Transaction distribution
+system.membus.trans_dist::ReadExResp 73 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 892 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 892 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 28544 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 12.3 # Layer utilization (%)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 879056047 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 558 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 336 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 894 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17856 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 10752 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 28608 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 28608 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000009 # Number of seconds simulated
-sim_ticks 9350000 # Number of ticks simulated
-final_tick 9350000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000012 # Number of seconds simulated
+sim_ticks 11848000 # Number of ticks simulated
+final_tick 11848000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 14656 # Simulator instruction rate (inst/s)
-host_op_rate 14654 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 57391857 # Simulator tick rate (ticks/s)
-host_mem_usage 269408 # Number of bytes of host memory used
-host_seconds 0.16 # Real time elapsed on the host
+host_inst_rate 800 # Simulator instruction rate (inst/s)
+host_op_rate 800 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3968846 # Simulator tick rate (ticks/s)
+host_mem_usage 226160 # Number of bytes of host memory used
+host_seconds 2.99 # Real time elapsed on the host
sim_insts 2387 # Number of instructions simulated
sim_ops 2387 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
system.physmem.num_reads::total 272 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1280000000 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 581818182 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1861818182 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1280000000 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1280000000 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1280000000 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 581818182 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1861818182 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1010128292 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 459149223 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1469277515 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1010128292 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1010128292 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1010128292 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 459149223 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1469277515 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 272 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 272 # Reqs generatd by CPU via cache - shady
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 39 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 25 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 9 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 22 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 7 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 6 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 19 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 6 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 17 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 29 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 16 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 16 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 18 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 21 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 2 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 24 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 18 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 24 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 37 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 60 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 2 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 14 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 9 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 17 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 51 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 12 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 1 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 9280500 # Total gap between requests
+system.physmem.totGap 11758500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 148 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 87 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 158 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 1327750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 7871500 # Sum of mem lat for all requests
+system.physmem.bytesPerActivate::samples 33 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 277.333333 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 136.700631 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 448.761258 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64 20 60.61% 60.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128 1 3.03% 63.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192 2 6.06% 69.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256 1 3.03% 72.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320 2 6.06% 78.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448 1 3.03% 81.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512 2 6.06% 87.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768 2 6.06% 93.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152 1 3.03% 96.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304 1 3.03% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 33 # Bytes accessed per row activation
+system.physmem.totQLat 1380750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 6920750 # Sum of mem lat for all requests
system.physmem.totBusLat 1360000 # Total cycles spent in databus access
-system.physmem.totBankLat 5183750 # Total cycles spent in bank access
-system.physmem.avgQLat 4881.43 # Average queueing delay per request
-system.physmem.avgBankLat 19057.90 # Average bank access latency per request
+system.physmem.totBankLat 4180000 # Total cycles spent in bank access
+system.physmem.avgQLat 5076.29 # Average queueing delay per request
+system.physmem.avgBankLat 15367.65 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 28939.34 # Average memory access latency
-system.physmem.avgRdBW 1861.82 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 25443.93 # Average memory access latency
+system.physmem.avgRdBW 1469.28 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1861.82 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1469.28 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 14.55 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.84 # Average read queue length over time
+system.physmem.busUtil 11.48 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.58 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 207 # Number of row buffer hits during reads
+system.physmem.readRowHits 239 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 76.10 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 87.87 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 34119.49 # Average gap between requests
-system.cpu.branchPred.lookups 1154 # Number of BP lookups
-system.cpu.branchPred.condPredicted 581 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 258 # Number of conditional branches incorrect
+system.physmem.avgGap 43229.78 # Average gap between requests
+system.membus.throughput 1469277515 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 248 # Transaction distribution
+system.membus.trans_dist::ReadResp 248 # Transaction distribution
+system.membus.trans_dist::ReadExReq 24 # Transaction distribution
+system.membus.trans_dist::ReadExResp 24 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 544 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 544 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 17408 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 17408 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 17408 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 337000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
+system.membus.respLayer1.occupancy 2542750 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 21.5 # Layer utilization (%)
+system.cpu.branchPred.lookups 1157 # Number of BP lookups
+system.cpu.branchPred.condPredicted 604 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 257 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 791 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 226 # Number of BTB hits
+system.cpu.branchPred.BTBHits 240 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 28.571429 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 39 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 30.341340 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 212 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 37 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 708 # DTB read hits
+system.cpu.dtb.read_hits 704 # DTB read hits
system.cpu.dtb.read_misses 28 # DTB read misses
system.cpu.dtb.read_acv 1 # DTB read access violations
-system.cpu.dtb.read_accesses 736 # DTB read accesses
-system.cpu.dtb.write_hits 357 # DTB write hits
-system.cpu.dtb.write_misses 20 # DTB write misses
+system.cpu.dtb.read_accesses 732 # DTB read accesses
+system.cpu.dtb.write_hits 354 # DTB write hits
+system.cpu.dtb.write_misses 19 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 377 # DTB write accesses
-system.cpu.dtb.data_hits 1065 # DTB hits
-system.cpu.dtb.data_misses 48 # DTB misses
+system.cpu.dtb.write_accesses 373 # DTB write accesses
+system.cpu.dtb.data_hits 1058 # DTB hits
+system.cpu.dtb.data_misses 47 # DTB misses
system.cpu.dtb.data_acv 1 # DTB access violations
-system.cpu.dtb.data_accesses 1113 # DTB accesses
-system.cpu.itb.fetch_hits 1043 # ITB hits
+system.cpu.dtb.data_accesses 1105 # DTB accesses
+system.cpu.itb.fetch_hits 1045 # ITB hits
system.cpu.itb.fetch_misses 30 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 1073 # ITB accesses
+system.cpu.itb.fetch_accesses 1075 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
-system.cpu.numCycles 18701 # number of cpu cycles simulated
+system.cpu.numCycles 23697 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 4191 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 6947 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 1154 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 450 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 1194 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 869 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 306 # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles 4326 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 6897 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 1157 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 452 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 1190 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 858 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 471 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1024 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingTrapStallCycles 1121 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 1043 # Number of cache lines fetched
+system.cpu.fetch.CacheLines 1045 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 182 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 7322 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.948784 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.362451 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 7700 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.895714 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.301681 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 6128 83.69% 83.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 54 0.74% 84.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 114 1.56% 85.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 92 1.26% 87.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 168 2.29% 89.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 73 1.00% 90.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 64 0.87% 91.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 64 0.87% 92.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 565 7.72% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 6510 84.55% 84.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 52 0.68% 85.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 117 1.52% 86.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 91 1.18% 87.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 172 2.23% 90.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 75 0.97% 91.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 61 0.79% 91.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 67 0.87% 92.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 555 7.21% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 7322 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.061708 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.371477 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 5334 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 332 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 1148 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 8 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 500 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total 7700 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.048825 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.291049 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 5567 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 499 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 1144 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 5 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 485 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 163 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 6173 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 500 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 5434 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 109 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 186 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 1056 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 37 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 5903 # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 16 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 4293 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 6642 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 6630 # Number of integer rename lookups
+system.cpu.decode.DecodedInsts 6120 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 292 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 485 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 5671 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 178 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 1044 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 32 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 5812 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 10 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 4232 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 6563 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 6551 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 2525 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 2464 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 133 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 964 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 466 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 5010 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts 121 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 948 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 455 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 4912 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 4065 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 2458 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1421 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 4000 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 63 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 2288 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1369 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 7322 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.555176 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.266886 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 7700 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.519481 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.232756 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 5697 77.81% 77.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 561 7.66% 85.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 397 5.42% 90.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 261 3.56% 94.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 207 2.83% 97.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 126 1.72% 99.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 50 0.68% 99.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 15 0.20% 99.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 8 0.11% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 6104 79.27% 79.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 546 7.09% 86.36% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 391 5.08% 91.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 259 3.36% 94.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 207 2.69% 97.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 122 1.58% 99.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 48 0.62% 99.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 15 0.19% 99.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 8 0.10% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 7322 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 7700 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 2 4.35% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 21 45.65% 50.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 23 50.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 2 4.55% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 19 43.18% 47.73% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 23 52.27% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 2890 71.09% 71.09% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.12% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 787 19.36% 90.48% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 387 9.52% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 2840 71.00% 71.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 778 19.45% 90.47% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 381 9.53% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 4065 # Type of FU issued
-system.cpu.iq.rate 0.217368 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 46 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.011316 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 15538 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 7472 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 3658 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 4000 # Type of FU issued
+system.cpu.iq.rate 0.168798 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 44 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.011000 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 15794 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 7204 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 3598 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 4104 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 4037 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 36 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 549 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 533 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 172 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 161 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 10 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 500 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 100 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 5355 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 129 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 964 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 466 # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles 485 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 153 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 5240 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 948 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 455 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 53 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 159 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 215 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 3852 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 737 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 213 # Number of squashed instructions skipped in execute
+system.cpu.iew.branchMispredicts 212 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 3798 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 733 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 202 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 339 # number of nop insts executed
-system.cpu.iew.exec_refs 1114 # number of memory reference insts executed
-system.cpu.iew.exec_branches 649 # Number of branches executed
-system.cpu.iew.exec_stores 377 # Number of stores executed
-system.cpu.iew.exec_rate 0.205978 # Inst execution rate
-system.cpu.iew.wb_sent 3743 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 3664 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1729 # num instructions producing a value
-system.cpu.iew.wb_consumers 2228 # num instructions consuming a value
+system.cpu.iew.exec_nop 322 # number of nop insts executed
+system.cpu.iew.exec_refs 1106 # number of memory reference insts executed
+system.cpu.iew.exec_branches 638 # Number of branches executed
+system.cpu.iew.exec_stores 373 # Number of stores executed
+system.cpu.iew.exec_rate 0.160273 # Inst execution rate
+system.cpu.iew.wb_sent 3682 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 3604 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1694 # num instructions producing a value
+system.cpu.iew.wb_consumers 2179 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.195925 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.776032 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.152087 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.777421 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 2758 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 2655 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 6822 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.377602 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.238659 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 179 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 7215 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.357034 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.202430 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 5958 87.34% 87.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 201 2.95% 90.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 310 4.54% 94.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 116 1.70% 96.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 63 0.92% 97.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 50 0.73% 98.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 32 0.47% 98.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 23 0.34% 98.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 69 1.01% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 6348 87.98% 87.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 203 2.81% 90.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 309 4.28% 95.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 113 1.57% 96.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 69 0.96% 97.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 52 0.72% 98.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 33 0.46% 98.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 22 0.30% 99.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 66 0.91% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 6822 # Number of insts commited each cycle
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system.cpu.commit.committedInsts 2576 # Number of instructions committed
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 44.507812 # Cycle average of tags in use
-system.cpu.dcache.total_refs 763 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.333333 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
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system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59811.475410 # average ReadReq mshr miss latency
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+system.cpu.dcache.demand_mshr_miss_rate::total 0.089380 # mshr miss rate for demand accesses
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+system.cpu.dcache.overall_avg_mshr_miss_latency::total 75317.647059 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 1297500 # Number of ticks simulated
final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 34130 # Simulator instruction rate (inst/s)
-host_op_rate 34121 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 17175609 # Simulator tick rate (ticks/s)
-host_mem_usage 260900 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 388869 # Simulator instruction rate (inst/s)
+host_op_rate 388153 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 195100518 # Simulator tick rate (ticks/s)
+host_mem_usage 215488 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7969171484 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3910597303 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11879768786 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 11879768786 # Throughput (bytes/s)
+system.membus.data_through_bus 15414 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
sim_ticks 16524000 # Number of ticks simulated
final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 14244 # Simulator instruction rate (inst/s)
-host_op_rate 14243 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 91318433 # Simulator tick rate (ticks/s)
-host_mem_usage 268332 # Number of bytes of host memory used
-host_seconds 0.18 # Real time elapsed on the host
+host_inst_rate 252355 # Simulator instruction rate (inst/s)
+host_op_rate 251860 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1611932908 # Simulator tick rate (ticks/s)
+host_mem_usage 223992 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 631324135 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 317598644 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 948922779 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 948922779 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 218 # Transaction distribution
+system.membus.trans_dist::ReadResp 218 # Transaction distribution
+system.membus.trans_dist::ReadExReq 27 # Transaction distribution
+system.membus.trans_dist::ReadExResp 27 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 490 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 490 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15680 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 15680 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 15680 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 245000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 1.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 2205000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 13.3 # Layer utilization (%)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 948922779 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 218 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 326 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 164 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 490 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 10432 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 5248 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 15680 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 15680 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 244500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000014 # Number of seconds simulated
-sim_ticks 13706000 # Number of ticks simulated
-final_tick 13706000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000016 # Number of seconds simulated
+sim_ticks 16387000 # Number of ticks simulated
+final_tick 16387000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 599 # Simulator instruction rate (inst/s)
-host_op_rate 748 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1788642 # Simulator tick rate (ticks/s)
-host_mem_usage 284080 # Number of bytes of host memory used
-host_seconds 7.66 # Real time elapsed on the host
+host_inst_rate 31359 # Simulator instruction rate (inst/s)
+host_op_rate 39125 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 111893890 # Simulator tick rate (ticks/s)
+host_mem_usage 244352 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5729 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory
-system.physmem.bytes_read::total 25216 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 25152 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 394 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1270100686 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 569677513 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1839778199 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1270100686 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1270100686 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1270100686 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 569677513 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1839778199 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 394 # Total number of read requests seen
+system.physmem.num_reads::total 393 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1058399951 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 476475255 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1534875206 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1058399951 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1058399951 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1058399951 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 476475255 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1534875206 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 393 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 25216 # Total number of bytes read from memory
+system.physmem.cpureqs 393 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 25152 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 26 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 40 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 12 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 36 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 22 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 18 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 7 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 43 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 33 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 9 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 15 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 42 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 17 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 35 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 10 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 8 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 42 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 9 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 6 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 13648500 # Total gap between requests
+system.physmem.totGap 16329500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 394 # Categorize read packet sizes
+system.physmem.readPktSize::6 393 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 213 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2507750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 11751500 # Sum of mem lat for all requests
-system.physmem.totBusLat 1970000 # Total cycles spent in databus access
-system.physmem.totBankLat 7273750 # Total cycles spent in bank access
-system.physmem.avgQLat 6364.85 # Average queueing delay per request
-system.physmem.avgBankLat 18461.29 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 45 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 335.644444 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 165.301810 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 465.758285 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64 21 46.67% 46.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128 5 11.11% 57.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192 4 8.89% 66.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256 3 6.67% 73.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320 2 4.44% 77.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448 1 2.22% 80.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512 1 2.22% 82.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704 1 2.22% 84.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960 1 2.22% 86.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024 1 2.22% 88.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152 1 2.22% 91.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation
+system.physmem.totQLat 2029000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 9466500 # Sum of mem lat for all requests
+system.physmem.totBusLat 1965000 # Total cycles spent in databus access
+system.physmem.totBankLat 5472500 # Total cycles spent in bank access
+system.physmem.avgQLat 5162.85 # Average queueing delay per request
+system.physmem.avgBankLat 13924.94 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 29826.14 # Average memory access latency
-system.physmem.avgRdBW 1839.78 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 24087.79 # Average memory access latency
+system.physmem.avgRdBW 1534.88 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1839.78 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1534.88 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 14.37 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.86 # Average read queue length over time
+system.physmem.busUtil 11.99 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.58 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 294 # Number of row buffer hits during reads
+system.physmem.readRowHits 348 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 34640.86 # Average gap between requests
-system.cpu.branchPred.lookups 2491 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1787 # Number of conditional branches predicted
+system.physmem.avgGap 41550.89 # Average gap between requests
+system.membus.throughput 1534875206 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 352 # Transaction distribution
+system.membus.trans_dist::ReadResp 352 # Transaction distribution
+system.membus.trans_dist::ReadExReq 41 # Transaction distribution
+system.membus.trans_dist::ReadExResp 41 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 786 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 786 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 25152 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 25152 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 25152 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 480500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
+system.membus.respLayer1.occupancy 3664000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 22.4 # Layer utilization (%)
+system.cpu.branchPred.lookups 2471 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1774 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1976 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 700 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 1960 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 695 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 35.425101 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 35.459184 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions.
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.numCycles 27413 # number of cpu cycles simulated
+system.cpu.numCycles 32775 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 6976 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 11965 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2491 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 992 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1618 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 2255 # Number of cycles fetch has spent blocked
-system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 12987 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.170247 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.582932 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 11884 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2471 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 987 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2620 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1611 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 2625 # Number of cycles fetch has spent blocked
+system.cpu.fetch.CacheLines 1942 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 13325 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.128105 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.544240 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10343 79.64% 79.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 225 1.73% 81.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 203 1.56% 82.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 225 1.73% 84.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 221 1.70% 86.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 273 2.10% 88.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 93 0.72% 89.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 147 1.13% 90.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1257 9.68% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10705 80.34% 80.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 226 1.70% 82.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 201 1.51% 83.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 224 1.68% 85.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 220 1.65% 86.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 270 2.03% 88.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 92 0.69% 89.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 146 1.10% 90.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1241 9.31% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 12987 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.090869 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.436472 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 6960 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2563 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2438 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 957 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 388 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 13303 # Number of instructions handled by decode
+system.cpu.fetch.rateDist::total 13325 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.075393 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.362593 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 6989 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 2898 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2415 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 950 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 13178 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 957 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 7226 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 330 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2238 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 12535 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 12533 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 56960 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 56600 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups
+system.cpu.rename.SquashCycles 950 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 7255 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 368 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 2315 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2217 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 12419 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 12443 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 56366 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 56110 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 256 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6860 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 6770 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 41 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 677 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2799 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts 688 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2784 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1569 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 11241 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 11162 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8967 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 119 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 5221 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14417 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 5126 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14148 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 12987 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.690460 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.397167 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 13325 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.669493 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.373683 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 9407 72.43% 72.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1316 10.13% 82.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 806 6.21% 88.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 531 4.09% 92.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 466 3.59% 96.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 267 2.06% 98.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 125 0.96% 99.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 55 0.42% 99.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 14 0.11% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 9737 73.07% 73.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1330 9.98% 83.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 808 6.06% 89.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 537 4.03% 93.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 465 3.49% 96.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 260 1.95% 98.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 124 0.93% 99.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 52 0.39% 99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 12987 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 13325 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 8 3.48% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 144 62.61% 66.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 78 33.91% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 6 2.69% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 139 62.33% 65.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 78 34.98% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5390 60.11% 60.11% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.22% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2344 26.14% 86.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1223 13.64% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5362 60.11% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2334 26.16% 86.40% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8967 # Type of FU issued
-system.cpu.iq.rate 0.327108 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 230 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.025650 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 31234 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 16481 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 8073 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 8921 # Type of FU issued
+system.cpu.iq.rate 0.272189 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 223 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.024997 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 31465 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 16306 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 9177 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 9124 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1599 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1584 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 22 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 654 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 631 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 957 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 11290 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2799 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles 950 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 232 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 11211 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2784 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1569 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations
+system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 271 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 379 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8545 # Number of executed instructions
+system.cpu.iew.predictedNotTakenIncorrect 269 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 8517 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 422 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3301 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1438 # Number of branches executed
-system.cpu.iew.exec_stores 1167 # Number of stores executed
-system.cpu.iew.exec_rate 0.311713 # Inst execution rate
-system.cpu.iew.wb_sent 8247 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 8089 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 3894 # num instructions producing a value
-system.cpu.iew.wb_consumers 7825 # num instructions consuming a value
+system.cpu.iew.exec_refs 3294 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1436 # Number of branches executed
+system.cpu.iew.exec_stores 1160 # Number of stores executed
+system.cpu.iew.exec_rate 0.259863 # Inst execution rate
+system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 8068 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 3885 # num instructions producing a value
+system.cpu.iew.wb_consumers 7780 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.295079 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.497636 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.246163 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.499357 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 5566 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 5487 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 12030 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.476226 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.310563 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 12375 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.462949 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.295788 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 9744 81.00% 81.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1074 8.93% 89.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 398 3.31% 93.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 256 2.13% 95.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 181 1.50% 96.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 49 0.41% 98.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 35 0.29% 98.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 121 1.01% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 10091 81.54% 81.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1074 8.68% 90.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 396 3.20% 93.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 256 2.07% 95.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 180 1.45% 96.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 172 1.39% 98.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 35 0.28% 99.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 12030 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 12375 # Number of insts commited each cycle
system.cpu.commit.committedInsts 4591 # Number of instructions committed
system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 4976 # Number of committed integer instructions.
system.cpu.commit.function_calls 82 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 23047 # The number of ROB reads
-system.cpu.rob.rob_writes 23560 # The number of ROB writes
+system.cpu.rob.rob_reads 23312 # The number of ROB reads
+system.cpu.rob.rob_writes 23396 # The number of ROB writes
system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 14426 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 19450 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4591 # Number of Instructions Simulated
system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 4591 # Number of Instructions Simulated
-system.cpu.cpi 5.971030 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 5.971030 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.167475 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.167475 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 39296 # number of integer regfile reads
-system.cpu.int_regfile_writes 8001 # number of integer regfile writes
+system.cpu.cpi 7.138968 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.138968 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.140076 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.140076 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 39187 # number of integer regfile reads
+system.cpu.int_regfile_writes 7985 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 2981 # number of misc regfile reads
+system.cpu.misc_regfile_reads 2976 # number of misc regfile reads
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
-system.cpu.icache.replacements 3 # number of replacements
-system.cpu.icache.tagsinuse 146.948464 # Cycle average of tags in use
-system.cpu.icache.total_refs 1590 # Total number of references to valid blocks.
+system.cpu.toL2Bus.throughput 1706718740 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 293 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 875 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9344 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 27968 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 436500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 221495 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
+system.cpu.icache.replacements 4 # number of replacements
+system.cpu.icache.tagsinuse 145.578272 # Cycle average of tags in use
+system.cpu.icache.total_refs 1578 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 5.463918 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 5.422680 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 146.948464 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.071752 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.071752 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 1590 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1590 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1590 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1590 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1590 # number of overall hits
-system.cpu.icache.overall_hits::total 1590 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses
-system.cpu.icache.overall_misses::total 360 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 17732500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 17732500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 17732500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 17732500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 17732500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 17732500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1950 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1950 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1950 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1950 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1950 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184615 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.184615 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.184615 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.184615 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.184615 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.184615 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49256.944444 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 49256.944444 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 49256.944444 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 49256.944444 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 49256.944444 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 49256.944444 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst 145.578272 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.071083 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.071083 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 1578 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1578 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1578 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1578 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1578 # number of overall hits
+system.cpu.icache.overall_hits::total 1578 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses
+system.cpu.icache.overall_misses::total 364 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 22955000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 22955000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 22955000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 22955000 # number of demand (read+write) miss cycles
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+system.cpu.icache.overall_miss_latency::total 22955000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1942 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1942 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1942 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1942 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1942 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1942 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187436 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.187436 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.187436 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.187436 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.187436 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.187436 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63063.186813 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 63063.186813 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 63063.186813 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 63063.186813 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 121 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 40.333333 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14598500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 14598500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14598500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 14598500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14598500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 14598500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149231 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.149231 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.149231 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50166.666667 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50166.666667 # average ReadReq mshr miss latency
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-system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits
-system.cpu.dcache.overall_hits::total 2369 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 193 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 193 # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data 2366 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2366 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2366 # number of overall hits
+system.cpu.dcache.overall_hits::total 2366 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses
-system.cpu.dcache.overall_misses::total 500 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 8675500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 8675500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 14874500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 14874500 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 23550000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 23550000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 23550000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 23550000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses
+system.cpu.dcache.overall_misses::total 497 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 10638500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 10638500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 19663000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 19663000 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 127500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 127500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 30301500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 30301500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 30301500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 30301500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1950 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098671 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.098671 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2863 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2863 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097436 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.097436 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.174277 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.174277 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.174277 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.174277 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44950.777202 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 44950.777202 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.140065 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 48451.140065 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 47100 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 47100 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 47100 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 47100 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data 0.173594 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.173594 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.173594 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.173594 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55992.105263 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55992.105263 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64048.859935 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64048.859935 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63750 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63750 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 60968.812877 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 60968.812877 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 103 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.666667 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.333333 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 87 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 353 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 353 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 353 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 353 # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5218000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 5218000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2444500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 2444500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7662500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 7662500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7662500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 7662500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6438005 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 6438005 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3034500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3034500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9472505 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 9472505 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9472505 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 9472505 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054359 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054359 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59621.951220 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.051345 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.051345 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60735.896226 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60735.896226 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74012.195122 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74012.195122 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000014 # Number of seconds simulated
-sim_ticks 13706000 # Number of ticks simulated
-final_tick 13706000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000016 # Number of seconds simulated
+sim_ticks 16387000 # Number of ticks simulated
+final_tick 16387000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 7143 # Simulator instruction rate (inst/s)
-host_op_rate 8913 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 21323596 # Simulator tick rate (ticks/s)
-host_mem_usage 284080 # Number of bytes of host memory used
-host_seconds 0.64 # Real time elapsed on the host
+host_inst_rate 36614 # Simulator instruction rate (inst/s)
+host_op_rate 45680 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 130634561 # Simulator tick rate (ticks/s)
+host_mem_usage 244344 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5729 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory
-system.physmem.bytes_read::total 25216 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 25152 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 394 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1270100686 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 569677513 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1839778199 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1270100686 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1270100686 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1270100686 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 569677513 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1839778199 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 394 # Total number of read requests seen
+system.physmem.num_reads::total 393 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1058399951 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 476475255 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1534875206 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1058399951 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1058399951 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1058399951 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 476475255 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1534875206 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 393 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 25216 # Total number of bytes read from memory
+system.physmem.cpureqs 393 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 25152 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 26 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 40 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 12 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 36 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 22 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 18 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 7 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 43 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 33 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 9 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 15 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 42 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 17 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 35 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 10 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 8 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 42 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 9 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 6 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 13648500 # Total gap between requests
+system.physmem.totGap 16329500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 394 # Categorize read packet sizes
+system.physmem.readPktSize::6 393 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 213 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2507750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 11751500 # Sum of mem lat for all requests
-system.physmem.totBusLat 1970000 # Total cycles spent in databus access
-system.physmem.totBankLat 7273750 # Total cycles spent in bank access
-system.physmem.avgQLat 6364.85 # Average queueing delay per request
-system.physmem.avgBankLat 18461.29 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 45 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 335.644444 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 165.301810 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 465.758285 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64 21 46.67% 46.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128 5 11.11% 57.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192 4 8.89% 66.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256 3 6.67% 73.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320 2 4.44% 77.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448 1 2.22% 80.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512 1 2.22% 82.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704 1 2.22% 84.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960 1 2.22% 86.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024 1 2.22% 88.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1152 1 2.22% 91.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation
+system.physmem.totQLat 2029000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 9466500 # Sum of mem lat for all requests
+system.physmem.totBusLat 1965000 # Total cycles spent in databus access
+system.physmem.totBankLat 5472500 # Total cycles spent in bank access
+system.physmem.avgQLat 5162.85 # Average queueing delay per request
+system.physmem.avgBankLat 13924.94 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 29826.14 # Average memory access latency
-system.physmem.avgRdBW 1839.78 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 24087.79 # Average memory access latency
+system.physmem.avgRdBW 1534.88 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1839.78 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1534.88 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 14.37 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.86 # Average read queue length over time
+system.physmem.busUtil 11.99 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.58 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 294 # Number of row buffer hits during reads
+system.physmem.readRowHits 348 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 34640.86 # Average gap between requests
-system.cpu.branchPred.lookups 2491 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1787 # Number of conditional branches predicted
+system.physmem.avgGap 41550.89 # Average gap between requests
+system.membus.throughput 1534875206 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 352 # Transaction distribution
+system.membus.trans_dist::ReadResp 352 # Transaction distribution
+system.membus.trans_dist::ReadExReq 41 # Transaction distribution
+system.membus.trans_dist::ReadExResp 41 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 786 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 786 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 25152 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 25152 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 25152 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 480500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 2.9 # Layer utilization (%)
+system.membus.respLayer1.occupancy 3664000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 22.4 # Layer utilization (%)
+system.cpu.branchPred.lookups 2471 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1774 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1976 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 700 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 1960 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 695 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 35.425101 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 35.459184 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
-system.cpu.numCycles 27413 # number of cpu cycles simulated
+system.cpu.numCycles 32775 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 6976 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 11965 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2491 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 992 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1618 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 2255 # Number of cycles fetch has spent blocked
-system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 12987 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.170247 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.582932 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 11884 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2471 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 987 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2620 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1611 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 2625 # Number of cycles fetch has spent blocked
+system.cpu.fetch.CacheLines 1942 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 13325 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.128105 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.544240 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10343 79.64% 79.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 225 1.73% 81.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 203 1.56% 82.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 225 1.73% 84.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 221 1.70% 86.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 273 2.10% 88.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 93 0.72% 89.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 147 1.13% 90.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1257 9.68% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10705 80.34% 80.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 226 1.70% 82.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 201 1.51% 83.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 224 1.68% 85.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 220 1.65% 86.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 270 2.03% 88.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 92 0.69% 89.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 146 1.10% 90.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1241 9.31% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 12987 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.090869 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.436472 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 6960 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2563 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2438 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 957 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 388 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 13303 # Number of instructions handled by decode
+system.cpu.fetch.rateDist::total 13325 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.075393 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.362593 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 6989 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 2898 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2415 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 950 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 13178 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 957 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 7226 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 330 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2238 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 12535 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 12533 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 56960 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 56600 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups
+system.cpu.rename.SquashCycles 950 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 7255 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 368 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 2315 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2217 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 12419 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 12443 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 56366 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 56110 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 256 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6860 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 6770 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 41 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 677 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2799 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts 688 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2784 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1569 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 11241 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 11162 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8967 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 119 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 5221 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14417 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 5126 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14148 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 12987 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.690460 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.397167 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 13325 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.669493 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.373683 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 9407 72.43% 72.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1316 10.13% 82.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 806 6.21% 88.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 531 4.09% 92.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 466 3.59% 96.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 267 2.06% 98.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 125 0.96% 99.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 55 0.42% 99.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 14 0.11% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 9737 73.07% 73.07% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1330 9.98% 83.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 808 6.06% 89.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 537 4.03% 93.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 465 3.49% 96.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 260 1.95% 98.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 124 0.93% 99.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 52 0.39% 99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 12987 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 13325 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 8 3.48% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 144 62.61% 66.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 78 33.91% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 6 2.69% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 139 62.33% 65.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 78 34.98% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5390 60.11% 60.11% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.19% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.22% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.22% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2344 26.14% 86.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1223 13.64% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5362 60.11% 60.11% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.21% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2334 26.16% 86.40% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8967 # Type of FU issued
-system.cpu.iq.rate 0.327108 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 230 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.025650 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 31234 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 16481 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 8073 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 8921 # Type of FU issued
+system.cpu.iq.rate 0.272189 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 223 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.024997 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 31465 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 16306 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 9177 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 9124 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1599 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1584 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 22 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 654 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 631 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 957 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 11290 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2799 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles 950 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 232 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 11211 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2784 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1569 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations
+system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 271 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 379 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8545 # Number of executed instructions
+system.cpu.iew.predictedNotTakenIncorrect 269 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 8517 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 422 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3301 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1438 # Number of branches executed
-system.cpu.iew.exec_stores 1167 # Number of stores executed
-system.cpu.iew.exec_rate 0.311713 # Inst execution rate
-system.cpu.iew.wb_sent 8247 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 8089 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 3894 # num instructions producing a value
-system.cpu.iew.wb_consumers 7825 # num instructions consuming a value
+system.cpu.iew.exec_refs 3294 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1436 # Number of branches executed
+system.cpu.iew.exec_stores 1160 # Number of stores executed
+system.cpu.iew.exec_rate 0.259863 # Inst execution rate
+system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 8068 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 3885 # num instructions producing a value
+system.cpu.iew.wb_consumers 7780 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.295079 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.497636 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.246163 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.499357 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 5566 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 5487 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 12030 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.476226 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.310563 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 12375 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.462949 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.295788 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 9744 81.00% 81.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1074 8.93% 89.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 398 3.31% 93.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 256 2.13% 95.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 181 1.50% 96.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 49 0.41% 98.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 35 0.29% 98.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 121 1.01% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 10091 81.54% 81.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1074 8.68% 90.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 396 3.20% 93.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 256 2.07% 95.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 180 1.45% 96.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 172 1.39% 98.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 35 0.28% 99.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 12030 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 12375 # Number of insts commited each cycle
system.cpu.commit.committedInsts 4591 # Number of instructions committed
system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 4976 # Number of committed integer instructions.
system.cpu.commit.function_calls 82 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 23047 # The number of ROB reads
-system.cpu.rob.rob_writes 23560 # The number of ROB writes
+system.cpu.rob.rob_reads 23312 # The number of ROB reads
+system.cpu.rob.rob_writes 23396 # The number of ROB writes
system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 14426 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 19450 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4591 # Number of Instructions Simulated
system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 4591 # Number of Instructions Simulated
-system.cpu.cpi 5.971030 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 5.971030 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.167475 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.167475 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 39296 # number of integer regfile reads
-system.cpu.int_regfile_writes 8001 # number of integer regfile writes
+system.cpu.cpi 7.138968 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.138968 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.140076 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.140076 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 39187 # number of integer regfile reads
+system.cpu.int_regfile_writes 7985 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 2981 # number of misc regfile reads
+system.cpu.misc_regfile_reads 2976 # number of misc regfile reads
system.cpu.misc_regfile_writes 24 # number of misc regfile writes
-system.cpu.icache.replacements 3 # number of replacements
-system.cpu.icache.tagsinuse 146.948464 # Cycle average of tags in use
-system.cpu.icache.total_refs 1590 # Total number of references to valid blocks.
+system.cpu.toL2Bus.throughput 1706718740 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 293 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 875 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9344 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 27968 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 436500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 221495 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
+system.cpu.icache.replacements 4 # number of replacements
+system.cpu.icache.tagsinuse 145.578272 # Cycle average of tags in use
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+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3034500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3034500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9472505 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 9472505 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9472505 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 9472505 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054359 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054359 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59621.951220 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.051345 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.051345 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60735.896226 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60735.896226 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74012.195122 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74012.195122 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 2870500 # Number of ticks simulated
final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1926 # Simulator instruction rate (inst/s)
-host_op_rate 2404 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1204405 # Simulator tick rate (ticks/s)
-host_mem_usage 275696 # Number of bytes of host memory used
-host_seconds 2.38 # Real time elapsed on the host
+host_inst_rate 686137 # Simulator instruction rate (inst/s)
+host_op_rate 854515 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 427336749 # Simulator tick rate (ticks/s)
+host_mem_usage 232512 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5729 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 9251001568 # Throughput (bytes/s)
+system.membus.data_through_bus 26555 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
system.cpu.checker.dtb.read_hits 0 # DTB read hits
sim_ticks 2870500 # Number of ticks simulated
final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 122854 # Simulator instruction rate (inst/s)
-host_op_rate 153228 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 76735417 # Simulator tick rate (ticks/s)
-host_mem_usage 275692 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
+host_inst_rate 723203 # Simulator instruction rate (inst/s)
+host_op_rate 900650 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 450384934 # Simulator tick rate (ticks/s)
+host_mem_usage 232532 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5729 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 9251001568 # Throughput (bytes/s)
+system.membus.data_through_bus 26555 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
sim_ticks 25969000 # Number of ticks simulated
final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 66941 # Simulator instruction rate (inst/s)
-host_op_rate 83151 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 380602116 # Simulator tick rate (ticks/s)
-host_mem_usage 284140 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
+host_inst_rate 220478 # Simulator instruction rate (inst/s)
+host_op_rate 273604 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1251201624 # Simulator tick rate (ticks/s)
+host_mem_usage 241012 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
sim_insts 4565 # Number of instructions simulated
sim_ops 5672 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 554507297 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 308059610 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 862566907 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 862566907 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 307 # Transaction distribution
+system.membus.trans_dist::ReadResp 307 # Transaction distribution
+system.membus.trans_dist::ReadExReq 43 # Transaction distribution
+system.membus.trans_dist::ReadExResp 43 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 700 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 700 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 22400 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 22400 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 22400 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 350000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
+system.membus.respLayer1.occupancy 3150000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 12.1 # Layer utilization (%)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 941430167 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 482 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 282 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 764 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 15424 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9024 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 24448 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 24448 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000019 # Number of seconds simulated
-sim_ticks 19339000 # Number of ticks simulated
-final_tick 19339000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000025 # Number of seconds simulated
+sim_ticks 24539000 # Number of ticks simulated
+final_tick 24539000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 26477 # Simulator instruction rate (inst/s)
-host_op_rate 26474 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 88053451 # Simulator tick rate (ticks/s)
-host_mem_usage 270344 # Number of bytes of host memory used
-host_seconds 0.22 # Real time elapsed on the host
+host_inst_rate 40560 # Simulator instruction rate (inst/s)
+host_op_rate 40552 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 171130571 # Simulator tick rate (ticks/s)
+host_mem_usage 226208 # Number of bytes of host memory used
+host_seconds 0.14 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 455 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1049071824 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 456693728 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1505765551 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1049071824 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1049071824 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1049071824 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 456693728 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1505765551 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 826765557 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 359916867 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1186682424 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 826765557 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 826765557 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 826765557 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 359916867 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1186682424 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 455 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 89 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 11 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 15 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 32 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 22 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 36 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 33 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 15 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 29 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 45 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 36 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 5 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 25 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 10 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 37 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 28 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 8 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 51 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 59 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 75 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 36 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 19 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 52 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 77 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 7 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 19292000 # Total gap between requests
+system.physmem.totGap 24472000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 293 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 301 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2650000 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 13958750 # Sum of mem lat for all requests
+system.physmem.bytesPerActivate::samples 94 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 251.234043 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 163.011055 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 299.928179 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64 34 36.17% 36.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128 16 17.02% 53.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192 9 9.57% 62.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256 9 9.57% 72.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320 4 4.26% 76.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384 9 9.57% 86.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448 1 1.06% 87.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512 2 2.13% 89.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576 2 2.13% 91.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704 2 2.13% 93.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768 2 2.13% 95.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832 1 1.06% 96.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960 1 1.06% 97.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024 1 1.06% 98.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2240 1 1.06% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 94 # Bytes accessed per row activation
+system.physmem.totQLat 2632000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 13115750 # Sum of mem lat for all requests
system.physmem.totBusLat 2275000 # Total cycles spent in databus access
-system.physmem.totBankLat 9033750 # Total cycles spent in bank access
-system.physmem.avgQLat 5824.18 # Average queueing delay per request
-system.physmem.avgBankLat 19854.40 # Average bank access latency per request
+system.physmem.totBankLat 8208750 # Total cycles spent in bank access
+system.physmem.avgQLat 5784.62 # Average queueing delay per request
+system.physmem.avgBankLat 18041.21 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 30678.57 # Average memory access latency
-system.physmem.avgRdBW 1505.77 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 28825.82 # Average memory access latency
+system.physmem.avgRdBW 1186.68 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1505.77 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1186.68 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 11.76 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.72 # Average read queue length over time
+system.physmem.busUtil 9.27 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.53 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 334 # Number of row buffer hits during reads
+system.physmem.readRowHits 361 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 73.41 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 79.34 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 42400.00 # Average gap between requests
-system.cpu.branchPred.lookups 1154 # Number of BP lookups
-system.cpu.branchPred.condPredicted 858 # Number of conditional branches predicted
+system.physmem.avgGap 53784.62 # Average gap between requests
+system.membus.throughput 1186682424 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 404 # Transaction distribution
+system.membus.trans_dist::ReadResp 404 # Transaction distribution
+system.membus.trans_dist::ReadExReq 51 # Transaction distribution
+system.membus.trans_dist::ReadExResp 51 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 910 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 910 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 29120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 29120 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 551000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4265750 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 17.4 # Layer utilization (%)
+system.cpu.branchPred.lookups 1157 # Number of BP lookups
+system.cpu.branchPred.condPredicted 861 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 603 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 877 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 336 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 880 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 339 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 38.312429 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 38.522727 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 86 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions.
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 8 # Number of system calls
-system.cpu.numCycles 38679 # number of cpu cycles simulated
+system.cpu.numCycles 49079 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.predictedTaken 429 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedTaken 432 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 725 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 5127 # Number of Reads from Int. Register File
+system.cpu.regfile_manager.intRegFileReads 5089 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 8523 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses 8485 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 1292 # Number of Registers Read Through Forwarding Logic
+system.cpu.regfile_manager.regForwards 1328 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 2229 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 274 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 594 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 321 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 64.918033 # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions 3135 # Number of Instructions Executed.
+system.cpu.execution_unit.executions 3133 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 9463 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 9516 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 477 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 33303 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 5376 # Number of cycles cpu stages are processed.
-system.cpu.activity 13.899015 # Percentage of cycles cpu is active
+system.cpu.timesIdled 488 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 43696 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 5383 # Number of cycles cpu stages are processed.
+system.cpu.activity 10.968031 # Percentage of cycles cpu is active
system.cpu.comLoads 1163 # Number of Load instructions committed
system.cpu.comStores 925 # Number of Store instructions committed
system.cpu.comBranches 915 # Number of Branches instructions committed
system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total)
-system.cpu.cpi 6.652735 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 8.441520 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 6.652735 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.150314 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 8.441520 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.118462 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 0.150314 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 35030 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 3649 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 9.434060 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 35863 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 2816 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 7.280436 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 35914 # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total 0.118462 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 45429 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 3650 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 7.436989 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 46265 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 2814 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 5.733613 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 46314 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 2765 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 7.148582 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 37453 # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 1226 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 3.169679 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 35777 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 2902 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 7.502779 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.utilization 5.633774 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 47841 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 2.522464 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 46189 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 2890 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 5.888466 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 13 # number of replacements
-system.cpu.icache.tagsinuse 149.398891 # Cycle average of tags in use
-system.cpu.icache.total_refs 429 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 150.599216 # Cycle average of tags in use
+system.cpu.icache.total_refs 428 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 1.344828 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 1.341693 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 149.398891 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.072949 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.072949 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 429 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 429 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 429 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 429 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 429 # number of overall hits
-system.cpu.icache.overall_hits::total 429 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 346 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 346 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 346 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 346 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 346 # number of overall misses
-system.cpu.icache.overall_misses::total 346 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 18937500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 18937500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 18937500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 18937500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 18937500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 18937500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 775 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 775 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 775 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 775 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 775 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 775 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.446452 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.446452 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.446452 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.446452 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.446452 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.446452 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54732.658960 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 54732.658960 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 54732.658960 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 54732.658960 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 54732.658960 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 54732.658960 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 150.599216 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.073535 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.073535 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 428 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 428 # number of overall hits
+system.cpu.icache.overall_hits::total 428 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses
+system.cpu.icache.overall_misses::total 350 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 25149500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 25149500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 25149500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 25149500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 25149500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 25149500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 778 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 778 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 778 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 778 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.449871 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.449871 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.449871 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.449871 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.449871 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.449871 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71855.714286 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 71855.714286 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 71855.714286 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 71855.714286 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 71855.714286 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 71855.714286 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 27 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 27 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 27 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 27 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 31 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 31 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 31 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 31 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 31 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 31 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 319 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 319 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 319 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17329000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 17329000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17329000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 17329000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17329000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 17329000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.411613 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.411613 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.411613 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.411613 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.411613 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.411613 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54322.884013 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54322.884013 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54322.884013 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 54322.884013 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54322.884013 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 54322.884013 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22969000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 22969000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22969000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 22969000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22969000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 22969000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.410026 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.410026 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.410026 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72003.134796 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72003.134796 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72003.134796 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 72003.134796 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72003.134796 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 72003.134796 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 1191898610 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 638 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 914 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 20416 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 29248 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 29248 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 478500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 206.866533 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 208.333773 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 151.045990 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 55.820543 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.001704 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.006313 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst 152.278645 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 56.055128 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.004647 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.001711 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.006358 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses
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+system.cpu.dcache.demand_mshr_miss_latency::total 10504000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10504000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10504000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60408.045977 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60408.045977 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51264.705882 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51264.705882 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57028.985507 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 57028.985507 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57028.985507 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 57028.985507 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78270.114943 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78270.114943 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72441.176471 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72441.176471 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.942029 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.942029 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76115.942029 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 76115.942029 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000017 # Number of seconds simulated
-sim_ticks 17026500 # Number of ticks simulated
-final_tick 17026500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000022 # Number of seconds simulated
+sim_ticks 21759500 # Number of ticks simulated
+final_tick 21759500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 19281 # Simulator instruction rate (inst/s)
-host_op_rate 19280 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 63663526 # Simulator tick rate (ticks/s)
-host_mem_usage 270344 # Number of bytes of host memory used
-host_seconds 0.27 # Real time elapsed on the host
+host_inst_rate 43168 # Simulator instruction rate (inst/s)
+host_op_rate 43158 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 182102261 # Simulator tick rate (ticks/s)
+host_mem_usage 228268 # Number of bytes of host memory used
+host_seconds 0.12 # Real time elapsed on the host
sim_insts 5156 # Number of instructions simulated
sim_ops 5156 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory
system.physmem.num_reads::total 478 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1262972425 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 533756204 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1796728629 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1262972425 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1262972425 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1262972425 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 533756204 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1796728629 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 988258002 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 417656656 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1405914658 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 988258002 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 988258002 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 988258002 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 417656656 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1405914658 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 478 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 478 # Reqs generatd by CPU via cache - shady
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 93 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 11 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 17 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 23 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 36 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 16 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 30 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 51 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 38 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 5 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 38 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 30 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 13 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 54 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 64 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 77 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 44 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 20 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 51 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 29 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 77 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 16967000 # Total gap between requests
+system.physmem.totGap 21680500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 253 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2843000 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 14596750 # Sum of mem lat for all requests
+system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 242.330097 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 156.624939 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 303.862985 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64 39 37.86% 37.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128 15 14.56% 52.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192 16 15.53% 67.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256 7 6.80% 74.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320 8 7.77% 82.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384 2 1.94% 84.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448 4 3.88% 88.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512 1 0.97% 89.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576 4 3.88% 93.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704 1 0.97% 94.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832 2 1.94% 96.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960 1 0.97% 97.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024 2 1.94% 99.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368 1 0.97% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation
+system.physmem.totQLat 2435500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 13501750 # Sum of mem lat for all requests
system.physmem.totBusLat 2390000 # Total cycles spent in databus access
-system.physmem.totBankLat 9363750 # Total cycles spent in bank access
-system.physmem.avgQLat 5947.70 # Average queueing delay per request
-system.physmem.avgBankLat 19589.44 # Average bank access latency per request
+system.physmem.totBankLat 8676250 # Total cycles spent in bank access
+system.physmem.avgQLat 5095.19 # Average queueing delay per request
+system.physmem.avgBankLat 18151.15 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 30537.13 # Average memory access latency
-system.physmem.avgRdBW 1796.73 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 28246.34 # Average memory access latency
+system.physmem.avgRdBW 1405.91 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1796.73 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1405.91 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 14.04 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.86 # Average read queue length over time
+system.physmem.busUtil 10.98 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.62 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 351 # Number of row buffer hits during reads
+system.physmem.readRowHits 375 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 73.43 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 78.45 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 35495.82 # Average gap between requests
-system.cpu.branchPred.lookups 2218 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1500 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 439 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1689 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 508 # Number of BTB hits
+system.physmem.avgGap 45356.69 # Average gap between requests
+system.membus.throughput 1405914658 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 427 # Transaction distribution
+system.membus.trans_dist::ReadResp 427 # Transaction distribution
+system.membus.trans_dist::ReadExReq 51 # Transaction distribution
+system.membus.trans_dist::ReadExResp 51 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 956 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 956 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30592 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 30592 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 30592 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 590000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 2.7 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4475750 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 20.6 # Layer utilization (%)
+system.cpu.branchPred.lookups 2196 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1494 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1671 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 505 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 30.076969 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 271 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 30.221424 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 262 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions.
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 8 # Number of system calls
-system.cpu.numCycles 34054 # number of cpu cycles simulated
+system.cpu.numCycles 43520 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 8765 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 13373 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2218 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 3270 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1400 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 1014 # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles 8865 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 13232 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2196 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 767 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 3240 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1388 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 1327 # Number of cycles fetch has spent blocked
system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 2012 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 279 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 14123 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.946895 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.257314 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 1994 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 14495 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.912867 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.222713 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10853 76.85% 76.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1348 9.54% 86.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 105 0.74% 87.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 135 0.96% 88.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 305 2.16% 90.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 118 0.84% 91.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 156 1.10% 92.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 160 1.13% 93.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 943 6.68% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 11255 77.65% 77.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1338 9.23% 86.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 104 0.72% 87.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 132 0.91% 88.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 307 2.12% 90.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 118 0.81% 91.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 149 1.03% 92.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 158 1.09% 93.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 934 6.44% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 14123 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.065132 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.392700 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 8861 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 1237 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 3093 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 44 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 888 # Number of cycles decode is squashing
+system.cpu.fetch.rateDist::total 14495 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.050460 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.304044 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 8953 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 1558 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 3054 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 877 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 168 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 44 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 12489 # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts 12351 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 888 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 9042 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 324 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 802 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2958 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 109 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 11987 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
+system.cpu.rename.SquashCycles 877 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 9138 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 511 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 897 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2924 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 11915 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 93 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 7237 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 14212 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 14208 # Number of integer rename lookups
+system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 7195 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 14132 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 14128 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 3839 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 18 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 276 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2482 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1199 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.UndoneMaps 3797 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 17 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 333 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2463 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 9295 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8318 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 3635 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 2167 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 14123 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.588968 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.255126 # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded 9245 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 8313 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 42 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 3584 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 2108 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 14495 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.573508 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.239818 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10544 74.66% 74.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1399 9.91% 84.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 897 6.35% 90.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 565 4.00% 94.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 359 2.54% 97.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 225 1.59% 99.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 87 0.62% 99.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 29 0.21% 99.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 18 0.13% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 10895 75.16% 75.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1434 9.89% 85.06% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 892 6.15% 91.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 557 3.84% 95.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 358 2.47% 97.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 226 1.56% 99.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 86 0.59% 99.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 14123 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 14495 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 5 3.14% 3.14% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 3.14% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 4943 59.43% 59.43% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.49% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.53% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2262 27.19% 86.73% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1104 13.27% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 4947 59.51% 59.51% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.57% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.59% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.62% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2253 27.10% 86.72% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1104 13.28% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8318 # Type of FU issued
-system.cpu.iq.rate 0.244259 # Inst issue rate
+system.cpu.iq.FU_type_0::total 8313 # Type of FU issued
+system.cpu.iq.rate 0.191016 # Inst issue rate
system.cpu.iq.fu_busy_cnt 159 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.019115 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 30960 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 12952 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 7465 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate 0.019127 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 31318 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 12850 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 7467 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 8475 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 8470 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1319 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1300 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 274 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 888 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 223 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 10854 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2482 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1199 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewSquashCycles 877 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 334 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 10786 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 86 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2463 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 106 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 102 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 359 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 7932 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2125 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 386 # Number of squashed instructions skipped in execute
+system.cpu.iew.branchMispredicts 461 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 7936 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2118 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 377 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1546 # number of nop insts executed
-system.cpu.iew.exec_refs 3202 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1355 # Number of branches executed
-system.cpu.iew.exec_stores 1077 # Number of stores executed
-system.cpu.iew.exec_rate 0.232924 # Inst execution rate
-system.cpu.iew.wb_sent 7556 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 7467 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 2949 # num instructions producing a value
-system.cpu.iew.wb_consumers 4258 # num instructions consuming a value
+system.cpu.iew.exec_nop 1529 # number of nop insts executed
+system.cpu.iew.exec_refs 3196 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1356 # Number of branches executed
+system.cpu.iew.exec_stores 1078 # Number of stores executed
+system.cpu.iew.exec_rate 0.182353 # Inst execution rate
+system.cpu.iew.wb_sent 7562 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 7469 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 2922 # num instructions producing a value
+system.cpu.iew.wb_consumers 4200 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.219269 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.692579 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.171622 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.695714 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 5033 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 4965 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 13235 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.439214 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.223104 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 395 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 13618 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.426862 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.205287 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 10851 81.99% 81.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 966 7.30% 89.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 635 4.80% 94.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 328 2.48% 96.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 148 1.12% 97.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 96 0.73% 98.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 63 0.48% 98.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 41 0.31% 99.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 107 0.81% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 11210 82.32% 82.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1002 7.36% 89.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 633 4.65% 94.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 319 2.34% 96.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 147 1.08% 97.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 94 0.69% 98.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 67 0.49% 98.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 40 0.29% 99.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 13235 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 13618 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5813 # Number of instructions committed
system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
system.cpu.commit.int_insts 5111 # Number of committed integer instructions.
system.cpu.commit.function_calls 87 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 23961 # The number of ROB reads
-system.cpu.rob.rob_writes 22589 # The number of ROB writes
-system.cpu.timesIdled 287 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 19931 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 24277 # The number of ROB reads
+system.cpu.rob.rob_writes 22442 # The number of ROB writes
+system.cpu.timesIdled 289 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 29025 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5156 # Number of Instructions Simulated
system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 5156 # Number of Instructions Simulated
-system.cpu.cpi 6.604732 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 6.604732 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.151407 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.151407 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 10750 # number of integer regfile reads
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59791.317992 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 91.619831 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2424 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 91.370944 # Cycle average of tags in use
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system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 17.070423 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 16.901408 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.dcache.occ_percent::cpu.data 0.022368 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.022368 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 1852 # number of ReadReq hits
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system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
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-system.cpu.dcache.overall_avg_miss_latency::cpu.data 48092.812375 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 48092.812375 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 488 # number of cycles access was blocked
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+system.cpu.dcache.overall_avg_miss_latency::cpu.data 64407.043053 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 64407.043053 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 642 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.363636 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.363636 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits
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-system.cpu.dcache.overall_mshr_hits::total 359 # number of overall MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses
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-system.cpu.dcache.overall_mshr_miss_latency::total 8716499 # number of overall MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048547 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.048547 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048547 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.048547 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66016.483516 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66016.483516 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53117.627451 # average WriteReq mshr miss latency
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-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61383.795775 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 61383.795775 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61383.795775 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 61383.795775 # average overall mshr miss latency
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+system.cpu.dcache.demand_mshr_miss_rate::total 0.048780 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048780 # mshr miss rate for overall accesses
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78725.274725 # average ReadReq mshr miss latency
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+system.cpu.dcache.overall_avg_mshr_miss_latency::total 77887.316901 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 2907000 # Number of ticks simulated
final_tick 2907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 85249 # Simulator instruction rate (inst/s)
-host_op_rate 85225 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 42601271 # Simulator tick rate (ticks/s)
-host_mem_usage 261900 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
+host_inst_rate 727521 # Simulator instruction rate (inst/s)
+host_op_rate 725084 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 361375060 # Simulator tick rate (ticks/s)
+host_mem_usage 216568 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 23260 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 8001375989 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2762985896 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10764361885 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 10764361885 # Throughput (bytes/s)
+system.membus.data_through_bus 31292 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
sim_ticks 31633000 # Number of ticks simulated
final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3112 # Simulator instruction rate (inst/s)
-host_op_rate 3112 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 16931146 # Simulator tick rate (ticks/s)
-host_mem_usage 270356 # Number of bytes of host memory used
-host_seconds 1.87 # Real time elapsed on the host
+host_inst_rate 482351 # Simulator instruction rate (inst/s)
+host_op_rate 481309 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2613274672 # Simulator tick rate (ticks/s)
+host_mem_usage 225064 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 608984289 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 279202099 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 888186388 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 888186388 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 388 # Transaction distribution
+system.membus.trans_dist::ReadResp 388 # Transaction distribution
+system.membus.trans_dist::ReadExReq 51 # Transaction distribution
+system.membus.trans_dist::ReadExResp 51 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 878 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 878 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28096 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 28096 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 28096 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 439000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
+system.membus.respLayer1.occupancy 3951000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 12.5 # Layer utilization (%)
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 892232795 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 390 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 390 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 606 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 882 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19392 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 28224 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 28224 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 454500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000015 # Number of seconds simulated
-sim_ticks 14724500 # Number of ticks simulated
-final_tick 14724500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000018 # Number of seconds simulated
+sim_ticks 18326500 # Number of ticks simulated
+final_tick 18326500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 11850 # Simulator instruction rate (inst/s)
-host_op_rate 11850 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 30123505 # Simulator tick rate (ticks/s)
-host_mem_usage 266600 # Number of bytes of host memory used
-host_seconds 0.49 # Real time elapsed on the host
+host_inst_rate 41507 # Simulator instruction rate (inst/s)
+host_op_rate 41499 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 131284333 # Simulator tick rate (ticks/s)
+host_mem_usage 224304 # Number of bytes of host memory used
+host_seconds 0.14 # Real time elapsed on the host
sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory
system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1499541580 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 438996231 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1938537811 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1499541580 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1499541580 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1499541580 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 438996231 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1938537811 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1204812703 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 352713284 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1557525987 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1204812703 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1204812703 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1204812703 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 352713284 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1557525987 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 446 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 446 # Reqs generatd by CPU via cache - shady
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 38 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 56 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 27 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 10 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 33 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 39 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 9 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 18 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 52 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 11 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 8 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 23 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 22 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 19 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 54 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 59 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 53 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 61 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 52 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 13 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 8 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 2 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 4 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 14617000 # Total gap between requests
+system.physmem.totGap 18199000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 231 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 148 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 248 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2285750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 12779500 # Sum of mem lat for all requests
+system.physmem.bytesPerActivate::samples 66 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 306.424242 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 157.375410 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 461.580898 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64 31 46.97% 46.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128 7 10.61% 57.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192 7 10.61% 68.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256 4 6.06% 74.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320 2 3.03% 77.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384 1 1.52% 78.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448 1 1.52% 80.30% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512 2 3.03% 83.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576 3 4.55% 87.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704 2 3.03% 90.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960 1 1.52% 92.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088 2 3.03% 95.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920 1 1.52% 96.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984 1 1.52% 98.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2304 1 1.52% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 66 # Bytes accessed per row activation
+system.physmem.totQLat 2004500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 10972000 # Sum of mem lat for all requests
system.physmem.totBusLat 2230000 # Total cycles spent in databus access
-system.physmem.totBankLat 8263750 # Total cycles spent in bank access
-system.physmem.avgQLat 5125.00 # Average queueing delay per request
-system.physmem.avgBankLat 18528.59 # Average bank access latency per request
+system.physmem.totBankLat 6737500 # Total cycles spent in bank access
+system.physmem.avgQLat 4494.39 # Average queueing delay per request
+system.physmem.avgBankLat 15106.50 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 28653.59 # Average memory access latency
-system.physmem.avgRdBW 1938.54 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 24600.90 # Average memory access latency
+system.physmem.avgRdBW 1557.53 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1938.54 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1557.53 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 15.14 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.87 # Average read queue length over time
+system.physmem.busUtil 12.17 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.60 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 338 # Number of row buffer hits during reads
+system.physmem.readRowHits 380 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 75.78 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 85.20 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 32773.54 # Average gap between requests
-system.cpu.branchPred.lookups 2226 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1794 # Number of conditional branches predicted
+system.physmem.avgGap 40804.93 # Average gap between requests
+system.membus.throughput 1557525987 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 399 # Transaction distribution
+system.membus.trans_dist::ReadResp 399 # Transaction distribution
+system.membus.trans_dist::ReadExReq 47 # Transaction distribution
+system.membus.trans_dist::ReadExResp 47 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 892 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 892 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28544 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 28544 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 28544 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 559500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 3.1 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4174500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 22.8 # Layer utilization (%)
+system.cpu.branchPred.lookups 2238 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1804 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1842 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 599 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 1851 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 603 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 32.519001 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 198 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 32.576985 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions.
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 9 # Number of system calls
-system.cpu.numCycles 29450 # number of cpu cycles simulated
+system.cpu.numCycles 36654 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 7448 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 13075 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2226 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 797 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2246 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1279 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 1007 # Number of cycles fetch has spent blocked
-system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 11551 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.131937 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.547334 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 7507 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 13158 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2238 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 802 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2262 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1292 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 1225 # Number of cycles fetch has spent blocked
+system.cpu.fetch.CacheLines 1813 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 11857 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.109724 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.526984 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 9305 80.56% 80.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 175 1.52% 82.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 174 1.51% 83.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 140 1.21% 84.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 227 1.97% 86.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 132 1.14% 87.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 256 2.22% 90.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 108 0.93% 91.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1034 8.95% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 9595 80.92% 80.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 178 1.50% 82.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 176 1.48% 83.91% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 141 1.19% 85.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 227 1.91% 87.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 133 1.12% 88.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 257 2.17% 90.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 110 0.93% 91.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1040 8.77% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 11551 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.075586 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.443973 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 7514 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 1178 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2083 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 697 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 338 # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total 11857 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.061057 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.358979 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 7580 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 1390 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2096 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 81 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 710 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 341 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 11641 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 431 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 697 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 7699 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 476 # Number of cycles rename is blocking
+system.cpu.decode.DecodedInsts 11719 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 710 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 7768 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 673 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 449 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 1969 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 261 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 11203 # Number of instructions processed by rename
+system.cpu.rename.RunCycles 1984 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 273 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 11300 # Number of instructions processed by rename
system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 218 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 9614 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 18041 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 17986 # Number of integer rename lookups
+system.cpu.rename.LSQFullEvents 232 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 9692 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 18178 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 18123 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 4616 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 4694 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 27 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 553 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 1993 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 53 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 10211 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts 580 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2023 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 10310 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8907 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 171 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 4167 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 3342 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 8903 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 4245 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 3499 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 11551 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.771102 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.501710 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 11857 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.750864 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.481785 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 8211 71.08% 71.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1072 9.28% 80.37% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 790 6.84% 87.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 498 4.31% 91.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 466 4.03% 95.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 301 2.61% 98.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 134 1.16% 99.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 44 0.38% 99.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 35 0.30% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 8486 71.57% 71.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1113 9.39% 80.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 789 6.65% 87.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 496 4.18% 91.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 461 3.89% 95.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 303 2.56% 98.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 131 1.10% 99.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 45 0.38% 99.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 33 0.28% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 11551 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 11857 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 8 4.68% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.68% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 69 40.35% 45.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 94 54.97% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 71 41.52% 46.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 92 53.80% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5470 61.41% 61.41% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.41% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 1795 20.15% 81.59% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1640 18.41% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5478 61.53% 61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.55% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 1796 20.17% 81.73% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1627 18.27% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8907 # Type of FU issued
-system.cpu.iq.rate 0.302445 # Inst issue rate
+system.cpu.iq.FU_type_0::total 8903 # Type of FU issued
+system.cpu.iq.rate 0.242893 # Inst issue rate
system.cpu.iq.fu_busy_cnt 171 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.019198 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 29645 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 14405 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 8123 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate 0.019207 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 30013 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 14583 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 8130 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 9044 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 9040 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1032 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1062 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 757 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 785 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 697 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 276 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 10268 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 710 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 456 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 10367 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 55 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 1993 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts 2023 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations
+system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 329 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8493 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 1673 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 328 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 8502 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 1678 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 401 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3204 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1349 # Number of branches executed
-system.cpu.iew.exec_stores 1531 # Number of stores executed
-system.cpu.iew.exec_rate 0.288387 # Inst execution rate
-system.cpu.iew.wb_sent 8266 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 8150 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 4198 # num instructions producing a value
-system.cpu.iew.wb_consumers 6619 # num instructions consuming a value
+system.cpu.iew.exec_refs 3201 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1351 # Number of branches executed
+system.cpu.iew.exec_stores 1523 # Number of stores executed
+system.cpu.iew.exec_rate 0.231953 # Inst execution rate
+system.cpu.iew.wb_sent 8272 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 8157 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 4222 # num instructions producing a value
+system.cpu.iew.wb_consumers 6684 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.276740 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.634235 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.222541 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.631658 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 4482 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 4581 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 10854 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.533628 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.332953 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 11147 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.519602 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.320329 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 8474 78.07% 78.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 999 9.20% 87.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 620 5.71% 92.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 267 2.46% 95.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 174 1.60% 97.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 109 1.00% 98.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 67 0.62% 98.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 43 0.40% 99.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 101 0.93% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 8765 78.63% 78.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1011 9.07% 87.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 612 5.49% 93.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 265 2.38% 95.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 170 1.53% 97.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 108 0.97% 98.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 71 0.64% 98.70% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 44 0.39% 99.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 101 0.91% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 10854 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 11147 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5792 # Number of instructions committed
system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.function_calls 103 # Number of function calls committed.
system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 21027 # The number of ROB reads
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4842049 # number of overall MSHR miss cycles
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 63.324326 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2181 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses)
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+system.cpu.dcache.blocked_cycles::no_mshrs 500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.800000 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 100 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 46 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses
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system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses
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-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038946 # mshr miss rate for overall accesses
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58845.454545 # average ReadReq mshr miss latency
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-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60725.480392 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 60725.480392 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038887 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.038887 # mshr miss rate for demand accesses
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76154.545455 # average ReadReq mshr miss latency
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+system.cpu.dcache.overall_avg_mshr_miss_latency::total 77112.735294 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 2896000 # Number of ticks simulated
final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 57024 # Simulator instruction rate (inst/s)
-host_op_rate 57013 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 28496468 # Simulator tick rate (ticks/s)
-host_mem_usage 257792 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
+host_inst_rate 671850 # Simulator instruction rate (inst/s)
+host_op_rate 669870 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 333940022 # Simulator tick rate (ticks/s)
+host_mem_usage 212612 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 5793 # Number of instructions simulated
sim_ops 5793 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 23172 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 8001381215 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2737914365 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10739295580 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 10739295580 # Throughput (bytes/s)
+system.membus.data_through_bus 31101 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000017 # Number of seconds simulated
-sim_ticks 16783500 # Number of ticks simulated
-final_tick 16783500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000021 # Number of seconds simulated
+sim_ticks 20764500 # Number of ticks simulated
+final_tick 20764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 18770 # Simulator instruction rate (inst/s)
-host_op_rate 18768 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 59128079 # Simulator tick rate (ticks/s)
-host_mem_usage 276316 # Number of bytes of host memory used
-host_seconds 0.28 # Real time elapsed on the host
+host_inst_rate 44697 # Simulator instruction rate (inst/s)
+host_op_rate 44687 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 174155494 # Simulator tick rate (ticks/s)
+host_mem_usage 232524 # Number of bytes of host memory used
+host_seconds 0.12 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
system.physmem.num_reads::total 423 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1102034736 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 510978044 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1613012780 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1102034736 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1102034736 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1102034736 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 510978044 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1613012780 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 890751041 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 413012594 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1303763635 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 890751041 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 890751041 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 890751041 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 413012594 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1303763635 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 423 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 37 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 5 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 10 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 19 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 39 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 11 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 28 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 46 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 46 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 24 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 7 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 78 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 80 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 62 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 35 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 14 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 20 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 10 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 34 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 71 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 10 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 52 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 12 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 21 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 16708000 # Total gap between requests
+system.physmem.totGap 20696000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 251 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2671750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 12995500 # Sum of mem lat for all requests
+system.physmem.bytesPerActivate::samples 65 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 326.892308 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 170.513476 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 484.792485 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64 29 44.62% 44.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128 8 12.31% 56.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192 2 3.08% 60.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256 4 6.15% 66.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320 1 1.54% 67.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384 5 7.69% 75.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448 2 3.08% 78.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512 2 3.08% 81.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576 4 6.15% 87.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640 3 4.62% 92.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024 1 1.54% 93.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1280 1 1.54% 95.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536 1 1.54% 96.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728 1 1.54% 98.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3008 1 1.54% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 65 # Bytes accessed per row activation
+system.physmem.totQLat 3131250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 11791250 # Sum of mem lat for all requests
system.physmem.totBusLat 2115000 # Total cycles spent in databus access
-system.physmem.totBankLat 8208750 # Total cycles spent in bank access
-system.physmem.avgQLat 6316.19 # Average queueing delay per request
-system.physmem.avgBankLat 19406.03 # Average bank access latency per request
+system.physmem.totBankLat 6545000 # Total cycles spent in bank access
+system.physmem.avgQLat 7402.48 # Average queueing delay per request
+system.physmem.avgBankLat 15472.81 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 30722.22 # Average memory access latency
-system.physmem.avgRdBW 1613.01 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 27875.30 # Average memory access latency
+system.physmem.avgRdBW 1303.76 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1613.01 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1303.76 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 12.60 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.77 # Average read queue length over time
+system.physmem.busUtil 10.19 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.57 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 300 # Number of row buffer hits during reads
+system.physmem.readRowHits 358 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 70.92 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 84.63 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 39498.82 # Average gap between requests
+system.physmem.avgGap 48926.71 # Average gap between requests
+system.membus.throughput 1303763635 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 342 # Transaction distribution
+system.membus.trans_dist::ReadResp 342 # Transaction distribution
+system.membus.trans_dist::ReadExReq 81 # Transaction distribution
+system.membus.trans_dist::ReadExResp 81 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 846 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 846 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 27072 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 27072 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 27072 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
+system.membus.respLayer1.occupancy 3936500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 19.0 # Layer utilization (%)
system.cpu.branchPred.lookups 1636 # Number of BP lookups
system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect
system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 33568 # number of cpu cycles simulated
+system.cpu.numCycles 41530 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True).
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 9657 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 9717 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 481 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 27323 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 6245 # Number of cycles cpu stages are processed.
-system.cpu.activity 18.604028 # Percentage of cycles cpu is active
+system.cpu.timesIdled 483 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 35284 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 6246 # Number of cycles cpu stages are processed.
+system.cpu.activity 15.039730 # Percentage of cycles cpu is active
system.cpu.comLoads 715 # Number of Load instructions committed
system.cpu.comStores 673 # Number of Store instructions committed
system.cpu.comBranches 1115 # Number of Branches instructions committed
system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total)
-system.cpu.cpi 6.301483 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 7.796133 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 6.301483 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.158693 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 7.796133 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.128269 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 0.158693 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 28928 # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total 0.128269 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 36890 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 13.822688 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 30373 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.utilization 11.172646 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 38335 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 9.517993 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 30535 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.utilization 7.693234 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 38497 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 9.035391 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 32593 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.utilization 7.303154 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 40555 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 2.904552 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 30411 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.utilization 2.347700 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 38373 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 9.404790 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.utilization 7.601734 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 141.184744 # Cycle average of tags in use
-system.cpu.icache.total_refs 896 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 142.226837 # Cycle average of tags in use
+system.cpu.icache.total_refs 892 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 3.079038 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 3.065292 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 141.184744 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.068938 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.068938 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 896 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 896 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 896 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 896 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 896 # number of overall hits
-system.cpu.icache.overall_hits::total 896 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses
-system.cpu.icache.overall_misses::total 362 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 18997500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 18997500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 18997500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 18997500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 18997500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 18997500 # number of overall miss cycles
+system.cpu.icache.occ_blocks::cpu.inst 142.226837 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.069447 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.069447 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 892 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 892 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 892 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 892 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 892 # number of overall hits
+system.cpu.icache.overall_hits::total 892 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses
+system.cpu.icache.overall_misses::total 366 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 25702500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 25702500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 25702500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 25702500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 25702500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 25702500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 1258 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 1258 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 1258 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.287758 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.287758 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.287758 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.287758 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.287758 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.287758 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52479.281768 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 52479.281768 # average ReadReq miss latency
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+system.cpu.dcache.demand_miss_latency::cpu.data 31077000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 31077000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 31077000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 31077000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62581.967213 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 62581.967213 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52813.559322 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 52813.559322 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 54070.675105 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 54070.675105 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54070.675105 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54070.675105 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 557 # number of cycles access was blocked
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70754.098361 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 70754.098361 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64796.610169 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 64796.610169 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 65563.291139 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 65563.291139 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 65563.291139 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 65563.291139 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 781 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 17.406250 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.406250 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3385500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 3385500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4793500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4793500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8179000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 8179000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8179000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 8179000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3832000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 3832000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5987500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5987500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9819500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 9819500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9819500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 9819500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62694.444444 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62694.444444 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59179.012346 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59179.012346 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60585.185185 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 60585.185185 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60585.185185 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 60585.185185 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70962.962963 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70962.962963 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73919.753086 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73919.753086 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72737.037037 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 72737.037037 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72737.037037 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 72737.037037 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 2694500 # Number of ticks simulated
final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 73566 # Simulator instruction rate (inst/s)
-host_op_rate 73547 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 37192728 # Simulator tick rate (ticks/s)
-host_mem_usage 269044 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
+host_inst_rate 565055 # Simulator instruction rate (inst/s)
+host_op_rate 563581 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 284338324 # Simulator tick rate (ticks/s)
+host_mem_usage 222908 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7971794396 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3587678605 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 11559473001 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 11559473001 # Throughput (bytes/s)
+system.membus.data_through_bus 31147 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 5390 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
sim_ticks 27800000 # Number of ticks simulated
final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 116604 # Simulator instruction rate (inst/s)
-host_op_rate 116555 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 608021957 # Simulator tick rate (ticks/s)
-host_mem_usage 277492 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 413138 # Simulator instruction rate (inst/s)
+host_op_rate 412367 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2148212772 # Simulator tick rate (ticks/s)
+host_mem_usage 231400 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 587050360 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 308489209 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 895539568 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 895539568 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 308 # Transaction distribution
+system.membus.trans_dist::ReadResp 308 # Transaction distribution
+system.membus.trans_dist::ReadExReq 81 # Transaction distribution
+system.membus.trans_dist::ReadExResp 81 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 778 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 778 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 24896 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 24896 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 24896 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 389000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
+system.membus.respLayer1.occupancy 3501000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 12.6 # Layer utilization (%)
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 55600 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 902446043 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 311 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 514 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 270 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 784 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 16448 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8640 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 25088 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 25088 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000016 # Number of seconds simulated
-sim_ticks 16021500 # Number of ticks simulated
-final_tick 16021500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000020 # Number of seconds simulated
+sim_ticks 19589000 # Number of ticks simulated
+final_tick 19589000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 25477 # Simulator instruction rate (inst/s)
-host_op_rate 46153 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 75857343 # Simulator tick rate (ticks/s)
-host_mem_usage 290184 # Number of bytes of host memory used
-host_seconds 0.21 # Real time elapsed on the host
+host_inst_rate 1364 # Simulator instruction rate (inst/s)
+host_op_rate 2472 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4967212 # Simulator tick rate (ticks/s)
+host_mem_usage 245432 # Number of bytes of host memory used
+host_seconds 3.94 # Real time elapsed on the host
sim_insts 5380 # Number of instructions simulated
sim_ops 9747 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9152 # Number of bytes read from this memory
-system.physmem.bytes_read::total 26944 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 143 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 421 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1110507755 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 571232406 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1681740162 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1110507755 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1110507755 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1110507755 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 571232406 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1681740162 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 422 # Total number of read requests seen
+system.physmem.bytes_read::cpu.inst 17472 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory
+system.physmem.bytes_read::total 26432 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 17472 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 17472 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 273 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 413 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 891929144 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 457399561 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1349328705 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 891929144 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 891929144 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 891929144 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 457399561 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1349328705 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 414 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 422 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 26944 # Total number of bytes read from memory
+system.physmem.cpureqs 414 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 26432 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 26944 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 26432 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 45 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 14 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 23 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 28 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 35 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 33 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 1 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 5 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 8 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 50 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 26 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 33 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 24 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 7 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 33 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 39 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 12 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 3 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 24 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 36 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 73 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 63 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 2 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 6 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 16004000 # Total gap between requests
+system.physmem.totGap 19541000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 422 # Categorize read packet sizes
+system.physmem.readPktSize::6 414 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 233 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 249 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2229750 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 13029750 # Sum of mem lat for all requests
-system.physmem.totBusLat 2110000 # Total cycles spent in databus access
-system.physmem.totBankLat 8690000 # Total cycles spent in bank access
-system.physmem.avgQLat 5283.77 # Average queueing delay per request
-system.physmem.avgBankLat 20592.42 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 87 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 216.275862 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 131.153640 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 325.056442 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64 43 49.43% 49.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128 13 14.94% 64.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192 9 10.34% 74.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256 4 4.60% 79.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320 7 8.05% 87.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384 3 3.45% 90.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512 1 1.15% 91.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640 1 1.15% 93.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704 1 1.15% 94.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768 1 1.15% 95.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960 2 2.30% 97.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1344 1 1.15% 98.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2368 1 1.15% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 87 # Bytes accessed per row activation
+system.physmem.totQLat 1394000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 11081500 # Sum of mem lat for all requests
+system.physmem.totBusLat 2070000 # Total cycles spent in databus access
+system.physmem.totBankLat 7617500 # Total cycles spent in bank access
+system.physmem.avgQLat 3367.15 # Average queueing delay per request
+system.physmem.avgBankLat 18399.76 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 30876.18 # Average memory access latency
-system.physmem.avgRdBW 1681.74 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 26766.91 # Average memory access latency
+system.physmem.avgRdBW 1349.33 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1681.74 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1349.33 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 13.14 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.81 # Average read queue length over time
+system.physmem.busUtil 10.54 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.57 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 302 # Number of row buffer hits during reads
+system.physmem.readRowHits 327 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 71.56 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 78.99 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 37924.17 # Average gap between requests
-system.cpu.branchPred.lookups 3090 # Number of BP lookups
-system.cpu.branchPred.condPredicted 3090 # Number of conditional branches predicted
+system.physmem.avgGap 47200.48 # Average gap between requests
+system.membus.throughput 1349328705 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 337 # Transaction distribution
+system.membus.trans_dist::ReadResp 336 # Transaction distribution
+system.membus.trans_dist::ReadExReq 77 # Transaction distribution
+system.membus.trans_dist::ReadExResp 77 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 827 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 827 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port 827 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 827 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26432 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26432 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.physmem.port 26432 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 26432 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 26432 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 498000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 2.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 3864000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 19.7 # Layer utilization (%)
+system.cpu.branchPred.lookups 3089 # Number of BP lookups
+system.cpu.branchPred.condPredicted 3089 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 541 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 2310 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 714 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 2286 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 726 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 30.909091 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 211 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 78 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 31.758530 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 207 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 72 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 32044 # number of cpu cycles simulated
+system.cpu.numCycles 39179 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 9523 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 14230 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 3090 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 925 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 3948 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2389 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 3636 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 47 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 340 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 1965 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 259 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 19279 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.312568 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.813131 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 10273 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 14155 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 3089 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 933 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 3944 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 2474 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 5406 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 59 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 375 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 1981 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 21925 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.151015 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.666624 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 15433 80.05% 80.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 214 1.11% 81.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 145 0.75% 81.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 217 1.13% 83.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 192 1.00% 84.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 169 0.88% 84.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 290 1.50% 86.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 155 0.80% 87.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 2464 12.78% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 18081 82.47% 82.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 213 0.97% 83.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 143 0.65% 84.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 223 1.02% 85.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 185 0.84% 85.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 200 0.91% 86.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 277 1.26% 88.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 158 0.72% 88.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 2445 11.15% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 19279 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.096430 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.444077 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 10008 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 3780 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 3579 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 127 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1785 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 24215 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 1785 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 10348 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 2654 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 416 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 3350 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 726 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 22708 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 31 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 620 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 25234 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 54863 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 54847 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 21925 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.078843 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.361290 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 11051 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 5299 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 3578 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1857 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 24188 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 1857 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 11417 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 3782 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 753 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 3333 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 783 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 22649 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 35 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 669 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 25230 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 54980 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 54964 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 14171 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 30 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 1819 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2277 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1616 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 17 # Number of conflicting loads.
+system.cpu.rename.UndoneMaps 14167 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 32 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 32 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 2073 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2281 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1568 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 20098 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 17004 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 251 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 9536 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 13688 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 19279 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.881996 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.736426 # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded 20212 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 17024 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 290 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 9720 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 13890 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 21925 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.776465 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.650682 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 13831 71.74% 71.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1491 7.73% 79.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 1108 5.75% 85.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 718 3.72% 88.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 686 3.56% 92.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 589 3.06% 95.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 582 3.02% 98.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 230 1.19% 99.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 44 0.23% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 16429 74.93% 74.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1551 7.07% 82.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 1089 4.97% 86.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 725 3.31% 90.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 705 3.22% 93.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 574 2.62% 96.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 578 2.64% 98.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 230 1.05% 99.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 44 0.20% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 19279 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 21925 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 127 76.51% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 24 14.46% 90.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 15 9.04% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 139 76.80% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 76.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 27 14.92% 91.71% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 15 8.29% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 13619 80.09% 80.11% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.13% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.18% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 1977 11.63% 91.80% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1394 8.20% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 13662 80.25% 80.27% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.29% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.33% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 1972 11.58% 91.92% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1376 8.08% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 17004 # Type of FU issued
-system.cpu.iq.rate 0.530645 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 166 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.009762 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 53696 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 29666 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 15641 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 17024 # Type of FU issued
+system.cpu.iq.rate 0.434518 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 181 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.010632 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 56436 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 29967 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 15651 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 17163 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 17198 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 167 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 173 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1224 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1228 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 681 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 633 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 19 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1785 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1955 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 34 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 20123 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 54 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2277 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1616 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 1857 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 2975 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 20240 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 40 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2281 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1568 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 121 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 553 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 674 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 16111 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 1853 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 893 # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect 114 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 569 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 683 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 16133 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 1855 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 891 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 3149 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1620 # Number of branches executed
-system.cpu.iew.exec_stores 1296 # Number of stores executed
-system.cpu.iew.exec_rate 0.502777 # Inst execution rate
-system.cpu.iew.wb_sent 15852 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 15645 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 10112 # num instructions producing a value
-system.cpu.iew.wb_consumers 15481 # num instructions consuming a value
+system.cpu.iew.exec_refs 3133 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1621 # Number of branches executed
+system.cpu.iew.exec_stores 1278 # Number of stores executed
+system.cpu.iew.exec_rate 0.411777 # Inst execution rate
+system.cpu.iew.wb_sent 15873 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 15655 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 10119 # num instructions producing a value
+system.cpu.iew.wb_consumers 15566 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.488235 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.653188 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.399576 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.650071 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 10375 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 10504 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 582 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 17494 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.557162 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.425293 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 20068 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.485699 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.341238 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 13941 79.69% 79.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1339 7.65% 87.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 594 3.40% 90.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 714 4.08% 94.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 361 2.06% 96.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 136 0.78% 97.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 122 0.70% 98.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 74 0.42% 98.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 213 1.22% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 16495 82.20% 82.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1364 6.80% 88.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 592 2.95% 91.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 713 3.55% 95.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 362 1.80% 97.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 137 0.68% 97.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 121 0.60% 98.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 71 0.35% 98.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 213 1.06% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 17494 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 20068 # Number of insts commited each cycle
system.cpu.commit.committedInsts 5380 # Number of instructions committed
system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.function_calls 106 # Number of function calls committed.
system.cpu.commit.bw_lim_events 213 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 37403 # The number of ROB reads
-system.cpu.rob.rob_writes 42056 # The number of ROB writes
-system.cpu.timesIdled 165 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 12765 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 40106 # The number of ROB reads
+system.cpu.rob.rob_writes 42382 # The number of ROB writes
+system.cpu.timesIdled 168 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 17254 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5380 # Number of Instructions Simulated
system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 5380 # Number of Instructions Simulated
-system.cpu.cpi 5.956134 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 5.956134 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.167894 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.167894 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 28607 # number of integer regfile reads
-system.cpu.int_regfile_writes 17139 # number of integer regfile writes
+system.cpu.cpi 7.282342 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.282342 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.137318 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.137318 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 28721 # number of integer regfile reads
+system.cpu.int_regfile_writes 17199 # number of integer regfile writes
system.cpu.fp_regfile_reads 4 # number of floating regfile reads
-system.cpu.misc_regfile_reads 7155 # number of misc regfile reads
+system.cpu.misc_regfile_reads 7135 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
+system.cpu.toL2Bus.throughput 1355862984 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 338 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 77 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 77 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 548 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 283 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 831 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17536 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9024 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 26560 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 26560 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 208000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 411000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 134.419040 # Cycle average of tags in use
-system.cpu.icache.total_refs 1594 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 5.713262 # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse 130.964375 # Cycle average of tags in use
+system.cpu.icache.total_refs 1611 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 274 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 5.879562 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 134.419040 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.065634 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.065634 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 1594 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1594 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1594 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1594 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1594 # number of overall hits
-system.cpu.icache.overall_hits::total 1594 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 371 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 371 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 371 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 371 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 371 # number of overall misses
-system.cpu.icache.overall_misses::total 371 # number of overall misses
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+system.cpu.dcache.overall_mshr_miss_latency::total 10484500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040448 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040448 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.082353 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.082353 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.056448 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.056448 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.056448 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60552.238806 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60552.238806 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55636.363636 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55636.363636 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57923.611111 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 57923.611111 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57923.611111 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 57923.611111 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055862 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.055862 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055862 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.055862 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76753.846154 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76753.846154 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71370.129870 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71370.129870 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73834.507042 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 73834.507042 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73834.507042 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 73834.507042 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
system.physmem.bw_total::cpu.inst 9779519145 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2525022262 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12304541407 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 12304541407 # Throughput (bytes/s)
+system.membus.data_through_bus 69090 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 11231 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.physmem.bw_total::cpu.inst 512306933 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 302419070 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 814726003 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 814726003 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 282 # Transaction distribution
+system.membus.trans_dist::ReadResp 282 # Transaction distribution
+system.membus.trans_dist::ReadExReq 79 # Transaction distribution
+system.membus.trans_dist::ReadExResp 79 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::system.physmem.port 722 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 23104 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 361000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
+system.membus.respLayer1.occupancy 3249000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 11.5 # Layer utilization (%)
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 56716 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 816982862 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 283 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 456 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 268 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 724 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 14592 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8576 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 23168 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 23168 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
sim_seconds 0.000024 # Number of seconds simulated
-sim_ticks 24422500 # Number of ticks simulated
-final_tick 24422500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 23841000 # Number of ticks simulated
+final_tick 23841000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 26625 # Simulator instruction rate (inst/s)
-host_op_rate 26623 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 51014333 # Simulator tick rate (ticks/s)
-host_mem_usage 270288 # Number of bytes of host memory used
-host_seconds 0.48 # Real time elapsed on the host
+host_inst_rate 85306 # Simulator instruction rate (inst/s)
+host_op_rate 85298 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 159545701 # Simulator tick rate (ticks/s)
+host_mem_usage 228064 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
sim_insts 12745 # Number of instructions simulated
sim_ops 12745 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 39808 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 22272 # Number of bytes read from this memory
-system.physmem.bytes_read::total 62080 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 39808 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 39808 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 622 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 348 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 970 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1629972362 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 911945951 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2541918313 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1629972362 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1629972362 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1629972362 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 911945951 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2541918313 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 970 # Total number of read requests seen
+system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 22400 # Number of bytes read from this memory
+system.physmem.bytes_read::total 62400 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 40000 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 40000 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 625 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 350 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 975 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1677781972 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 939557904 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2617339877 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1677781972 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1677781972 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1677781972 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 939557904 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2617339877 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 975 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 970 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 62080 # Total number of bytes read from memory
+system.physmem.cpureqs 975 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 62400 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 62080 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 62400 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 101 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 34 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 45 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 100 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 103 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 116 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 66 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 88 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 40 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 21 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 60 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 91 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 83 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 154 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 77 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 59 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 86 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 49 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 33 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 49 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 41 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 39 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 33 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 121 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 70 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 36 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 24269500 # Total gap between requests
+system.physmem.totGap 23399000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 970 # Categorize read packet sizes
+system.physmem.readPktSize::6 975 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 167 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 262 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 252 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 173 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 87 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 28 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 347 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 345 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 183 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 78 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 22107000 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 52930750 # Sum of mem lat for all requests
-system.physmem.totBusLat 4850000 # Total cycles spent in databus access
-system.physmem.totBankLat 25973750 # Total cycles spent in bank access
-system.physmem.avgQLat 22790.72 # Average queueing delay per request
-system.physmem.avgBankLat 26777.06 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 181 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 309.392265 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 160.897114 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 490.133684 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64 75 41.44% 41.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128 28 15.47% 56.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192 19 10.50% 67.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256 20 11.05% 78.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320 2 1.10% 79.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384 4 2.21% 81.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448 4 2.21% 83.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512 3 1.66% 85.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576 2 1.10% 86.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640 4 2.21% 88.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704 2 1.10% 90.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768 1 0.55% 90.61% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896 1 0.55% 91.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960 2 1.10% 92.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024 2 1.10% 93.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1088 2 1.10% 94.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216 1 0.55% 95.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1472 1 0.55% 95.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1728 1 0.55% 96.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856 1 0.55% 96.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920 2 1.10% 97.79% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112 1 0.55% 98.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2432 1 0.55% 98.90% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2880 2 1.10% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 181 # Bytes accessed per row activation
+system.physmem.totQLat 6851500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 28281500 # Sum of mem lat for all requests
+system.physmem.totBusLat 4875000 # Total cycles spent in databus access
+system.physmem.totBankLat 16555000 # Total cycles spent in bank access
+system.physmem.avgQLat 7027.18 # Average queueing delay per request
+system.physmem.avgBankLat 16979.49 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 54567.78 # Average memory access latency
-system.physmem.avgRdBW 2541.92 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 29006.67 # Average memory access latency
+system.physmem.avgRdBW 2617.34 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 2541.92 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 2617.34 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 19.86 # Data bus utilization in percentage
-system.physmem.avgRdQLen 2.17 # Average read queue length over time
+system.physmem.busUtil 20.45 # Data bus utilization in percentage
+system.physmem.avgRdQLen 1.19 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 449 # Number of row buffer hits during reads
+system.physmem.readRowHits 794 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 46.29 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 25020.10 # Average gap between requests
-system.cpu.branchPred.lookups 6091 # Number of BP lookups
-system.cpu.branchPred.condPredicted 3456 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1235 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 4406 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 1013 # Number of BTB hits
+system.physmem.avgGap 23998.97 # Average gap between requests
+system.membus.throughput 2617339877 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 829 # Transaction distribution
+system.membus.trans_dist::ReadResp 829 # Transaction distribution
+system.membus.trans_dist::ReadExReq 146 # Transaction distribution
+system.membus.trans_dist::ReadExResp 146 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 1950 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 1950 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 62400 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 62400 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 62400 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 1213500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 5.1 # Layer utilization (%)
+system.membus.respLayer1.occupancy 9055000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 38.0 # Layer utilization (%)
+system.cpu.branchPred.lookups 6923 # Number of BP lookups
+system.cpu.branchPred.condPredicted 3910 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1532 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 5090 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 950 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 22.991375 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 798 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 18.664047 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 864 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 198 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 4448 # DTB read hits
-system.cpu.dtb.read_misses 96 # DTB read misses
+system.cpu.dtb.read_hits 4694 # DTB read hits
+system.cpu.dtb.read_misses 109 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 4544 # DTB read accesses
-system.cpu.dtb.write_hits 2020 # DTB write hits
-system.cpu.dtb.write_misses 84 # DTB write misses
+system.cpu.dtb.read_accesses 4803 # DTB read accesses
+system.cpu.dtb.write_hits 2055 # DTB write hits
+system.cpu.dtb.write_misses 93 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 2104 # DTB write accesses
-system.cpu.dtb.data_hits 6468 # DTB hits
-system.cpu.dtb.data_misses 180 # DTB misses
+system.cpu.dtb.write_accesses 2148 # DTB write accesses
+system.cpu.dtb.data_hits 6749 # DTB hits
+system.cpu.dtb.data_misses 202 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 6648 # DTB accesses
-system.cpu.itb.fetch_hits 4827 # ITB hits
-system.cpu.itb.fetch_misses 49 # ITB misses
+system.cpu.dtb.data_accesses 6951 # DTB accesses
+system.cpu.itb.fetch_hits 5431 # ITB hits
+system.cpu.itb.fetch_misses 58 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 4876 # ITB accesses
+system.cpu.itb.fetch_accesses 5489 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload0.num_syscalls 17 # Number of system calls
system.cpu.workload1.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 48846 # number of cpu cycles simulated
+system.cpu.numCycles 47683 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 1375 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 33885 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 6091 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1811 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 5723 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1593 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 523 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines 4827 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 809 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 28036 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.208625 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.641797 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 1647 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 37826 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 6923 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1814 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 6352 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1907 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 435 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines 5431 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 913 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 28904 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.308677 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.731944 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 22313 79.59% 79.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 519 1.85% 81.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 362 1.29% 82.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 384 1.37% 84.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 439 1.57% 85.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 391 1.39% 87.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 437 1.56% 88.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 371 1.32% 89.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 2820 10.06% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 22552 78.02% 78.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 590 2.04% 80.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 356 1.23% 81.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 460 1.59% 82.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 445 1.54% 84.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 430 1.49% 85.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 481 1.66% 87.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 392 1.36% 88.94% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 3198 11.06% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 28036 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.124698 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.693711 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 38743 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 9028 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 4948 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 475 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 2422 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 482 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 289 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 30410 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 547 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 2422 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 39365 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 6014 # Number of cycles rename is blocking
+system.cpu.fetch.rateDist::total 28904 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.145188 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.793281 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 39785 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 9139 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 5505 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 442 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 2806 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 644 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 419 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 33037 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 796 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 2806 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 40500 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 6036 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 969 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 4720 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 2126 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 28231 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 57 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 2058 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 21224 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 34730 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 34696 # Number of integer rename lookups
+system.cpu.rename.RunCycles 5106 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 2260 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 30593 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 58 # Number of times rename has blocked due to ROB full
+system.cpu.rename.LSQFullEvents 2227 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 22886 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 37694 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 37660 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 12084 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 49 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 5609 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2913 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1333 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads.
+system.cpu.rename.UndoneMaps 13746 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 54 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 5822 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 3090 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1408 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.memDep1.insertedLoads 2720 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep1.insertedStores 1281 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep1.conflictingLoads 6 # Number of conflicting loads.
+system.cpu.memDep1.insertedLoads 3019 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep1.insertedStores 1424 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep1.conflictingLoads 3 # Number of conflicting loads.
system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 25056 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 73 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 20851 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 67 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 11467 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 7098 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 28036 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.743722 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.323178 # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded 26797 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 83 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 22164 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 13006 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 8107 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 28904 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.766814 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.345310 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 18861 67.27% 67.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 3429 12.23% 79.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 2549 9.09% 88.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 1540 5.49% 94.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 935 3.33% 97.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 455 1.62% 99.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 194 0.69% 99.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 59 0.21% 99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 14 0.05% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 19221 66.50% 66.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 3610 12.49% 78.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 2656 9.19% 88.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 1611 5.57% 93.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 1014 3.51% 97.26% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 491 1.70% 98.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 230 0.80% 99.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 50 0.17% 99.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 21 0.07% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 28036 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 28904 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 5 2.99% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 103 61.68% 64.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 59 35.33% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 5 2.84% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 106 60.23% 63.07% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 65 36.93% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 6975 65.76% 65.78% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.79% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.79% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.81% # Type of FU issued
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-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.81% # Type of FU issued
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-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.81% # Type of FU issued
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-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.81% # Type of FU issued
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-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.81% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2523 23.79% 89.60% # Type of FU issued
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+system.cpu.iq.FU_type_0::IntAlu 7310 65.49% 65.51% # Type of FU issued
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+system.cpu.iq.FU_type_0::MemRead 2686 24.06% 89.60% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 10606 # Type of FU issued
+system.cpu.iq.FU_type_0::total 11162 # Type of FU issued
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_1::IntAlu 6760 65.98% 66.00% # Type of FU issued
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-system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.03% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.03% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.03% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.03% # Type of FU issued
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-system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.03% # Type of FU issued
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-system.cpu.iq.FU_type_1::MemRead 2371 23.14% 89.18% # Type of FU issued
-system.cpu.iq.FU_type_1::MemWrite 1109 10.82% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::total 10245 # Type of FU issued
+system.cpu.iq.FU_type_1::total 11002 # Type of FU issued
system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type::IntAlu 13735 65.87% 65.89% # Type of FU issued
-system.cpu.iq.FU_type::IntMult 2 0.01% 65.90% # Type of FU issued
-system.cpu.iq.FU_type::IntDiv 0 0.00% 65.90% # Type of FU issued
-system.cpu.iq.FU_type::FloatAdd 4 0.02% 65.92% # Type of FU issued
-system.cpu.iq.FU_type::FloatCmp 0 0.00% 65.92% # Type of FU issued
-system.cpu.iq.FU_type::FloatCvt 0 0.00% 65.92% # Type of FU issued
-system.cpu.iq.FU_type::FloatMult 0 0.00% 65.92% # Type of FU issued
-system.cpu.iq.FU_type::FloatDiv 0 0.00% 65.92% # Type of FU issued
-system.cpu.iq.FU_type::FloatSqrt 0 0.00% 65.92% # Type of FU issued
-system.cpu.iq.FU_type::SimdAdd 0 0.00% 65.92% # Type of FU issued
-system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 65.92% # Type of FU issued
-system.cpu.iq.FU_type::SimdAlu 0 0.00% 65.92% # Type of FU issued
-system.cpu.iq.FU_type::SimdCmp 0 0.00% 65.92% # Type of FU issued
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-system.cpu.iq.FU_type::SimdMult 0 0.00% 65.92% # Type of FU issued
-system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 65.92% # Type of FU issued
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-system.cpu.iq.FU_type::SimdSqrt 0 0.00% 65.92% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 65.92% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued
-system.cpu.iq.FU_type::MemRead 4894 23.47% 89.39% # Type of FU issued
-system.cpu.iq.FU_type::MemWrite 2212 10.61% 100.00% # Type of FU issued
+system.cpu.iq.FU_type::IntAlu 14565 65.71% 65.73% # Type of FU issued
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+system.cpu.iq.FU_type::IntDiv 0 0.00% 65.74% # Type of FU issued
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+system.cpu.iq.FU_type::FloatMult 0 0.00% 65.76% # Type of FU issued
+system.cpu.iq.FU_type::FloatDiv 0 0.00% 65.76% # Type of FU issued
+system.cpu.iq.FU_type::FloatSqrt 0 0.00% 65.76% # Type of FU issued
+system.cpu.iq.FU_type::SimdAdd 0 0.00% 65.76% # Type of FU issued
+system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 65.76% # Type of FU issued
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+system.cpu.iq.FU_type::SimdCmp 0 0.00% 65.76% # Type of FU issued
+system.cpu.iq.FU_type::SimdCvt 0 0.00% 65.76% # Type of FU issued
+system.cpu.iq.FU_type::SimdMisc 0 0.00% 65.76% # Type of FU issued
+system.cpu.iq.FU_type::SimdMult 0 0.00% 65.76% # Type of FU issued
+system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 65.76% # Type of FU issued
+system.cpu.iq.FU_type::SimdShift 0 0.00% 65.76% # Type of FU issued
+system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 65.76% # Type of FU issued
+system.cpu.iq.FU_type::SimdSqrt 0 0.00% 65.76% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 65.76% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 65.76% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 65.76% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 65.76% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 65.76% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 65.76% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 65.76% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 65.76% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 65.76% # Type of FU issued
+system.cpu.iq.FU_type::MemRead 5281 23.83% 89.59% # Type of FU issued
+system.cpu.iq.FU_type::MemWrite 2308 10.41% 100.00% # Type of FU issued
system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type::total 20851 # Type of FU issued
-system.cpu.iq.rate 0.426872 # Inst issue rate
+system.cpu.iq.FU_type::total 22164 # Type of FU issued
+system.cpu.iq.rate 0.464820 # Inst issue rate
system.cpu.iq.fu_busy_cnt::0 86 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::1 81 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::total 167 # FU busy when requested
-system.cpu.iq.fu_busy_rate::0 0.004125 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::1 0.003885 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::total 0.008009 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 69931 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 36600 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 18226 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 41 # Number of floating instruction queue reads
+system.cpu.iq.fu_busy_cnt::1 90 # FU busy when requested
+system.cpu.iq.fu_busy_cnt::total 176 # FU busy when requested
+system.cpu.iq.fu_busy_rate::0 0.003880 # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::1 0.004061 # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::total 0.007941 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 73490 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 39895 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 19126 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 20993 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 21 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses 22314 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 66 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1730 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 468 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1907 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 543 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 422 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread1.forwLoads 60 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.cacheBlocked 358 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.forwLoads 56 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread1.squashedLoads 1537 # Number of loads squashed
-system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations
-system.cpu.iew.lsq.thread1.squashedStores 416 # Number of stores squashed
+system.cpu.iew.lsq.thread1.squashedLoads 1836 # Number of loads squashed
+system.cpu.iew.lsq.thread1.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread1.memOrderViolation 16 # Number of memory ordering violations
+system.cpu.iew.lsq.thread1.squashedStores 559 # Number of stores squashed
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread1.cacheBlocked 292 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.cacheBlocked 384 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 2422 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 2853 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 25308 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 582 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 5633 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 2614 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 73 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 221 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 905 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1126 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 19605 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts::0 2348 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::1 2207 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::total 4555 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1246 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 2806 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 2710 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 27087 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 546 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 6109 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 2832 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 83 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 23 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 31 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 255 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1078 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1333 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 20623 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts::0 2441 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::1 2376 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::total 4817 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1541 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
-system.cpu.iew.exec_nop::0 98 # number of nop insts executed
-system.cpu.iew.exec_nop::1 81 # number of nop insts executed
-system.cpu.iew.exec_nop::total 179 # number of nop insts executed
-system.cpu.iew.exec_refs::0 3414 # number of memory reference insts executed
-system.cpu.iew.exec_refs::1 3257 # number of memory reference insts executed
-system.cpu.iew.exec_refs::total 6671 # number of memory reference insts executed
-system.cpu.iew.exec_branches::0 1525 # Number of branches executed
-system.cpu.iew.exec_branches::1 1521 # Number of branches executed
-system.cpu.iew.exec_branches::total 3046 # Number of branches executed
-system.cpu.iew.exec_stores::0 1066 # Number of stores executed
-system.cpu.iew.exec_stores::1 1050 # Number of stores executed
-system.cpu.iew.exec_stores::total 2116 # Number of stores executed
-system.cpu.iew.exec_rate 0.401363 # Inst execution rate
-system.cpu.iew.wb_sent::0 9356 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::1 9171 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::total 18527 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count::0 9213 # cumulative count of insts written-back
-system.cpu.iew.wb_count::1 9033 # cumulative count of insts written-back
-system.cpu.iew.wb_count::total 18246 # cumulative count of insts written-back
-system.cpu.iew.wb_producers::0 4732 # num instructions producing a value
-system.cpu.iew.wb_producers::1 4628 # num instructions producing a value
-system.cpu.iew.wb_producers::total 9360 # num instructions producing a value
-system.cpu.iew.wb_consumers::0 6204 # num instructions consuming a value
-system.cpu.iew.wb_consumers::1 6054 # num instructions consuming a value
-system.cpu.iew.wb_consumers::total 12258 # num instructions consuming a value
+system.cpu.iew.exec_nop::0 115 # number of nop insts executed
+system.cpu.iew.exec_nop::1 92 # number of nop insts executed
+system.cpu.iew.exec_nop::total 207 # number of nop insts executed
+system.cpu.iew.exec_refs::0 3520 # number of memory reference insts executed
+system.cpu.iew.exec_refs::1 3467 # number of memory reference insts executed
+system.cpu.iew.exec_refs::total 6987 # number of memory reference insts executed
+system.cpu.iew.exec_branches::0 1642 # Number of branches executed
+system.cpu.iew.exec_branches::1 1654 # Number of branches executed
+system.cpu.iew.exec_branches::total 3296 # Number of branches executed
+system.cpu.iew.exec_stores::0 1079 # Number of stores executed
+system.cpu.iew.exec_stores::1 1091 # Number of stores executed
+system.cpu.iew.exec_stores::total 2170 # Number of stores executed
+system.cpu.iew.exec_rate 0.432502 # Inst execution rate
+system.cpu.iew.wb_sent::0 9753 # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::1 9719 # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::total 19472 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count::0 9565 # cumulative count of insts written-back
+system.cpu.iew.wb_count::1 9581 # cumulative count of insts written-back
+system.cpu.iew.wb_count::total 19146 # cumulative count of insts written-back
+system.cpu.iew.wb_producers::0 4912 # num instructions producing a value
+system.cpu.iew.wb_producers::1 4854 # num instructions producing a value
+system.cpu.iew.wb_producers::total 9766 # num instructions producing a value
+system.cpu.iew.wb_consumers::0 6410 # num instructions consuming a value
+system.cpu.iew.wb_consumers::1 6363 # num instructions consuming a value
+system.cpu.iew.wb_consumers::total 12773 # num instructions consuming a value
system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate::0 0.188613 # insts written-back per cycle
-system.cpu.iew.wb_rate::1 0.184928 # insts written-back per cycle
-system.cpu.iew.wb_rate::total 0.373541 # insts written-back per cycle
-system.cpu.iew.wb_fanout::0 0.762734 # average fanout of values written-back
-system.cpu.iew.wb_fanout::1 0.764453 # average fanout of values written-back
-system.cpu.iew.wb_fanout::total 0.763583 # average fanout of values written-back
+system.cpu.iew.wb_rate::0 0.200596 # insts written-back per cycle
+system.cpu.iew.wb_rate::1 0.200931 # insts written-back per cycle
+system.cpu.iew.wb_rate::total 0.401527 # insts written-back per cycle
+system.cpu.iew.wb_fanout::0 0.766303 # average fanout of values written-back
+system.cpu.iew.wb_fanout::1 0.762848 # average fanout of values written-back
+system.cpu.iew.wb_fanout::total 0.764582 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 12541 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 14336 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 961 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 27993 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.456507 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.239608 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1138 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 28841 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.443084 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.197327 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 22231 79.42% 79.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 3185 11.38% 90.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 1025 3.66% 94.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 479 1.71% 96.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 332 1.19% 97.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 227 0.81% 98.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 194 0.69% 98.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 80 0.29% 99.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 240 0.86% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 22992 79.72% 79.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 3164 10.97% 90.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 1129 3.91% 94.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 501 1.74% 96.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 358 1.24% 97.58% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 236 0.82% 98.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 188 0.65% 99.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 70 0.24% 99.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 203 0.70% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 27993 # Number of insts commited each cycle
-system.cpu.commit.committedInsts::0 6389 # Number of instructions committed
-system.cpu.commit.committedInsts::1 6390 # Number of instructions committed
+system.cpu.commit.committed_per_cycle::total 28841 # Number of insts commited each cycle
+system.cpu.commit.committedInsts::0 6390 # Number of instructions committed
+system.cpu.commit.committedInsts::1 6389 # Number of instructions committed
system.cpu.commit.committedInsts::total 12779 # Number of instructions committed
-system.cpu.commit.committedOps::0 6389 # Number of ops (including micro ops) committed
-system.cpu.commit.committedOps::1 6390 # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps::0 6390 # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps::1 6389 # Number of ops (including micro ops) committed
system.cpu.commit.committedOps::total 12779 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed
system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed
system.cpu.commit.function_calls::0 127 # Number of function calls committed.
system.cpu.commit.function_calls::1 127 # Number of function calls committed.
system.cpu.commit.function_calls::total 254 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 240 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 203 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits
system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits
system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 126718 # The number of ROB reads
-system.cpu.rob.rob_writes 53072 # The number of ROB writes
-system.cpu.timesIdled 387 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 20810 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts::0 6372 # Number of Instructions Simulated
-system.cpu.committedInsts::1 6373 # Number of Instructions Simulated
-system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated
-system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated
+system.cpu.rob.rob_reads 132883 # The number of ROB reads
+system.cpu.rob.rob_writes 57054 # The number of ROB writes
+system.cpu.timesIdled 370 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 18779 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts::0 6373 # Number of Instructions Simulated
+system.cpu.committedInsts::1 6372 # Number of Instructions Simulated
+system.cpu.committedOps::0 6373 # Number of Ops (including micro ops) Simulated
+system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 12745 # Number of Instructions Simulated
-system.cpu.cpi::0 7.665725 # CPI: Cycles Per Instruction
-system.cpu.cpi::1 7.664522 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.832562 # CPI: Total CPI of All Threads
-system.cpu.ipc::0 0.130451 # IPC: Instructions Per Cycle
-system.cpu.ipc::1 0.130471 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.260922 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 24678 # number of integer regfile reads
-system.cpu.int_regfile_writes 13757 # number of integer regfile writes
+system.cpu.cpi::0 7.482034 # CPI: Cycles Per Instruction
+system.cpu.cpi::1 7.483208 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.741310 # CPI: Total CPI of All Threads
+system.cpu.ipc::0 0.133654 # IPC: Instructions Per Cycle
+system.cpu.ipc::1 0.133633 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.267286 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 25857 # number of integer regfile reads
+system.cpu.int_regfile_writes 14461 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
system.cpu.misc_regfile_writes 2 # number of misc regfile writes
+system.cpu.toL2Bus.throughput 2622708779 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 831 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 831 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1254 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 700 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 1954 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 40128 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 22400 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 62528 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 62528 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 488500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 940500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 3.9 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 525000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%)
system.cpu.icache.replacements::0 6 # number of replacements
system.cpu.icache.replacements::1 0 # number of replacements
system.cpu.icache.replacements::total 6 # number of replacements
-system.cpu.icache.tagsinuse 293.126270 # Cycle average of tags in use
-system.cpu.icache.total_refs 3772 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 624 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 6.044872 # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse 313.799979 # Cycle average of tags in use
+system.cpu.icache.total_refs 4370 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 627 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 6.969697 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 293.126270 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.143128 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.143128 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 3772 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 3772 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 3772 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 3772 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 3772 # number of overall hits
-system.cpu.icache.overall_hits::total 3772 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1048 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1048 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1048 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1048 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1048 # number of overall misses
-system.cpu.icache.overall_misses::total 1048 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 78261996 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 78261996 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 78261996 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 78261996 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 78261996 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 78261996 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 4820 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 4820 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 4820 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 4820 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 4820 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 4820 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217427 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.217427 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.217427 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.217427 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.217427 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.217427 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74677.477099 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 74677.477099 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 74677.477099 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 74677.477099 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 74677.477099 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 74677.477099 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 3131 # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst 313.799979 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.153223 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.153223 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 4370 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 4370 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 4370 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 4370 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 4370 # number of overall hits
+system.cpu.icache.overall_hits::total 4370 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1055 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1055 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1055 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1055 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1055 # number of overall misses
+system.cpu.icache.overall_misses::total 1055 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 67889996 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 67889996 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 67889996 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 67889996 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 67889996 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 67889996 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 5425 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 5425 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 5425 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 5425 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 5425 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 5425 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194470 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.194470 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.194470 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.194470 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.194470 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.194470 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64350.707109 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 64350.707109 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997579 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997593 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63981.344051 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75970.633663 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66920.466019 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70906.212329 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70906.212329 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63981.344051 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73845.905172 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67520.382474 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63981.344051 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73845.905172 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67520.382474 # average overall mshr miss latency
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68253.676471 # average ReadReq mshr miss latency
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+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60081.200000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64543.571429 # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61683.076923 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements::0 0 # number of replacements
system.cpu.dcache.replacements::1 0 # number of replacements
system.cpu.dcache.replacements::total 0 # number of replacements
-system.cpu.dcache.tagsinuse 203.203118 # Cycle average of tags in use
-system.cpu.dcache.total_refs 4334 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 348 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 12.454023 # Average number of references to valid blocks.
+system.cpu.dcache.tagsinuse 213.416851 # Cycle average of tags in use
+system.cpu.dcache.total_refs 4586 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 350 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 13.102857 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 203.203118 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.049610 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.049610 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 3312 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 3312 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 1022 # number of WriteReq hits
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-system.cpu.dcache.demand_hits::total 4334 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 4334 # number of overall hits
-system.cpu.dcache.overall_hits::total 4334 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 323 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 323 # number of ReadReq misses
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-system.cpu.dcache.WriteReq_misses::total 708 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 1031 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1031 # number of demand (read+write) misses
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-system.cpu.dcache.overall_misses::total 1031 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 25422500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 25422500 # number of ReadReq miss cycles
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-system.cpu.dcache.WriteReq_miss_latency::total 53416467 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 78838967 # number of demand (read+write) miss cycles
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-system.cpu.dcache.overall_miss_latency::cpu.data 78838967 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 78838967 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 3635 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 3635 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.occ_blocks::cpu.data 213.416851 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.052104 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.052104 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 3569 # number of ReadReq hits
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system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
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-system.cpu.dcache.demand_accesses::total 5365 # number of demand (read+write) accesses
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-system.cpu.dcache.overall_accesses::total 5365 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.088858 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.088858 # miss rate for ReadReq accesses
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-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78707.430341 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 78707.430341 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75446.987288 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 75446.987288 # average WriteReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 76468.445199 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 76468.445199 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 76468.445199 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 4608 # number of cycles access was blocked
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+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71434.049080 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 71434.049080 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60344.230014 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 60344.230014 # average WriteReq miss latency
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+system.cpu.dcache.demand_avg_miss_latency::total 63823.807507 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 63823.807507 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 63823.807507 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 4266 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 92 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 128 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.086957 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.328125 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 121 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 121 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 562 # number of WriteReq MSHR hits
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-system.cpu.dcache.demand_mshr_hits::total 683 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 683 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 683 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses
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+system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses
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-system.cpu.dcache.demand_mshr_misses::total 348 # number of demand (read+write) MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total 348 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18013500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 18013500 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.WriteReq_mshr_miss_latency::total 12283998 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30297498 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 30297498 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30297498 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 30297498 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055571 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055571 # mshr miss rate for ReadReq accesses
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+system.cpu.dcache.overall_mshr_miss_latency::total 27237995 # number of overall MSHR miss cycles
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+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052375 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064865 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.064865 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064865 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.064865 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89175.742574 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89175.742574 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84136.972603 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84136.972603 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87061.775862 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 87061.775862 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87061.775862 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 87061.775862 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062222 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.062222 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062222 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.062222 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81509.803922 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81509.803922 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72671.198630 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72671.198630 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77822.842857 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 77822.842857 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77822.842857 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 77822.842857 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000023 # Number of seconds simulated
-sim_ticks 23146500 # Number of ticks simulated
-final_tick 23146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000027 # Number of seconds simulated
+sim_ticks 27167500 # Number of ticks simulated
+final_tick 27167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 95077 # Simulator instruction rate (inst/s)
-host_op_rate 95070 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 145124480 # Simulator tick rate (ticks/s)
-host_mem_usage 230244 # Number of bytes of host memory used
-host_seconds 0.16 # Real time elapsed on the host
+host_inst_rate 49297 # Simulator instruction rate (inst/s)
+host_op_rate 49293 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 88314525 # Simulator tick rate (ticks/s)
+host_mem_usage 232472 # Number of bytes of host memory used
+host_seconds 0.31 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
system.physmem.num_reads::total 436 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 823969067 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 381569568 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1205538634 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 823969067 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 823969067 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 823969067 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 381569568 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1205538634 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 702015276 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 325094322 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1027109598 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 702015276 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 702015276 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 702015276 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 325094322 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1027109598 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 436 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 36 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 31 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 28 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 6 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 10 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 26 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 84 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 39 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 7 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 24 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 97 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 28 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 38 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 20 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 16 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 29 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 48 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 58 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 33 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 23113000 # Total gap between requests
+system.physmem.totGap 27134000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 116 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 32 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2156250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 12063750 # Sum of mem lat for all requests
+system.physmem.bytesPerActivate::samples 49 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 344.816327 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 179.016062 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 498.456939 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64 18 36.73% 36.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128 9 18.37% 55.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192 3 6.12% 61.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256 5 10.20% 71.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320 3 6.12% 77.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384 1 2.04% 79.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448 1 2.04% 81.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576 2 4.08% 85.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704 1 2.04% 87.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768 1 2.04% 89.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896 1 2.04% 91.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1600 1 2.04% 93.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856 1 2.04% 95.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1920 1 2.04% 97.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2048 1 2.04% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 49 # Bytes accessed per row activation
+system.physmem.totQLat 1645750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 10137000 # Sum of mem lat for all requests
system.physmem.totBusLat 2180000 # Total cycles spent in databus access
-system.physmem.totBankLat 7727500 # Total cycles spent in bank access
-system.physmem.avgQLat 4945.53 # Average queueing delay per request
-system.physmem.avgBankLat 17723.62 # Average bank access latency per request
+system.physmem.totBankLat 6311250 # Total cycles spent in bank access
+system.physmem.avgQLat 3774.66 # Average queueing delay per request
+system.physmem.avgBankLat 14475.34 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 27669.15 # Average memory access latency
-system.physmem.avgRdBW 1205.54 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 23250.00 # Average memory access latency
+system.physmem.avgRdBW 1027.11 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1205.54 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1027.11 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 9.42 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.52 # Average read queue length over time
+system.physmem.busUtil 8.02 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.37 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 339 # Number of row buffer hits during reads
+system.physmem.readRowHits 387 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 77.75 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 88.76 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 53011.47 # Average gap between requests
+system.physmem.avgGap 62233.94 # Average gap between requests
+system.membus.throughput 1024753842 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 351 # Transaction distribution
+system.membus.trans_dist::ReadResp 350 # Transaction distribution
+system.membus.trans_dist::ReadExReq 85 # Transaction distribution
+system.membus.trans_dist::ReadExResp 85 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 871 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 871 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 27840 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 27840 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 27840 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 519000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 1.9 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4057250 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 14.9 # Layer utilization (%)
system.cpu.branchPred.lookups 5146 # Number of BP lookups
system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 2366 # Number of conditional branches incorrect
system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 18 # Number of system calls
-system.cpu.numCycles 46294 # number of cpu cycles simulated
+system.cpu.numCycles 54336 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True).
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 21905 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 21896 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 505 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 28726 # Number of cycles cpu's stages were not processed
+system.cpu.timesIdled 498 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 36768 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 17568 # Number of cycles cpu stages are processed.
-system.cpu.activity 37.948762 # Percentage of cycles cpu is active
+system.cpu.activity 32.332155 # Percentage of cycles cpu is active
system.cpu.comLoads 2225 # Number of Load instructions committed
system.cpu.comStores 1448 # Number of Store instructions committed
system.cpu.comBranches 3358 # Number of Branches instructions committed
system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total)
-system.cpu.cpi 3.053291 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 3.583696 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 3.053291 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.327515 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 3.583696 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.279042 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 0.327515 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 32868 # Number of cycles 0 instructions are processed.
+system.cpu.ipc_total 0.279042 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 40910 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 29.001598 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 36941 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.utilization 24.709217 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 44983 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 20.203482 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 37491 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.utilization 17.213266 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 45533 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 19.015423 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 43416 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.utilization 16.201045 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 51458 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 6.216788 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 36985 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.utilization 5.296673 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 45027 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 20.108437 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.utilization 17.132288 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 172.164652 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 168.384950 # Cycle average of tags in use
system.cpu.icache.total_refs 3004 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 10.046823 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 172.164652 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.084065 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.084065 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst 168.384950 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.082219 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.082219 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits
system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses
system.cpu.icache.overall_misses::total 381 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 18686000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 18686000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 18686000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 18686000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 18686000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 18686000 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 25319500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 25319500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 25319500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 25319500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 25319500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 25319500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses
system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49044.619423 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 49044.619423 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 49044.619423 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 49044.619423 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 49044.619423 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 49044.619423 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66455.380577 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 66455.380577 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 66455.380577 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 66455.380577 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 66455.380577 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 66455.380577 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14960000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 14960000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14960000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 14960000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14960000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 14960000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20038500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 20038500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20038500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 20038500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20038500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 20038500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49700.996678 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49700.996678 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49700.996678 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 49700.996678 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49700.996678 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 49700.996678 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66573.089701 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66573.089701 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66573.089701 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 66573.089701 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66573.089701 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57952.898551 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 57952.898551 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71377.358491 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71377.358491 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70188.235294 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70188.235294 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70644.927536 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 70644.927536 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70644.927536 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 70644.927536 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000024 # Number of seconds simulated
-sim_ticks 23775500 # Number of ticks simulated
-final_tick 23775500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000026 # Number of seconds simulated
+sim_ticks 26399500 # Number of ticks simulated
+final_tick 26399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 12604 # Simulator instruction rate (inst/s)
-host_op_rate 12604 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 20757401 # Simulator tick rate (ticks/s)
-host_mem_usage 277264 # Number of bytes of host memory used
-host_seconds 1.15 # Real time elapsed on the host
+host_inst_rate 93938 # Simulator instruction rate (inst/s)
+host_op_rate 93929 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 171756334 # Simulator tick rate (ticks/s)
+host_mem_usage 234512 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30912 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 30848 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 483 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 904460474 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 395701457 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1300161931 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 904460474 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 904460474 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 904460474 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 395701457 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1300161931 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 483 # Total number of read requests seen
+system.physmem.num_reads::total 482 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 812136593 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 356370386 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1168506979 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 812136593 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 812136593 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 812136593 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 356370386 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1168506979 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 482 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 483 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 30912 # Total number of bytes read from memory
+system.physmem.cpureqs 482 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 30848 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 30912 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 75 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 37 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 40 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 17 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 8 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 12 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 33 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 91 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 41 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 8 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 19 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 28 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 102 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 50 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 24 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 19 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 1 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 57 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 61 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 36 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 23715500 # Total gap between requests
+system.physmem.totGap 26239500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 483 # Categorize read packet sizes
+system.physmem.readPktSize::6 482 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 4632000 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 15613250 # Sum of mem lat for all requests
-system.physmem.totBusLat 2415000 # Total cycles spent in databus access
-system.physmem.totBankLat 8566250 # Total cycles spent in bank access
-system.physmem.avgQLat 9590.06 # Average queueing delay per request
-system.physmem.avgBankLat 17735.51 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 52 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 361.846154 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 181.816034 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 531.077461 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64 20 38.46% 38.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128 7 13.46% 51.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192 5 9.62% 61.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256 5 9.62% 71.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320 3 5.77% 76.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384 2 3.85% 80.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512 1 1.92% 82.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640 1 1.92% 84.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768 1 1.92% 86.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832 1 1.92% 88.46% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::960 2 3.85% 92.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1856 2 3.85% 96.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2112 1 1.92% 98.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::2176 1 1.92% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 52 # Bytes accessed per row activation
+system.physmem.totQLat 1765750 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 10927000 # Sum of mem lat for all requests
+system.physmem.totBusLat 2410000 # Total cycles spent in databus access
+system.physmem.totBankLat 6751250 # Total cycles spent in bank access
+system.physmem.avgQLat 3663.38 # Average queueing delay per request
+system.physmem.avgBankLat 14006.74 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 32325.57 # Average memory access latency
-system.physmem.avgRdBW 1300.16 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 22670.12 # Average memory access latency
+system.physmem.avgRdBW 1168.51 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1300.16 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1168.51 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 10.16 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.66 # Average read queue length over time
+system.physmem.busUtil 9.13 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.41 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 369 # Number of row buffer hits during reads
+system.physmem.readRowHits 430 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 76.40 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 89.21 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 49100.41 # Average gap between requests
-system.cpu.branchPred.lookups 6770 # Number of BP lookups
-system.cpu.branchPred.condPredicted 4525 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1074 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 4668 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 2447 # Number of BTB hits
+system.physmem.avgGap 54438.80 # Average gap between requests
+system.membus.throughput 1168506979 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 399 # Transaction distribution
+system.membus.trans_dist::ReadResp 399 # Transaction distribution
+system.membus.trans_dist::ReadExReq 83 # Transaction distribution
+system.membus.trans_dist::ReadExResp 83 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 964 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 964 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30848 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 30848 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 30848 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 583000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4486500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 17.0 # Layer utilization (%)
+system.cpu.branchPred.lookups 6719 # Number of BP lookups
+system.cpu.branchPred.condPredicted 4457 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1075 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 5025 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 2433 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 52.420737 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 48.417910 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 18 # Number of system calls
-system.cpu.numCycles 47552 # number of cpu cycles simulated
+system.cpu.numCycles 52800 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 12221 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 31483 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 6770 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 2889 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 9186 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 3077 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 8387 # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles 12414 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 31130 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 6719 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 2877 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 9133 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 3041 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 8772 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1048 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 5341 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 447 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 32753 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.961225 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.154417 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 994 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 5381 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 470 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 33187 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.938018 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.130523 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 23567 71.95% 71.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 4524 13.81% 85.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 464 1.42% 87.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 371 1.13% 88.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 671 2.05% 90.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 764 2.33% 92.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 234 0.71% 93.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 254 0.78% 94.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1904 5.81% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 24054 72.48% 72.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 4509 13.59% 86.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 475 1.43% 87.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 392 1.18% 88.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 680 2.05% 90.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 706 2.13% 92.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 235 0.71% 93.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 253 0.76% 94.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1883 5.67% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 32753 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.142370 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.662075 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 12951 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 9300 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 8402 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 193 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1907 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 29379 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 1907 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 13601 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 381 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 8395 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 8002 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 467 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 26943 # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 138 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 24189 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 49982 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 49982 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 33187 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.127254 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.589583 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 13016 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 9761 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 8340 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 200 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1870 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 29004 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 1870 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 13656 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 501 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 8734 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 7953 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 473 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 26651 # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 147 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 23943 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 49443 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 49443 # Number of integer rename lookups
system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 10370 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 10124 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 691 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 693 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 2748 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 3537 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 2327 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.tempSerializingInsts 694 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 2734 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 3527 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 2284 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 22737 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 650 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 21278 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 107 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 8171 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 5645 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 175 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 32753 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.649650 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.272846 # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded 22510 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 655 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 21113 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 96 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 7896 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 5507 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 33187 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.636183 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.261114 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 23497 71.74% 71.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 3507 10.71% 82.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 2330 7.11% 89.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 1726 5.27% 94.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 921 2.81% 97.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 469 1.43% 99.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 236 0.72% 99.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 48 0.15% 99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 23946 72.15% 72.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 3557 10.72% 82.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 2326 7.01% 89.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 1693 5.10% 94.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 889 2.68% 97.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 472 1.42% 99.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 239 0.72% 99.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 45 0.14% 99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 32753 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 33187 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 45 29.41% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.41% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 27 17.65% 47.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 81 52.94% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 26 17.69% 48.98% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 75 51.02% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 15764 74.09% 74.09% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 15643 74.09% 74.09% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.09% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.09% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.09% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.09% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 3369 15.83% 89.92% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 2145 10.08% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 3362 15.92% 90.02% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 2108 9.98% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 21278 # Type of FU issued
-system.cpu.iq.rate 0.447468 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 153 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.007191 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 75569 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 31584 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 19647 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 21113 # Type of FU issued
+system.cpu.iq.rate 0.399867 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 147 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.006963 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 75656 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 31087 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 19513 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 21431 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 21260 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1312 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1302 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 879 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 836 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1907 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 246 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 24523 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 379 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 3537 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 2327 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 650 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 1870 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 357 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 20 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 24299 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 398 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 3527 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 2284 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 655 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 254 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 264 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 945 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1199 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 20204 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 3219 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1074 # Number of squashed instructions skipped in execute
+system.cpu.iew.branchMispredicts 1209 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 20068 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 3202 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1045 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1136 # number of nop insts executed
-system.cpu.iew.exec_refs 5272 # number of memory reference insts executed
-system.cpu.iew.exec_branches 4246 # Number of branches executed
-system.cpu.iew.exec_stores 2053 # Number of stores executed
-system.cpu.iew.exec_rate 0.424882 # Inst execution rate
-system.cpu.iew.wb_sent 19870 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 19647 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 9208 # num instructions producing a value
-system.cpu.iew.wb_consumers 11364 # num instructions consuming a value
+system.cpu.iew.exec_nop 1134 # number of nop insts executed
+system.cpu.iew.exec_refs 5224 # number of memory reference insts executed
+system.cpu.iew.exec_branches 4238 # Number of branches executed
+system.cpu.iew.exec_stores 2022 # Number of stores executed
+system.cpu.iew.exec_rate 0.380076 # Inst execution rate
+system.cpu.iew.wb_sent 19741 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 19513 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 9111 # num instructions producing a value
+system.cpu.iew.wb_consumers 11226 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.413169 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.810278 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.369564 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.811598 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 9288 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 9039 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1074 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 30846 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.491539 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.188551 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 1075 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 31317 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.484146 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.180879 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 23538 76.31% 76.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 4051 13.13% 89.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 1362 4.42% 93.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 765 2.48% 96.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 357 1.16% 97.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 268 0.87% 98.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 325 1.05% 99.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 66 0.21% 99.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 114 0.37% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 23994 76.62% 76.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 4076 13.02% 89.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 1358 4.34% 93.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 763 2.44% 96.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 350 1.12% 97.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 272 0.87% 98.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 322 1.03% 99.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 67 0.21% 99.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 115 0.37% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 30846 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 31317 # Number of insts commited each cycle
system.cpu.commit.committedInsts 15162 # Number of instructions committed
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 12174 # Number of committed integer instructions.
system.cpu.commit.function_calls 187 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 115 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 54359 # The number of ROB reads
-system.cpu.rob.rob_writes 50813 # The number of ROB writes
-system.cpu.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 14799 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 54580 # The number of ROB reads
+system.cpu.rob.rob_writes 50280 # The number of ROB writes
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system.cpu.committedInsts 14436 # Number of Instructions Simulated
system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 14436 # Number of Instructions Simulated
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-system.cpu.cpi_total 3.293987 # CPI: Total CPI of All Threads
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-system.cpu.ipc_total 0.303583 # IPC: Total IPC of All Threads
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system.cpu.misc_regfile_writes 569 # number of misc regfile writes
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+system.cpu.dcache.demand_mshr_hits::cpu.data 388 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 388 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 388 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 388 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4894000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4894000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5244500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 5244500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10138500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10138500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10138500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10138500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020585 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020585 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4656000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4656000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5790000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5790000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10446000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10446000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10446000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10446000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032301 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.032301 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032301 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.032301 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76468.750000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76468.750000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63186.746988 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63186.746988 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68969.387755 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 68969.387755 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68969.387755 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 68969.387755 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.032450 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72750 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72750 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69759.036145 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69759.036145 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71061.224490 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 71061.224490 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71061.224490 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 71061.224490 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 7612000 # Number of ticks simulated
final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 30969 # Simulator instruction rate (inst/s)
-host_op_rate 30968 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 15546804 # Simulator tick rate (ticks/s)
-host_mem_usage 268968 # Number of bytes of host memory used
-host_seconds 0.49 # Real time elapsed on the host
+host_inst_rate 451796 # Simulator instruction rate (inst/s)
+host_op_rate 451441 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 226479305 # Simulator tick rate (ticks/s)
+host_mem_usage 222832 # Number of bytes of host memory used
+host_seconds 0.03 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 60828 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 7991066737 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2677877036 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 10668943773 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 10676563321 # Throughput (bytes/s)
+system.membus.data_through_bus 81270 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 15225 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
sim_ticks 41368000 # Number of ticks simulated
final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 26295 # Simulator instruction rate (inst/s)
-host_op_rate 26295 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 71739884 # Simulator tick rate (ticks/s)
-host_mem_usage 277420 # Number of bytes of host memory used
-host_seconds 0.58 # Real time elapsed on the host
+host_inst_rate 479032 # Simulator instruction rate (inst/s)
+host_op_rate 478642 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1304958787 # Simulator tick rate (ticks/s)
+host_mem_usage 231320 # Number of bytes of host memory used
+host_seconds 0.03 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 643589248 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 331 # Transaction distribution
+system.membus.trans_dist::ReadResp 331 # Transaction distribution
+system.membus.trans_dist::ReadExReq 85 # Transaction distribution
+system.membus.trans_dist::ReadExResp 85 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side 832 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 832 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 26624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 26624 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 26624 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
+system.membus.respLayer1.occupancy 3744000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 9.1 # Layer utilization (%)
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 82736 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.throughput 646683427 # Throughput (bytes/s)
+system.cpu.toL2Bus.trans_dist::ReadReq 333 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 560 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count 836 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 17920 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.tot_pkt_size 26752 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.data_through_bus 26752 # Total data (bytes)
+system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 420000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000106 # Number of seconds simulated
-sim_ticks 105945500 # Number of ticks simulated
-final_tick 105945500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000110 # Number of seconds simulated
+sim_ticks 110344500 # Number of ticks simulated
+final_tick 110344500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 48441 # Simulator instruction rate (inst/s)
-host_op_rate 48441 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4953275 # Simulator tick rate (ticks/s)
-host_mem_usage 291288 # Number of bytes of host memory used
-host_seconds 21.39 # Real time elapsed on the host
-sim_insts 1036095 # Number of instructions simulated
-sim_ops 1036095 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 22848 # Number of bytes read from this memory
+host_inst_rate 97195 # Simulator instruction rate (inst/s)
+host_op_rate 97194 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 10306929 # Simulator tick rate (ticks/s)
+host_mem_usage 249456 # Number of bytes of host memory used
+host_seconds 10.71 # Real time elapsed on the host
+sim_insts 1040548 # Number of instructions simulated
+sim_ops 1040548 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 4992 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 512 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst 192 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
-system.physmem.bytes_read::total 42240 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 22848 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 4992 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 512 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst 192 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 28544 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst 357 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 42176 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 22784 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst 384 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 28480 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu0.inst 356 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 78 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 8 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst 3 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 660 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 215658051 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 101486141 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 47118566 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 12081684 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 4832673 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 7853094 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 1812253 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 7853094 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 398695556 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 215658051 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 47118566 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 4832673 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 1812253 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 269421542 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 215658051 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 101486141 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 47118566 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 12081684 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 4832673 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 7853094 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 1812253 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 7853094 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 398695556 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 661 # Total number of read requests seen
+system.physmem.num_reads::total 659 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 206480613 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 97440289 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 46400138 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 11600034 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 1740005 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 7540022 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 3480010 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 7540022 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 382221135 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 206480613 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 46400138 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 1740005 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 3480010 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 258100766 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 206480613 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 97440289 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 46400138 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 11600034 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 1740005 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 7540022 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 3480010 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 7540022 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 382221135 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 660 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 735 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 42240 # Total number of bytes read from memory
+system.physmem.bytesRead 42176 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 42240 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 42176 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 74 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis
+system.physmem.neitherReadNorWrite 75 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 115 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 74 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 69 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 58 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 38 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 30 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 14 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 13 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 37 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 60 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 74 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 23 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 60 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 65 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 27 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 18 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 24 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 7 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 60 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 38 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 17 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 98 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 105917500 # Total gap between requests
+system.physmem.totGap 110316500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 661 # Categorize read packet sizes
+system.physmem.readPktSize::6 660 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 378 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 204 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 407 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 192 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 47 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 4080500 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 20695500 # Sum of mem lat for all requests
-system.physmem.totBusLat 3305000 # Total cycles spent in databus access
-system.physmem.totBankLat 13310000 # Total cycles spent in bank access
-system.physmem.avgQLat 6173.22 # Average queueing delay per request
-system.physmem.avgBankLat 20136.16 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 128 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 282 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 172.796288 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 318.984215 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64 51 39.84% 39.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128 11 8.59% 48.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::192 15 11.72% 60.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256 9 7.03% 67.19% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::320 10 7.81% 75.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384 5 3.91% 78.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::448 3 2.34% 81.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512 4 3.12% 84.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::576 3 2.34% 86.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640 4 3.12% 89.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::704 2 1.56% 91.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768 2 1.56% 92.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::832 2 1.56% 94.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024 4 3.12% 97.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1216 1 0.78% 98.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1536 1 0.78% 99.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1984 1 0.78% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 128 # Bytes accessed per row activation
+system.physmem.totQLat 3607500 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 17921250 # Sum of mem lat for all requests
+system.physmem.totBusLat 3300000 # Total cycles spent in databus access
+system.physmem.totBankLat 11013750 # Total cycles spent in bank access
+system.physmem.avgQLat 5465.91 # Average queueing delay per request
+system.physmem.avgBankLat 16687.50 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 31309.38 # Average memory access latency
-system.physmem.avgRdBW 398.70 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 27153.41 # Average memory access latency
+system.physmem.avgRdBW 382.22 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 398.70 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 382.22 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 3.11 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.19 # Average read queue length over time
+system.physmem.busUtil 2.99 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.16 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 465 # Number of row buffer hits during reads
+system.physmem.readRowHits 532 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 70.35 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 160238.28 # Average gap between requests
-system.cpu0.branchPred.lookups 82343 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 80122 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 1236 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 79627 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 77569 # Number of BTB hits
+system.physmem.avgGap 167146.21 # Average gap between requests
+system.membus.throughput 382221135 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 529 # Transaction distribution
+system.membus.trans_dist::ReadResp 528 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 284 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 75 # Transaction distribution
+system.membus.trans_dist::ReadExReq 164 # Transaction distribution
+system.membus.trans_dist::ReadExResp 131 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side 1711 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 1711 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side 42176 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 42176 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 42176 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 906000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.8 # Layer utilization (%)
+system.membus.respLayer0.occupancy 6286926 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 5.7 # Layer utilization (%)
+system.toL2Bus.throughput 1697085038 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 2531 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2530 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 287 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 287 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 395 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 395 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1175 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 585 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 850 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 363 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 856 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 356 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 860 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 363 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count 5408 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 37568 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 27200 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1600 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu2.icache.mem_side 27392 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu2.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu3.icache.mem_side 27520 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu3.dcache.mem_side 1536 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size 135488 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 135488 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 51776 # Total snoop data (bytes)
+system.toL2Bus.reqLayer0.occupancy 1621980 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 2642498 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 1437498 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 1913498 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 1.7 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 1155972 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 1.0 # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy 1929492 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization 1.7 # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy 1158481 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 1.0 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 1936496 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization 1.8 # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy 1165479 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%)
+system.cpu0.branchPred.lookups 82851 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 80650 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 80180 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 78131 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 97.415450 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 525 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.BTBHitPct 97.444500 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 512 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions.
system.cpu0.workload.num_syscalls 89 # Number of system calls
-system.cpu0.numCycles 211892 # number of cpu cycles simulated
+system.cpu0.numCycles 220690 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 17012 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 488761 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 82343 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 78094 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 160351 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 3870 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles 13040 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.icacheStallCycles 17257 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 491686 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 82851 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 78643 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 161395 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 3805 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles 13763 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 1377 # Number of stall cycles due to pending traps
-system.cpu0.fetch.CacheLines 5901 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 484 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples 194270 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 2.515885 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.216000 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.PendingTrapStallCycles 1562 # Number of stall cycles due to pending traps
+system.cpu0.fetch.CacheLines 5835 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 494 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples 196421 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 2.503225 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.215279 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 33919 17.46% 17.46% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 79392 40.87% 58.33% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 605 0.31% 58.64% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 996 0.51% 59.15% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 467 0.24% 59.39% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 75436 38.83% 98.22% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 571 0.29% 98.52% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 375 0.19% 98.71% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 2509 1.29% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 35026 17.83% 17.83% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 79943 40.70% 58.53% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 578 0.29% 58.83% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 973 0.50% 59.32% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 477 0.24% 59.56% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 76047 38.72% 98.28% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 571 0.29% 98.57% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 349 0.18% 98.75% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 2457 1.25% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 194270 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.388608 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 2.306652 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 17669 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 14482 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 159353 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 281 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 2485 # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts 485695 # Number of instructions handled by decode
-system.cpu0.rename.SquashCycles 2485 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 18316 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 722 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 13165 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 159020 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 562 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 482913 # Number of instructions processed by rename
-system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 156 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands 330456 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 963041 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 963041 # Number of integer rename lookups
-system.cpu0.rename.CommittedMaps 316991 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 13465 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 886 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 906 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 3563 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 154365 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 77987 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 75234 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 75049 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 403722 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 919 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 400870 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 11014 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 10026 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 360 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 194270 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 2.063468 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.094328 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 196421 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.375418 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 2.227949 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 17908 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 15370 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 160419 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 285 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 2439 # Number of cycles decode is squashing
+system.cpu0.decode.DecodedInsts 488842 # Number of instructions handled by decode
+system.cpu0.rename.SquashCycles 2439 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 18575 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 759 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 14008 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 160070 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 570 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 485981 # Number of instructions processed by rename
+system.cpu0.rename.LSQFullEvents 199 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands 332328 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 969157 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 969157 # Number of integer rename lookups
+system.cpu0.rename.CommittedMaps 319407 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 12921 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 867 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 888 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 3600 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 155469 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 78571 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 75822 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 75638 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 406410 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 911 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 403726 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 135 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 10718 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 9636 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 352 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 196421 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 2.055412 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.097532 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 33101 17.04% 17.04% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 4910 2.53% 19.57% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 77039 39.66% 59.22% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 76515 39.39% 98.61% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 1655 0.85% 99.46% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 696 0.36% 99.82% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 259 0.13% 99.95% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 77 0.04% 99.99% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 34004 17.31% 17.31% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 4909 2.50% 19.81% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 77804 39.61% 59.42% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 77117 39.26% 98.68% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 1569 0.80% 99.48% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 649 0.33% 99.81% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 264 0.13% 99.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 194270 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 196421 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 50 22.22% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 22.22% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 62 27.56% 49.78% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 113 50.22% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 57 25.68% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 53 23.87% 49.55% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 112 50.45% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 169604 42.31% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 153865 38.38% 80.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 77401 19.31% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 170720 42.29% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 155014 38.40% 80.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 77992 19.32% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 400870 # Type of FU issued
-system.cpu0.iq.rate 1.891860 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 225 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.000561 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 996359 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 415710 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 399019 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.FU_type_0::total 403726 # Type of FU issued
+system.cpu0.iq.rate 1.829381 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 222 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.000550 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 1004230 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 418093 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 401910 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 401095 # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses 403948 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 74761 # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.forwLoads 75361 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 2280 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 55 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 1438 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 2176 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.cacheBlocked 20 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 2485 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 453 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 480419 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 309 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 154365 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 77987 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 807 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewSquashCycles 2439 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 333 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 32 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 483693 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 313 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 155469 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 78571 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 799 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 55 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 346 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 1112 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 1458 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 399786 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 153534 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 1084 # Number of squashed instructions skipped in execute
+system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 342 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 1106 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 1448 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 402662 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 154684 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 1064 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 75778 # number of nop insts executed
-system.cpu0.iew.exec_refs 230828 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 79388 # Number of branches executed
-system.cpu0.iew.exec_stores 77294 # Number of stores executed
-system.cpu0.iew.exec_rate 1.886744 # Inst execution rate
-system.cpu0.iew.wb_sent 399367 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 399019 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 236486 # num instructions producing a value
-system.cpu0.iew.wb_consumers 239045 # num instructions consuming a value
+system.cpu0.iew.exec_nop 76372 # number of nop insts executed
+system.cpu0.iew.exec_refs 232577 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 79993 # Number of branches executed
+system.cpu0.iew.exec_stores 77893 # Number of stores executed
+system.cpu0.iew.exec_rate 1.824559 # Inst execution rate
+system.cpu0.iew.wb_sent 402239 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 401910 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 238133 # num instructions producing a value
+system.cpu0.iew.wb_consumers 240585 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 1.883124 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.989295 # average fanout of values written-back
+system.cpu0.iew.wb_rate 1.821152 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.989808 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 12546 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitSquashedInsts 12210 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 1236 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 191785 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 2.439388 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 2.136415 # Number of insts commited each cycle
+system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 193982 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 2.430442 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 2.136125 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 33586 17.51% 17.51% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 79020 41.20% 58.71% # Number of insts commited each cycle
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-system.cpu0.commit.committed_per_cycle::5 74531 38.86% 99.45% # Number of insts commited each cycle
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-system.cpu0.commit.committed_per_cycle::7 248 0.13% 99.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 310 0.16% 100.00% # Number of insts commited each cycle
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system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu0.commit.function_calls 223 # Number of function calls committed.
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system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu0.idleCycles 17622 # Total number of cycles that the CPU has spent unscheduled due to idling
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-system.cpu0.committedOps 392586 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 392586 # Number of Instructions Simulated
-system.cpu0.cpi 0.539734 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 0.539734 # CPI: Total CPI of All Threads
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-system.cpu0.ipc_total 1.852765 # IPC: Total IPC of All Threads
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+system.cpu0.cpi_total 0.557853 # CPI: Total CPI of All Threads
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system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
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system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
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-system.cpu0.icache.ReadReq_avg_miss_latency::total 35612.600536 # average ReadReq miss latency
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-system.cpu0.icache.ReadReq_mshr_misses::total 590 # number of ReadReq MSHR misses
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-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 35875.423729 # average overall mshr miss latency
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+system.cpu0.dcache.WriteReq_misses::total 545 # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 1019 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 1019 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 1019 # number of overall misses
-system.cpu0.dcache.overall_misses::total 1019 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11954500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 11954500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24681495 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 24681495 # number of WriteReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 599500 # number of SwapReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::total 599500 # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 36635995 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 36635995 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 36635995 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 36635995 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 78694 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 78694 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 76507 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 76507 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.demand_misses::cpu0.data 951 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 951 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 951 # number of overall misses
+system.cpu0.dcache.overall_misses::total 951 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 12750500 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 12750500 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35495482 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 35495482 # number of WriteReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 416500 # number of SwapReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::total 416500 # number of SwapReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 48245982 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 48245982 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 48245982 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 48245982 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 79262 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 79262 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 77111 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 77111 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 155201 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 155201 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 155201 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 155201 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006036 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.006036 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007110 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.007110 # miss rate for WriteReq accesses
+system.cpu0.dcache.demand_accesses::cpu0.data 156373 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 156373 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 156373 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 156373 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005122 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.005122 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007068 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.007068 # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006566 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.006566 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006566 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.006566 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25167.368421 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 25167.368421 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45370.395221 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 45370.395221 # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 28547.619048 # average SwapReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::total 28547.619048 # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35952.890088 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 35952.890088 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35952.890088 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 35952.890088 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 184 # number of cycles access was blocked
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006082 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.006082 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006082 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.006082 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31405.172414 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 31405.172414 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65129.324771 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 65129.324771 # average WriteReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19833.333333 # average SwapReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::total 19833.333333 # average SwapReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50731.842271 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 50731.842271 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50731.842271 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 50731.842271 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 499 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.142857 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.761905 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 286 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 286 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 373 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 373 # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 659 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 659 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 659 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 659 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 189 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 171 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 171 # number of WriteReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 220 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 220 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 590 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 590 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 590 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 590 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 186 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 186 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5407500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5407500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5740000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5740000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 557500 # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::total 557500 # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11147500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 11147500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11147500 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 11147500 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002402 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002402 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002235 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002235 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6035502 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6035502 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7873000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7873000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 374500 # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::total 374500 # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13908502 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 13908502 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13908502 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 13908502 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002347 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002347 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002269 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002269 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002320 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.002320 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002320 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.002320 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28611.111111 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28611.111111 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33567.251462 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33567.251462 # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26547.619048 # average SwapReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26547.619048 # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30965.277778 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30965.277778 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30965.277778 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30965.277778 # average overall mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.002309 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002309 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.002309 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32448.935484 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32448.935484 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44988.571429 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44988.571429 # average WriteReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17833.333333 # average SwapReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17833.333333 # average SwapReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38527.706371 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38527.706371 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38527.706371 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38527.706371 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 56473 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 53777 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 1278 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 50438 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 49675 # Number of BTB hits
+system.cpu1.branchPred.lookups 58259 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 55591 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 1274 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 52252 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 51480 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 98.487252 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 680 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.BTBHitPct 98.522545 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 650 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
-system.cpu1.numCycles 175078 # number of cpu cycles simulated
+system.cpu1.numCycles 176870 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 25485 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 320653 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 56473 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 50355 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 109933 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 3703 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles 25650 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.icacheStallCycles 24483 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 332703 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 58259 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 52130 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 112942 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 3669 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles 23224 # Number of cycles fetch has spent blocked
system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.NoActiveThreadStallCycles 6381 # Number of stall cycles due to no active thread to fetch from
-system.cpu1.fetch.PendingTrapStallCycles 795 # Number of stall cycles due to pending traps
-system.cpu1.fetch.CacheLines 16660 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 170597 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.879593 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.199930 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.NoActiveThreadStallCycles 7326 # Number of stall cycles due to no active thread to fetch from
+system.cpu1.fetch.PendingTrapStallCycles 755 # Number of stall cycles due to pending traps
+system.cpu1.fetch.CacheLines 15523 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 171052 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.945040 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.217476 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 60664 35.56% 35.56% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 55109 32.30% 67.86% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 4624 2.71% 70.57% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 3194 1.87% 72.45% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 685 0.40% 72.85% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 41191 24.15% 96.99% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1119 0.66% 97.65% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 783 0.46% 98.11% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 3228 1.89% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 58110 33.97% 33.97% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 56330 32.93% 66.90% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 4061 2.37% 69.28% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 3192 1.87% 71.14% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 642 0.38% 71.52% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 43436 25.39% 96.91% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1285 0.75% 97.66% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 751 0.44% 98.10% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 3245 1.90% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 170597 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.322559 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 1.831487 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 29160 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 23609 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 105420 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 3678 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 2349 # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts 317245 # Number of instructions handled by decode
-system.cpu1.rename.SquashCycles 2349 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 29851 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 11179 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 11654 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 102051 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 7132 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 315250 # Number of instructions processed by rename
-system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 41 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands 222317 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 613423 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 613423 # Number of integer rename lookups
-system.cpu1.rename.CommittedMaps 209500 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 12817 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 1100 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 1225 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 9565 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 91347 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 44397 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 43115 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 39365 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 263703 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 4783 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 264442 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 134 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 10738 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 10286 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 531 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 170597 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 1.550098 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.309842 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 171052 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.329389 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 1.881060 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 27575 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 21737 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 108940 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 3156 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 2318 # Number of cycles decode is squashing
+system.cpu1.decode.DecodedInsts 329200 # Number of instructions handled by decode
+system.cpu1.rename.SquashCycles 2318 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 28271 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 9057 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 11940 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 106039 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 6101 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 326983 # Number of instructions processed by rename
+system.cpu1.rename.LSQFullEvents 23 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands 231035 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 638817 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 638817 # Number of integer rename lookups
+system.cpu1.rename.CommittedMaps 218174 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 12861 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 1086 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 1205 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 8759 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 95375 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 46677 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 44840 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 41648 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 274055 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 4247 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 274319 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 86 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 10569 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 10360 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 496 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 171052 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 1.603717 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.300528 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 57935 33.96% 33.96% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 18114 10.62% 44.58% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 44440 26.05% 70.63% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 45139 26.46% 97.09% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 3372 1.98% 99.06% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1210 0.71% 99.77% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 275 0.16% 99.93% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 55274 32.31% 32.31% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 16462 9.62% 41.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 46955 27.45% 69.39% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 47561 27.80% 97.19% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 3274 1.91% 99.11% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1158 0.68% 99.78% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 257 0.15% 99.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 170597 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 171052 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 17 5.80% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.80% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 66 22.53% 28.33% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 210 71.67% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 17 6.05% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.05% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 54 19.22% 25.27% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 210 74.73% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 126483 47.83% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 94216 35.63% 83.46% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 43743 16.54% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 130533 47.58% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.58% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 97787 35.65% 83.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 45999 16.77% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 264442 # Type of FU issued
-system.cpu1.iq.rate 1.510424 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 293 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.001108 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 699908 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 279269 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 262662 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total 274319 # Type of FU issued
+system.cpu1.iq.rate 1.550964 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 281 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.001024 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 720057 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 288914 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 272470 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 264735 # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses 274600 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 39130 # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads 41423 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 2377 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2326 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1437 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 2349 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 1341 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 312497 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 345 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 91347 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 44397 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 1061 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 64 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles 2318 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 743 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 324068 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 389 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 95375 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 46677 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 1041 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 950 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 1409 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 263311 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 90404 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 1131 # Number of squashed instructions skipped in execute
+system.cpu1.iew.memOrderViolationEvents 43 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 463 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 924 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 1387 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 273134 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 94466 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1185 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 44011 # number of nop insts executed
-system.cpu1.iew.exec_refs 134069 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 53318 # Number of branches executed
-system.cpu1.iew.exec_stores 43665 # Number of stores executed
-system.cpu1.iew.exec_rate 1.503964 # Inst execution rate
-system.cpu1.iew.wb_sent 262943 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 262662 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 150856 # num instructions producing a value
-system.cpu1.iew.wb_consumers 155566 # num instructions consuming a value
+system.cpu1.iew.exec_nop 45766 # number of nop insts executed
+system.cpu1.iew.exec_refs 140389 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 55097 # Number of branches executed
+system.cpu1.iew.exec_stores 45923 # Number of stores executed
+system.cpu1.iew.exec_rate 1.544264 # Inst execution rate
+system.cpu1.iew.wb_sent 272765 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 272470 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 157153 # num instructions producing a value
+system.cpu1.iew.wb_consumers 161823 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 1.500257 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.969723 # average fanout of values written-back
+system.cpu1.iew.wb_rate 1.540510 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.971141 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 12295 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 4252 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 1278 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 161867 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 1.854590 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 2.083667 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 12117 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 3751 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 1274 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 161408 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 1.932674 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 2.096378 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 55765 34.45% 34.45% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 51311 31.70% 66.15% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 6076 3.75% 69.90% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 5204 3.21% 73.12% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1553 0.96% 74.08% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 39486 24.39% 98.47% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 647 0.40% 98.87% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 1002 0.62% 99.49% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 823 0.51% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 51564 31.95% 31.95% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 53244 32.99% 64.93% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 6086 3.77% 68.70% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 4696 2.91% 71.61% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1571 0.97% 72.59% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 41954 25.99% 98.58% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 476 0.29% 98.87% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 1001 0.62% 99.49% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 816 0.51% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 161867 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 300197 # Number of instructions committed
-system.cpu1.commit.committedOps 300197 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 161408 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 311949 # Number of instructions committed
+system.cpu1.commit.committedOps 311949 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 131930 # Number of memory references committed
-system.cpu1.commit.loads 88970 # Number of loads committed
-system.cpu1.commit.membars 3544 # Number of memory barriers committed
-system.cpu1.commit.branches 52469 # Number of branches committed
+system.cpu1.commit.refs 138308 # Number of memory references committed
+system.cpu1.commit.loads 93049 # Number of loads committed
+system.cpu1.commit.membars 3038 # Number of memory barriers committed
+system.cpu1.commit.branches 54264 # Number of branches committed
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 206526 # Number of committed integer instructions.
+system.cpu1.commit.int_insts 214693 # Number of committed integer instructions.
system.cpu1.commit.function_calls 322 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 823 # number cycles where commit BW limit reached
+system.cpu1.commit.bw_lim_events 816 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 472949 # The number of ROB reads
-system.cpu1.rob.rob_writes 627337 # The number of ROB writes
-system.cpu1.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 4481 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 36812 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 253388 # Number of Instructions Simulated
-system.cpu1.committedOps 253388 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 253388 # Number of Instructions Simulated
-system.cpu1.cpi 0.690948 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 0.690948 # CPI: Total CPI of All Threads
-system.cpu1.ipc 1.447286 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 1.447286 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 460976 # number of integer regfile reads
-system.cpu1.int_regfile_writes 214498 # number of integer regfile writes
+system.cpu1.rob.rob_reads 484071 # The number of ROB reads
+system.cpu1.rob.rob_writes 650455 # The number of ROB writes
+system.cpu1.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 5818 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 43818 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 263856 # Number of Instructions Simulated
+system.cpu1.committedOps 263856 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 263856 # Number of Instructions Simulated
+system.cpu1.cpi 0.670328 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 0.670328 # CPI: Total CPI of All Threads
+system.cpu1.ipc 1.491808 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 1.491808 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 479823 # number of integer regfile reads
+system.cpu1.int_regfile_writes 223101 # number of integer regfile writes
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 135647 # number of misc regfile reads
+system.cpu1.misc_regfile_reads 141972 # number of misc regfile reads
system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
system.cpu1.icache.replacements 317 # number of replacements
-system.cpu1.icache.tagsinuse 85.226466 # Cycle average of tags in use
-system.cpu1.icache.total_refs 16176 # Total number of references to valid blocks.
+system.cpu1.icache.tagsinuse 82.334562 # Cycle average of tags in use
+system.cpu1.icache.total_refs 15036 # Total number of references to valid blocks.
system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 38.061176 # Average number of references to valid blocks.
+system.cpu1.icache.avg_refs 35.378824 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 85.226466 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.166458 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.166458 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 16176 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 16176 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 16176 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 16176 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 16176 # number of overall hits
-system.cpu1.icache.overall_hits::total 16176 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 484 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 484 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 484 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 484 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 484 # number of overall misses
-system.cpu1.icache.overall_misses::total 484 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10452000 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 10452000 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 10452000 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 10452000 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 10452000 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 10452000 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 16660 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 16660 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 16660 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 16660 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 16660 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 16660 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029052 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.029052 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029052 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.029052 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029052 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.029052 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21595.041322 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 21595.041322 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21595.041322 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 21595.041322 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21595.041322 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 21595.041322 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 44 # number of cycles access was blocked
+system.cpu1.icache.occ_blocks::cpu1.inst 82.334562 # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst 0.160810 # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total 0.160810 # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst 15036 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 15036 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 15036 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 15036 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 15036 # number of overall hits
+system.cpu1.icache.overall_hits::total 15036 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 487 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 487 # number of ReadReq misses
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+system.cpu1.icache.demand_misses::total 487 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 487 # number of overall misses
+system.cpu1.icache.overall_misses::total 487 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 12109000 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 12109000 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 12109000 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 12109000 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 12109000 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 12109000 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 15523 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 15523 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 15523 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 15523 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 15523 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 15523 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.031373 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.031373 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.031373 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.031373 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.031373 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.031373 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24864.476386 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 24864.476386 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24864.476386 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 24864.476386 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24864.476386 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 24864.476386 # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs 84 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 59 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst 59 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst 59 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total 59 # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 62 # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst 62 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst 62 # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total 62 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 425 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 425 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 425 # number of overall MSHR misses
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system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1452501 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1452501 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 420000 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total 420000 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2798528 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 2798528 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2798528 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 2798528 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002923 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002923 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002390 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002390 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.835821 # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.835821 # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002678 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.002678 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002678 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.002678 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 8684.045161 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 8684.045161 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13449.083333 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13449.083333 # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7500 # average SwapReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7500 # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 10640.790875 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 10640.790875 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 10640.790875 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 10640.790875 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.branchPred.lookups 48435 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 45756 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 1281 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 42366 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 41626 # Number of BTB hits
+system.cpu2.branchPred.lookups 40256 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 37554 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 1244 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 34216 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 33404 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 98.253316 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 643 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.BTBHitPct 97.626841 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 656 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
-system.cpu2.numCycles 174747 # number of cpu cycles simulated
+system.cpu2.numCycles 176505 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 30691 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 266889 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 48435 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 42269 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 96584 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 3759 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles 36275 # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.NoActiveThreadStallCycles 6390 # Number of stall cycles due to no active thread to fetch from
-system.cpu2.fetch.PendingTrapStallCycles 712 # Number of stall cycles due to pending traps
-system.cpu2.fetch.CacheLines 22267 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples 173057 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.542203 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.085998 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles 35945 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 212693 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 40256 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 34060 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 82824 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 3666 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.BlockedCycles 45362 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.NoActiveThreadStallCycles 7326 # Number of stall cycles due to no active thread to fetch from
+system.cpu2.fetch.PendingTrapStallCycles 778 # Number of stall cycles due to pending traps
+system.cpu2.fetch.CacheLines 27473 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 251 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples 174585 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.218278 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 1.916616 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 76473 44.19% 44.19% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 49798 28.78% 72.96% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 7404 4.28% 77.24% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 3211 1.86% 79.10% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 674 0.39% 79.49% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 30262 17.49% 96.97% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 1242 0.72% 97.69% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 752 0.43% 98.13% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 3241 1.87% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 91761 52.56% 52.56% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 44191 25.31% 77.87% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 10007 5.73% 83.60% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 3161 1.81% 85.41% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 734 0.42% 85.83% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 19642 11.25% 97.09% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 1038 0.59% 97.68% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 777 0.45% 98.12% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 3274 1.88% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 173057 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.277172 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 1.527288 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 36897 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 31644 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 89441 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 6284 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 2401 # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts 263319 # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles 2401 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 37621 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 18625 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 12236 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 83428 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 12356 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 261093 # Number of instructions processed by rename
+system.cpu2.fetch.rateDist::total 174585 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.228073 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 1.205025 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 44684 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 38236 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 73287 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 8707 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 2345 # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts 209159 # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles 2345 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 45347 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 25711 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 11752 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 64880 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 17224 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 207132 # Number of instructions processed by rename
system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents 35 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands 181374 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 493566 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 493566 # Number of integer rename lookups
-system.cpu2.rename.CommittedMaps 168473 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 12901 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 1100 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 1220 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 15080 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 72313 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 33498 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 35025 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 28444 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 214608 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 7657 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 217768 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 130 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 10976 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 11107 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 637 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 173057 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.258360 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.300957 # Number of insts issued each cycle
+system.cpu2.rename.LSQFullEvents 18 # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenamedOperands 141115 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 375802 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 375802 # Number of integer rename lookups
+system.cpu2.rename.CommittedMaps 128666 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 12449 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 1089 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 1217 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 19740 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 53610 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 22854 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 26965 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 17848 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 166370 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 10183 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 172186 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 129 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 10670 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 10572 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 668 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 174585 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 0.986259 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.235789 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 74099 42.82% 42.82% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 26214 15.15% 57.97% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 33561 19.39% 77.36% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 34357 19.85% 97.21% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 3304 1.91% 99.12% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 1156 0.67% 99.79% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 256 0.15% 99.94% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 89355 51.18% 51.18% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 33684 19.29% 70.48% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 23026 13.19% 83.66% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 23727 13.59% 97.25% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 3246 1.86% 99.11% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 1164 0.67% 99.78% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 273 0.16% 99.94% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 173057 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 174585 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 17 5.65% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 74 24.58% 30.23% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 210 69.77% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 12 4.35% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 4.35% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 54 19.57% 23.91% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 210 76.09% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 107188 49.22% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.22% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 77805 35.73% 84.95% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 32775 15.05% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 88373 51.32% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 61586 35.77% 87.09% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 22227 12.91% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 217768 # Type of FU issued
-system.cpu2.iq.rate 1.246190 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 301 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.001382 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 609024 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 233287 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 215963 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.FU_type_0::total 172186 # Type of FU issued
+system.cpu2.iq.rate 0.975530 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 276 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.001603 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 519362 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 187269 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 170462 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 218069 # Number of integer alu accesses
+system.cpu2.iq.int_alu_accesses 172462 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 28178 # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.forwLoads 17592 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 2489 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 2439 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 1471 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedStores 1401 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 2401 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 915 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 258202 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 343 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 72313 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 33498 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 1067 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 66 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewSquashCycles 2345 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 684 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 40 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 204373 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 344 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 53610 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 22854 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 46 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 926 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 1391 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 216605 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 71227 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 1163 # Number of squashed instructions skipped in execute
+system.cpu2.iew.predictedTakenIncorrect 451 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 900 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 1351 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 171090 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 52536 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 1096 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 35937 # number of nop insts executed
-system.cpu2.iew.exec_refs 103922 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 45106 # Number of branches executed
-system.cpu2.iew.exec_stores 32695 # Number of stores executed
-system.cpu2.iew.exec_rate 1.239535 # Inst execution rate
-system.cpu2.iew.wb_sent 216253 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 215963 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 120625 # num instructions producing a value
-system.cpu2.iew.wb_consumers 125288 # num instructions consuming a value
+system.cpu2.iew.exec_nop 27820 # number of nop insts executed
+system.cpu2.iew.exec_refs 74679 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 36982 # Number of branches executed
+system.cpu2.iew.exec_stores 22143 # Number of stores executed
+system.cpu2.iew.exec_rate 0.969321 # Inst execution rate
+system.cpu2.iew.wb_sent 170734 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 170462 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 91387 # num instructions producing a value
+system.cpu2.iew.wb_consumers 96059 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 1.235861 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.962782 # average fanout of values written-back
+system.cpu2.iew.wb_rate 0.965763 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.951363 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 12625 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 7020 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 1281 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 164266 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.494880 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.964665 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 12267 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 9515 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 1244 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 164914 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.164777 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 1.788510 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 74448 45.32% 45.32% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 43200 26.30% 71.62% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 6076 3.70% 75.32% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 7927 4.83% 80.15% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 1577 0.96% 81.11% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 28745 17.50% 98.60% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 476 0.29% 98.89% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 1000 0.61% 99.50% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 817 0.50% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 91274 55.35% 55.35% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 35097 21.28% 76.63% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 6075 3.68% 80.31% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 10441 6.33% 86.64% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 1560 0.95% 87.59% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 18154 11.01% 98.60% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 495 0.30% 98.90% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 1006 0.61% 99.51% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 812 0.49% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 164266 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 245558 # Number of instructions committed
-system.cpu2.commit.committedOps 245558 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 164914 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 192088 # Number of instructions committed
+system.cpu2.commit.committedOps 192088 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 101851 # Number of memory references committed
-system.cpu2.commit.loads 69824 # Number of loads committed
-system.cpu2.commit.membars 6301 # Number of memory barriers committed
-system.cpu2.commit.branches 44289 # Number of branches committed
+system.cpu2.commit.refs 72624 # Number of memory references committed
+system.cpu2.commit.loads 51171 # Number of loads committed
+system.cpu2.commit.membars 8798 # Number of memory barriers committed
+system.cpu2.commit.branches 36206 # Number of branches committed
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 168258 # Number of committed integer instructions.
+system.cpu2.commit.int_insts 130952 # Number of committed integer instructions.
system.cpu2.commit.function_calls 322 # Number of function calls committed.
-system.cpu2.commit.bw_lim_events 817 # number cycles where commit BW limit reached
+system.cpu2.commit.bw_lim_events 812 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 421045 # The number of ROB reads
-system.cpu2.rob.rob_writes 518771 # The number of ROB writes
-system.cpu2.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 1690 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 37143 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 204183 # Number of Instructions Simulated
-system.cpu2.committedOps 204183 # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total 204183 # Number of Instructions Simulated
-system.cpu2.cpi 0.855835 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 0.855835 # CPI: Total CPI of All Threads
-system.cpu2.ipc 1.168449 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 1.168449 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 370277 # number of integer regfile reads
-system.cpu2.int_regfile_writes 173276 # number of integer regfile writes
+system.cpu2.rob.rob_reads 367870 # The number of ROB reads
+system.cpu2.rob.rob_writes 411061 # The number of ROB writes
+system.cpu2.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 1920 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 44183 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 156297 # Number of Instructions Simulated
+system.cpu2.committedOps 156297 # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total 156297 # Number of Instructions Simulated
+system.cpu2.cpi 1.129292 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 1.129292 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.885510 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.885510 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 282509 # number of integer regfile reads
+system.cpu2.int_regfile_writes 133289 # number of integer regfile writes
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 105484 # number of misc regfile reads
+system.cpu2.misc_regfile_reads 76201 # number of misc regfile reads
system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
-system.cpu2.icache.replacements 319 # number of replacements
-system.cpu2.icache.tagsinuse 83.493778 # Cycle average of tags in use
-system.cpu2.icache.total_refs 21789 # Total number of references to valid blocks.
-system.cpu2.icache.sampled_refs 430 # Sample count of references to valid blocks.
-system.cpu2.icache.avg_refs 50.672093 # Average number of references to valid blocks.
+system.cpu2.icache.replacements 318 # number of replacements
+system.cpu2.icache.tagsinuse 76.657940 # Cycle average of tags in use
+system.cpu2.icache.total_refs 26999 # Total number of references to valid blocks.
+system.cpu2.icache.sampled_refs 428 # Sample count of references to valid blocks.
+system.cpu2.icache.avg_refs 63.081776 # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.icache.occ_blocks::cpu2.inst 83.493778 # Average occupied blocks per requestor
-system.cpu2.icache.occ_percent::cpu2.inst 0.163074 # Average percentage of cache occupancy
-system.cpu2.icache.occ_percent::total 0.163074 # Average percentage of cache occupancy
-system.cpu2.icache.ReadReq_hits::cpu2.inst 21789 # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total 21789 # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst 21789 # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total 21789 # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst 21789 # number of overall hits
-system.cpu2.icache.overall_hits::total 21789 # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst 478 # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total 478 # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst 478 # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total 478 # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst 478 # number of overall misses
-system.cpu2.icache.overall_misses::total 478 # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6833500 # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total 6833500 # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst 6833500 # number of demand (read+write) miss cycles
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+system.cpu2.dcache.overall_miss_rate::total 0.008009 # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 11711.356467 # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total 11711.356467 # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20705.223881 # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::total 20705.223881 # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9870.370370 # average SwapReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::total 9870.370370 # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14383.592018 # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 14383.592018 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14383.592018 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 14383.592018 # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
-system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 246 # number of ReadReq MSHR hits
-system.cpu2.dcache.ReadReq_mshr_hits::total 246 # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 156 # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits::total 156 # number of ReadReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits
system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits
-system.cpu2.dcache.demand_mshr_hits::cpu2.data 279 # number of demand (read+write) MSHR hits
-system.cpu2.dcache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits::cpu2.data 279 # number of overall MSHR hits
-system.cpu2.dcache.overall_mshr_hits::total 279 # number of overall MSHR hits
+system.cpu2.dcache.demand_mshr_hits::cpu2.data 189 # number of demand (read+write) MSHR hits
+system.cpu2.dcache.demand_mshr_hits::total 189 # number of demand (read+write) MSHR hits
+system.cpu2.dcache.overall_mshr_hits::cpu2.data 189 # number of overall MSHR hits
+system.cpu2.dcache.overall_mshr_hits::total 189 # number of overall MSHR hits
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses
system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 54 # number of SwapReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses
system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses
system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses
system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses
system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1373500 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1373500 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1349000 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1349000 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 456000 # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total 456000 # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2722500 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total 2722500 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2722500 # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total 2722500 # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003741 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003741 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003161 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003161 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.794521 # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.794521 # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003494 # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total 0.003494 # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003494 # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total 0.003494 # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8531.055901 # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8531.055901 # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13356.435644 # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13356.435644 # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7862.068966 # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7862.068966 # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 10391.221374 # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 10391.221374 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 10391.221374 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 10391.221374 # average overall mshr miss latency
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1142519 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1142519 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1333500 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1333500 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 425000 # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::total 425000 # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2476019 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total 2476019 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2476019 # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total 2476019 # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004609 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004609 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.004724 # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.004724 # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.760563 # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.760563 # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004653 # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_miss_rate::total 0.004653 # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004653 # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_miss_rate::total 0.004653 # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 7096.391304 # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7096.391304 # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13202.970297 # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13202.970297 # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7870.370370 # average SwapReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7870.370370 # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9450.454198 # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9450.454198 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9450.454198 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9450.454198 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.branchPred.lookups 45379 # Number of BP lookups
-system.cpu3.branchPred.condPredicted 42609 # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect 1294 # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups 39317 # Number of BTB lookups
-system.cpu3.branchPred.BTBHits 38445 # Number of BTB hits
+system.cpu3.branchPred.lookups 52069 # Number of BP lookups
+system.cpu3.branchPred.condPredicted 49356 # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect 1283 # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups 46005 # Number of BTB lookups
+system.cpu3.branchPred.BTBHits 45233 # Number of BTB hits
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct 97.782130 # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS 651 # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.BTBHitPct 98.321922 # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS 642 # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
-system.cpu3.numCycles 174437 # number of cpu cycles simulated
+system.cpu3.numCycles 176161 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles 32466 # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts 246453 # Number of instructions fetch has processed
-system.cpu3.fetch.Branches 45379 # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches 39096 # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles 91198 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles 3791 # Number of cycles fetch has spent squashing
-system.cpu3.fetch.BlockedCycles 39692 # Number of cycles fetch has spent blocked
+system.cpu3.fetch.icacheStallCycles 28821 # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts 290359 # Number of instructions fetch has processed
+system.cpu3.fetch.Branches 52069 # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches 45875 # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles 102938 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles 3745 # Number of cycles fetch has spent squashing
+system.cpu3.fetch.BlockedCycles 32453 # Number of cycles fetch has spent blocked
system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.NoActiveThreadStallCycles 6399 # Number of stall cycles due to no active thread to fetch from
-system.cpu3.fetch.PendingTrapStallCycles 699 # Number of stall cycles due to pending traps
-system.cpu3.fetch.CacheLines 24152 # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples 172879 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean 1.425581 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev 2.034525 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.NoActiveThreadStallCycles 7327 # Number of stall cycles due to no active thread to fetch from
+system.cpu3.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps
+system.cpu3.fetch.CacheLines 20536 # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.rateDist::samples 174715 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 1.661901 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev 2.131946 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0 81681 47.25% 47.25% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1 47531 27.49% 74.74% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2 8280 4.79% 79.53% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3 3183 1.84% 81.37% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4 751 0.43% 81.81% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5 26265 15.19% 97.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6 1130 0.65% 97.65% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7 760 0.44% 98.09% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8 3298 1.91% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 71777 41.08% 41.08% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 52540 30.07% 71.15% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2 6531 3.74% 74.89% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3 3210 1.84% 76.73% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4 677 0.39% 77.12% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 34730 19.88% 97.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6 1243 0.71% 97.71% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7 745 0.43% 98.13% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8 3262 1.87% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total 172879 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate 0.260145 # Number of branch fetches per cycle
-system.cpu3.fetch.rate 1.412848 # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles 39667 # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles 34044 # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles 83244 # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles 7105 # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles 2420 # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts 242894 # Number of instructions handled by decode
-system.cpu3.rename.SquashCycles 2420 # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles 40390 # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles 21128 # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles 12127 # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles 76402 # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles 14013 # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts 240516 # Number of instructions processed by rename
-system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LSQFullEvents 44 # Number of times rename has blocked due to LSQ full
-system.cpu3.rename.RenamedOperands 166179 # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups 449032 # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups 449032 # Number of integer rename lookups
-system.cpu3.rename.CommittedMaps 153365 # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps 12814 # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts 1105 # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts 1221 # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts 16705 # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads 65194 # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores 29511 # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads 31885 # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores 24466 # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded 196370 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded 8514 # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued 200412 # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued 127 # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined 10978 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined 11006 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved 643 # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples 172879 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean 1.159262 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev 1.284832 # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total 174715 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate 0.295576 # Number of branch fetches per cycle
+system.cpu3.fetch.rate 1.648259 # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles 34404 # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles 28518 # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles 96588 # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles 5492 # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles 2386 # Number of cycles decode is squashing
+system.cpu3.decode.DecodedInsts 286754 # Number of instructions handled by decode
+system.cpu3.rename.SquashCycles 2386 # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles 35116 # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles 15951 # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles 11812 # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles 91334 # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles 10789 # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts 284513 # Number of instructions processed by rename
+system.cpu3.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LSQFullEvents 22 # Number of times rename has blocked due to LSQ full
+system.cpu3.rename.RenamedOperands 198512 # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups 543834 # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups 543834 # Number of integer rename lookups
+system.cpu3.rename.CommittedMaps 185460 # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps 13052 # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts 1098 # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts 1218 # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts 13448 # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads 80352 # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores 37945 # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads 38583 # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores 32886 # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded 235223 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded 6760 # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued 237671 # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined 10910 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined 10900 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved 576 # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples 174715 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean 1.360335 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev 1.308190 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0 79312 45.88% 45.88% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1 28822 16.67% 62.55% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2 29551 17.09% 79.64% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3 30339 17.55% 97.19% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4 3334 1.93% 99.12% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5 1154 0.67% 99.79% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6 261 0.15% 99.94% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7 49 0.03% 99.97% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0 69245 39.63% 39.63% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1 23718 13.58% 53.21% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2 38151 21.84% 75.04% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3 38808 22.21% 97.26% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4 3275 1.87% 99.13% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5 1152 0.66% 99.79% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6 254 0.15% 99.94% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total 172879 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total 174715 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu 12 4.07% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 4.07% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead 73 24.75% 28.81% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite 210 71.19% 100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu 17 5.94% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 5.94% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead 59 20.63% 26.57% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite 210 73.43% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu 100076 49.94% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.94% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead 71520 35.69% 85.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite 28816 14.38% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu 115348 48.53% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.53% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead 85085 35.80% 84.33% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite 37238 15.67% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total 200412 # Type of FU issued
-system.cpu3.iq.rate 1.148908 # Inst issue rate
-system.cpu3.iq.fu_busy_cnt 295 # FU busy when requested
-system.cpu3.iq.fu_busy_rate 0.001472 # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads 574125 # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes 215907 # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses 198595 # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.FU_type_0::total 237671 # Type of FU issued
+system.cpu3.iq.rate 1.349169 # Inst issue rate
+system.cpu3.iq.fu_busy_cnt 286 # FU busy when requested
+system.cpu3.iq.fu_busy_rate 0.001203 # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads 650461 # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes 252939 # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses 235820 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses 200707 # Number of integer alu accesses
+system.cpu3.iq.int_alu_accesses 237957 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads 24188 # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.forwLoads 32638 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads 2497 # Number of loads squashed
+system.cpu3.iew.lsq.thread0.squashedLoads 2448 # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores 1474 # Number of stores squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores 1468 # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles 2420 # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles 942 # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts 237691 # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts 354 # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts 65194 # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts 29511 # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts 1069 # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents 58 # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewSquashCycles 2386 # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles 609 # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts 281506 # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts 366 # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts 80352 # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts 37945 # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents 45 # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect 475 # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect 932 # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts 1407 # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts 199248 # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts 64095 # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts 1164 # Number of squashed instructions skipped in execute
+system.cpu3.iew.memOrderViolationEvents 46 # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect 925 # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts 1395 # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts 236476 # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts 79331 # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts 1195 # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp 0 # number of swp insts executed
-system.cpu3.iew.exec_nop 32807 # number of nop insts executed
-system.cpu3.iew.exec_refs 92831 # number of memory reference insts executed
-system.cpu3.iew.exec_branches 41971 # Number of branches executed
-system.cpu3.iew.exec_stores 28736 # Number of stores executed
-system.cpu3.iew.exec_rate 1.142235 # Inst execution rate
-system.cpu3.iew.wb_sent 198881 # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count 198595 # cumulative count of insts written-back
-system.cpu3.iew.wb_producers 109565 # num instructions producing a value
-system.cpu3.iew.wb_consumers 114222 # num instructions consuming a value
+system.cpu3.iew.exec_nop 39523 # number of nop insts executed
+system.cpu3.iew.exec_refs 116486 # number of memory reference insts executed
+system.cpu3.iew.exec_branches 48746 # Number of branches executed
+system.cpu3.iew.exec_stores 37155 # Number of stores executed
+system.cpu3.iew.exec_rate 1.342386 # Inst execution rate
+system.cpu3.iew.wb_sent 236114 # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count 235820 # cumulative count of insts written-back
+system.cpu3.iew.wb_producers 133214 # num instructions producing a value
+system.cpu3.iew.wb_consumers 137877 # num instructions consuming a value
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate 1.138491 # insts written-back per cycle
-system.cpu3.iew.wb_fanout 0.959229 # average fanout of values written-back
+system.cpu3.iew.wb_rate 1.338662 # insts written-back per cycle
+system.cpu3.iew.wb_fanout 0.966180 # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitSquashedInsts 12643 # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls 7871 # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts 1294 # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples 164060 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean 1.371620 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev 1.908371 # Number of insts commited each cycle
+system.cpu3.commit.commitSquashedInsts 12531 # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls 6184 # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts 1283 # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples 165002 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean 1.630011 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev 2.014402 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0 80528 49.08% 49.08% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1 40048 24.41% 73.50% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2 6110 3.72% 77.22% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3 8758 5.34% 82.56% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4 1552 0.95% 83.50% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5 24728 15.07% 98.58% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6 520 0.32% 98.89% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7 1010 0.62% 99.51% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8 806 0.49% 100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0 67849 41.12% 41.12% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1 46915 28.43% 69.55% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2 6084 3.69% 73.24% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3 7112 4.31% 77.55% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4 1576 0.96% 78.51% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5 33196 20.12% 98.62% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6 454 0.28% 98.90% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7 1000 0.61% 99.51% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8 816 0.49% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total 164060 # Number of insts commited each cycle
-system.cpu3.commit.committedInsts 225028 # Number of instructions committed
-system.cpu3.commit.committedOps 225028 # Number of ops (including micro ops) committed
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+system.cpu3.commit.committedInsts 268955 # Number of instructions committed
+system.cpu3.commit.committedOps 268955 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu3.commit.refs 90734 # Number of memory references committed
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-system.cpu3.commit.membars 7153 # Number of memory barriers committed
-system.cpu3.commit.branches 41151 # Number of branches committed
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system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu3.commit.int_insts 154003 # Number of committed integer instructions.
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system.cpu3.commit.function_calls 322 # Number of function calls committed.
-system.cpu3.commit.bw_lim_events 806 # number cycles where commit BW limit reached
+system.cpu3.commit.bw_lim_events 816 # number cycles where commit BW limit reached
system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu3.rob.rob_reads 400338 # The number of ROB reads
-system.cpu3.rob.rob_writes 477767 # The number of ROB writes
-system.cpu3.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles 1558 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles 37453 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts 185938 # Number of Instructions Simulated
-system.cpu3.committedOps 185938 # Number of Ops (including micro ops) Simulated
-system.cpu3.committedInsts_total 185938 # Number of Instructions Simulated
-system.cpu3.cpi 0.938146 # CPI: Cycles Per Instruction
-system.cpu3.cpi_total 0.938146 # CPI: Total CPI of All Threads
-system.cpu3.ipc 1.065932 # IPC: Instructions Per Cycle
-system.cpu3.ipc_total 1.065932 # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads 337021 # number of integer regfile reads
-system.cpu3.int_regfile_writes 158120 # number of integer regfile writes
+system.cpu3.rob.rob_reads 445085 # The number of ROB reads
+system.cpu3.rob.rob_writes 565364 # The number of ROB writes
+system.cpu3.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles 1446 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles 44527 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts 224789 # Number of Instructions Simulated
+system.cpu3.committedOps 224789 # Number of Ops (including micro ops) Simulated
+system.cpu3.committedInsts_total 224789 # Number of Instructions Simulated
+system.cpu3.cpi 0.783673 # CPI: Cycles Per Instruction
+system.cpu3.cpi_total 0.783673 # CPI: Total CPI of All Threads
+system.cpu3.ipc 1.276043 # IPC: Instructions Per Cycle
+system.cpu3.ipc_total 1.276043 # IPC: Total IPC of All Threads
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system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu3.misc_regfile_reads 94371 # number of misc regfile reads
+system.cpu3.misc_regfile_reads 118055 # number of misc regfile reads
system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
-system.cpu3.icache.replacements 318 # number of replacements
-system.cpu3.icache.tagsinuse 80.241223 # Cycle average of tags in use
-system.cpu3.icache.total_refs 23677 # Total number of references to valid blocks.
-system.cpu3.icache.sampled_refs 429 # Sample count of references to valid blocks.
-system.cpu3.icache.avg_refs 55.191142 # Average number of references to valid blocks.
+system.cpu3.icache.replacements 319 # number of replacements
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system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu3.icache.occ_percent::total 0.156721 # Average percentage of cache occupancy
-system.cpu3.icache.ReadReq_hits::cpu3.inst 23677 # number of ReadReq hits
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-system.cpu3.icache.overall_hits::total 23677 # number of overall hits
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-system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses
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-system.cpu3.icache.overall_misses::total 475 # number of overall misses
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-system.cpu3.icache.ReadReq_miss_latency::total 6195500 # number of ReadReq miss cycles
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-system.cpu3.icache.demand_miss_latency::total 6195500 # number of demand (read+write) miss cycles
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-system.cpu3.icache.overall_miss_latency::total 6195500 # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst 24152 # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total 24152 # number of ReadReq accesses(hits+misses)
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-system.cpu3.icache.demand_accesses::total 24152 # number of demand (read+write) accesses
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-system.cpu3.icache.ReadReq_miss_rate::total 0.019667 # miss rate for ReadReq accesses
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-system.cpu3.icache.demand_miss_rate::total 0.019667 # miss rate for demand accesses
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-system.cpu3.icache.ReadReq_avg_miss_latency::total 13043.157895 # average ReadReq miss latency
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-system.cpu3.icache.demand_avg_miss_latency::total 13043.157895 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13043.157895 # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 13043.157895 # average overall miss latency
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+system.cpu3.icache.overall_miss_latency::total 6428500 # number of overall miss cycles
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+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13476.939203 # average overall miss latency
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system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.cache_copies 0 # number of cache copies performed
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-system.cpu3.icache.overall_mshr_hits::total 46 # number of overall MSHR hits
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-system.cpu3.icache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses
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-system.cpu3.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses
-system.cpu3.icache.overall_mshr_misses::cpu3.inst 429 # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_misses::total 429 # number of overall MSHR misses
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-system.cpu3.icache.ReadReq_mshr_miss_latency::total 4977500 # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4977500 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total 4977500 # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4977500 # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total 4977500 # number of overall MSHR miss cycles
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-system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017763 # mshr miss rate for ReadReq accesses
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-system.cpu3.icache.demand_mshr_miss_rate::total 0.017763 # mshr miss rate for demand accesses
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-system.cpu3.icache.overall_mshr_miss_rate::total 0.017763 # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11602.564103 # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11602.564103 # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11602.564103 # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 11602.564103 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11602.564103 # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 11602.564103 # average overall mshr miss latency
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+system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5181004 # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::total 5181004 # number of demand (read+write) MSHR miss cycles
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+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12048.846512 # average overall mshr miss latency
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system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.dcache.replacements 0 # number of replacements
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system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks.
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+system.cpu3.dcache.avg_refs 1517.535714 # Average number of references to valid blocks.
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu3.dcache.ReadReq_hits::total 39468 # number of ReadReq hits
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-system.cpu3.dcache.WriteReq_hits::total 27827 # number of WriteReq hits
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-system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits
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-system.cpu3.dcache.demand_hits::total 67295 # number of demand (read+write) hits
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-system.cpu3.dcache.overall_hits::total 67295 # number of overall hits
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-system.cpu3.dcache.ReadReq_misses::total 421 # number of ReadReq misses
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+system.cpu3.dcache.ReadReq_hits::total 46335 # number of ReadReq hits
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+system.cpu3.dcache.WriteReq_hits::total 36269 # number of WriteReq hits
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+system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits
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+system.cpu3.dcache.overall_hits::total 82604 # number of overall hits
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system.cpu3.dcache.WriteReq_misses::cpu3.data 138 # number of WriteReq misses
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system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.l2c.replacements 0 # number of replacements
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+system.l2c.demand_mshr_miss_rate::cpu2.inst 0.007009 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.311792 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for overall accesses
+system.l2c.demand_mshr_miss_rate::total 0.311762 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.183529 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst 0.018605 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst 0.007009 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst 0.013953 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.311792 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 38447.729050 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 49906 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40372.589744 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82608 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 39469.625000 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56251 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 37917.666667 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56251 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40993.700000 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10222.777778 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10050.900000 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10118.411765 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10553.368421 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10237.229730 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 45181.468085 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64596.538462 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60000.833333 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50709.166667 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 48972.007634 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38447.729050 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47262.511905 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40372.589744 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70900.550000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 39469.625000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 37917.666667 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51135.461538 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 42574.877458 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38447.729050 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47262.511905 # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70900.550000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 39469.625000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 37917.666667 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51135.461538 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 42574.877458 # average overall mshr miss latency
+system.l2c.overall_mshr_miss_rate::total 0.311762 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 54942.577031 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61550.675676 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58906.250000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62250 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 60583.333333 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 76250 # average ReadReq mshr miss latency
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 76250 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 56749.527410 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10563.437500 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10120.986667 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66630.319149 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65711.538462 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62937.500000 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 58604.166667 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 65465.648855 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 54942.577031 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64392.857143 # average overall mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64500 # average overall mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63961.538462 # average overall mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 59961.538462 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 58479.545455 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 54942.577031 # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60583.333333 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63961.538462 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 61458.333333 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 59961.538462 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 58479.545455 # average overall mshr miss latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 87707000 # Number of ticks simulated
final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 205117 # Simulator instruction rate (inst/s)
-host_op_rate 205116 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 26560282 # Simulator tick rate (ticks/s)
-host_mem_usage 1206900 # Number of bytes of host memory used
-host_seconds 3.30 # Real time elapsed on the host
+host_inst_rate 1256528 # Simulator instruction rate (inst/s)
+host_op_rate 1256465 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 162691956 # Simulator tick rate (ticks/s)
+host_mem_usage 1160656 # Number of bytes of host memory used
+host_seconds 0.54 # Real time elapsed on the host
sim_insts 677327 # Number of instructions simulated
sim_ops 677327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory
system.physmem.bw_total::cpu3.inst 1459405 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 407903588 # Throughput (bytes/s)
+system.membus.data_through_bus 35776 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.toL2Bus.throughput 1893577480 # Throughput (bytes/s)
+system.toL2Bus.data_through_bus 166080 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu0.workload.num_syscalls 89 # Number of system calls
system.cpu0.numCycles 175415 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
---------- Begin Simulation Statistics ----------
sim_seconds 0.000263 # Number of seconds simulated
-sim_ticks 262970500 # Number of ticks simulated
-final_tick 262970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 262793500 # Number of ticks simulated
+final_tick 262793500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 110323 # Simulator instruction rate (inst/s)
-host_op_rate 110323 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 43749084 # Simulator tick rate (ticks/s)
-host_mem_usage 287188 # Number of bytes of host memory used
-host_seconds 6.01 # Real time elapsed on the host
-sim_insts 663135 # Number of instructions simulated
-sim_ops 663135 # Number of ops (including micro ops) simulated
+host_inst_rate 1490059 # Simulator instruction rate (inst/s)
+host_op_rate 1490014 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 590046557 # Simulator tick rate (ticks/s)
+host_mem_usage 244196 # Number of bytes of host memory used
+host_seconds 0.45 # Real time elapsed on the host
+sim_insts 663601 # Number of instructions simulated
+sim_ops 663601 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 4224 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 1472 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst 512 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory
system.physmem.bytes_read::total 36608 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 4224 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst 512 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 66 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 23 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory
system.physmem.num_reads::total 572 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 69361392 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 40156596 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 16062638 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 5597586 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 486747 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 3650600 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 243373 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 3650600 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 139209531 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 69361392 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 16062638 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 486747 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 243373 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 86154150 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 69361392 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 40156596 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 16062638 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 5597586 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 486747 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 3650600 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 243373 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 3650600 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 139209531 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 69408109 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 40183642 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 14368696 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 5357819 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 487074 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 3653058 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 1948298 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 3896596 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 139303293 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 69408109 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 14368696 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 487074 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 1948298 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 86212178 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 69408109 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 40183642 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 14368696 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 5357819 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 487074 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 3653058 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 1948298 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 3896596 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 139303293 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 139303293 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 430 # Transaction distribution
+system.membus.trans_dist::ReadResp 430 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 272 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 77 # Transaction distribution
+system.membus.trans_dist::ReadExReq 208 # Transaction distribution
+system.membus.trans_dist::ReadExResp 142 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side 1559 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 1559 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side 36608 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 36608 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 36608 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 855296 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
+system.membus.respLayer0.occupancy 5423500 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 2.1 # Layer utilization (%)
+system.toL2Bus.throughput 646591335 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 934 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 580 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 732 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 388 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side 732 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side 359 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side 734 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side 361 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count 4820 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 29888 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 10944 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 23424 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 1664 # Cumulative packet size per connected master and slave (bytes)
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-system.cpu0.dcache.ReadReq_avg_miss_latency::total 27388.888889 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38301.630435 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 38301.630435 # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14019.230769 # average SwapReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::total 14019.230769 # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33045.070423 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 33045.070423 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33045.070423 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 33045.070423 # average overall miss latency
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+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26955.882353 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 26955.882353 # average ReadReq miss latency
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+system.cpu0.dcache.SwapReq_avg_miss_latency::total 13865.384615 # average SwapReq miss latency
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+system.cpu0.dcache.demand_avg_miss_latency::total 32749.291785 # average overall miss latency
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+system.cpu0.dcache.overall_avg_miss_latency::total 32749.291785 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 171 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 171 # number of ReadReq MSHR misses
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-system.cpu0.dcache.WriteReq_mshr_misses::total 184 # number of WriteReq MSHR misses
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system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses
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-system.cpu0.dcache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses
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-system.cpu0.dcache.overall_mshr_misses::total 355 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4341500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4341500 # number of ReadReq MSHR miss cycles
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-system.cpu0.dcache.demand_mshr_miss_latency::total 11021000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11021000 # number of overall MSHR miss cycles
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-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003490 # mshr miss rate for ReadReq accesses
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system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
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-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36301.630435 # average WriteReq mshr miss latency
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-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12019.230769 # average SwapReq mshr miss latency
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-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31045.070423 # average overall mshr miss latency
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+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30735.181303 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.numCycles 525940 # number of cpu cycles simulated
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system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 166746 # Number of instructions committed
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+system.cpu1.committedInsts 173389 # Number of instructions committed
+system.cpu1.committedOps 173389 # Number of ops (including micro ops) committed
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system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 637 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 32184 # number of instructions that are conditional controls
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system.cpu1.num_fp_insts 0 # number of float instructions
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system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
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-system.cpu1.num_load_insts 40871 # Number of load instructions
-system.cpu1.num_store_insts 13517 # Number of store instructions
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-system.cpu1.num_busy_cycles 456603.130098 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.868166 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.131834 # Percentage of idle cycles
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system.cpu1.icache.replacements 280 # number of replacements
-system.cpu1.icache.tagsinuse 70.021877 # Cycle average of tags in use
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system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 454.680328 # Average number of references to valid blocks.
+system.cpu1.icache.avg_refs 472.830601 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses
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system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses
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-system.cpu1.icache.demand_avg_miss_latency::total 20669.398907 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20669.398907 # average overall miss latency
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system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
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system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
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-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18669.398907 # average ReadReq mshr miss latency
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-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18669.398907 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 18669.398907 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18669.398907 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 18669.398907 # average overall mshr miss latency
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+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18597.024590 # average ReadReq mshr miss latency
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+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18597.024590 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 18597.024590 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 0 # number of replacements
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-system.cpu1.dcache.total_refs 29411 # Total number of references to valid blocks.
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system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 980.366667 # Average number of references to valid blocks.
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system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu1.dcache.occ_percent::total 0.054075 # Average percentage of cache occupancy
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-system.cpu1.dcache.ReadReq_misses::total 153 # number of ReadReq misses
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-system.cpu1.dcache.overall_miss_latency::total 4916500 # number of overall miss cycles
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-system.cpu1.dcache.demand_avg_miss_latency::total 18982.625483 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18982.625483 # average overall miss latency
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+system.cpu1.dcache.SwapReq_avg_miss_latency::total 4338.461538 # average SwapReq miss latency
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+system.cpu1.dcache.demand_avg_miss_latency::total 19802.158273 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19802.158273 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 19802.158273 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 153 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses
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system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
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-system.cpu1.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses
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-system.cpu1.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses
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-system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2648500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2648500 # number of ReadReq MSHR miss cycles
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-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1750000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 174000 # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total 174000 # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4398500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 4398500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4398500 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 4398500 # number of overall MSHR miss cycles
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-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003744 # mshr miss rate for ReadReq accesses
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-system.cpu1.dcache.demand_mshr_miss_rate::total 0.004769 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004769 # mshr miss rate for overall accesses
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-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17310.457516 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17310.457516 # average ReadReq mshr miss latency
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-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16509.433962 # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3480 # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3480 # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16982.625483 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16982.625483 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16982.625483 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16982.625483 # average overall mshr miss latency
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+system.cpu1.dcache.SwapReq_mshr_misses::total 65 # number of SwapReq MSHR misses
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+system.cpu1.dcache.overall_mshr_misses::total 278 # number of overall MSHR misses
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+system.cpu1.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles
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+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17282.203488 # average ReadReq mshr miss latency
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+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17750.140288 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17750.140288 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17750.140288 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.numCycles 525941 # number of cpu cycles simulated
+system.cpu2.numCycles 525587 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.committedInsts 169995 # Number of instructions committed
-system.cpu2.committedOps 169995 # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses 110917 # Number of integer alu accesses
+system.cpu2.committedInsts 164870 # Number of instructions committed
+system.cpu2.committedOps 164870 # Number of ops (including micro ops) committed
+system.cpu2.num_int_alu_accesses 112982 # Number of integer alu accesses
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+system.cpu2.dcache.WriteReq_miss_rate::total 0.006424 # miss rate for WriteReq accesses
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+system.cpu2.dcache.SwapReq_miss_rate::total 0.838710 # miss rate for SwapReq accesses
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+system.cpu2.dcache.ReadReq_avg_miss_latency::total 13518.987342 # average ReadReq miss latency
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+system.cpu2.dcache.WriteReq_avg_miss_latency::total 17674.311927 # average WriteReq miss latency
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+system.cpu2.dcache.SwapReq_avg_miss_latency::total 4115.384615 # average SwapReq miss latency
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+system.cpu2.dcache.demand_avg_miss_latency::total 15215.355805 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15215.355805 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 15215.355805 # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 157 # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses
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-system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
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-system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses
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-system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses
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-system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses
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-system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2440500 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1704500 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1704500 # number of WriteReq MSHR miss cycles
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-system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003818 # mshr miss rate for ReadReq accesses
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-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15544.585987 # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16233.333333 # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16233.333333 # average WriteReq mshr miss latency
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-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3607.843137 # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 15820.610687 # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 15820.610687 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 15820.610687 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 15820.610687 # average overall mshr miss latency
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+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13192.936330 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.numCycles 525940 # number of cpu cycles simulated
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system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.committedInsts 167814 # Number of instructions committed
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+system.cpu3.committedInsts 166768 # Number of instructions committed
+system.cpu3.committedOps 166768 # Number of ops (including micro ops) committed
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system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu3.num_func_calls 637 # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts 32222 # number of instructions that are conditional controls
-system.cpu3.num_int_insts 111369 # number of integer instructions
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system.cpu3.num_fp_insts 0 # number of float instructions
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system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu3.num_mem_refs 55316 # number of memory refs
-system.cpu3.num_load_insts 41342 # Number of load instructions
-system.cpu3.num_store_insts 13974 # Number of store instructions
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-system.cpu3.num_busy_cycles 456095.131066 # Number of busy cycles
-system.cpu3.not_idle_fraction 0.867200 # Percentage of non-idle cycles
-system.cpu3.idle_fraction 0.132800 # Percentage of idle cycles
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system.cpu3.icache.replacements 281 # number of replacements
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system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks.
-system.cpu3.icache.avg_refs 456.348774 # Average number of references to valid blocks.
+system.cpu3.icache.avg_refs 453.498638 # Average number of references to valid blocks.
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.occ_blocks::cpu3.inst 67.672766 # Average occupied blocks per requestor
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system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses
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system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses
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+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14029.972752 # average overall miss latency
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system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses
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system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses
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-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12065.395095 # average ReadReq mshr miss latency
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-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12065.395095 # average overall mshr miss latency
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-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12065.395095 # average overall mshr miss latency
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+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12028.613079 # average overall mshr miss latency
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system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks.
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system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
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system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.replacements 0 # number of replacements
-system.l2c.tagsinuse 349.061652 # Cycle average of tags in use
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 7257449 # Number of ticks simulated
final_tick 7257449 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
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sim_ticks 7481441 # Number of ticks simulated
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sim_freq 1000000000 # Frequency of simulated ticks
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sim_ticks 6151475 # Number of ticks simulated
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sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 46771 # Simulator tick rate (ticks/s)
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+system.funcbus.data_through_bus 0 # Total data (bytes)
system.ruby.l1_cntrl4.L1Dcache.demand_hits 20 # Number of cache demand hits
system.ruby.l1_cntrl4.L1Dcache.demand_misses 76947 # Number of cache demand misses
system.ruby.l1_cntrl4.L1Dcache.demand_accesses 76967 # Number of cache demand accesses
sim_ticks 5795833 # Number of ticks simulated
final_tick 5795833 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 45179 # Simulator tick rate (ticks/s)
-host_mem_usage 298344 # Number of bytes of host memory used
-host_seconds 128.29 # Real time elapsed on the host
+host_tick_rate 39688 # Simulator tick rate (ticks/s)
+host_mem_usage 251648 # Number of bytes of host memory used
+host_seconds 146.03 # Real time elapsed on the host
+system.funcbus.throughput 0 # Throughput (bytes/s)
+system.funcbus.data_through_bus 0 # Total data (bytes)
system.ruby.l1_cntrl4.L1Dcache.demand_hits 14 # Number of cache demand hits
system.ruby.l1_cntrl4.L1Dcache.demand_misses 77212 # Number of cache demand misses
system.ruby.l1_cntrl4.L1Dcache.demand_accesses 77226 # Number of cache demand accesses
sim_ticks 8664886 # Number of ticks simulated
final_tick 8664886 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 174865 # Simulator tick rate (ticks/s)
-host_mem_usage 297912 # Number of bytes of host memory used
-host_seconds 49.55 # Real time elapsed on the host
+host_tick_rate 321644 # Simulator tick rate (ticks/s)
+host_mem_usage 252216 # Number of bytes of host memory used
+host_seconds 26.94 # Real time elapsed on the host
+system.funcbus.throughput 0 # Throughput (bytes/s)
+system.funcbus.data_through_bus 0 # Total data (bytes)
system.ruby.l1_cntrl4.cacheMemory.demand_hits 0 # Number of cache demand hits
system.ruby.l1_cntrl4.cacheMemory.demand_misses 77331 # Number of cache demand misses
system.ruby.l1_cntrl4.cacheMemory.demand_accesses 77331 # Number of cache demand accesses
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000761 # Number of seconds simulated
-sim_ticks 761435500 # Number of ticks simulated
-final_tick 761435500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000650 # Number of seconds simulated
+sim_ticks 649827000 # Number of ticks simulated
+final_tick 649827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 112752764 # Simulator tick rate (ticks/s)
-host_mem_usage 399024 # Number of bytes of host memory used
-host_seconds 6.75 # Real time elapsed on the host
-system.physmem.bytes_read::cpu0 92287 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 88521 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 93126 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 92216 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 93858 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 91205 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 94911 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 89917 # Number of bytes read from this memory
-system.physmem.bytes_read::total 736041 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 486336 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5427 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5222 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5377 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5288 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5289 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5451 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5508 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5340 # Number of bytes written to this memory
-system.physmem.bytes_written::total 529238 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 11206 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 11157 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 11163 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 11261 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 11265 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 11258 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 11247 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 11104 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 89661 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 7599 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5427 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5222 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5377 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5288 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5289 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5451 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5508 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5340 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 50501 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 121201336 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 116255415 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 122303202 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 121108091 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 123264544 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 119780336 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 124647459 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 118088794 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 966649178 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 638709385 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 7127327 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 6858099 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 7061662 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 6944777 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 6946091 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 7158847 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 7233705 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 7013069 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 695052962 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 638709385 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 128328663 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 123113514 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 129364864 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 128052869 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 130210635 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 126939183 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 131881164 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 125101864 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1661702140 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 15611 # number of replacements
-system.l2c.tagsinuse 803.524746 # Cycle average of tags in use
-system.l2c.total_refs 152738 # Total number of references to valid blocks.
-system.l2c.sampled_refs 16409 # Sample count of references to valid blocks.
-system.l2c.avg_refs 9.308185 # Average number of references to valid blocks.
+host_tick_rate 87337651 # Simulator tick rate (ticks/s)
+host_mem_usage 355516 # Number of bytes of host memory used
+host_seconds 7.44 # Real time elapsed on the host
+system.physmem.bytes_read::cpu0 81682 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1 82403 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2 82634 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3 80397 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4 83903 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5 81493 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6 81053 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7 80348 # Number of bytes read from this memory
+system.physmem.bytes_read::total 653913 # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks 411392 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0 5392 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1 5164 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2 5249 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3 5478 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4 5343 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5 5429 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6 5380 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7 5399 # Number of bytes written to this memory
+system.physmem.bytes_written::total 454226 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0 10933 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1 11024 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2 11066 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3 11034 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4 11012 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5 10870 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6 10997 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7 10859 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 87795 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 6428 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0 5392 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1 5164 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2 5249 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3 5478 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4 5343 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5 5429 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6 5380 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7 5399 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 49262 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0 125698070 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1 126807596 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2 127163076 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3 123720621 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4 129115903 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5 125407224 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6 124730120 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7 123645216 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1006287827 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 633079266 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0 8297593 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1 7946730 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2 8077534 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3 8429936 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4 8222188 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5 8354531 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6 8279127 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7 8308365 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 698995271 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 633079266 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0 133995663 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1 134754327 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2 135240610 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3 132150557 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4 137338092 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5 133761755 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6 133009247 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7 131953581 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1705283098 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 1705280021 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 84626 # Transaction distribution
+system.membus.trans_dist::ReadResp 84624 # Transaction distribution
+system.membus.trans_dist::WriteReq 42834 # Transaction distribution
+system.membus.trans_dist::WriteResp 42832 # Transaction distribution
+system.membus.trans_dist::Writeback 6428 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 56782 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 46322 # Transaction distribution
+system.membus.trans_dist::ReadExReq 48493 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3169 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side 416110 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 416110 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side 1108137 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 1108137 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 1108137 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.reqLayer0.occupancy 287607668 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 44.3 # Layer utilization (%)
+system.membus.respLayer0.occupancy 310731500 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 47.8 # Layer utilization (%)
+system.l2c.replacements 13443 # number of replacements
+system.l2c.tagsinuse 785.847638 # Cycle average of tags in use
+system.l2c.total_refs 148477 # Total number of references to valid blocks.
+system.l2c.sampled_refs 14254 # Sample count of references to valid blocks.
+system.l2c.avg_refs 10.416515 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 740.398086 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0 7.878873 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1 7.659983 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2 8.123766 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3 7.474129 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu4 8.226019 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu5 8.053219 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu6 8.543884 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu7 7.166787 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.723045 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0 0.007694 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1 0.007480 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2 0.007933 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu3 0.007299 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu4 0.008033 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu5 0.007864 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu6 0.008344 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu7 0.006999 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.784692 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0 10900 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1 10939 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2 10998 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3 10816 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu4 11039 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu5 10812 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu6 11089 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu7 11073 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 87666 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 77271 # number of Writeback hits
-system.l2c.Writeback_hits::total 77271 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0 347 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1 357 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2 381 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3 350 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4 354 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5 346 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6 406 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7 354 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 2895 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0 1978 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1 2136 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2 2005 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3 1996 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu4 1979 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu5 2046 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu6 2087 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu7 2088 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 16315 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0 12878 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1 13075 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2 13003 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3 12812 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu4 13018 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu5 12858 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu6 13176 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu7 13161 # number of demand (read+write) hits
-system.l2c.demand_hits::total 103981 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0 12878 # number of overall hits
-system.l2c.overall_hits::cpu1 13075 # number of overall hits
-system.l2c.overall_hits::cpu2 13003 # number of overall hits
-system.l2c.overall_hits::cpu3 12812 # number of overall hits
-system.l2c.overall_hits::cpu4 13018 # number of overall hits
-system.l2c.overall_hits::cpu5 12858 # number of overall hits
-system.l2c.overall_hits::cpu6 13176 # number of overall hits
-system.l2c.overall_hits::cpu7 13161 # number of overall hits
-system.l2c.overall_hits::total 103981 # number of overall hits
-system.l2c.ReadReq_misses::cpu0 842 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1 806 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2 858 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3 816 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu4 872 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu5 849 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu6 881 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu7 820 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 6744 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0 1862 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1 1924 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2 1971 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3 1858 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu4 1932 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu5 1882 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu6 1937 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu7 1981 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 15347 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0 4273 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1 4353 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2 4268 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3 4257 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu4 4400 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu5 4320 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu6 4282 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu7 4210 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 34363 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0 5115 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1 5159 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2 5126 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3 5073 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu4 5272 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu5 5169 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu6 5163 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu7 5030 # number of demand (read+write) misses
-system.l2c.demand_misses::total 41107 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0 5115 # number of overall misses
-system.l2c.overall_misses::cpu1 5159 # number of overall misses
-system.l2c.overall_misses::cpu2 5126 # number of overall misses
-system.l2c.overall_misses::cpu3 5073 # number of overall misses
-system.l2c.overall_misses::cpu4 5272 # number of overall misses
-system.l2c.overall_misses::cpu5 5169 # number of overall misses
-system.l2c.overall_misses::cpu6 5163 # number of overall misses
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.num_reads 99397 # number of read accesses completed
-system.cpu0.num_writes 53728 # number of write accesses completed
+system.funcbus.throughput 0 # Throughput (bytes/s)
+system.funcbus.data_through_bus 0 # Total data (bytes)
+system.toL2Bus.throughput 51050793519 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 365486 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 365476 # Transaction distribution
+system.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 42834 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 42830 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 73993 # Transaction distribution
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+system.toL2Bus.trans_dist::ReadExResp 155781 # Transaction distribution
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+system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side 1725043 # Cumulative packet size per connected master and slave (bytes)
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+system.toL2Bus.tot_pkt_size 13854312 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 13854312 # Total data (bytes)
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system.cpu0.num_copies 0 # number of copy accesses completed
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system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
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+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28424.944749 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28424.944749 # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.num_copies 0 # number of copy accesses completed
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-system.cpu1.l1c.avg_refs 0.596120 # Average number of references to valid blocks.
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system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu1.l1c.demand_avg_miss_latency::total 41297.433119 # average overall miss latency
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system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu1.l1c.demand_mshr_miss_latency::total 2311207435 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2311207435 # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total 2311207435 # number of overall MSHR miss cycles
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-system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1137526156 # number of overall MSHR uncacheable cycles
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-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 35248.022435 # average ReadReq mshr miss latency
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-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 39297.560658 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 39297.560658 # average overall mshr miss latency
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+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28387.789739 # average overall mshr miss latency
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system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu2.num_writes 53724 # number of write accesses completed
+system.cpu2.num_reads 100000 # number of read accesses completed
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system.cpu2.num_copies 0 # number of copy accesses completed
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-system.cpu2.l1c.avg_refs 0.586044 # Average number of references to valid blocks.
+system.cpu2.l1c.replacements 22360 # number of replacements
+system.cpu2.l1c.tagsinuse 394.888678 # Cycle average of tags in use
+system.cpu2.l1c.total_refs 13327 # Total number of references to valid blocks.
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system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.occ_blocks::cpu2 395.972858 # Average occupied blocks per requestor
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-system.cpu2.l1c.occ_percent::total 0.773384 # Average percentage of cache occupancy
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-system.cpu2.l1c.ReadReq_hits::total 8816 # number of ReadReq hits
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-system.cpu2.l1c.overall_avg_miss_latency::cpu2 41052.740978 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 41052.740978 # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs 1437012 # number of cycles access was blocked
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+system.cpu2.l1c.ReadReq_avg_miss_latency::total 26184.962616 # average ReadReq miss latency
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system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu2.l1c.writebacks::total 9964 # number of writebacks
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-system.cpu2.l1c.overall_mshr_misses::total 59358 # number of overall MSHR misses
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-system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1274713340 # number of ReadReq MSHR miss cycles
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-system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1043385259 # number of WriteReq MSHR miss cycles
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-system.cpu2.l1c.demand_mshr_miss_latency::total 2318098599 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2318098599 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total 2318098599 # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 709358616 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 709358616 # number of ReadReq MSHR uncacheable cycles
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-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 436023988 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1145382604 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1145382604 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.804232 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.804232 # mshr miss rate for ReadReq accesses
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-system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953835 # mshr miss rate for WriteReq accesses
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-system.cpu2.l1c.demand_mshr_miss_rate::total 0.856611 # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.856611 # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total 0.856611 # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 35196.546925 # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 35196.546925 # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 45088.166415 # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 45088.166415 # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 39052.842060 # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 39052.842060 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 39052.842060 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 39052.842060 # average overall mshr miss latency
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+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 34970.430944 # average WriteReq mshr miss latency
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+system.cpu2.l1c.demand_avg_mshr_miss_latency::total 28332.864860 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 28332.864860 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 28332.864860 # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu3.num_writes 53057 # number of write accesses completed
+system.cpu3.num_reads 98539 # number of read accesses completed
+system.cpu3.num_writes 53510 # number of write accesses completed
system.cpu3.num_copies 0 # number of copy accesses completed
-system.cpu3.l1c.replacements 21593 # number of replacements
-system.cpu3.l1c.tagsinuse 392.026155 # Cycle average of tags in use
-system.cpu3.l1c.total_refs 13022 # Total number of references to valid blocks.
-system.cpu3.l1c.sampled_refs 21995 # Sample count of references to valid blocks.
-system.cpu3.l1c.avg_refs 0.592044 # Average number of references to valid blocks.
+system.cpu3.l1c.replacements 21926 # number of replacements
+system.cpu3.l1c.tagsinuse 394.806744 # Cycle average of tags in use
+system.cpu3.l1c.total_refs 12847 # Total number of references to valid blocks.
+system.cpu3.l1c.sampled_refs 22328 # Sample count of references to valid blocks.
+system.cpu3.l1c.avg_refs 0.575376 # Average number of references to valid blocks.
system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.occ_blocks::cpu3 392.026155 # Average occupied blocks per requestor
-system.cpu3.l1c.occ_percent::cpu3 0.765676 # Average percentage of cache occupancy
-system.cpu3.l1c.occ_percent::total 0.765676 # Average percentage of cache occupancy
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-system.cpu3.l1c.overall_hits::total 9589 # number of overall hits
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-system.cpu3.l1c.ReadReq_misses::total 35616 # number of ReadReq misses
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-system.cpu3.l1c.WriteReq_misses::total 22828 # number of WriteReq misses
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-system.cpu3.l1c.overall_misses::total 58444 # number of overall misses
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-system.cpu3.l1c.ReadReq_miss_latency::total 1343250290 # number of ReadReq miss cycles
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-system.cpu3.l1c.ReadReq_avg_miss_latency::total 37714.799248 # average ReadReq miss latency
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-system.cpu3.l1c.demand_avg_miss_latency::total 41417.300613 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 41417.300613 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 41417.300613 # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs 1437847 # number of cycles access was blocked
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+system.cpu3.l1c.occ_percent::total 0.771107 # Average percentage of cache occupancy
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+system.cpu3.l1c.ReadReq_hits::total 8426 # number of ReadReq hits
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+system.cpu3.l1c.ReadReq_avg_miss_latency::total 26157.819793 # average ReadReq miss latency
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+system.cpu3.l1c.WriteReq_avg_miss_latency::total 36962.735978 # average WriteReq miss latency
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system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu3.l1c.writebacks::total 9543 # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35616 # number of ReadReq MSHR misses
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-system.cpu3.l1c.WriteReq_mshr_misses::total 22828 # number of WriteReq MSHR misses
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-system.cpu3.l1c.demand_mshr_misses::total 58444 # number of demand (read+write) MSHR misses
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-system.cpu3.l1c.overall_mshr_misses::total 58444 # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1272022290 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1272022290 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1031688427 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1031688427 # number of WriteReq MSHR miss cycles
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-system.cpu3.l1c.demand_mshr_miss_latency::total 2303710717 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2303710717 # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total 2303710717 # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 723405993 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 723405993 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 425307050 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 425307050 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1148713043 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1148713043 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.806357 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.806357 # mshr miss rate for ReadReq accesses
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-system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.956587 # mshr miss rate for WriteReq accesses
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-system.cpu3.l1c.overall_mshr_miss_rate::total 0.859054 # mshr miss rate for overall accesses
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-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 35714.911557 # average ReadReq mshr miss latency
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-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 45193.991020 # average WriteReq mshr miss latency
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-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 39417.403275 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 39417.403275 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 39417.403275 # average overall mshr miss latency
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system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu4.num_reads 99668 # number of read accesses completed
-system.cpu4.num_writes 53668 # number of write accesses completed
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system.cpu4.num_copies 0 # number of copy accesses completed
-system.cpu4.l1c.replacements 22398 # number of replacements
-system.cpu4.l1c.tagsinuse 394.185618 # Cycle average of tags in use
-system.cpu4.l1c.total_refs 13312 # Total number of references to valid blocks.
-system.cpu4.l1c.sampled_refs 22817 # Sample count of references to valid blocks.
-system.cpu4.l1c.avg_refs 0.583425 # Average number of references to valid blocks.
+system.cpu4.l1c.replacements 21884 # number of replacements
+system.cpu4.l1c.tagsinuse 394.848687 # Cycle average of tags in use
+system.cpu4.l1c.total_refs 13028 # Total number of references to valid blocks.
+system.cpu4.l1c.sampled_refs 22289 # Sample count of references to valid blocks.
+system.cpu4.l1c.avg_refs 0.584504 # Average number of references to valid blocks.
system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.occ_blocks::cpu4 394.185618 # Average occupied blocks per requestor
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-system.cpu4.l1c.occ_percent::total 0.769894 # Average percentage of cache occupancy
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-system.cpu4.l1c.ReadReq_misses::total 36283 # number of ReadReq misses
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-system.cpu4.l1c.WriteReq_misses::total 23024 # number of WriteReq misses
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-system.cpu4.l1c.ReadReq_miss_latency::total 1350032249 # number of ReadReq miss cycles
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-system.cpu4.l1c.overall_miss_rate::total 0.858179 # miss rate for overall accesses
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-system.cpu4.l1c.ReadReq_avg_miss_latency::total 37208.396467 # average ReadReq miss latency
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-system.cpu4.l1c.WriteReq_avg_miss_latency::total 47007.809416 # average WriteReq miss latency
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-system.cpu4.l1c.demand_avg_miss_latency::total 41012.697540 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::cpu4 41012.697540 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::total 41012.697540 # average overall miss latency
-system.cpu4.l1c.blocked_cycles::no_mshrs 1437185 # number of cycles access was blocked
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+system.cpu4.l1c.occ_percent::total 0.771189 # Average percentage of cache occupancy
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+system.cpu4.l1c.ReadReq_hits::total 8503 # number of ReadReq hits
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+system.cpu4.l1c.overall_hits::total 9608 # number of overall hits
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+system.cpu4.l1c.ReadReq_misses::total 35561 # number of ReadReq misses
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+system.cpu4.l1c.WriteReq_misses::total 23022 # number of WriteReq misses
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+system.cpu4.l1c.overall_misses::total 58583 # number of overall misses
+system.cpu4.l1c.ReadReq_miss_latency::cpu4 936314772 # number of ReadReq miss cycles
+system.cpu4.l1c.ReadReq_miss_latency::total 936314772 # number of ReadReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::cpu4 859386922 # number of WriteReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::total 859386922 # number of WriteReq miss cycles
+system.cpu4.l1c.demand_miss_latency::cpu4 1795701694 # number of demand (read+write) miss cycles
+system.cpu4.l1c.demand_miss_latency::total 1795701694 # number of demand (read+write) miss cycles
+system.cpu4.l1c.overall_miss_latency::cpu4 1795701694 # number of overall miss cycles
+system.cpu4.l1c.overall_miss_latency::total 1795701694 # number of overall miss cycles
+system.cpu4.l1c.ReadReq_accesses::cpu4 44064 # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.ReadReq_accesses::total 44064 # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::cpu4 24127 # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::total 24127 # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.demand_accesses::cpu4 68191 # number of demand (read+write) accesses
+system.cpu4.l1c.demand_accesses::total 68191 # number of demand (read+write) accesses
+system.cpu4.l1c.overall_accesses::cpu4 68191 # number of overall (read+write) accesses
+system.cpu4.l1c.overall_accesses::total 68191 # number of overall (read+write) accesses
+system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807031 # miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_miss_rate::total 0.807031 # miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954201 # miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::total 0.954201 # miss rate for WriteReq accesses
+system.cpu4.l1c.demand_miss_rate::cpu4 0.859102 # miss rate for demand accesses
+system.cpu4.l1c.demand_miss_rate::total 0.859102 # miss rate for demand accesses
+system.cpu4.l1c.overall_miss_rate::cpu4 0.859102 # miss rate for overall accesses
+system.cpu4.l1c.overall_miss_rate::total 0.859102 # miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 26329.821209 # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_miss_latency::total 26329.821209 # average ReadReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 37328.942837 # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::total 37328.942837 # average WriteReq miss latency
+system.cpu4.l1c.demand_avg_miss_latency::cpu4 30652.265913 # average overall miss latency
+system.cpu4.l1c.demand_avg_miss_latency::total 30652.265913 # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::cpu4 30652.265913 # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::total 30652.265913 # average overall miss latency
+system.cpu4.l1c.blocked_cycles::no_mshrs 1016374 # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs 67419 # number of cycles access was blocked
+system.cpu4.l1c.blocked::no_mshrs 61728 # number of cycles access was blocked
system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs 21.317210 # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_mshrs 16.465364 # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
-system.cpu4.l1c.writebacks::writebacks 9672 # number of writebacks
-system.cpu4.l1c.writebacks::total 9672 # number of writebacks
-system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36283 # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_misses::total 36283 # number of ReadReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23024 # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::total 23024 # number of WriteReq MSHR misses
-system.cpu4.l1c.demand_mshr_misses::cpu4 59307 # number of demand (read+write) MSHR misses
-system.cpu4.l1c.demand_mshr_misses::total 59307 # number of demand (read+write) MSHR misses
-system.cpu4.l1c.overall_mshr_misses::cpu4 59307 # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_misses::total 59307 # number of overall MSHR misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1277470249 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1277470249 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1036263804 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1036263804 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2313734053 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::total 2313734053 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2313734053 # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total 2313734053 # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 713854071 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 713854071 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 422821531 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 422821531 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1136675602 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1136675602 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805841 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805841 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.956027 # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.956027 # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858179 # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_miss_rate::total 0.858179 # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858179 # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_miss_rate::total 0.858179 # mshr miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 35208.506711 # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 35208.506711 # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 45007.983148 # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 45007.983148 # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 39012.832431 # average overall mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 39012.832431 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 39012.832431 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 39012.832431 # average overall mshr miss latency
+system.cpu4.l1c.writebacks::writebacks 9520 # number of writebacks
+system.cpu4.l1c.writebacks::total 9520 # number of writebacks
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+system.cpu4.l1c.ReadReq_mshr_misses::total 35561 # number of ReadReq MSHR misses
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+system.cpu4.l1c.ReadReq_mshr_miss_latency::total 862769237 # number of ReadReq MSHR miss cycles
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+system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1674799615 # number of overall MSHR miss cycles
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+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 700729623 # number of ReadReq MSHR uncacheable cycles
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+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1644067080 # number of WriteReq MSHR uncacheable cycles
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+system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2344796703 # number of overall MSHR uncacheable cycles
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+system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859102 # mshr miss rate for demand accesses
+system.cpu4.l1c.demand_mshr_miss_rate::total 0.859102 # mshr miss rate for demand accesses
+system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859102 # mshr miss rate for overall accesses
+system.cpu4.l1c.overall_mshr_miss_rate::total 0.859102 # mshr miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24261.669722 # average ReadReq mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24261.669722 # average ReadReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 35271.930241 # average WriteReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 35271.930241 # average WriteReq mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 28588.491798 # average overall mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::total 28588.491798 # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 28588.491798 # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::total 28588.491798 # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu5.num_reads 98297 # number of read accesses completed
-system.cpu5.num_writes 53409 # number of write accesses completed
+system.cpu5.num_reads 98869 # number of read accesses completed
+system.cpu5.num_writes 53477 # number of write accesses completed
system.cpu5.num_copies 0 # number of copy accesses completed
-system.cpu5.l1c.replacements 21793 # number of replacements
-system.cpu5.l1c.tagsinuse 394.840854 # Cycle average of tags in use
-system.cpu5.l1c.total_refs 13019 # Total number of references to valid blocks.
-system.cpu5.l1c.sampled_refs 22214 # Sample count of references to valid blocks.
-system.cpu5.l1c.avg_refs 0.586072 # Average number of references to valid blocks.
+system.cpu5.l1c.replacements 22131 # number of replacements
+system.cpu5.l1c.tagsinuse 394.954130 # Cycle average of tags in use
+system.cpu5.l1c.total_refs 13197 # Total number of references to valid blocks.
+system.cpu5.l1c.sampled_refs 22529 # Sample count of references to valid blocks.
+system.cpu5.l1c.avg_refs 0.585778 # Average number of references to valid blocks.
system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.occ_blocks::cpu5 394.840854 # Average occupied blocks per requestor
-system.cpu5.l1c.occ_percent::cpu5 0.771174 # Average percentage of cache occupancy
-system.cpu5.l1c.occ_percent::total 0.771174 # Average percentage of cache occupancy
-system.cpu5.l1c.ReadReq_hits::cpu5 8574 # number of ReadReq hits
-system.cpu5.l1c.ReadReq_hits::total 8574 # number of ReadReq hits
-system.cpu5.l1c.WriteReq_hits::cpu5 1037 # number of WriteReq hits
-system.cpu5.l1c.WriteReq_hits::total 1037 # number of WriteReq hits
-system.cpu5.l1c.demand_hits::cpu5 9611 # number of demand (read+write) hits
-system.cpu5.l1c.demand_hits::total 9611 # number of demand (read+write) hits
-system.cpu5.l1c.overall_hits::cpu5 9611 # number of overall hits
-system.cpu5.l1c.overall_hits::total 9611 # number of overall hits
-system.cpu5.l1c.ReadReq_misses::cpu5 35608 # number of ReadReq misses
-system.cpu5.l1c.ReadReq_misses::total 35608 # number of ReadReq misses
-system.cpu5.l1c.WriteReq_misses::cpu5 22949 # number of WriteReq misses
-system.cpu5.l1c.WriteReq_misses::total 22949 # number of WriteReq misses
-system.cpu5.l1c.demand_misses::cpu5 58557 # number of demand (read+write) misses
-system.cpu5.l1c.demand_misses::total 58557 # number of demand (read+write) misses
-system.cpu5.l1c.overall_misses::cpu5 58557 # number of overall misses
-system.cpu5.l1c.overall_misses::total 58557 # number of overall misses
-system.cpu5.l1c.ReadReq_miss_latency::cpu5 1333115373 # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_latency::total 1333115373 # number of ReadReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::cpu5 1089027179 # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::total 1089027179 # number of WriteReq miss cycles
-system.cpu5.l1c.demand_miss_latency::cpu5 2422142552 # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_latency::total 2422142552 # number of demand (read+write) miss cycles
-system.cpu5.l1c.overall_miss_latency::cpu5 2422142552 # number of overall miss cycles
-system.cpu5.l1c.overall_miss_latency::total 2422142552 # number of overall miss cycles
-system.cpu5.l1c.ReadReq_accesses::cpu5 44182 # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_accesses::total 44182 # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::cpu5 23986 # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::total 23986 # number of WriteReq accesses(hits+misses)
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-system.cpu5.l1c.demand_accesses::total 68168 # number of demand (read+write) accesses
-system.cpu5.l1c.overall_accesses::cpu5 68168 # number of overall (read+write) accesses
-system.cpu5.l1c.overall_accesses::total 68168 # number of overall (read+write) accesses
-system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.805939 # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_miss_rate::total 0.805939 # miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.956766 # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::total 0.956766 # miss rate for WriteReq accesses
-system.cpu5.l1c.demand_miss_rate::cpu5 0.859010 # miss rate for demand accesses
-system.cpu5.l1c.demand_miss_rate::total 0.859010 # miss rate for demand accesses
-system.cpu5.l1c.overall_miss_rate::cpu5 0.859010 # miss rate for overall accesses
-system.cpu5.l1c.overall_miss_rate::total 0.859010 # miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 37438.647860 # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_miss_latency::total 37438.647860 # average ReadReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 47454.232385 # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::total 47454.232385 # average WriteReq miss latency
-system.cpu5.l1c.demand_avg_miss_latency::cpu5 41363.842956 # average overall miss latency
-system.cpu5.l1c.demand_avg_miss_latency::total 41363.842956 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 41363.842956 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 41363.842956 # average overall miss latency
-system.cpu5.l1c.blocked_cycles::no_mshrs 1437965 # number of cycles access was blocked
+system.cpu5.l1c.occ_blocks::cpu5 394.954130 # Average occupied blocks per requestor
+system.cpu5.l1c.occ_percent::cpu5 0.771395 # Average percentage of cache occupancy
+system.cpu5.l1c.occ_percent::total 0.771395 # Average percentage of cache occupancy
+system.cpu5.l1c.ReadReq_hits::cpu5 8594 # number of ReadReq hits
+system.cpu5.l1c.ReadReq_hits::total 8594 # number of ReadReq hits
+system.cpu5.l1c.WriteReq_hits::cpu5 1100 # number of WriteReq hits
+system.cpu5.l1c.WriteReq_hits::total 1100 # number of WriteReq hits
+system.cpu5.l1c.demand_hits::cpu5 9694 # number of demand (read+write) hits
+system.cpu5.l1c.demand_hits::total 9694 # number of demand (read+write) hits
+system.cpu5.l1c.overall_hits::cpu5 9694 # number of overall hits
+system.cpu5.l1c.overall_hits::total 9694 # number of overall hits
+system.cpu5.l1c.ReadReq_misses::cpu5 35827 # number of ReadReq misses
+system.cpu5.l1c.ReadReq_misses::total 35827 # number of ReadReq misses
+system.cpu5.l1c.WriteReq_misses::cpu5 23090 # number of WriteReq misses
+system.cpu5.l1c.WriteReq_misses::total 23090 # number of WriteReq misses
+system.cpu5.l1c.demand_misses::cpu5 58917 # number of demand (read+write) misses
+system.cpu5.l1c.demand_misses::total 58917 # number of demand (read+write) misses
+system.cpu5.l1c.overall_misses::cpu5 58917 # number of overall misses
+system.cpu5.l1c.overall_misses::total 58917 # number of overall misses
+system.cpu5.l1c.ReadReq_miss_latency::cpu5 936035832 # number of ReadReq miss cycles
+system.cpu5.l1c.ReadReq_miss_latency::total 936035832 # number of ReadReq miss cycles
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+system.cpu5.l1c.WriteReq_miss_latency::total 858178388 # number of WriteReq miss cycles
+system.cpu5.l1c.demand_miss_latency::cpu5 1794214220 # number of demand (read+write) miss cycles
+system.cpu5.l1c.demand_miss_latency::total 1794214220 # number of demand (read+write) miss cycles
+system.cpu5.l1c.overall_miss_latency::cpu5 1794214220 # number of overall miss cycles
+system.cpu5.l1c.overall_miss_latency::total 1794214220 # number of overall miss cycles
+system.cpu5.l1c.ReadReq_accesses::cpu5 44421 # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_accesses::total 44421 # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::cpu5 24190 # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::total 24190 # number of WriteReq accesses(hits+misses)
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+system.cpu5.l1c.overall_accesses::cpu5 68611 # number of overall (read+write) accesses
+system.cpu5.l1c.overall_accesses::total 68611 # number of overall (read+write) accesses
+system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806533 # miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_miss_rate::total 0.806533 # miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954527 # miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::total 0.954527 # miss rate for WriteReq accesses
+system.cpu5.l1c.demand_miss_rate::cpu5 0.858711 # miss rate for demand accesses
+system.cpu5.l1c.demand_miss_rate::total 0.858711 # miss rate for demand accesses
+system.cpu5.l1c.overall_miss_rate::cpu5 0.858711 # miss rate for overall accesses
+system.cpu5.l1c.overall_miss_rate::total 0.858711 # miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26126.547911 # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_miss_latency::total 26126.547911 # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 37166.669034 # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::total 37166.669034 # average WriteReq miss latency
+system.cpu5.l1c.demand_avg_miss_latency::cpu5 30453.251523 # average overall miss latency
+system.cpu5.l1c.demand_avg_miss_latency::total 30453.251523 # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::cpu5 30453.251523 # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::total 30453.251523 # average overall miss latency
+system.cpu5.l1c.blocked_cycles::no_mshrs 1010232 # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs 66766 # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_mshrs 61688 # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs 21.537384 # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs 16.376475 # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
-system.cpu5.l1c.writebacks::writebacks 9530 # number of writebacks
-system.cpu5.l1c.writebacks::total 9530 # number of writebacks
-system.cpu5.l1c.ReadReq_mshr_misses::cpu5 35608 # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_misses::total 35608 # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22949 # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::total 22949 # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses::cpu5 58557 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.demand_mshr_misses::total 58557 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses::cpu5 58557 # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_misses::total 58557 # number of overall MSHR misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1261899373 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1261899373 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1043133179 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1043133179 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2305032552 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::total 2305032552 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2305032552 # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total 2305032552 # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 722637545 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 722637545 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 432075918 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 432075918 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1154713463 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1154713463 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.805939 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.805939 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.956766 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.956766 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859010 # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_miss_rate::total 0.859010 # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859010 # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total 0.859010 # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 35438.647860 # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 35438.647860 # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 45454.406684 # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 45454.406684 # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 39363.911266 # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 39363.911266 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 39363.911266 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 39363.911266 # average overall mshr miss latency
+system.cpu5.l1c.writebacks::writebacks 9611 # number of writebacks
+system.cpu5.l1c.writebacks::total 9611 # number of writebacks
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+system.cpu5.l1c.WriteReq_mshr_misses::total 23090 # number of WriteReq MSHR misses
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+system.cpu5.l1c.ReadReq_mshr_miss_latency::total 861924856 # number of ReadReq MSHR miss cycles
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+system.cpu5.l1c.demand_mshr_miss_latency::total 1672577269 # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1672577269 # number of overall MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::total 1672577269 # number of overall MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 694440055 # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 694440055 # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1653385505 # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1653385505 # number of WriteReq MSHR uncacheable cycles
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+system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2347825560 # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806533 # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806533 # mshr miss rate for ReadReq accesses
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+system.cpu5.l1c.demand_mshr_miss_rate::total 0.858711 # mshr miss rate for demand accesses
+system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858711 # mshr miss rate for overall accesses
+system.cpu5.l1c.overall_mshr_miss_rate::total 0.858711 # mshr miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 24057.969018 # average ReadReq mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 24057.969018 # average ReadReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 35108.376483 # average WriteReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 35108.376483 # average WriteReq mshr miss latency
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+system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28388.703922 # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28388.703922 # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28388.703922 # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu6.num_reads 100000 # number of read accesses completed
-system.cpu6.num_writes 53851 # number of write accesses completed
+system.cpu6.num_reads 99583 # number of read accesses completed
+system.cpu6.num_writes 53438 # number of write accesses completed
system.cpu6.num_copies 0 # number of copy accesses completed
-system.cpu6.l1c.replacements 22533 # number of replacements
-system.cpu6.l1c.tagsinuse 396.232181 # Cycle average of tags in use
-system.cpu6.l1c.total_refs 13413 # Total number of references to valid blocks.
-system.cpu6.l1c.sampled_refs 22918 # Sample count of references to valid blocks.
-system.cpu6.l1c.avg_refs 0.585260 # Average number of references to valid blocks.
+system.cpu6.l1c.replacements 21939 # number of replacements
+system.cpu6.l1c.tagsinuse 394.903585 # Cycle average of tags in use
+system.cpu6.l1c.total_refs 13339 # Total number of references to valid blocks.
+system.cpu6.l1c.sampled_refs 22346 # Sample count of references to valid blocks.
+system.cpu6.l1c.avg_refs 0.596930 # Average number of references to valid blocks.
system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.occ_blocks::cpu6 396.232181 # Average occupied blocks per requestor
-system.cpu6.l1c.occ_percent::cpu6 0.773891 # Average percentage of cache occupancy
-system.cpu6.l1c.occ_percent::total 0.773891 # Average percentage of cache occupancy
-system.cpu6.l1c.ReadReq_hits::cpu6 8765 # number of ReadReq hits
-system.cpu6.l1c.ReadReq_hits::total 8765 # number of ReadReq hits
-system.cpu6.l1c.WriteReq_hits::cpu6 1112 # number of WriteReq hits
-system.cpu6.l1c.WriteReq_hits::total 1112 # number of WriteReq hits
-system.cpu6.l1c.demand_hits::cpu6 9877 # number of demand (read+write) hits
-system.cpu6.l1c.demand_hits::total 9877 # number of demand (read+write) hits
-system.cpu6.l1c.overall_hits::cpu6 9877 # number of overall hits
-system.cpu6.l1c.overall_hits::total 9877 # number of overall hits
-system.cpu6.l1c.ReadReq_misses::cpu6 36287 # number of ReadReq misses
-system.cpu6.l1c.ReadReq_misses::total 36287 # number of ReadReq misses
-system.cpu6.l1c.WriteReq_misses::cpu6 23071 # number of WriteReq misses
-system.cpu6.l1c.WriteReq_misses::total 23071 # number of WriteReq misses
-system.cpu6.l1c.demand_misses::cpu6 59358 # number of demand (read+write) misses
-system.cpu6.l1c.demand_misses::total 59358 # number of demand (read+write) misses
-system.cpu6.l1c.overall_misses::cpu6 59358 # number of overall misses
-system.cpu6.l1c.overall_misses::total 59358 # number of overall misses
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-system.cpu6.l1c.ReadReq_miss_latency::total 1346746093 # number of ReadReq miss cycles
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-system.cpu6.l1c.WriteReq_miss_latency::total 1082399151 # number of WriteReq miss cycles
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-system.cpu6.l1c.demand_miss_latency::total 2429145244 # number of demand (read+write) miss cycles
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-system.cpu6.l1c.overall_miss_latency::total 2429145244 # number of overall miss cycles
-system.cpu6.l1c.ReadReq_accesses::cpu6 45052 # number of ReadReq accesses(hits+misses)
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-system.cpu6.l1c.overall_accesses::total 69235 # number of overall (read+write) accesses
-system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805447 # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_miss_rate::total 0.805447 # miss rate for ReadReq accesses
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-system.cpu6.l1c.WriteReq_miss_rate::total 0.954017 # miss rate for WriteReq accesses
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-system.cpu6.l1c.demand_miss_rate::total 0.857341 # miss rate for demand accesses
-system.cpu6.l1c.overall_miss_rate::cpu6 0.857341 # miss rate for overall accesses
-system.cpu6.l1c.overall_miss_rate::total 0.857341 # miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 37113.734753 # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_miss_latency::total 37113.734753 # average ReadReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 46916.004985 # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::total 46916.004985 # average WriteReq miss latency
-system.cpu6.l1c.demand_avg_miss_latency::cpu6 40923.636982 # average overall miss latency
-system.cpu6.l1c.demand_avg_miss_latency::total 40923.636982 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 40923.636982 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 40923.636982 # average overall miss latency
-system.cpu6.l1c.blocked_cycles::no_mshrs 1436888 # number of cycles access was blocked
+system.cpu6.l1c.occ_blocks::cpu6 394.903585 # Average occupied blocks per requestor
+system.cpu6.l1c.occ_percent::cpu6 0.771296 # Average percentage of cache occupancy
+system.cpu6.l1c.occ_percent::total 0.771296 # Average percentage of cache occupancy
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+system.cpu6.l1c.ReadReq_hits::total 8764 # number of ReadReq hits
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+system.cpu6.l1c.WriteReq_hits::total 1067 # number of WriteReq hits
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+system.cpu6.l1c.overall_hits::total 9831 # number of overall hits
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+system.cpu6.l1c.ReadReq_misses::total 36046 # number of ReadReq misses
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+system.cpu6.l1c.WriteReq_misses::total 22895 # number of WriteReq misses
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+system.cpu6.l1c.overall_misses::total 58941 # number of overall misses
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+system.cpu6.l1c.WriteReq_miss_latency::total 845796556 # number of WriteReq miss cycles
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+system.cpu6.l1c.demand_miss_latency::total 1784076243 # number of demand (read+write) miss cycles
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+system.cpu6.l1c.overall_miss_latency::total 1784076243 # number of overall miss cycles
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+system.cpu6.l1c.ReadReq_accesses::total 44810 # number of ReadReq accesses(hits+misses)
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+system.cpu6.l1c.WriteReq_accesses::total 23962 # number of WriteReq accesses(hits+misses)
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+system.cpu6.l1c.overall_accesses::total 68772 # number of overall (read+write) accesses
+system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.804419 # miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_miss_rate::total 0.804419 # miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.955471 # miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::total 0.955471 # miss rate for WriteReq accesses
+system.cpu6.l1c.demand_miss_rate::cpu6 0.857049 # miss rate for demand accesses
+system.cpu6.l1c.demand_miss_rate::total 0.857049 # miss rate for demand accesses
+system.cpu6.l1c.overall_miss_rate::cpu6 0.857049 # miss rate for overall accesses
+system.cpu6.l1c.overall_miss_rate::total 0.857049 # miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26030.064002 # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_miss_latency::total 26030.064002 # average ReadReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 36942.413453 # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::total 36942.413453 # average WriteReq miss latency
+system.cpu6.l1c.demand_avg_miss_latency::cpu6 30268.849239 # average overall miss latency
+system.cpu6.l1c.demand_avg_miss_latency::total 30268.849239 # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::cpu6 30268.849239 # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::total 30268.849239 # average overall miss latency
+system.cpu6.l1c.blocked_cycles::no_mshrs 1009249 # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs 67354 # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_mshrs 61784 # number of cycles access was blocked
system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_mshrs 21.333373 # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_mshrs 16.335119 # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
-system.cpu6.l1c.writebacks::writebacks 9760 # number of writebacks
-system.cpu6.l1c.writebacks::total 9760 # number of writebacks
-system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36287 # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_misses::total 36287 # number of ReadReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23071 # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::total 23071 # number of WriteReq MSHR misses
-system.cpu6.l1c.demand_mshr_misses::cpu6 59358 # number of demand (read+write) MSHR misses
-system.cpu6.l1c.demand_mshr_misses::total 59358 # number of demand (read+write) MSHR misses
-system.cpu6.l1c.overall_mshr_misses::cpu6 59358 # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_misses::total 59358 # number of overall MSHR misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1274178093 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1274178093 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1036259151 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1036259151 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2310437244 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::total 2310437244 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2310437244 # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total 2310437244 # number of overall MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 716759617 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 716759617 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 439137857 # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 439137857 # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1155897474 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1155897474 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805447 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805447 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954017 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954017 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.857341 # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_miss_rate::total 0.857341 # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.857341 # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total 0.857341 # mshr miss rate for overall accesses
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-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 35113.900102 # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 44916.091674 # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 44916.091674 # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 38923.771758 # average overall mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 38923.771758 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 38923.771758 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 38923.771758 # average overall mshr miss latency
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+system.cpu6.l1c.writebacks::total 9560 # number of writebacks
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+system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.857049 # mshr miss rate for overall accesses
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+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 23960.683876 # average ReadReq mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 23960.683876 # average ReadReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34883.951605 # average WriteReq mshr miss latency
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+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 28203.710202 # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::total 28203.710202 # average overall mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu7.num_reads 99311 # number of read accesses completed
-system.cpu7.num_writes 53396 # number of write accesses completed
+system.cpu7.num_reads 99199 # number of read accesses completed
+system.cpu7.num_writes 53517 # number of write accesses completed
system.cpu7.num_copies 0 # number of copy accesses completed
-system.cpu7.l1c.replacements 22280 # number of replacements
-system.cpu7.l1c.tagsinuse 395.094392 # Cycle average of tags in use
-system.cpu7.l1c.total_refs 13351 # Total number of references to valid blocks.
-system.cpu7.l1c.sampled_refs 22696 # Sample count of references to valid blocks.
-system.cpu7.l1c.avg_refs 0.588253 # Average number of references to valid blocks.
+system.cpu7.l1c.replacements 22063 # number of replacements
+system.cpu7.l1c.tagsinuse 393.496696 # Cycle average of tags in use
+system.cpu7.l1c.total_refs 13289 # Total number of references to valid blocks.
+system.cpu7.l1c.sampled_refs 22472 # Sample count of references to valid blocks.
+system.cpu7.l1c.avg_refs 0.591358 # Average number of references to valid blocks.
system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.occ_blocks::cpu7 395.094392 # Average occupied blocks per requestor
-system.cpu7.l1c.occ_percent::cpu7 0.771669 # Average percentage of cache occupancy
-system.cpu7.l1c.occ_percent::total 0.771669 # Average percentage of cache occupancy
-system.cpu7.l1c.ReadReq_hits::cpu7 8656 # number of ReadReq hits
-system.cpu7.l1c.ReadReq_hits::total 8656 # number of ReadReq hits
-system.cpu7.l1c.WriteReq_hits::cpu7 1129 # number of WriteReq hits
-system.cpu7.l1c.WriteReq_hits::total 1129 # number of WriteReq hits
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-system.cpu7.l1c.overall_hits::total 9785 # number of overall hits
-system.cpu7.l1c.ReadReq_misses::cpu7 36252 # number of ReadReq misses
-system.cpu7.l1c.ReadReq_misses::total 36252 # number of ReadReq misses
-system.cpu7.l1c.WriteReq_misses::cpu7 23067 # number of WriteReq misses
-system.cpu7.l1c.WriteReq_misses::total 23067 # number of WriteReq misses
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-system.cpu7.l1c.demand_misses::total 59319 # number of demand (read+write) misses
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-system.cpu7.l1c.overall_misses::total 59319 # number of overall misses
-system.cpu7.l1c.ReadReq_miss_latency::cpu7 1344539775 # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_latency::total 1344539775 # number of ReadReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::cpu7 1092348717 # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::total 1092348717 # number of WriteReq miss cycles
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-system.cpu7.l1c.demand_miss_latency::total 2436888492 # number of demand (read+write) miss cycles
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-system.cpu7.l1c.overall_miss_latency::total 2436888492 # number of overall miss cycles
-system.cpu7.l1c.ReadReq_accesses::cpu7 44908 # number of ReadReq accesses(hits+misses)
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-system.cpu7.l1c.WriteReq_accesses::total 24196 # number of WriteReq accesses(hits+misses)
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-system.cpu7.l1c.overall_accesses::total 69104 # number of overall (read+write) accesses
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-system.cpu7.l1c.ReadReq_miss_rate::total 0.807250 # miss rate for ReadReq accesses
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-system.cpu7.l1c.demand_miss_rate::total 0.858402 # miss rate for demand accesses
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-system.cpu7.l1c.overall_miss_rate::total 0.858402 # miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 37088.706140 # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_miss_latency::total 37088.706140 # average ReadReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 47355.473924 # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::total 47355.473924 # average WriteReq miss latency
-system.cpu7.l1c.demand_avg_miss_latency::cpu7 41081.078440 # average overall miss latency
-system.cpu7.l1c.demand_avg_miss_latency::total 41081.078440 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::cpu7 41081.078440 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::total 41081.078440 # average overall miss latency
-system.cpu7.l1c.blocked_cycles::no_mshrs 1437300 # number of cycles access was blocked
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+system.cpu7.l1c.occ_percent::cpu7 0.768548 # Average percentage of cache occupancy
+system.cpu7.l1c.occ_percent::total 0.768548 # Average percentage of cache occupancy
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+system.cpu7.l1c.ReadReq_hits::total 8670 # number of ReadReq hits
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+system.cpu7.l1c.overall_hits::total 9798 # number of overall hits
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+system.cpu7.l1c.ReadReq_misses::total 35926 # number of ReadReq misses
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+system.cpu7.l1c.WriteReq_misses::total 23139 # number of WriteReq misses
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+system.cpu7.l1c.overall_misses::total 59065 # number of overall misses
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+system.cpu7.l1c.ReadReq_accesses::total 44596 # number of ReadReq accesses(hits+misses)
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+system.cpu7.l1c.overall_accesses::total 68863 # number of overall (read+write) accesses
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+system.cpu7.l1c.ReadReq_miss_rate::total 0.805588 # miss rate for ReadReq accesses
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+system.cpu7.l1c.WriteReq_miss_rate::total 0.953517 # miss rate for WriteReq accesses
+system.cpu7.l1c.demand_miss_rate::cpu7 0.857717 # miss rate for demand accesses
+system.cpu7.l1c.demand_miss_rate::total 0.857717 # miss rate for demand accesses
+system.cpu7.l1c.overall_miss_rate::cpu7 0.857717 # miss rate for overall accesses
+system.cpu7.l1c.overall_miss_rate::total 0.857717 # miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 25979.432222 # average ReadReq miss latency
+system.cpu7.l1c.ReadReq_avg_miss_latency::total 25979.432222 # average ReadReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37203.187130 # average WriteReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::total 37203.187130 # average WriteReq miss latency
+system.cpu7.l1c.demand_avg_miss_latency::cpu7 30376.392601 # average overall miss latency
+system.cpu7.l1c.demand_avg_miss_latency::total 30376.392601 # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::cpu7 30376.392601 # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::total 30376.392601 # average overall miss latency
+system.cpu7.l1c.blocked_cycles::no_mshrs 1011426 # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_mshrs 67375 # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_mshrs 62031 # number of cycles access was blocked
system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.332839 # average number of cycles each access was blocked
+system.cpu7.l1c.avg_blocked_cycles::no_mshrs 16.305170 # average number of cycles each access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
-system.cpu7.l1c.writebacks::writebacks 9656 # number of writebacks
-system.cpu7.l1c.writebacks::total 9656 # number of writebacks
-system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36252 # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_misses::total 36252 # number of ReadReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23067 # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses::total 23067 # number of WriteReq MSHR misses
-system.cpu7.l1c.demand_mshr_misses::cpu7 59319 # number of demand (read+write) MSHR misses
-system.cpu7.l1c.demand_mshr_misses::total 59319 # number of demand (read+write) MSHR misses
-system.cpu7.l1c.overall_mshr_misses::cpu7 59319 # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_misses::total 59319 # number of overall MSHR misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1272035775 # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1272035775 # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1046218717 # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1046218717 # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2318254492 # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency::total 2318254492 # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2318254492 # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::total 2318254492 # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 709343608 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 709343608 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 432591529 # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 432591529 # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1141935137 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1141935137 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807250 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807250 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953339 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953339 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858402 # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_miss_rate::total 0.858402 # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858402 # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_miss_rate::total 0.858402 # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 35088.706140 # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 35088.706140 # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 45355.647332 # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 45355.647332 # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 39081.145872 # average overall mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 39081.145872 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 39081.145872 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::total 39081.145872 # average overall mshr miss latency
+system.cpu7.l1c.writebacks::writebacks 9494 # number of writebacks
+system.cpu7.l1c.writebacks::total 9494 # number of writebacks
+system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35926 # number of ReadReq MSHR misses
+system.cpu7.l1c.ReadReq_mshr_misses::total 35926 # number of ReadReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23139 # number of WriteReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::total 23139 # number of WriteReq MSHR misses
+system.cpu7.l1c.demand_mshr_misses::cpu7 59065 # number of demand (read+write) MSHR misses
+system.cpu7.l1c.demand_mshr_misses::total 59065 # number of demand (read+write) MSHR misses
+system.cpu7.l1c.overall_mshr_misses::cpu7 59065 # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_misses::total 59065 # number of overall MSHR misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 859043599 # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_latency::total 859043599 # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 813252475 # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::total 813252475 # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1672296074 # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::total 1672296074 # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1672296074 # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::total 1672296074 # number of overall MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 693959592 # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 693959592 # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1654672592 # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1654672592 # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2348632184 # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2348632184 # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805588 # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805588 # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953517 # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953517 # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857717 # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_miss_rate::total 0.857717 # mshr miss rate for demand accesses
+system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857717 # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_miss_rate::total 0.857717 # mshr miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 23911.473557 # average ReadReq mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 23911.473557 # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 35146.396776 # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 35146.396776 # average WriteReq mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 28312.809176 # average overall mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::total 28312.809176 # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 28312.809176 # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::total 28312.809176 # average overall mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
sim_ticks 100000000000 # Number of ticks simulated
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 31852968745 # Simulator tick rate (ticks/s)
-host_mem_usage 226592 # Number of bytes of host memory used
-host_seconds 3.14 # Real time elapsed on the host
-system.physmem.bytes_read::cpu 213337536 # Number of bytes read from this memory
-system.physmem.bytes_read::total 213337536 # Number of bytes read from this memory
-system.physmem.num_reads::cpu 3333399 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 3333399 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu 2133375360 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2133375360 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu 2133375360 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2133375360 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 3333400 # Total number of read requests seen
+host_tick_rate 12296459257 # Simulator tick rate (ticks/s)
+host_mem_usage 231220 # Number of bytes of host memory used
+host_seconds 8.13 # Real time elapsed on the host
+system.physmem.bytes_read::cpu 213331136 # Number of bytes read from this memory
+system.physmem.bytes_read::total 213331136 # Number of bytes read from this memory
+system.physmem.num_reads::cpu 3333299 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 3333299 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu 2133311360 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2133311360 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu 2133311360 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2133311360 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 3333300 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 3333400 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 213337536 # Total number of bytes read from memory
+system.physmem.cpureqs 3333300 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 213331136 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 213337536 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 213331136 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 211200 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 210200 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 208000 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 208000 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 208000 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 208000 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 208000 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 208000 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 208000 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 208000 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 208000 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 208000 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 208000 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 208000 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 208000 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 208000 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 217600 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 217600 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 217600 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 217600 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 210100 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 204800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 204800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 204800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 204800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 204800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 204800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 204800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 204800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 204800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 204800 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 204800 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 99999990000 # Total gap between requests
+system.physmem.totGap 99999960000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 3333400 # Categorize read packet sizes
+system.physmem.readPktSize::6 3333300 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 0 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 3200711 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 105371 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 4811 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 4280 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3757 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 3749 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 3205 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 2146 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 1602 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 2148 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1074 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 546 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 3301421 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 26232 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 1073 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 946 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 938 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 802 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 538 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 402 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 540 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 270 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 138 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.totQLat 6112380100 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 69501990100 # Sum of mem lat for all requests
-system.physmem.totBusLat 16667000000 # Total cycles spent in databus access
-system.physmem.totBankLat 46722610000 # Total cycles spent in bank access
-system.physmem.avgQLat 1833.68 # Average queueing delay per request
-system.physmem.avgBankLat 14016.50 # Average bank access latency per request
+system.physmem.bytesPerActivate::samples 26100 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 8168.810421 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 8140.398372 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 356.874580 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::64-65 16 0.06% 0.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::3392-3393 99 0.38% 0.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::8192-8193 25985 99.56% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 26100 # Bytes accessed per row activation
+system.physmem.totQLat 1278758950 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 63884930200 # Sum of mem lat for all requests
+system.physmem.totBusLat 16666500000 # Total cycles spent in databus access
+system.physmem.totBankLat 45939671250 # Total cycles spent in bank access
+system.physmem.avgQLat 383.63 # Average queueing delay per request
+system.physmem.avgBankLat 13782.04 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 20850.18 # Average memory access latency
-system.physmem.avgRdBW 2133.38 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 19165.67 # Average memory access latency
+system.physmem.avgRdBW 2133.31 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 2133.38 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 2133.31 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 16.67 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.70 # Average read queue length over time
+system.physmem.avgRdQLen 0.64 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 3229200 # Number of row buffer hits during reads
+system.physmem.readRowHits 3307200 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 96.87 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 99.22 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 29999.40 # Average gap between requests
-system.monitor.readBurstLengthHist::samples 3333400 # Histogram of burst lengths of transmitted packets
+system.physmem.avgGap 30000.29 # Average gap between requests
+system.membus.throughput 2133311360 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 3333300 # Transaction distribution
+system.membus.trans_dist::ReadResp 3333299 # Transaction distribution
+system.membus.pkt_count_system.monitor-master 6666599 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 6666599 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.monitor-master 213331136 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 213331136 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 213331136 # Total data (bytes)
+system.membus.reqLayer0.occupancy 6333270000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 6.3 # Layer utilization (%)
+system.membus.respLayer0.occupancy 17184426300 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 17.2 # Layer utilization (%)
+system.cpu.numPackets 3333300 # Number of packets generated
+system.cpu.numRetries 0 # Number of retries
+system.cpu.retryTicks 0 # Time spent waiting due to back-pressure (ticks)
+system.monitor.readBurstLengthHist::samples 3333300 # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::stdev 0 # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::52-55 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::56-59 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::60-63 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::64-67 3333400 100.00% 100.00% # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::64-67 3333300 100.00% 100.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::68-71 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::72-75 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::76-79 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.readBurstLengthHist::total 3333400 # Histogram of burst lengths of transmitted packets
+system.monitor.readBurstLengthHist::total 3333300 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::samples 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::mean nan # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::gmean nan # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::19 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::total 0 # Histogram of burst lengths of transmitted packets
system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::mean 2133375360 # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::gmean 2133375359.990565 # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.readBandwidthHist::stdev 6400.010343 # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::mean 2133311360 # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::gmean 2133311359.990499 # Histogram of read bandwidth per sample period (bytes/s)
+system.monitor.readBandwidthHist::stdev 6399.944145 # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::2.41592e+09-2.55014e+09 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::2.55014e+09-2.68435e+09 0 0.00% 100.00% # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::total 100 # Histogram of read bandwidth per sample period (bytes/s)
-system.monitor.averageReadBandwidth 2133375360 0.00% 0.00% # Average read bandwidth (bytes/s)
-system.monitor.totalReadBytes 213337536 # Number of bytes read
+system.monitor.averageReadBandwidth 2133311360 0.00% 0.00% # Average read bandwidth (bytes/s)
+system.monitor.totalReadBytes 213331136 # Number of bytes read
system.monitor.writeBandwidthHist::samples 100 # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::mean 0 # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::gmean 0 # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::total 100 # Histogram of write bandwidth (bytes/s)
system.monitor.averageWriteBandwidth 0 # Average write bandwidth (bytes/s)
system.monitor.totalWrittenBytes 0 # Number of bytes written
-system.monitor.readLatencyHist::samples 3333399 # Read request-response latency
-system.monitor.readLatencyHist::mean 20878.092191 # Read request-response latency
-system.monitor.readLatencyHist::gmean 19621.155070 # Read request-response latency
-system.monitor.readLatencyHist::stdev 15688.085413 # Read request-response latency
-system.monitor.readLatencyHist::0-32767 3201881 96.05% 96.05% # Read request-response latency
-system.monitor.readLatencyHist::32768-65535 104731 3.14% 99.20% # Read request-response latency
-system.monitor.readLatencyHist::65536-98303 5355 0.16% 99.36% # Read request-response latency
-system.monitor.readLatencyHist::98304-131071 4826 0.14% 99.50% # Read request-response latency
-system.monitor.readLatencyHist::131072-163839 4267 0.13% 99.63% # Read request-response latency
-system.monitor.readLatencyHist::163840-196607 3205 0.10% 99.73% # Read request-response latency
-system.monitor.readLatencyHist::196608-229375 3236 0.10% 99.82% # Read request-response latency
-system.monitor.readLatencyHist::229376-262143 2130 0.06% 99.89% # Read request-response latency
-system.monitor.readLatencyHist::262144-294911 1602 0.05% 99.94% # Read request-response latency
-system.monitor.readLatencyHist::294912-327679 1620 0.05% 99.98% # Read request-response latency
-system.monitor.readLatencyHist::327680-360447 546 0.02% 100.00% # Read request-response latency
+system.monitor.readLatencyHist::samples 3333299 # Read request-response latency
+system.monitor.readLatencyHist::mean 39172.137513 # Read request-response latency
+system.monitor.readLatencyHist::gmean 38967.643311 # Read request-response latency
+system.monitor.readLatencyHist::stdev 6823.352873 # Read request-response latency
+system.monitor.readLatencyHist::0-32767 12686 0.38% 0.38% # Read request-response latency
+system.monitor.readLatencyHist::32768-65535 3289137 98.68% 99.06% # Read request-response latency
+system.monitor.readLatencyHist::65536-98303 26638 0.80% 99.85% # Read request-response latency
+system.monitor.readLatencyHist::98304-131071 937 0.03% 99.88% # Read request-response latency
+system.monitor.readLatencyHist::131072-163839 1073 0.03% 99.92% # Read request-response latency
+system.monitor.readLatencyHist::163840-196607 808 0.02% 99.94% # Read request-response latency
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+system.monitor.readLatencyHist::294912-327679 270 0.01% 100.00% # Read request-response latency
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system.monitor.readLatencyHist::360448-393215 0 0.00% 100.00% # Read request-response latency
system.monitor.readLatencyHist::393216-425983 0 0.00% 100.00% # Read request-response latency
system.monitor.readLatencyHist::425984-458751 0 0.00% 100.00% # Read request-response latency
system.monitor.readLatencyHist::557056-589823 0 0.00% 100.00% # Read request-response latency
system.monitor.readLatencyHist::589824-622591 0 0.00% 100.00% # Read request-response latency
system.monitor.readLatencyHist::622592-655359 0 0.00% 100.00% # Read request-response latency
-system.monitor.readLatencyHist::total 3333399 # Read request-response latency
+system.monitor.readLatencyHist::total 3333299 # Read request-response latency
system.monitor.writeLatencyHist::samples 0 # Write request-response latency
system.monitor.writeLatencyHist::mean nan # Write request-response latency
system.monitor.writeLatencyHist::gmean nan # Write request-response latency
system.monitor.writeLatencyHist::18 0 # Write request-response latency
system.monitor.writeLatencyHist::19 0 # Write request-response latency
system.monitor.writeLatencyHist::total 0 # Write request-response latency
-system.monitor.ittReadRead::samples 3333399 # Read-to-read inter transaction time
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system.monitor.ittReadRead::underflows 0 0.00% 0.00% # Read-to-read inter transaction time
system.monitor.ittReadRead::1-5000 0 0.00% 0.00% # Read-to-read inter transaction time
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system.monitor.ittReadRead::10001-15000 0 0.00% 0.00% # Read-to-read inter transaction time
system.monitor.ittReadRead::15001-20000 0 0.00% 0.00% # Read-to-read inter transaction time
system.monitor.ittReadRead::20001-25000 0 0.00% 0.00% # Read-to-read inter transaction time
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system.monitor.ittReadRead::30001-35000 0 0.00% 100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::35001-40000 0 0.00% 100.00% # Read-to-read inter transaction time
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system.monitor.ittReadRead::40001-45000 0 0.00% 100.00% # Read-to-read inter transaction time
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system.monitor.ittReadRead::90001-95000 0 0.00% 100.00% # Read-to-read inter transaction time
system.monitor.ittReadRead::95001-100000 0 0.00% 100.00% # Read-to-read inter transaction time
system.monitor.ittReadRead::overflows 0 0.00% 100.00% # Read-to-read inter transaction time
-system.monitor.ittReadRead::min_value 10000 # Read-to-read inter transaction time
-system.monitor.ittReadRead::max_value 30000 # Read-to-read inter transaction time
-system.monitor.ittReadRead::total 3333399 # Read-to-read inter transaction time
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system.monitor.ittWriteWrite::samples 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::mean nan # Write-to-write inter transaction time
system.monitor.ittWriteWrite::stdev nan # Write-to-write inter transaction time
system.monitor.ittWriteWrite::min_value 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::max_value 0 # Write-to-write inter transaction time
system.monitor.ittWriteWrite::total 0 # Write-to-write inter transaction time
-system.monitor.ittReqReq::samples 3333399 # Request-to-request inter transaction time
-system.monitor.ittReqReq::mean 29999.406012 # Request-to-request inter transaction time
-system.monitor.ittReqReq::stdev 108.992737 # Request-to-request inter transaction time
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system.monitor.ittReqReq::underflows 0 0.00% 0.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::1-5000 0 0.00% 0.00% # Request-to-request inter transaction time
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system.monitor.ittReqReq::10001-15000 0 0.00% 0.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::15001-20000 0 0.00% 0.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::20001-25000 0 0.00% 0.00% # Request-to-request inter transaction time
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system.monitor.ittReqReq::30001-35000 0 0.00% 100.00% # Request-to-request inter transaction time
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system.monitor.ittReqReq::40001-45000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::45001-50000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::50001-55000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::90001-95000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::95001-100000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::overflows 0 0.00% 100.00% # Request-to-request inter transaction time
-system.monitor.ittReqReq::min_value 10000 # Request-to-request inter transaction time
-system.monitor.ittReqReq::max_value 30000 # Request-to-request inter transaction time
-system.monitor.ittReqReq::total 3333399 # Request-to-request inter transaction time
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system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions
system.monitor.outstandingReadsHist::mean 1 # Outstanding read transactions
system.monitor.outstandingReadsHist::gmean 1 # Outstanding read transactions
system.monitor.outstandingWritesHist::19 0 0.00% 100.00% # Outstanding write transactions
system.monitor.outstandingWritesHist::total 100 # Outstanding write transactions
system.monitor.readTransHist::samples 100 # Histogram of read transactions per sample period
-system.monitor.readTransHist::mean 33334 # Histogram of read transactions per sample period
-system.monitor.readTransHist::gmean 33334.000000 # Histogram of read transactions per sample period
+system.monitor.readTransHist::mean 33333 # Histogram of read transactions per sample period
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system.monitor.readTransHist::stdev 0 # Histogram of read transactions per sample period
system.monitor.readTransHist::0-2047 0 0.00% 0.00% # Histogram of read transactions per sample period
system.monitor.readTransHist::2048-4095 0 0.00% 0.00% # Histogram of read transactions per sample period
sim_ticks 100000000000 # Number of ticks simulated
final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 15527580566 # Simulator tick rate (ticks/s)
-host_mem_usage 226756 # Number of bytes of host memory used
-host_seconds 6.44 # Real time elapsed on the host
+host_tick_rate 7576487056 # Simulator tick rate (ticks/s)
+host_mem_usage 230980 # Number of bytes of host memory used
+host_seconds 13.20 # Real time elapsed on the host
system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory
system.physmem.bytes_read::total 64 # Number of bytes read from this memory
-system.physmem.bytes_written::cpu 213335552 # Number of bytes written to this memory
-system.physmem.bytes_written::total 213335552 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu 213329152 # Number of bytes written to this memory
+system.physmem.bytes_written::total 213329152 # Number of bytes written to this memory
system.physmem.num_reads::cpu 1 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu 3333368 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 3333368 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu 3333268 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 3333268 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu 640 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 640 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu 2133355520 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2133355520 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu 2133356160 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2133356160 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::cpu 2133291520 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2133291520 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu 2133292160 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2133292160 # Total bandwidth to/from this memory (bytes/s)
+system.membus.throughput 2133292160 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 1 # Transaction distribution
+system.membus.trans_dist::ReadResp 1 # Transaction distribution
+system.membus.trans_dist::WriteReq 3333268 # Transaction distribution
+system.membus.trans_dist::WriteResp 3333267 # Transaction distribution
+system.membus.pkt_count_system.monitor-master 6666537 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count 6666537 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.monitor-master 213329216 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size 213329216 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 213329216 # Total data (bytes)
+system.membus.reqLayer0.occupancy 16666342328 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 16.7 # Layer utilization (%)
+system.membus.respLayer0.occupancy 3333272000 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 3.3 # Layer utilization (%)
+system.cpu.numPackets 3333269 # Number of packets generated
+system.cpu.numRetries 1 # Number of retries
+system.cpu.retryTicks 1672 # Time spent waiting due to back-pressure (ticks)
system.monitor.readBurstLengthHist::samples 1 # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::72-75 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::76-79 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
system.monitor.readBurstLengthHist::total 1 # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::samples 3333368 # Histogram of burst lengths of transmitted packets
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system.monitor.writeBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::stdev 0 # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::52-55 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::56-59 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::60-63 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::64-67 3333368 100.00% 100.00% # Histogram of burst lengths of transmitted packets
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system.monitor.writeBurstLengthHist::68-71 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::72-75 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
system.monitor.writeBurstLengthHist::76-79 0 0.00% 100.00% # Histogram of burst lengths of transmitted packets
-system.monitor.writeBurstLengthHist::total 3333368 # Histogram of burst lengths of transmitted packets
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system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::mean 640 # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.readBandwidthHist::gmean 0 # Histogram of read bandwidth per sample period (bytes/s)
system.monitor.averageReadBandwidth 640 0.00% 0.00% # Average read bandwidth (bytes/s)
system.monitor.totalReadBytes 64 # Number of bytes read
system.monitor.writeBandwidthHist::samples 100 # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::mean 2133355520 # Histogram of write bandwidth (bytes/s)
-system.monitor.writeBandwidthHist::gmean 2133355510.261974 # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::mean 2133291520 # Histogram of write bandwidth (bytes/s)
+system.monitor.writeBandwidthHist::gmean 2133291510.261604 # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::stdev 204800 # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::2.41592e+09-2.55014e+09 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::2.55014e+09-2.68435e+09 0 0.00% 100.00% # Histogram of write bandwidth (bytes/s)
system.monitor.writeBandwidthHist::total 100 # Histogram of write bandwidth (bytes/s)
-system.monitor.averageWriteBandwidth 2133355520 0.00% 0.00% # Average write bandwidth (bytes/s)
-system.monitor.totalWrittenBytes 213335552 # Number of bytes written
+system.monitor.averageWriteBandwidth 2133291520 0.00% 0.00% # Average write bandwidth (bytes/s)
+system.monitor.totalWrittenBytes 213329152 # Number of bytes written
system.monitor.readLatencyHist::samples 1 # Read request-response latency
system.monitor.readLatencyHist::mean 30000 # Read request-response latency
system.monitor.readLatencyHist::gmean 30000.000000 # Read request-response latency
system.monitor.readLatencyHist::36864-38911 0 0.00% 100.00% # Read request-response latency
system.monitor.readLatencyHist::38912-40959 0 0.00% 100.00% # Read request-response latency
system.monitor.readLatencyHist::total 1 # Read request-response latency
-system.monitor.writeLatencyHist::samples 3333367 # Write request-response latency
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system.monitor.writeLatencyHist::mean 30000.000098 # Write request-response latency
system.monitor.writeLatencyHist::gmean 30000.000081 # Write request-response latency
-system.monitor.writeLatencyHist::stdev 0.179652 # Write request-response latency
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system.monitor.writeLatencyHist::0-2047 0 0.00% 0.00% # Write request-response latency
system.monitor.writeLatencyHist::2048-4095 0 0.00% 0.00% # Write request-response latency
system.monitor.writeLatencyHist::4096-6143 0 0.00% 0.00% # Write request-response latency
system.monitor.writeLatencyHist::22528-24575 0 0.00% 0.00% # Write request-response latency
system.monitor.writeLatencyHist::24576-26623 0 0.00% 0.00% # Write request-response latency
system.monitor.writeLatencyHist::26624-28671 0 0.00% 0.00% # Write request-response latency
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system.monitor.writeLatencyHist::30720-32767 0 0.00% 100.00% # Write request-response latency
system.monitor.writeLatencyHist::32768-34815 0 0.00% 100.00% # Write request-response latency
system.monitor.writeLatencyHist::34816-36863 0 0.00% 100.00% # Write request-response latency
system.monitor.writeLatencyHist::36864-38911 0 0.00% 100.00% # Write request-response latency
system.monitor.writeLatencyHist::38912-40959 0 0.00% 100.00% # Write request-response latency
-system.monitor.writeLatencyHist::total 3333367 # Write request-response latency
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system.monitor.ittReadRead::samples 0 # Read-to-read inter transaction time
system.monitor.ittReadRead::mean nan # Read-to-read inter transaction time
system.monitor.ittReadRead::stdev nan # Read-to-read inter transaction time
system.monitor.ittReadRead::min_value 0 # Read-to-read inter transaction time
system.monitor.ittReadRead::max_value 0 # Read-to-read inter transaction time
system.monitor.ittReadRead::total 0 # Read-to-read inter transaction time
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system.monitor.ittWriteWrite::underflows 0 0.00% 0.00% # Write-to-write inter transaction time
system.monitor.ittWriteWrite::1-5000 0 0.00% 0.00% # Write-to-write inter transaction time
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system.monitor.ittWriteWrite::90001-95000 0 0.00% 100.00% # Write-to-write inter transaction time
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system.monitor.ittReqReq::underflows 0 0.00% 0.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::1-5000 1 0.00% 0.00% # Request-to-request inter transaction time
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system.monitor.ittReqReq::10001-15000 0 0.00% 0.00% # Request-to-request inter transaction time
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system.monitor.ittReqReq::30001-35000 0 0.00% 100.00% # Request-to-request inter transaction time
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system.monitor.ittReqReq::40001-45000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::45001-50000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::50001-55000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::95001-100000 0 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::overflows 1 0.00% 100.00% # Request-to-request inter transaction time
system.monitor.ittReqReq::min_value 4672 # Request-to-request inter transaction time
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system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions
system.monitor.outstandingReadsHist::mean 0 # Outstanding read transactions
system.monitor.outstandingReadsHist::gmean 0 # Outstanding read transactions
system.monitor.readTransHist::19 0 0.00% 100.00% # Histogram of read transactions per sample period
system.monitor.readTransHist::total 100 # Histogram of read transactions per sample period
system.monitor.writeTransHist::samples 100 # Histogram of read transactions per sample period
-system.monitor.writeTransHist::mean 33333.680000 # Histogram of read transactions per sample period
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system.monitor.writeTransHist::stdev 3.200000 # Histogram of read transactions per sample period
system.monitor.writeTransHist::0-2047 0 0.00% 0.00% # Histogram of read transactions per sample period
system.monitor.writeTransHist::2048-4095 0 0.00% 0.00% # Histogram of read transactions per sample period
projects / gem5.git / commitdiff