cores/liteeth_mini: adapt all phys to new migen

diff --git a/misoc/cores/liteeth_mini/phy/gmii.py b/misoc/cores/liteeth_mini/phy/gmii.py
index b08a421cc001a1d3975d5481d6f8530e1a87a2a9..bb3fc0bb9b877100e1d8b8fbb241d52bb24306cc 100644 (file)
--- a/misoc/cores/liteeth_mini/phy/gmii.py
+++ b/misoc/cores/liteeth_mini/phy/gmii.py
@@ -92,11 +92,7 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
 class LiteEthPHYGMII(Module, AutoCSR):
     def __init__(self, clock_pads, pads, with_hw_init_reset=True):
         self.dw = 8
-        self.submodules.crg = LiteEthPHYGMIICRG(clock_pads,
-                                                pads,
-                                                with_hw_init_reset)
-        self.submodules.tx = RenameClockDomains(LiteEthPHYGMIITX(pads),
-                                                "eth_tx")
-        self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIRX(pads),
-                                                "eth_rx")
+        self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset)
+        self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIITX(pads))
+        self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIRX(pads))
         self.sink, self.source = self.tx.sink, self.rx.source

diff --git a/misoc/cores/liteeth_mini/phy/mii.py b/misoc/cores/liteeth_mini/phy/mii.py
index 6ac19553a7c0de3be26930ccc6e9917fe5ae1216..c5bf5271aa2e7f5ec2d9407f63460ea275ab4a66 100644 (file)
--- a/misoc/cores/liteeth_mini/phy/mii.py
+++ b/misoc/cores/liteeth_mini/phy/mii.py
@@ -105,6 +105,6 @@ class LiteEthPHYMII(Module, AutoCSR):
     def __init__(self, clock_pads, pads, with_hw_init_reset=True):
         self.dw = 8
         self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads, with_hw_init_reset)
-        self.submodules.tx = RenameClockDomains(LiteEthPHYMIITX(pads), "eth_tx")
-        self.submodules.rx = RenameClockDomains(LiteEthPHYMIIRX(pads), "eth_rx")
+        self.submodules.tx =  ClockDomainsRenamer("eth_tx")(LiteEthPHYMIITX(pads))
+        self.submodules.rx = ClockDomainsRenamer("eth_tx")(LiteEthPHYMIIRX(pads))
         self.sink, self.source = self.tx.sink, self.rx.source

diff --git a/misoc/cores/liteeth_mini/phy/s6rgmii.py b/misoc/cores/liteeth_mini/phy/s6rgmii.py
index ccef3ac117c013180b9bf235f006abc434b48f22..1f312aceb549d256b2f8514916cb5601e99ed9d1 100644 (file)
--- a/misoc/cores/liteeth_mini/phy/s6rgmii.py
+++ b/misoc/cores/liteeth_mini/phy/s6rgmii.py
@@ -155,9 +155,7 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
 class LiteEthPHYRGMII(Module, AutoCSR):
     def __init__(self, clock_pads, pads, with_hw_init_reset=True):
         self.dw = 8
-        self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads,
-                                                 pads,
-                                                 with_hw_init_reset)
+        self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset)
         self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
         self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads))
         self.sink, self.source = self.tx.sink, self.rx.source