IntegratedBIOS: read only

diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py
index d89073da2e763319fea7b4f806a78e88de4677d5..646951664a0ce288542c5bf214f82afc8c0871c0 100644 (file)
--- a/misoclib/gensoc/__init__.py
+++ b/misoclib/gensoc/__init__.py
@@ -116,7 +116,7 @@ class GenSoC(Module):
 
 class IntegratedBIOS:
        def __init__(self, bios_size=0x8000):
-               self.submodules.rom = wishbone.SRAM(bios_size)
+               self.submodules.rom = wishbone.SRAM(bios_size, read_only=True)
                self.register_rom(self.rom.bus, bios_size)
 
        def init_bios_memory(self, data):