radeonsi: determine SPI_SHADER_Z_FORMAT outside of shader compilation
authorMarek Olšák <marek.olsak@amd.com>
Wed, 23 Dec 2015 15:02:46 +0000 (16:02 +0100)
committerMarek Olšák <marek.olsak@amd.com>
Thu, 7 Jan 2016 17:26:05 +0000 (18:26 +0100)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
src/gallium/drivers/radeonsi/si_shader.c
src/gallium/drivers/radeonsi/si_shader.h
src/gallium/drivers/radeonsi/si_state_shaders.c

index 4b49f9d6be33971506f6d3da37adf84cc1091562..b7c44b9d9aa05cbaedbd8ad7f8db193261c06a4c 100644 (file)
@@ -2247,13 +2247,6 @@ static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
                    si_shader_ctx->screen->b.family != CHIP_OLAND)
                        mask |= 0x1;
 
-               if (samplemask_index >= 0)
-                       si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
-               else if (stencil_index >= 0)
-                       si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
-               else
-                       si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
-
                /* Specify which components to enable */
                args[0] = lp_build_const_int32(base->gallivm, mask);
 
index 067704fd8384cd34b38a3e07b64869d834871212..3d14c79b803a787c1e16d6ba83f1be508e12e145 100644 (file)
@@ -278,7 +278,6 @@ struct si_shader {
        unsigned                        float_mode;
        unsigned                        scratch_bytes_per_wave;
        unsigned                        spi_shader_col_format;
-       unsigned                        spi_shader_z_format;
        unsigned                        cb_shader_mask;
        union si_shader_key             key;
 
index 41e331b6ba899da2a80fc263b831cf44edb093fa..61db8ef714c3f88bc8936ae5ec8677219922c91d 100644 (file)
@@ -431,7 +431,12 @@ static void si_shader_ps(struct si_shader *shader)
        si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
        si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
 
-       si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
+       si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
+                      info->writes_samplemask ? V_028710_SPI_SHADER_32_ABGR :
+                      info->writes_stencil ? V_028710_SPI_SHADER_32_GR :
+                      info->writes_z ? V_028710_SPI_SHADER_32_R :
+                      V_028710_SPI_SHADER_ZERO);
+
        si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
                       shader->spi_shader_col_format);
        si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);