si_shader_ctx->screen->b.family != CHIP_OLAND)
mask |= 0x1;
- if (samplemask_index >= 0)
- si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
- else if (stencil_index >= 0)
- si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
- else
- si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
-
/* Specify which components to enable */
args[0] = lp_build_const_int32(base->gallivm, mask);
si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
- si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
+ si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
+ info->writes_samplemask ? V_028710_SPI_SHADER_32_ABGR :
+ info->writes_stencil ? V_028710_SPI_SHADER_32_GR :
+ info->writes_z ? V_028710_SPI_SHADER_32_R :
+ V_028710_SPI_SHADER_ZERO);
+
si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
shader->spi_shader_col_format);
si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);