[xcc, sim, pk, opcodes] new instruction encoding!

diff --git a/riscv/decode.h b/riscv/decode.h
index 9278a35c4b50cac095654d9735978d9aa15f18c5..327da6ccf4dde7a0918ab308f313fe48b68e503a 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -37,6 +37,7 @@ const int FPRID_BITS = 5;
 const int NFPR = 1 << FPRID_BITS;
 
 const int IMM_BITS = 12;
+const int IMMLO_BITS = 5;
 const int TARGET_BITS = 25;
 const int SHAMT_BITS = 6;
 const int FUNCT_BITS = 3;
@@ -83,10 +84,20 @@ const int JUMP_ALIGN_BITS = 1;
 // note: bit fields are in little-endian order
 struct itype_t
 {
+  unsigned rd : GPRID_BITS;
+  unsigned rs1 : GPRID_BITS;
   signed imm12 : IMM_BITS;
   unsigned funct : FUNCT_BITS;
+  unsigned opcode : OPCODE_BITS;
+};
+
+struct btype_t
+{
+  unsigned immlo : IMMLO_BITS;
   unsigned rs1 : GPRID_BITS;
-  unsigned rdi : GPRID_BITS;
+  unsigned rs2 : GPRID_BITS;
+  signed immhi : IMM_BITS-IMMLO_BITS;
+  unsigned funct : FUNCT_BITS;
   unsigned opcode : OPCODE_BITS;
 };
 
@@ -98,28 +109,28 @@ struct jtype_t
 
 struct rtype_t
 {
-  unsigned rdr : GPRID_BITS;
-  unsigned functr : FUNCTR_BITS;
-  unsigned funct : FUNCT_BITS;
+  unsigned rd : GPRID_BITS;
   unsigned rs1 : GPRID_BITS;
   unsigned rs2 : GPRID_BITS;
+  unsigned functr : FUNCTR_BITS;
+  unsigned funct : FUNCT_BITS;
   unsigned opcode : OPCODE_BITS;
 };
 
-struct btype_t
+struct ltype_t
 {
+  unsigned rd : GPRID_BITS;
   unsigned bigimm : BIGIMM_BITS;
-  unsigned rdi : GPRID_BITS;
   unsigned opcode : OPCODE_BITS;
 };
 
 struct ftype_t
 {
-  unsigned rdr : FPRID_BITS;
-  unsigned rs3 : FPRID_BITS;
-  unsigned ffunct : FFUNCT_BITS;
+  unsigned rd  : FPRID_BITS;
   unsigned rs1 : FPRID_BITS;
   unsigned rs2 : FPRID_BITS;
+  unsigned rs3 : FPRID_BITS;
+  unsigned ffunct : FFUNCT_BITS;
   unsigned opcode : OPCODE_BITS;
 };
 
@@ -129,6 +140,7 @@ union insn_t
   jtype_t jtype;
   rtype_t rtype;
   btype_t btype;
+  ltype_t ltype;
   ftype_t ftype;
   uint32_t bits;
 };
@@ -160,21 +172,20 @@ private:
 // helpful macros, etc
 #define RS1 R[insn.rtype.rs1]
 #define RS2 R[insn.rtype.rs2]
-#define RDR do_writeback(R,insn.rtype.rdr)
-#define RDI do_writeback(R,insn.itype.rdi)
+#define RD do_writeback(R,insn.rtype.rd)
 #define FRS1 FR[insn.ftype.rs1]
 #define FRS2 FR[insn.ftype.rs2]
 #define FRS3 FR[insn.ftype.rs3]
-#define FRDR FR[insn.ftype.rdr]
-#define FRDI FR[insn.itype.rdi]
-#define BIGIMM insn.btype.bigimm
+#define FRD FR[insn.ftype.rd]
+#define BIGIMM insn.ltype.bigimm
 #define SIMM insn.itype.imm12
+#define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
 #define SHAMT (insn.itype.imm12 & 0x3F)
 #define SHAMTW (insn.itype.imm12 & 0x1F)
 #define TARGET insn.jtype.target
-#define BRANCH_TARGET (npc + (SIMM << BRANCH_ALIGN_BITS))
+#define BRANCH_TARGET (npc + (BIMM << BRANCH_ALIGN_BITS))
 #define JUMP_TARGET (npc + (TARGET << JUMP_ALIGN_BITS))
-#define RM ((insn.ftype.ffunct >> 1) & 3)
+#define RM (insn.ftype.ffunct & 3)
 
 #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
 #define require64 if(gprlen != 64) throw trap_illegal_instruction

diff --git a/riscv/execute.h b/riscv/execute.h
index d80c12fee948d91a5a69fcf0ef0b80828c51e091..ae8cfdf1ab70603eb84325cd9113cdb641a73d5c 100644 (file)
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -3,7 +3,7 @@ switch((insn.bits >> 0x19) & 0x7f)
 {
   case 0x0:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
@@ -33,7 +33,7 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x68:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x2:
       {
@@ -54,7 +54,7 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x69:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x2:
       {
@@ -75,166 +75,170 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x6a:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe007fe0) == 0xd40002a0)
+        if((insn.bits & 0xffff8000) == 0xd40a8000)
         {
           #include "insns/c_eq_s.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd40000a0)
+        if((insn.bits & 0xffff8000) == 0xd4028000)
         {
           #include "insns/sgninj_s.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd40001c0)
+        if((insn.bits & 0xfffffc00) == 0xd4070000)
         {
           #include "insns/cvt_s_w.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd40005e0)
+        if((insn.bits & 0xffff8000) == 0xd4000000)
         {
-          #include "insns/cvtu_s_w_rm.h"
+          #include "insns/add_s.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4000500)
+        if((insn.bits & 0xffff83e0) == 0xd42c0000)
         {
-          #include "insns/cvt_l_s_rm.h"
+          #include "insns/mff_s.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd4000000)
+        if((insn.bits & 0xfffffc00) == 0xd42e0000)
         {
-          #include "insns/add_s.h"
+          #include "insns/mtf_s.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd40005a0)
+        if((insn.bits & 0xffff8000) == 0xd4030000)
         {
-          #include "insns/cvtu_s_l_rm.h"
+          #include "insns/sgninjn_s.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd4000b00)
+        if((insn.bits & 0xfffffc00) == 0xd4078000)
         {
-          #include "insns/mff_s.h"
+          #include "insns/cvtu_s_w.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd4000b80)
+        if((insn.bits & 0xfffffc00) == 0xd4068000)
         {
-          #include "insns/mtf_s.h"
+          #include "insns/cvtu_s_l.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd40000c0)
+        if((insn.bits & 0xfffffc00) == 0xd4060000)
         {
-          #include "insns/sgninjn_s.h"
+          #include "insns/cvt_s_l.h"
           break;
         }
-        if((insn.bits & 0xfe0067e0) == 0xd4000440)
+        if((insn.bits & 0xffff8000) == 0xd4008000)
         {
-          #include "insns/mul_s_rm.h"
+          #include "insns/sub_s.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4000520)
+        if((insn.bits & 0xfffffc00) == 0xd4020000)
         {
-          #include "insns/cvtu_l_s_rm.h"
+          #include "insns/sqrt_s.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd40005c0)
+        if((insn.bits & 0xffff8000) == 0xd40b0000)
         {
-          #include "insns/cvt_s_w_rm.h"
+          #include "insns/c_lt_s.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd40001e0)
+        if((insn.bits & 0xffff8000) == 0xd4038000)
         {
-          #include "insns/cvtu_s_w.h"
+          #include "insns/sgnmul_s.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd40001a0)
+        if((insn.bits & 0xffff8000) == 0xd4018000)
         {
-          #include "insns/cvtu_s_l.h"
+          #include "insns/div_s.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4000480)
+        if((insn.bits & 0xfffffc00) == 0xd4098000)
         {
-          #include "insns/sqrt_s_rm.h"
+          #include "insns/cvt_s_d.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4000660)
+        if((insn.bits & 0xffff8000) == 0xd40b8000)
         {
-          #include "insns/cvt_s_d_rm.h"
+          #include "insns/c_le_s.h"
           break;
         }
-        if((insn.bits & 0xfe0067e0) == 0xd4000420)
+        if((insn.bits & 0xffff8000) == 0xd4010000)
         {
-          #include "insns/sub_s_rm.h"
+          #include "insns/mul_s.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd4000180)
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        if((insn.bits & 0xffcffc00) == 0xd4478000)
         {
-          #include "insns/cvt_s_l.h"
+          #include "insns/cvtu_s_w_rm.h"
           break;
         }
-        if((insn.bits & 0xfe0067e0) == 0xd4000460)
+        if((insn.bits & 0xffcffc00) == 0xd4440000)
         {
-          #include "insns/div_s_rm.h"
+          #include "insns/cvt_l_s_rm.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd4000020)
+        if((insn.bits & 0xffcffc00) == 0xd4468000)
         {
-          #include "insns/sub_s.h"
+          #include "insns/cvtu_s_l_rm.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4000580)
+        if((insn.bits & 0xffcf8000) == 0xd4410000)
         {
-          #include "insns/cvt_s_l_rm.h"
+          #include "insns/mul_s_rm.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd4000080)
+        if((insn.bits & 0xffcffc00) == 0xd4448000)
         {
-          #include "insns/sqrt_s.h"
+          #include "insns/cvtu_l_s_rm.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd40002c0)
+        if((insn.bits & 0xffcffc00) == 0xd4470000)
         {
-          #include "insns/c_lt_s.h"
+          #include "insns/cvt_s_w_rm.h"
           break;
         }
-        if((insn.bits & 0xfe0067e0) == 0xd4000400)
+        if((insn.bits & 0xffcffc00) == 0xd4420000)
         {
-          #include "insns/add_s_rm.h"
+          #include "insns/sqrt_s_rm.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd40000e0)
+        if((insn.bits & 0xffcffc00) == 0xd4498000)
         {
-          #include "insns/sgnmul_s.h"
+          #include "insns/cvt_s_d_rm.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd4000060)
+        if((insn.bits & 0xffcf8000) == 0xd4408000)
         {
-          #include "insns/div_s.h"
+          #include "insns/sub_s_rm.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd4000260)
+        if((insn.bits & 0xffcf8000) == 0xd4418000)
         {
-          #include "insns/cvt_s_d.h"
+          #include "insns/div_s_rm.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd40002e0)
+        if((insn.bits & 0xffcffc00) == 0xd4460000)
         {
-          #include "insns/c_le_s.h"
+          #include "insns/cvt_s_l_rm.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd4000040)
+        if((insn.bits & 0xffcf8000) == 0xd4400000)
         {
-          #include "insns/mul_s.h"
+          #include "insns/add_s_rm.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4000540)
+        if((insn.bits & 0xffcffc00) == 0xd4450000)
         {
           #include "insns/cvt_w_s_rm.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4000560)
+        if((insn.bits & 0xffcffc00) == 0xd4458000)
         {
           #include "insns/cvtu_w_s_rm.h"
           break;
@@ -243,162 +247,166 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x6:
       {
-        if((insn.bits & 0xfe0fffe0) == 0xd4006b00)
+        if((insn.bits & 0xffff83e0) == 0xd5ac0000)
         {
           #include "insns/mff_d.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd40060a0)
+        if((insn.bits & 0xffff8000) == 0xd5828000)
         {
           #include "insns/sgninj_d.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4006580)
-        {
-          #include "insns/cvt_d_l_rm.h"
-          break;
-        }
-        if((insn.bits & 0xfe007fe0) == 0xd4006060)
+        if((insn.bits & 0xffff8000) == 0xd5818000)
         {
           #include "insns/div_d.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd40062a0)
+        if((insn.bits & 0xffff8000) == 0xd58a8000)
         {
           #include "insns/c_eq_d.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd40061a0)
+        if((insn.bits & 0xfffffc00) == 0xd5868000)
         {
           #include "insns/cvtu_d_l.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4006540)
+        if((insn.bits & 0xfffffc00) == 0xd5878000)
         {
-          #include "insns/cvt_w_d_rm.h"
+          #include "insns/cvtu_d_w.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd40061e0)
+        if((insn.bits & 0xffff83e0) == 0xd5ac8000)
         {
-          #include "insns/cvtu_d_w.h"
+          #include "insns/mffl_d.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd4006b20)
+        if((insn.bits & 0xffff8000) == 0xd5838000)
         {
-          #include "insns/mffl_d.h"
+          #include "insns/sgnmul_d.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd4006000)
+        if((insn.bits & 0xffff8000) == 0xd5800000)
         {
           #include "insns/add_d.h"
           break;
         }
-        if((insn.bits & 0xfe0fffe0) == 0xd4006b40)
+        if((insn.bits & 0xffff83e0) == 0xd5ad0000)
         {
           #include "insns/mffh_d.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd40062e0)
+        if((insn.bits & 0xffff8000) == 0xd58b8000)
         {
           #include "insns/c_le_d.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd40060e0)
+        if((insn.bits & 0xffff8000) == 0xd5830000)
         {
-          #include "insns/sgnmul_d.h"
+          #include "insns/sgninjn_d.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4006560)
+        if((insn.bits & 0xffff8000) == 0xd5be0000)
         {
-          #include "insns/cvtu_w_d_rm.h"
+          #include "insns/mtflh_d.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4006480)
+        if((insn.bits & 0xffff8000) == 0xd5808000)
         {
-          #include "insns/sqrt_d_rm.h"
+          #include "insns/sub_d.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd40060c0)
+        if((insn.bits & 0xfffffc00) == 0xd5ae0000)
         {
-          #include "insns/sgninjn_d.h"
+          #include "insns/mtf_d.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd40065a0)
+        if((insn.bits & 0xfffffc00) == 0xd5820000)
         {
-          #include "insns/cvtu_d_l_rm.h"
+          #include "insns/sqrt_d.h"
           break;
         }
-        if((insn.bits & 0xfe0067e0) == 0xd4006400)
+        if((insn.bits & 0xfffffc00) == 0xd5880000)
         {
-          #include "insns/add_d_rm.h"
+          #include "insns/cvt_d_s.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4006500)
+        if((insn.bits & 0xfffffc00) == 0xd5870000)
         {
-          #include "insns/cvt_l_d_rm.h"
+          #include "insns/cvt_d_w.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd4006f80)
+        if((insn.bits & 0xfffffc00) == 0xd5860000)
         {
-          #include "insns/mtflh_d.h"
+          #include "insns/cvt_d_l.h"
           break;
         }
-        if((insn.bits & 0xfff067e0) == 0xd4006520)
+        if((insn.bits & 0xffff8000) == 0xd5810000)
         {
-          #include "insns/cvtu_l_d_rm.h"
+          #include "insns/mul_d.h"
           break;
         }
-        if((insn.bits & 0xfe0067e0) == 0xd4006440)
+        if((insn.bits & 0xffff8000) == 0xd58b0000)
         {
-          #include "insns/mul_d_rm.h"
+          #include "insns/c_lt_d.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd4006020)
+        #include "insns/unimp.h"
+      }
+      case 0x7:
+      {
+        if((insn.bits & 0xffcffc00) == 0xd5c60000)
         {
-          #include "insns/sub_d.h"
+          #include "insns/cvt_d_l_rm.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd4006b80)
+        if((insn.bits & 0xffcffc00) == 0xd5c50000)
         {
-          #include "insns/mtf_d.h"
+          #include "insns/cvt_w_d_rm.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd4006080)
+        if((insn.bits & 0xffcffc00) == 0xd5c58000)
         {
-          #include "insns/sqrt_d.h"
+          #include "insns/cvtu_w_d_rm.h"
           break;
         }
-        if((insn.bits & 0xfe0067e0) == 0xd4006460)
+        if((insn.bits & 0xffcffc00) == 0xd5c20000)
         {
-          #include "insns/div_d_rm.h"
+          #include "insns/sqrt_d_rm.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd4006200)
+        if((insn.bits & 0xffcffc00) == 0xd5c68000)
         {
-          #include "insns/cvt_d_s.h"
+          #include "insns/cvtu_d_l_rm.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd40061c0)
+        if((insn.bits & 0xffcf8000) == 0xd5c00000)
         {
-          #include "insns/cvt_d_w.h"
+          #include "insns/add_d_rm.h"
           break;
         }
-        if((insn.bits & 0xfff07fe0) == 0xd4006180)
+        if((insn.bits & 0xffcffc00) == 0xd5c40000)
         {
-          #include "insns/cvt_d_l.h"
+          #include "insns/cvt_l_d_rm.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd4006040)
+        if((insn.bits & 0xffcffc00) == 0xd5c48000)
         {
-          #include "insns/mul_d.h"
+          #include "insns/cvtu_l_d_rm.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xd40062c0)
+        if((insn.bits & 0xffcf8000) == 0xd5c10000)
         {
-          #include "insns/c_lt_d.h"
+          #include "insns/mul_d_rm.h"
           break;
         }
-        if((insn.bits & 0xfe0067e0) == 0xd4006420)
+        if((insn.bits & 0xffcf8000) == 0xd5c18000)
+        {
+          #include "insns/div_d_rm.h"
+          break;
+        }
+        if((insn.bits & 0xffcf8000) == 0xd5c08000)
         {
           #include "insns/sub_d_rm.h"
           break;
@@ -412,34 +420,43 @@ switch((insn.bits >> 0x19) & 0x7f)
     }
     break;
   }
-  case 0x6c:
+  case 0x6b:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe006400) == 0xd8000400)
+        if((insn.bits & 0xffffffe0) == 0xd6008000)
         {
-          #include "insns/madd_s_rm.h"
+          #include "insns/di.h"
           break;
         }
-        if((insn.bits & 0xfe007c00) == 0xd8000000)
+        if((insn.bits & 0xffffffe0) == 0xd6000000)
         {
-          #include "insns/madd_s.h"
+          #include "insns/ei.h"
           break;
         }
         #include "insns/unimp.h"
       }
-      case 0x6:
+      case 0x1:
       {
-        if((insn.bits & 0xfe006400) == 0xd8006400)
+        if((insn.bits & 0xffff83e0) == 0xd6400000)
         {
-          #include "insns/madd_d_rm.h"
+          #include "insns/mfpcr.h"
           break;
         }
-        if((insn.bits & 0xfe007c00) == 0xd8006000)
+        if((insn.bits & 0xffff801f) == 0xd6408000)
         {
-          #include "insns/madd_d.h"
+          #include "insns/mtpcr.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x2:
+      {
+        if((insn.bits & 0xffffffff) == 0xd6800000)
+        {
+          #include "insns/eret.h"
           break;
         }
         #include "insns/unimp.h"
@@ -451,38 +468,77 @@ switch((insn.bits >> 0x19) & 0x7f)
     }
     break;
   }
-  case 0x6d:
+  case 0x6c:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe006400) == 0xda000400)
+        if((insn.bits & 0xfff00000) == 0xd8000000)
         {
-          #include "insns/msub_s_rm.h"
+          #include "insns/madd_s.h"
           break;
         }
-        if((insn.bits & 0xfe007c00) == 0xda000000)
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        #include "insns/madd_s_rm.h"
+        break;
+      }
+      case 0x6:
+      {
+        if((insn.bits & 0xfff00000) == 0xd9800000)
         {
-          #include "insns/msub_s.h"
+          #include "insns/madd_d.h"
           break;
         }
         #include "insns/unimp.h"
       }
-      case 0x6:
+      case 0x7:
       {
-        if((insn.bits & 0xfe007c00) == 0xda006000)
+        #include "insns/madd_d_rm.h"
+        break;
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
+    }
+    break;
+  }
+  case 0x6d:
+  {
+    switch((insn.bits >> 0x16) & 0x7)
+    {
+      case 0x0:
+      {
+        if((insn.bits & 0xfff00000) == 0xda000000)
         {
-          #include "insns/msub_d.h"
+          #include "insns/msub_s.h"
           break;
         }
-        if((insn.bits & 0xfe006400) == 0xda006400)
+        #include "insns/unimp.h"
+      }
+      case 0x1:
+      {
+        #include "insns/msub_s_rm.h"
+        break;
+      }
+      case 0x6:
+      {
+        if((insn.bits & 0xfff00000) == 0xdb800000)
         {
-          #include "insns/msub_d_rm.h"
+          #include "insns/msub_d.h"
           break;
         }
         #include "insns/unimp.h"
       }
+      case 0x7:
+      {
+        #include "insns/msub_d_rm.h"
+        break;
+      }
       default:
       {
         #include "insns/unimp.h"
@@ -492,36 +548,36 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x6e:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe007c00) == 0xdc000000)
+        if((insn.bits & 0xfff00000) == 0xdc000000)
         {
           #include "insns/nmsub_s.h"
           break;
         }
-        if((insn.bits & 0xfe006400) == 0xdc000400)
-        {
-          #include "insns/nmsub_s_rm.h"
-          break;
-        }
         #include "insns/unimp.h"
       }
+      case 0x1:
+      {
+        #include "insns/nmsub_s_rm.h"
+        break;
+      }
       case 0x6:
       {
-        if((insn.bits & 0xfe007c00) == 0xdc006000)
+        if((insn.bits & 0xfff00000) == 0xdd800000)
         {
           #include "insns/nmsub_d.h"
           break;
         }
-        if((insn.bits & 0xfe006400) == 0xdc006400)
-        {
-          #include "insns/nmsub_d_rm.h"
-          break;
-        }
         #include "insns/unimp.h"
       }
+      case 0x7:
+      {
+        #include "insns/nmsub_d_rm.h"
+        break;
+      }
       default:
       {
         #include "insns/unimp.h"
@@ -531,36 +587,36 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x6f:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe007c00) == 0xde000000)
+        if((insn.bits & 0xfff00000) == 0xde000000)
         {
           #include "insns/nmadd_s.h"
           break;
         }
-        if((insn.bits & 0xfe006400) == 0xde000400)
-        {
-          #include "insns/nmadd_s_rm.h"
-          break;
-        }
         #include "insns/unimp.h"
       }
+      case 0x1:
+      {
+        #include "insns/nmadd_s_rm.h"
+        break;
+      }
       case 0x6:
       {
-        if((insn.bits & 0xfe007c00) == 0xde006000)
+        if((insn.bits & 0xfff00000) == 0xdf800000)
         {
           #include "insns/nmadd_d.h"
           break;
         }
-        if((insn.bits & 0xfe006400) == 0xde006400)
-        {
-          #include "insns/nmadd_d_rm.h"
-          break;
-        }
         #include "insns/unimp.h"
       }
+      case 0x7:
+      {
+        #include "insns/nmadd_d_rm.h"
+        break;
+      }
       default:
       {
         #include "insns/unimp.h"
@@ -573,9 +629,35 @@ switch((insn.bits >> 0x19) & 0x7f)
     #include "insns/lui.h"
     break;
   }
+  case 0x72:
+  {
+    switch((insn.bits >> 0x16) & 0x7)
+    {
+      case 0x0:
+      {
+        #include "insns/jalr_c.h"
+        break;
+      }
+      case 0x1:
+      {
+        #include "insns/jalr_r.h"
+        break;
+      }
+      case 0x2:
+      {
+        #include "insns/jalr_j.h"
+        break;
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
+    }
+    break;
+  }
   case 0x73:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
@@ -616,7 +698,7 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x74:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
@@ -650,17 +732,17 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x7:
       {
-        if((insn.bits & 0xfe007fc0) == 0xe8007080)
+        if((insn.bits & 0xffff0000) == 0xe9c20000)
         {
           #include "insns/srli.h"
           break;
         }
-        if((insn.bits & 0xfe007fc0) == 0xe80070c0)
+        if((insn.bits & 0xffff0000) == 0xe9c30000)
         {
           #include "insns/srai.h"
           break;
         }
-        if((insn.bits & 0xfe007fc0) == 0xe8007040)
+        if((insn.bits & 0xffff0000) == 0xe9c10000)
         {
           #include "insns/slli.h"
           break;
@@ -676,46 +758,46 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x75:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe007fe0) == 0xea000000)
+        if((insn.bits & 0xffff8000) == 0xea000000)
         {
           #include "insns/add.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea0000e0)
+        if((insn.bits & 0xffff8000) == 0xea038000)
         {
           #include "insns/nor.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea000060)
+        if((insn.bits & 0xffff8000) == 0xea018000)
         {
           #include "insns/sltu.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea0000c0)
+        if((insn.bits & 0xffff8000) == 0xea030000)
         {
           #include "insns/xor.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea000020)
+        if((insn.bits & 0xffff8000) == 0xea008000)
         {
           #include "insns/sub.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea0000a0)
+        if((insn.bits & 0xffff8000) == 0xea028000)
         {
           #include "insns/or.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea000040)
+        if((insn.bits & 0xffff8000) == 0xea010000)
         {
           #include "insns/slt.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea000080)
+        if((insn.bits & 0xffff8000) == 0xea020000)
         {
           #include "insns/and.h"
           break;
@@ -724,37 +806,37 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x1:
       {
-        if((insn.bits & 0xfe007fe0) == 0xea001000)
+        if((insn.bits & 0xffff8000) == 0xea400000)
         {
           #include "insns/mul.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea001080)
+        if((insn.bits & 0xffff8000) == 0xea420000)
         {
           #include "insns/div.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea0010c0)
+        if((insn.bits & 0xffff8000) == 0xea430000)
         {
           #include "insns/rem.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea001040)
+        if((insn.bits & 0xffff8000) == 0xea410000)
         {
           #include "insns/mulh.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea0010e0)
+        if((insn.bits & 0xffff8000) == 0xea438000)
         {
           #include "insns/remu.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea001060)
+        if((insn.bits & 0xffff8000) == 0xea418000)
         {
           #include "insns/mulhu.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea0010a0)
+        if((insn.bits & 0xffff8000) == 0xea428000)
         {
           #include "insns/divu.h"
           break;
@@ -763,17 +845,17 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x7:
       {
-        if((insn.bits & 0xfe007fe0) == 0xea0070c0)
+        if((insn.bits & 0xffff8000) == 0xebc30000)
         {
           #include "insns/sra.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea007080)
+        if((insn.bits & 0xffff8000) == 0xebc20000)
         {
           #include "insns/srl.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xea007040)
+        if((insn.bits & 0xffff8000) == 0xebc10000)
         {
           #include "insns/sll.h"
           break;
@@ -789,7 +871,7 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x76:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
@@ -798,17 +880,17 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x7:
       {
-        if((insn.bits & 0xfe007fe0) == 0xec007040)
+        if((insn.bits & 0xffff8000) == 0xedc10000)
         {
           #include "insns/slliw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xec007080)
+        if((insn.bits & 0xffff8000) == 0xedc20000)
         {
           #include "insns/srliw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xec0070c0)
+        if((insn.bits & 0xffff8000) == 0xedc30000)
         {
           #include "insns/sraiw.h"
           break;
@@ -824,16 +906,16 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x77:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfe007fe0) == 0xee000000)
+        if((insn.bits & 0xffff8000) == 0xee000000)
         {
           #include "insns/addw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xee000020)
+        if((insn.bits & 0xffff8000) == 0xee008000)
         {
           #include "insns/subw.h"
           break;
@@ -842,37 +924,37 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x1:
       {
-        if((insn.bits & 0xfe007fe0) == 0xee0010e0)
+        if((insn.bits & 0xffff8000) == 0xee438000)
         {
           #include "insns/remuw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xee0010a0)
+        if((insn.bits & 0xffff8000) == 0xee428000)
         {
           #include "insns/divuw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xee001060)
+        if((insn.bits & 0xffff8000) == 0xee418000)
         {
           #include "insns/mulhuw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xee001000)
+        if((insn.bits & 0xffff8000) == 0xee400000)
         {
           #include "insns/mulw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xee0010c0)
+        if((insn.bits & 0xffff8000) == 0xee430000)
         {
           #include "insns/remw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xee001040)
+        if((insn.bits & 0xffff8000) == 0xee410000)
         {
           #include "insns/mulhw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xee001080)
+        if((insn.bits & 0xffff8000) == 0xee420000)
         {
           #include "insns/divw.h"
           break;
@@ -881,17 +963,17 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x7:
       {
-        if((insn.bits & 0xfe007fe0) == 0xee007080)
+        if((insn.bits & 0xffff8000) == 0xefc20000)
         {
           #include "insns/srlw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xee0070c0)
+        if((insn.bits & 0xffff8000) == 0xefc30000)
         {
           #include "insns/sraw.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xee007040)
+        if((insn.bits & 0xffff8000) == 0xefc10000)
         {
           #include "insns/sllw.h"
           break;
@@ -907,7 +989,7 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x78:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
@@ -946,7 +1028,7 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x7:
       {
-        if((insn.bits & 0xfff07000) == 0xf0007000)
+        if((insn.bits & 0xffc0001f) == 0xf1c00000)
         {
           #include "insns/synci.h"
           break;
@@ -962,7 +1044,7 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x79:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
@@ -993,46 +1075,46 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x7a:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x2:
       {
-        if((insn.bits & 0xfe007fe0) == 0xf4002040)
+        if((insn.bits & 0xffff8000) == 0xf4828000)
         {
-          #include "insns/amow_and.h"
+          #include "insns/amow_max.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf4002080)
+        if((insn.bits & 0xffff8000) == 0xf4810000)
         {
-          #include "insns/amow_min.h"
+          #include "insns/amow_and.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf4002060)
+        if((insn.bits & 0xffff8000) == 0xf4820000)
         {
-          #include "insns/amow_or.h"
+          #include "insns/amow_min.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf40020a0)
+        if((insn.bits & 0xffff8000) == 0xf4818000)
         {
-          #include "insns/amow_max.h"
+          #include "insns/amow_or.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf40020c0)
+        if((insn.bits & 0xffff8000) == 0xf4830000)
         {
           #include "insns/amow_minu.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf4002000)
+        if((insn.bits & 0xffff8000) == 0xf4800000)
         {
           #include "insns/amow_add.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf4002020)
+        if((insn.bits & 0xffff8000) == 0xf4808000)
         {
           #include "insns/amow_swap.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf40020e0)
+        if((insn.bits & 0xffff8000) == 0xf4838000)
         {
           #include "insns/amow_maxu.h"
           break;
@@ -1041,42 +1123,42 @@ switch((insn.bits >> 0x19) & 0x7f)
       }
       case 0x3:
       {
-        if((insn.bits & 0xfe007fe0) == 0xf4003000)
+        if((insn.bits & 0xffff8000) == 0xf4c00000)
         {
           #include "insns/amo_add.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf4003020)
+        if((insn.bits & 0xffff8000) == 0xf4c08000)
         {
           #include "insns/amo_swap.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf4003060)
+        if((insn.bits & 0xffff8000) == 0xf4c18000)
         {
           #include "insns/amo_or.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf40030a0)
+        if((insn.bits & 0xffff8000) == 0xf4c28000)
         {
           #include "insns/amo_max.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf4003080)
+        if((insn.bits & 0xffff8000) == 0xf4c20000)
         {
           #include "insns/amo_min.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf40030c0)
+        if((insn.bits & 0xffff8000) == 0xf4c30000)
         {
           #include "insns/amo_minu.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf4003040)
+        if((insn.bits & 0xffff8000) == 0xf4c10000)
         {
           #include "insns/amo_and.h"
           break;
         }
-        if((insn.bits & 0xfe007fe0) == 0xf40030e0)
+        if((insn.bits & 0xffff8000) == 0xf4c38000)
         {
           #include "insns/amo_maxu.h"
           break;
@@ -1092,137 +1174,49 @@ switch((insn.bits >> 0x19) & 0x7f)
   }
   case 0x7b:
   {
-    switch((insn.bits >> 0xc) & 0x7)
+    switch((insn.bits >> 0x16) & 0x7)
     {
       case 0x0:
       {
-        if((insn.bits & 0xfff07fe0) == 0xf6000000)
-        {
-          #include "insns/jalr_c.h"
-          break;
-        }
-        if((insn.bits & 0xfff07fe0) == 0xf6000040)
-        {
-          #include "insns/jalr_j.h"
-          break;
-        }
-        if((insn.bits & 0xfff07fe0) == 0xf6000020)
-        {
-          #include "insns/jalr_r.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x1:
-      {
-        if((insn.bits & 0xffffffe0) == 0xf6001000)
+        if((insn.bits & 0xffffffe0) == 0xf6000000)
         {
           #include "insns/rdnpc.h"
           break;
         }
         #include "insns/unimp.h"
       }
-      case 0x2:
+      case 0x1:
       {
-        if((insn.bits & 0xfe0fffe0) == 0xf6002000)
+        if((insn.bits & 0xffff83e0) == 0xf6400000)
         {
           #include "insns/mfcr.h"
           break;
         }
-        #include "insns/unimp.h"
-      }
-      case 0x3:
-      {
-        if((insn.bits & 0xfe007fff) == 0xf6003000)
+        if((insn.bits & 0xffff801f) == 0xf6408000)
         {
           #include "insns/mtcr.h"
           break;
         }
         #include "insns/unimp.h"
       }
-      case 0x4:
+      case 0x2:
       {
-        if((insn.bits & 0xffffffff) == 0xf6004000)
+        if((insn.bits & 0xffffffff) == 0xf6800000)
         {
           #include "insns/sync.h"
           break;
         }
         #include "insns/unimp.h"
       }
-      case 0x5:
+      case 0x3:
       {
-        if((insn.bits & 0xfffff000) == 0xf6005000)
+        if((insn.bits & 0xffc003ff) == 0xf6c00000)
         {
           #include "insns/syscall.h"
           break;
         }
         #include "insns/unimp.h"
       }
-      case 0x6:
-      {
-        if((insn.bits & 0xfffff000) == 0xf6006000)
-        {
-          #include "insns/break.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      default:
-      {
-        #include "insns/unimp.h"
-      }
-    }
-    break;
-  }
-  case 0x7e:
-  {
-    switch((insn.bits >> 0xc) & 0x7)
-    {
-      case 0x0:
-      {
-        if((insn.bits & 0xffffffe0) == 0xfc000000)
-        {
-          #include "insns/ei.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x1:
-      {
-        if((insn.bits & 0xffffffe0) == 0xfc001000)
-        {
-          #include "insns/di.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x2:
-      {
-        if((insn.bits & 0xffffffff) == 0xfc002000)
-        {
-          #include "insns/eret.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x4:
-      {
-        if((insn.bits & 0xfe0fffe0) == 0xfc004000)
-        {
-          #include "insns/mfpcr.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
-      case 0x5:
-      {
-        if((insn.bits & 0xfe007fff) == 0xfc005000)
-        {
-          #include "insns/mtpcr.h"
-          break;
-        }
-        #include "insns/unimp.h"
-      }
       default:
       {
         #include "insns/unimp.h"

diff --git a/riscv/insns/add.h b/riscv/insns/add.h
index f7dede9f3de53530cf896ff7a103a97d513ad16e..a7ec78d0986aebbdb22406dd29421c556aebfd13 100644 (file)
--- a/riscv/insns/add.h
+++ b/riscv/insns/add.h
@@ -1,2 +1,2 @@
 require64;
-RDR = RS1 + RS2;
+RD = RS1 + RS2;

diff --git a/riscv/insns/add_d.h b/riscv/insns/add_d.h
index eae2c6ea2fc2ba82d602b7935388cb5ba3d43e79..f467eb6aa501999b89e9fb6bf10804e3183e126d 100644 (file)
--- a/riscv/insns/add_d.h
+++ b/riscv/insns/add_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f64_add(FRS1, FRS2);
+FRD = f64_add(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/add_d_rm.h b/riscv/insns/add_d_rm.h
index 2266a31acb45e731f5f35bf9b449aea16ee148c0..48c76a77ac5b3e5bec563ff63ae7d81eae2e44a0 100644 (file)
--- a/riscv/insns/add_d_rm.h
+++ b/riscv/insns/add_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f64_add(FRS1, FRS2);
+FRD = f64_add(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/add_s.h b/riscv/insns/add_s.h
index 7c9dc5073b811e32aecf012680a2ae94943d25ea..edae853790cae60a5e99f0b9e98b4b596547056a 100644 (file)
--- a/riscv/insns/add_s.h
+++ b/riscv/insns/add_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f32_add(FRS1, FRS2);
+FRD = f32_add(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/add_s_rm.h b/riscv/insns/add_s_rm.h
index 2c9730c36a08e2f7041eab255052da7ec96fd78d..2fd5429c481d54f95087ba41460354ad66015c27 100644 (file)
--- a/riscv/insns/add_s_rm.h
+++ b/riscv/insns/add_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f32_add(FRS1, FRS2);
+FRD = f32_add(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/addi.h b/riscv/insns/addi.h
index e813eaec63c261b756638a92eb0510e7aa2a7e4a..2b9bae3a046ed5d1209499d1f8cd9e6b576b1dfd 100644 (file)
--- a/riscv/insns/addi.h
+++ b/riscv/insns/addi.h
@@ -1,2 +1,2 @@
 require64;
-RDI = SIMM + RS1;
+RD = SIMM + RS1;

diff --git a/riscv/insns/addiw.h b/riscv/insns/addiw.h
index 6dfe5b1fab5643d3c8d3648e6234d3b2a03c9e00..cf97d342432921a6341bd88547d8c8aecad000e0 100644 (file)
--- a/riscv/insns/addiw.h
+++ b/riscv/insns/addiw.h
@@ -1 +1 @@
-RDI = sext32(SIMM + RS1);
+RD = sext32(SIMM + RS1);

diff --git a/riscv/insns/addw.h b/riscv/insns/addw.h
index d95c95f8b449464cd78bfa94488c0f1e35b0f85b..f8715e36c46ffcc90de48217ed358ffa67e14561 100644 (file)
--- a/riscv/insns/addw.h
+++ b/riscv/insns/addw.h
@@ -1,2 +1,2 @@
-RDR = sext32(RS1 + RS2);
+RD = sext32(RS1 + RS2);
 

diff --git a/riscv/insns/amo_add.h b/riscv/insns/amo_add.h
index 18f6f4e047a95557c2171bec5719a5beb68dff00..3b59ffd7a609e77073499e05a01c1c46cb33fe2a 100644 (file)
--- a/riscv/insns/amo_add.h
+++ b/riscv/insns/amo_add.h
@@ -1,4 +1,4 @@
 require64;
 reg_t v = mmu.load_uint64(RS1);
 mmu.store_uint64(RS1, RS2 + v);
-RDR = v;
+RD = v;

diff --git a/riscv/insns/amo_and.h b/riscv/insns/amo_and.h
index dd187df142a5d5a25bc2de84d2be155cfcf6ccb0..729550194e0ad85ee45f29781e0eb166625c5e62 100644 (file)
--- a/riscv/insns/amo_and.h
+++ b/riscv/insns/amo_and.h
@@ -1,4 +1,4 @@
 require64;
 reg_t v = mmu.load_uint64(RS1);
 mmu.store_uint64(RS1, RS2 & v);
-RDR = v;
+RD = v;

diff --git a/riscv/insns/amo_max.h b/riscv/insns/amo_max.h
index 296b86a620ffcb4383deaf9900100ae7159673ce..f67f1a3038e4bdaf9ba102dd854e07b83b882349 100644 (file)
--- a/riscv/insns/amo_max.h
+++ b/riscv/insns/amo_max.h
@@ -1,4 +1,4 @@
 require64;
 sreg_t v = mmu.load_int64(RS1);
 mmu.store_uint64(RS1, std::max(sreg_t(RS2),v));
-RDR = v;
+RD = v;

diff --git a/riscv/insns/amo_maxu.h b/riscv/insns/amo_maxu.h
index 533dde3ace98cb3e659ce22638d31d541de2d9b3..9a3d9f62f16c8faca26f505dcffba3d0d09f10f4 100644 (file)
--- a/riscv/insns/amo_maxu.h
+++ b/riscv/insns/amo_maxu.h
@@ -1,4 +1,4 @@
 require64;
 reg_t v = mmu.load_uint64(RS1);
 mmu.store_uint64(RS1, std::max(RS2,v));
-RDR = v;
+RD = v;

diff --git a/riscv/insns/amo_min.h b/riscv/insns/amo_min.h
index 7244e87d4ee8a84f66344d99cc30f742d6113014..4acfe74065219e8404d7f1cfe981a23ddb30f6b1 100644 (file)
--- a/riscv/insns/amo_min.h
+++ b/riscv/insns/amo_min.h
@@ -1,4 +1,4 @@
 require64;
 sreg_t v = mmu.load_int64(RS1);
 mmu.store_uint64(RS1, std::min(sreg_t(RS2),v));
-RDR = v;
+RD = v;

diff --git a/riscv/insns/amo_minu.h b/riscv/insns/amo_minu.h
index 3e365ab4a87153d92dbcbc2a8ca207ed2390e664..5af3b9da8e2c0dcd10e5b2203fbf03ed5381800b 100644 (file)
--- a/riscv/insns/amo_minu.h
+++ b/riscv/insns/amo_minu.h
@@ -1,4 +1,4 @@
 require64;
 reg_t v = mmu.load_uint64(RS1);
 mmu.store_uint64(RS1, std::min(RS2,v));
-RDR = v;
+RD = v;

diff --git a/riscv/insns/amo_or.h b/riscv/insns/amo_or.h
index e7d81a8cd0d43ae3398ae1d4c6a0194a7c7c488e..df4f2fec5c559f09f0ff2410ad5d1ddb38748481 100644 (file)
--- a/riscv/insns/amo_or.h
+++ b/riscv/insns/amo_or.h
@@ -1,4 +1,4 @@
 require64;
 reg_t v = mmu.load_uint64(RS1);
 mmu.store_uint64(RS1, RS2 | v);
-RDR = v;
+RD = v;

diff --git a/riscv/insns/amo_swap.h b/riscv/insns/amo_swap.h
index 0ee4ea21f36146920e1b4662ee013a06175cf5e8..688905531fc0b0d820d945deee0a722f5284a354 100644 (file)
--- a/riscv/insns/amo_swap.h
+++ b/riscv/insns/amo_swap.h
@@ -1,4 +1,4 @@
 require64;
 reg_t v = mmu.load_uint64(RS1);
 mmu.store_uint64(RS1, RS2);
-RDR = v;
+RD = v;

diff --git a/riscv/insns/amow_add.h b/riscv/insns/amow_add.h
index a55ddf9a3ad7e32678d00fc0b358710b61aea642..033b3c8007686667334ce7fde559c680667bf4fc 100644 (file)
--- a/riscv/insns/amow_add.h
+++ b/riscv/insns/amow_add.h
@@ -1,3 +1,3 @@
 reg_t v = mmu.load_int32(RS1);
 mmu.store_uint32(RS1, RS2 + v);
-RDR = v;
+RD = v;

diff --git a/riscv/insns/amow_and.h b/riscv/insns/amow_and.h
index f1670bde03a2ce28549e665b5c63b2e23434793d..18a92494856d83f4f846b514d6338fb74b936db7 100644 (file)
--- a/riscv/insns/amow_and.h
+++ b/riscv/insns/amow_and.h
@@ -1,3 +1,3 @@
 reg_t v = mmu.load_int32(RS1);
 mmu.store_uint32(RS1, RS2 & v);
-RDR = v;
+RD = v;

diff --git a/riscv/insns/amow_max.h b/riscv/insns/amow_max.h
index c4854d1662139dd5338919a49c6bc85dd37033e2..ff9c2da7923787f9232914074deca2008fbc36eb 100644 (file)
--- a/riscv/insns/amow_max.h
+++ b/riscv/insns/amow_max.h
@@ -1,3 +1,3 @@
 int32_t v = mmu.load_int32(RS1);
 mmu.store_uint32(RS1, std::max(int32_t(RS2),v));
-RDR = v;
+RD = v;

diff --git a/riscv/insns/amow_maxu.h b/riscv/insns/amow_maxu.h
index 37219a8d50ebcd3f97c2487891f172ecd8d2eeba..f7b0b7ff98319082d29b81e8766103bf6f7301f9 100644 (file)
--- a/riscv/insns/amow_maxu.h
+++ b/riscv/insns/amow_maxu.h
@@ -1,3 +1,3 @@
 uint32_t v = mmu.load_int32(RS1);
 mmu.store_uint32(RS1, std::max(uint32_t(RS2),v));
-RDR = v;
+RD = v;

diff --git a/riscv/insns/amow_min.h b/riscv/insns/amow_min.h
index ac1362393a8e32ad86a3ecec43b639cd9955049a..529ad50c1d286d3738f6348b46b78be8b4ec8c83 100644 (file)
--- a/riscv/insns/amow_min.h
+++ b/riscv/insns/amow_min.h
@@ -1,3 +1,3 @@
 int32_t v = mmu.load_int32(RS1);
 mmu.store_uint32(RS1, std::min(int32_t(RS2),v));
-RDR = v;
+RD = v;

diff --git a/riscv/insns/amow_minu.h b/riscv/insns/amow_minu.h
index de3ee566f0bd5a76528d0d6da0323ee59b2453b7..2e9fd17d0f5bee3dbce17feaac0bccddcb4c3cee 100644 (file)
--- a/riscv/insns/amow_minu.h
+++ b/riscv/insns/amow_minu.h
@@ -1,3 +1,3 @@
 uint32_t v = mmu.load_int32(RS1);
 mmu.store_uint32(RS1, std::min(uint32_t(RS2),v));
-RDR = v;
+RD = v;

diff --git a/riscv/insns/amow_or.h b/riscv/insns/amow_or.h
index e56966574381e4d9fb96fd19ae82440caee3a023..741fbefd9629f94a95d8fb04b87b873acc142173 100644 (file)
--- a/riscv/insns/amow_or.h
+++ b/riscv/insns/amow_or.h
@@ -1,3 +1,3 @@
 reg_t v = mmu.load_int32(RS1);
 mmu.store_uint32(RS1, RS2 | v);
-RDR = v;
+RD = v;

diff --git a/riscv/insns/amow_swap.h b/riscv/insns/amow_swap.h
index c8b108a114e1decdbd235ec4b6234d1fdbab8cd3..30e6102d56db733e167d88e89e34e29a33f40b69 100644 (file)
--- a/riscv/insns/amow_swap.h
+++ b/riscv/insns/amow_swap.h
@@ -1,3 +1,3 @@
 reg_t v = mmu.load_int32(RS1);
 mmu.store_uint32(RS1, RS2);
-RDR = v;
+RD = v;

diff --git a/riscv/insns/and.h b/riscv/insns/and.h
index a63e83f5feb35ea8755d7e80489b186366c464a5..88ac1d8738b7fc2b335d3b27e9b4472a92ee4126 100644 (file)
--- a/riscv/insns/and.h
+++ b/riscv/insns/and.h
@@ -1 +1 @@
-RDR = RS1 & RS2;
+RD = RS1 & RS2;

diff --git a/riscv/insns/andi.h b/riscv/insns/andi.h
index 2c90b8bd2844b439ed50c6efda23e39328609cc5..5caea164fbf0175f2d40f351157c1fb74f215109 100644 (file)
--- a/riscv/insns/andi.h
+++ b/riscv/insns/andi.h
@@ -1 +1 @@
-RDI = SIMM & RS1;
+RD = SIMM & RS1;

diff --git a/riscv/insns/break.h b/riscv/insns/break.h
deleted file mode 100644 (file)
index 7fd3d66..0000000
--- a/riscv/insns/break.h
+++ /dev/null
@@ -1 +0,0 @@
-throw trap_breakpoint;

diff --git a/riscv/insns/c_eq_d.h b/riscv/insns/c_eq_d.h
index 127e57e29360d3a781401e42eb16ea997fc14922..9db876060e2d2cab82419356644baea24e26165f 100644 (file)
--- a/riscv/insns/c_eq_d.h
+++ b/riscv/insns/c_eq_d.h
@@ -1,3 +1,3 @@
 require_fp;
-RDR = f64_eq(FRS1, FRS2);
+RD = f64_eq(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/c_eq_s.h b/riscv/insns/c_eq_s.h
index 0a2ccd916ff57672097565f62d3a54ed8a1e316c..658e8f6fe3dfb6af50be851bd69f86e5bfe41625 100644 (file)
--- a/riscv/insns/c_eq_s.h
+++ b/riscv/insns/c_eq_s.h
@@ -1,3 +1,3 @@
 require_fp;
-RDR = f32_eq(FRS1, FRS2);
+RD = f32_eq(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/c_le_d.h b/riscv/insns/c_le_d.h
index 23f97035d25140dbd2c3b93848a36755ae917e3c..da7618725c8c6cfd1d18f7d5b44fe3699b717eba 100644 (file)
--- a/riscv/insns/c_le_d.h
+++ b/riscv/insns/c_le_d.h
@@ -1,3 +1,3 @@
 require_fp;
-RDR = f64_le(FRS1, FRS2);
+RD = f64_le(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/c_le_s.h b/riscv/insns/c_le_s.h
index 7350a9e066111509d7d050fffde08754bd9962ab..9c83a17f00135d71f5d6a2fa23bafe4732af74a5 100644 (file)
--- a/riscv/insns/c_le_s.h
+++ b/riscv/insns/c_le_s.h
@@ -1,3 +1,3 @@
 require_fp;
-RDR = f32_le(FRS1, FRS2);
+RD = f32_le(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/c_lt_d.h b/riscv/insns/c_lt_d.h
index 77e7eec492b1647b2edfa57c4d7647220a50b082..01d135a93de845723f52517502feea8c98613aba 100644 (file)
--- a/riscv/insns/c_lt_d.h
+++ b/riscv/insns/c_lt_d.h
@@ -1,3 +1,3 @@
 require_fp;
-RDR = f64_lt(FRS1, FRS2);
+RD = f64_lt(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/c_lt_s.h b/riscv/insns/c_lt_s.h
index cdb43725474a8b56b3792917a77c7d0d9daf1e18..52eee5d34600f7ac8efca0f2bd974801fa526b27 100644 (file)
--- a/riscv/insns/c_lt_s.h
+++ b/riscv/insns/c_lt_s.h
@@ -1,3 +1,3 @@
 require_fp;
-RDR = f32_lt(FRS1, FRS2);
+RD = f32_lt(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_d_l.h b/riscv/insns/cvt_d_l.h
index 8a60e643ca7160a6ffd6728b202f8750c9aeaa33..28a03a915a3d1be95f3eda7e027ceaf06e111507 100644 (file)
--- a/riscv/insns/cvt_d_l.h
+++ b/riscv/insns/cvt_d_l.h
@@ -1,4 +1,4 @@
 require64;
 require_fp;
-FRDR = i64_to_f64(RS1);
+FRD = i64_to_f64(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_d_l_rm.h b/riscv/insns/cvt_d_l_rm.h
index 0e50864b1c19d88a1091b37407d7f09c3715dca9..84c1a712be2de1b17dd29b279f9e0c8141d4896f 100644 (file)
--- a/riscv/insns/cvt_d_l_rm.h
+++ b/riscv/insns/cvt_d_l_rm.h
@@ -1,5 +1,5 @@
 require64;
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = i64_to_f64(RS1);
+FRD = i64_to_f64(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_d_s.h b/riscv/insns/cvt_d_s.h
index 7a26f7092c09c9cfed257a77b979f093d64b4a0e..8e2b2f8529359b6b70cd8110127954570c0796dd 100644 (file)
--- a/riscv/insns/cvt_d_s.h
+++ b/riscv/insns/cvt_d_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f32_to_f64(FRS1);
+FRD = f32_to_f64(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_d_s_rm.h b/riscv/insns/cvt_d_s_rm.h
index 4c45e30e8fc4e1ae7bfaec531dca95305e0f7ed0..6b1a09cc5e604cbd31ff3bbc97631ca74fc334f1 100644 (file)
--- a/riscv/insns/cvt_d_s_rm.h
+++ b/riscv/insns/cvt_d_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f32_to_f64(FRS1);
+FRD = f32_to_f64(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_d_w.h b/riscv/insns/cvt_d_w.h
index 96acc2b53e920ff2598050166de90a3d7a76ca4a..94cd7703687bbba15746087a68369ba793033c71 100644 (file)
--- a/riscv/insns/cvt_d_w.h
+++ b/riscv/insns/cvt_d_w.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = i32_to_f64(RS1);
+FRD = i32_to_f64(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_d_w_rm.h b/riscv/insns/cvt_d_w_rm.h
index e91945b506ee8e9a8df77e833ab147301e16b989..638a5eca630b1f6d4b7b4dbb49ad08eb38a1cb81 100644 (file)
--- a/riscv/insns/cvt_d_w_rm.h
+++ b/riscv/insns/cvt_d_w_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = i32_to_f64(RS1);
+FRD = i32_to_f64(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_l_d_rm.h b/riscv/insns/cvt_l_d_rm.h
index 0d5e7deb76e71ff97dd10d1535be29d40a0d46a8..2747d6776908dc9458e9195a108f828ee6749a28 100644 (file)
--- a/riscv/insns/cvt_l_d_rm.h
+++ b/riscv/insns/cvt_l_d_rm.h
@@ -1,5 +1,5 @@
 require64;
 require_fp;
 softfloat_roundingMode = RM;
-RDR = f64_to_i64_r_minMag(FRS1,true);
+RD = f64_to_i64_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_l_s_rm.h b/riscv/insns/cvt_l_s_rm.h
index e05f46d6b4874241e4997e53d1102bc606e5c0e4..f5b053c09f11e6a4cf3a11510f64876c88f44704 100644 (file)
--- a/riscv/insns/cvt_l_s_rm.h
+++ b/riscv/insns/cvt_l_s_rm.h
@@ -1,5 +1,5 @@
 require64;
 require_fp;
 softfloat_roundingMode = RM;
-RDR = f32_to_i64_r_minMag(FRS1,true);
+RD = f32_to_i64_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_s_d.h b/riscv/insns/cvt_s_d.h
index 56d6fe36128fc1112c216c0a57051811685157a6..1c9b281df2fb0eab4bafa9f402bb1782cbf82f85 100644 (file)
--- a/riscv/insns/cvt_s_d.h
+++ b/riscv/insns/cvt_s_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f64_to_f32(FRS1);
+FRD = f64_to_f32(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_s_d_rm.h b/riscv/insns/cvt_s_d_rm.h
index 4e85fd760393385f1d21deff3fdb66ecd01971f2..e5289c4b0d1866f19744089b0d93b6ef9aef3c7a 100644 (file)
--- a/riscv/insns/cvt_s_d_rm.h
+++ b/riscv/insns/cvt_s_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f64_to_f32(FRS1);
+FRD = f64_to_f32(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_s_l.h b/riscv/insns/cvt_s_l.h
index fe10e85c3ec231467ff204b3859e1e78d3e42212..c89657d2381c10ffc7d74034d1772a588ab7c037 100644 (file)
--- a/riscv/insns/cvt_s_l.h
+++ b/riscv/insns/cvt_s_l.h
@@ -1,4 +1,4 @@
 require64;
 require_fp;
-FRDR = i64_to_f32(RS1);
+FRD = i64_to_f32(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_s_l_rm.h b/riscv/insns/cvt_s_l_rm.h
index 9b8d0ca82bacc938e40c21e5cd2ecb9630cbb29d..79fbc97af4e130ba08d700a9e0b8080b67c8e0d4 100644 (file)
--- a/riscv/insns/cvt_s_l_rm.h
+++ b/riscv/insns/cvt_s_l_rm.h
@@ -1,5 +1,5 @@
 require64;
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = i64_to_f32(RS1);
+FRD = i64_to_f32(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_s_w.h b/riscv/insns/cvt_s_w.h
index 8501547f3415f6cfb66dbdae2ee25837ec7e6ab5..b11d7836d328d4f021c3c7964a01df5a16fb20cf 100644 (file)
--- a/riscv/insns/cvt_s_w.h
+++ b/riscv/insns/cvt_s_w.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = i32_to_f32(RS1);
+FRD = i32_to_f32(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_s_w_rm.h b/riscv/insns/cvt_s_w_rm.h
index bfb4f445a9f81944100239ea53bc96910f02cde7..12b1e733f3031bb5e89ea4f3df235f520a3b147c 100644 (file)
--- a/riscv/insns/cvt_s_w_rm.h
+++ b/riscv/insns/cvt_s_w_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = i32_to_f32(RS1);
+FRD = i32_to_f32(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_w_d_rm.h b/riscv/insns/cvt_w_d_rm.h
index 48db66678d19e7ad08b62810d9fec1dd3d8646ca..e92446782e1b3fb803cb6c2969f0e7365d250672 100644 (file)
--- a/riscv/insns/cvt_w_d_rm.h
+++ b/riscv/insns/cvt_w_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RDR = f64_to_i32_r_minMag(FRS1,true);
+RD = f64_to_i32_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_w_s_rm.h b/riscv/insns/cvt_w_s_rm.h
index d7bc83947784221a8db99aa16774b3771b57643c..809797f8dc87d06237763c6c2770dcb5b6025ea2 100644 (file)
--- a/riscv/insns/cvt_w_s_rm.h
+++ b/riscv/insns/cvt_w_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RDR = f32_to_i32_r_minMag(FRS1,true);
+RD = f32_to_i32_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_d_l.h b/riscv/insns/cvtu_d_l.h
index 8a60e643ca7160a6ffd6728b202f8750c9aeaa33..28a03a915a3d1be95f3eda7e027ceaf06e111507 100644 (file)
--- a/riscv/insns/cvtu_d_l.h
+++ b/riscv/insns/cvtu_d_l.h
@@ -1,4 +1,4 @@
 require64;
 require_fp;
-FRDR = i64_to_f64(RS1);
+FRD = i64_to_f64(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_d_l_rm.h b/riscv/insns/cvtu_d_l_rm.h
index 0e50864b1c19d88a1091b37407d7f09c3715dca9..84c1a712be2de1b17dd29b279f9e0c8141d4896f 100644 (file)
--- a/riscv/insns/cvtu_d_l_rm.h
+++ b/riscv/insns/cvtu_d_l_rm.h
@@ -1,5 +1,5 @@
 require64;
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = i64_to_f64(RS1);
+FRD = i64_to_f64(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_d_w.h b/riscv/insns/cvtu_d_w.h
index 494f9b0bf924a5c219891a271a6210adc57f42d7..6a74d2d28c3d791cb4bb11ead2898ff5f2622465 100644 (file)
--- a/riscv/insns/cvtu_d_w.h
+++ b/riscv/insns/cvtu_d_w.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = ui32_to_f64(RS1);
+FRD = ui32_to_f64(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_d_w_rm.h b/riscv/insns/cvtu_d_w_rm.h
index 9477cbe2e4d5e16b589084bcf8b057e033b81474..2757790f1500d43986cfcf0970ec006f80d256d7 100644 (file)
--- a/riscv/insns/cvtu_d_w_rm.h
+++ b/riscv/insns/cvtu_d_w_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = ui32_to_f64(RS1);
+FRD = ui32_to_f64(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_l_d_rm.h b/riscv/insns/cvtu_l_d_rm.h
index 0d5e7deb76e71ff97dd10d1535be29d40a0d46a8..2747d6776908dc9458e9195a108f828ee6749a28 100644 (file)
--- a/riscv/insns/cvtu_l_d_rm.h
+++ b/riscv/insns/cvtu_l_d_rm.h
@@ -1,5 +1,5 @@
 require64;
 require_fp;
 softfloat_roundingMode = RM;
-RDR = f64_to_i64_r_minMag(FRS1,true);
+RD = f64_to_i64_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_l_s_rm.h b/riscv/insns/cvtu_l_s_rm.h
index e05f46d6b4874241e4997e53d1102bc606e5c0e4..f5b053c09f11e6a4cf3a11510f64876c88f44704 100644 (file)
--- a/riscv/insns/cvtu_l_s_rm.h
+++ b/riscv/insns/cvtu_l_s_rm.h
@@ -1,5 +1,5 @@
 require64;
 require_fp;
 softfloat_roundingMode = RM;
-RDR = f32_to_i64_r_minMag(FRS1,true);
+RD = f32_to_i64_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_s_l.h b/riscv/insns/cvtu_s_l.h
index fe10e85c3ec231467ff204b3859e1e78d3e42212..c89657d2381c10ffc7d74034d1772a588ab7c037 100644 (file)
--- a/riscv/insns/cvtu_s_l.h
+++ b/riscv/insns/cvtu_s_l.h
@@ -1,4 +1,4 @@
 require64;
 require_fp;
-FRDR = i64_to_f32(RS1);
+FRD = i64_to_f32(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_s_l_rm.h b/riscv/insns/cvtu_s_l_rm.h
index 9b8d0ca82bacc938e40c21e5cd2ecb9630cbb29d..79fbc97af4e130ba08d700a9e0b8080b67c8e0d4 100644 (file)
--- a/riscv/insns/cvtu_s_l_rm.h
+++ b/riscv/insns/cvtu_s_l_rm.h
@@ -1,5 +1,5 @@
 require64;
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = i64_to_f32(RS1);
+FRD = i64_to_f32(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_s_w.h b/riscv/insns/cvtu_s_w.h
index fb76e6d7490a3b910b8d709f77fc5c7d790c9fd5..79bb8295e9be7bb71154f17e6f670e391978dae1 100644 (file)
--- a/riscv/insns/cvtu_s_w.h
+++ b/riscv/insns/cvtu_s_w.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = ui32_to_f32(RS1);
+FRD = ui32_to_f32(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_s_w_rm.h b/riscv/insns/cvtu_s_w_rm.h
index da521ada9f1263c1d7b13875d96fa160c1f6e7c4..4c53c01ed02d5786fa61f5e67fef466676ce0bdf 100644 (file)
--- a/riscv/insns/cvtu_s_w_rm.h
+++ b/riscv/insns/cvtu_s_w_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = ui32_to_f32(RS1);
+FRD = ui32_to_f32(RS1);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_w_d_rm.h b/riscv/insns/cvtu_w_d_rm.h
index ef11a51f379059de0ed69e54d760cda5070693b6..93860e876b2d56e851a58406176da1efc6d9fd3c 100644 (file)
--- a/riscv/insns/cvtu_w_d_rm.h
+++ b/riscv/insns/cvtu_w_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RDR = f64_to_ui32_r_minMag(FRS1,true);
+RD = f64_to_ui32_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_w_s_rm.h b/riscv/insns/cvtu_w_s_rm.h
index 285de4f20a20b1e994562d369e74f4b36ca8de9c..04b8fb2764cb932d77bb797afa990dff00447fc8 100644 (file)
--- a/riscv/insns/cvtu_w_s_rm.h
+++ b/riscv/insns/cvtu_w_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-RDR = f32_to_ui32_r_minMag(FRS1,true);
+RD = f32_to_ui32_r_minMag(FRS1,true);
 set_fp_exceptions;

diff --git a/riscv/insns/di.h b/riscv/insns/di.h
index 0f3adf9c8adce2660a8520e1bc099a7db863e6e9..31280d5f63c2e577f93c5fe07b143eedd659c663 100644 (file)
--- a/riscv/insns/di.h
+++ b/riscv/insns/di.h
@@ -1,4 +1,4 @@
 require_supervisor;
 uint32_t temp = sr;
 set_sr(sr & ~SR_ET);
-RDR = temp;
+RD = temp;

diff --git a/riscv/insns/div.h b/riscv/insns/div.h
index 2d6edfca0e144956e88542384aea55dba8fd29d3..9b752aa48bdcf589ca1ee9df7a1dd66131d2ae33 100644 (file)
--- a/riscv/insns/div.h
+++ b/riscv/insns/div.h
@@ -1,2 +1,2 @@
 require64;
-RDR = sreg_t(RS1) / sreg_t(RS2);
+RD = sreg_t(RS1) / sreg_t(RS2);

diff --git a/riscv/insns/div_d.h b/riscv/insns/div_d.h
index 9902da6e4d2f2b84ff5492ba56d6c06a290ff4e7..9f756f0fd8ba0aaeb6ef1364c51f913ecd1e17fe 100644 (file)
--- a/riscv/insns/div_d.h
+++ b/riscv/insns/div_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f64_div(FRS1, FRS2);
+FRD = f64_div(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/div_d_rm.h b/riscv/insns/div_d_rm.h
index 1d929035f49bea9480aa20894a1ee0e2c34ade7f..aa00c98dcae8ae2e77c30f0e3ed933fa52619c1e 100644 (file)
--- a/riscv/insns/div_d_rm.h
+++ b/riscv/insns/div_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f64_div(FRS1, FRS2);
+FRD = f64_div(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/div_s.h b/riscv/insns/div_s.h
index 99e343c87dad6c758e165a5b8b7135e5e3f06d37..e70d085eafde70e0522735e49543e52885fdd59c 100644 (file)
--- a/riscv/insns/div_s.h
+++ b/riscv/insns/div_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f32_div(FRS1, FRS2);
+FRD = f32_div(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/div_s_rm.h b/riscv/insns/div_s_rm.h
index 07c879466fdff71c647145122abeef5d2ff33a99..8c765875180928f81f702fd28c119ed94b168e57 100644 (file)
--- a/riscv/insns/div_s_rm.h
+++ b/riscv/insns/div_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f32_div(FRS1, FRS2);
+FRD = f32_div(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/divu.h b/riscv/insns/divu.h
index 35eee14eae11774afdcbb4d27c49d2c51b6994e0..f1b65fd9169da15c3a49eeeac3e6f55f20257061 100644 (file)
--- a/riscv/insns/divu.h
+++ b/riscv/insns/divu.h
@@ -1,2 +1,2 @@
 require64;
-RDR = RS1 / RS2;
+RD = RS1 / RS2;

diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h
index f52fe5a536834ef372ef8c7e8bb1526ca6678629..46f78145cbf5a190a7c59164380f58b911725735 100644 (file)
--- a/riscv/insns/divuw.h
+++ b/riscv/insns/divuw.h
@@ -1,2 +1,2 @@
-RDR = sext32(uint32_t(RS1)/uint32_t(RS2));
+RD = sext32(uint32_t(RS1)/uint32_t(RS2));
 

diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h
index 938478c0c9391da50e27e84486804b1839a20c12..0654b490b8c3f3a081feb731a47fd1c91b3c013f 100644 (file)
--- a/riscv/insns/divw.h
+++ b/riscv/insns/divw.h
@@ -1,2 +1,2 @@
-RDR = sext32(int32_t(RS1)/int32_t(RS2));
+RD = sext32(int32_t(RS1)/int32_t(RS2));
 

diff --git a/riscv/insns/ei.h b/riscv/insns/ei.h
index f3e52075cc5c4f5550f6b884e7a07299ce978f9a..8306aebb96ace10b0f502ebe9a404394a0db80cf 100644 (file)
--- a/riscv/insns/ei.h
+++ b/riscv/insns/ei.h
@@ -1,4 +1,4 @@
 require_supervisor;
 uint32_t temp = sr;
 set_sr(sr | SR_ET);
-RDR = temp;
+RD = temp;

diff --git a/riscv/insns/jalr_c.h b/riscv/insns/jalr_c.h
index dade874cb807d6de6d11c4158d8de1d12d1da4af..d835b8737452a417b86423b13aa53ee3397b0798 100644 (file)
--- a/riscv/insns/jalr_c.h
+++ b/riscv/insns/jalr_c.h
@@ -1,3 +1,3 @@
-uint32_t temp = npc;
+uint32_t temp = npc + SIMM;
 npc = RS1;
-RDR = temp;
+RD = temp;

diff --git a/riscv/insns/l_d.h b/riscv/insns/l_d.h
index 8a06e3d0bce4324b7fb6e127c18fea7c1cb0faf1..123dea489ddc7c7c1696a5fa60e699f1251c857f 100644 (file)
--- a/riscv/insns/l_d.h
+++ b/riscv/insns/l_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRDI = mmu.load_int64(RS1+SIMM);
+FRD = mmu.load_int64(RS1+SIMM);

diff --git a/riscv/insns/l_s.h b/riscv/insns/l_s.h
index 1e9bbf7ee17540725ccbc9e6ea623978d28c95bc..335fd7d23e3e4b118403e8a83055d1a86b3d3f1b 100644 (file)
--- a/riscv/insns/l_s.h
+++ b/riscv/insns/l_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRDI = mmu.load_int32(RS1+SIMM);
+FRD = mmu.load_int32(RS1+SIMM);

diff --git a/riscv/insns/lb.h b/riscv/insns/lb.h
index 47e03d74c2403708006d1a020252d03d8e90f058..81ba7dec7f4c28c95007b651ca88e08babeb365a 100644 (file)
--- a/riscv/insns/lb.h
+++ b/riscv/insns/lb.h
@@ -1 +1 @@
-RDI = mmu.load_int8(RS1+SIMM);
+RD = mmu.load_int8(RS1+SIMM);

diff --git a/riscv/insns/lbu.h b/riscv/insns/lbu.h
index e378871edc14052d4b118a4663f6c56d0ccc35f9..12c688a2ce566352d557f858804b83f4aedd43dd 100644 (file)
--- a/riscv/insns/lbu.h
+++ b/riscv/insns/lbu.h
@@ -1 +1 @@
-RDI = mmu.load_uint8(RS1+SIMM);
+RD = mmu.load_uint8(RS1+SIMM);

diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h
index 9959d2698d828c46726dd892e8ccec6e32cd3357..973a8b3bc25370d6d5b2094716a06a6bc41b0381 100644 (file)
--- a/riscv/insns/ld.h
+++ b/riscv/insns/ld.h
@@ -1,2 +1,2 @@
 require64;
-RDI = mmu.load_int64(RS1+SIMM);
+RD = mmu.load_int64(RS1+SIMM);

diff --git a/riscv/insns/lh.h b/riscv/insns/lh.h
index 830b67339dba0543e1e85bdd68811c80c73a0ea4..ec25bc42553b7a097e63d23c89dc24bf0a53690e 100644 (file)
--- a/riscv/insns/lh.h
+++ b/riscv/insns/lh.h
@@ -1 +1 @@
-RDI = mmu.load_int16(RS1+SIMM);
+RD = mmu.load_int16(RS1+SIMM);

diff --git a/riscv/insns/lhu.h b/riscv/insns/lhu.h
index 961c42702145c58a62ab1df99164ccc14ce9f9a4..0999c0017b75d3df274758911b30326b8ff60f03 100644 (file)
--- a/riscv/insns/lhu.h
+++ b/riscv/insns/lhu.h
@@ -1 +1 @@
-RDI = mmu.load_uint16(RS1+SIMM);
+RD = mmu.load_uint16(RS1+SIMM);

diff --git a/riscv/insns/lui.h b/riscv/insns/lui.h
index 20a0af841fed2321730dda69b0e2ab98b4fca050..6af2a2a32c97df03c0c7e6323a7488d85d900fe5 100644 (file)
--- a/riscv/insns/lui.h
+++ b/riscv/insns/lui.h
@@ -1 +1 @@
-RDI = sext32(BIGIMM << IMM_BITS);
+RD = sext32(BIGIMM << IMM_BITS);

diff --git a/riscv/insns/lw.h b/riscv/insns/lw.h
index 6bd26463adba7445d6b2cc1569bbc4b9f4520edd..769c9fd9306c324eee0e2959b788423def816569 100644 (file)
--- a/riscv/insns/lw.h
+++ b/riscv/insns/lw.h
@@ -1 +1 @@
-RDI = mmu.load_int32(RS1+SIMM);
+RD = mmu.load_int32(RS1+SIMM);

diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h
index 3c597af1da84af4b0bd5ca39f46c25795392d211..5e62b0f09b5449c154f0797f8bef01557b687cf8 100644 (file)
--- a/riscv/insns/lwu.h
+++ b/riscv/insns/lwu.h
@@ -1 +1 @@
-RDI = mmu.load_uint32(RS1+SIMM);
+RD = mmu.load_uint32(RS1+SIMM);

diff --git a/riscv/insns/madd_d.h b/riscv/insns/madd_d.h
index c9d63186d99a06c8619476e30694f4a91ff77640..41de61385ccb8fdce77b80bc27aa1c8ef024bc18 100644 (file)
--- a/riscv/insns/madd_d.h
+++ b/riscv/insns/madd_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f64_mulAdd(FRS1, FRS2, FRS3);
+FRD = f64_mulAdd(FRS1, FRS2, FRS3);
 set_fp_exceptions;

diff --git a/riscv/insns/madd_d_rm.h b/riscv/insns/madd_d_rm.h
index ca5d178d08b29942e430c82a1eea2f6042fb913b..f67853eef3ebdab480a54d453c19f0a8e4df422e 100644 (file)
--- a/riscv/insns/madd_d_rm.h
+++ b/riscv/insns/madd_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f64_mulAdd(FRS1, FRS2, FRS3);
+FRD = f64_mulAdd(FRS1, FRS2, FRS3);
 set_fp_exceptions;

diff --git a/riscv/insns/madd_s.h b/riscv/insns/madd_s.h
index 49f4861007238de198b36344f49f97c5b1cb9780..ee26e3cdebecde4b082bc6a13ac91006a6d2b6bb 100644 (file)
--- a/riscv/insns/madd_s.h
+++ b/riscv/insns/madd_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f32_mulAdd(FRS1, FRS2, FRS3);
+FRD = f32_mulAdd(FRS1, FRS2, FRS3);
 set_fp_exceptions;

diff --git a/riscv/insns/madd_s_rm.h b/riscv/insns/madd_s_rm.h
index 39eaab647b83caabf2f1f62109e466c89ef7bb67..19db6421fd2f66d121f69d0df12b17514cdfabf2 100644 (file)
--- a/riscv/insns/madd_s_rm.h
+++ b/riscv/insns/madd_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f32_mulAdd(FRS1, FRS2, FRS3);
+FRD = f32_mulAdd(FRS1, FRS2, FRS3);
 set_fp_exceptions;

diff --git a/riscv/insns/mfcr.h b/riscv/insns/mfcr.h
index 1c7ec2d771cc232ff3ae99d58579d9e836fe3a8f..78b71d0605235888319a470711d9ff43cdb4c55f 100644 (file)
--- a/riscv/insns/mfcr.h
+++ b/riscv/insns/mfcr.h
@@ -14,4 +14,4 @@ switch(insn.rtype.rs2)
     val = -1;
 }
 
-RDR = gprlen == 64 ? val : sext32(val);
+RD = gprlen == 64 ? val : sext32(val);

diff --git a/riscv/insns/mff_d.h b/riscv/insns/mff_d.h
index 436043c3ac74f0255fd1b5c9320dd9844aa60ab6..ba535619c949461a99dcc2c24a9eb115e52432a8 100644 (file)
--- a/riscv/insns/mff_d.h
+++ b/riscv/insns/mff_d.h
@@ -1,3 +1,3 @@
 require64;
 require_fp;
-RDR = FRS2;
+RD = FRS2;

diff --git a/riscv/insns/mff_s.h b/riscv/insns/mff_s.h
index 4fdb7df76aab8395824394dadde31ea48033f584..589b33b7d769d45f8a873e2308dbdf131339eac6 100644 (file)
--- a/riscv/insns/mff_s.h
+++ b/riscv/insns/mff_s.h
@@ -1,2 +1,2 @@
 require_fp;
-RDR = sext32(FRS2);
+RD = sext32(FRS2);

diff --git a/riscv/insns/mffh_d.h b/riscv/insns/mffh_d.h
index 59f64768d302fb1f2c951f5ed47a61900a52ceb7..78b5423880b9be456467d4c3d3e9bba1b02646ea 100644 (file)
--- a/riscv/insns/mffh_d.h
+++ b/riscv/insns/mffh_d.h
@@ -1,2 +1,2 @@
 require_fp;
-RDR = sext32(FRS2 >> 32);
+RD = sext32(FRS2 >> 32);

diff --git a/riscv/insns/mffl_d.h b/riscv/insns/mffl_d.h
index 4fdb7df76aab8395824394dadde31ea48033f584..589b33b7d769d45f8a873e2308dbdf131339eac6 100644 (file)
--- a/riscv/insns/mffl_d.h
+++ b/riscv/insns/mffl_d.h
@@ -1,2 +1,2 @@
 require_fp;
-RDR = sext32(FRS2);
+RD = sext32(FRS2);

diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h
index 704e37bbcf5de9d1ac46888c098096f73a3260f5..54c62edccfe80b0d496c696384233fdea20f4532 100644 (file)
--- a/riscv/insns/mfpcr.h
+++ b/riscv/insns/mfpcr.h
@@ -45,4 +45,4 @@ switch(insn.rtype.rs2)
     val = -1;
 }
 
-RDR = gprlen == 64 ? val : sext32(val);
+RD = gprlen == 64 ? val : sext32(val);

diff --git a/riscv/insns/msub_d.h b/riscv/insns/msub_d.h
index 939baca41f7cdfbe272f88ccc673b5602858bd79..f3da45186d9ae055723ff2a169790f66c4e3aeff 100644 (file)
--- a/riscv/insns/msub_d.h
+++ b/riscv/insns/msub_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
+FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
 set_fp_exceptions;

diff --git a/riscv/insns/msub_d_rm.h b/riscv/insns/msub_d_rm.h
index 597c77925fa3ab5cfcb7ba194f02617a79c1260d..b1e93408f85abc46b8b99fb21405577dcf43152c 100644 (file)
--- a/riscv/insns/msub_d_rm.h
+++ b/riscv/insns/msub_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
+FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
 set_fp_exceptions;

diff --git a/riscv/insns/msub_s.h b/riscv/insns/msub_s.h
index b80895102b30e3803a30fa21d790c20f28ca658a..170e1a161288f8290e3dfbd703ceb493ace78a9a 100644 (file)
--- a/riscv/insns/msub_s.h
+++ b/riscv/insns/msub_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN);
+FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN);
 set_fp_exceptions;

diff --git a/riscv/insns/msub_s_rm.h b/riscv/insns/msub_s_rm.h
index 5ff5d594163bd53da8f0279fcc6b985bfc022f5f..d3349f5a32eb82ceeb453c269996f08027bed82e 100644 (file)
--- a/riscv/insns/msub_s_rm.h
+++ b/riscv/insns/msub_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN);
+FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN);
 set_fp_exceptions;

diff --git a/riscv/insns/mtf_d.h b/riscv/insns/mtf_d.h
index 6777689b948ff6f593df9d512a479cc6d1425bbc..44daa9e38cbd12465089dee3175210dc7009e643 100644 (file)
--- a/riscv/insns/mtf_d.h
+++ b/riscv/insns/mtf_d.h
@@ -1,3 +1,3 @@
 require64;
 require_fp;
-FRDR = RS1;
+FRD = RS1;

diff --git a/riscv/insns/mtf_s.h b/riscv/insns/mtf_s.h
index a1c22fddce956f5606c6f9842358fa6cbda694e2..54546ea23805f62dd3fd4a2b05169348ca6a411a 100644 (file)
--- a/riscv/insns/mtf_s.h
+++ b/riscv/insns/mtf_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRDR = RS1;
+FRD = RS1;

diff --git a/riscv/insns/mtflh_d.h b/riscv/insns/mtflh_d.h
index c48c726314bc7ddc92949916707cdfdf67617402..ed4014e8d3f6702a7769b5e1abaf371e13216ccb 100644 (file)
--- a/riscv/insns/mtflh_d.h
+++ b/riscv/insns/mtflh_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRDR = (RS1 & 0x00000000FFFFFFFF) | (RS2 << 32);
+FRD = (RS1 & 0x00000000FFFFFFFF) | (RS2 << 32);

diff --git a/riscv/insns/mul.h b/riscv/insns/mul.h
index 226873f9c883917f468b4b44e056b56d39ba7fc4..ff1e034007971a59342bc44f2108e7a39cfe2299 100644 (file)
--- a/riscv/insns/mul.h
+++ b/riscv/insns/mul.h
@@ -1,2 +1,2 @@
 require64;
-RDR = RS1 * RS2;
+RD = RS1 * RS2;

diff --git a/riscv/insns/mul_d.h b/riscv/insns/mul_d.h
index 75c7b94da1692c22a35c26540fec1a069eaaff02..6038728b66e1d6524dfc16372c0b0b0c7327bb2d 100644 (file)
--- a/riscv/insns/mul_d.h
+++ b/riscv/insns/mul_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f64_mul(FRS1, FRS2);
+FRD = f64_mul(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/mul_d_rm.h b/riscv/insns/mul_d_rm.h
index 3c938dae8a29402da6eb1c50f03d9cd532b502e9..a8adedd1bc17563aee013aef3f4bc76a0827b14f 100644 (file)
--- a/riscv/insns/mul_d_rm.h
+++ b/riscv/insns/mul_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f64_mul(FRS1, FRS2);
+FRD = f64_mul(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/mul_s.h b/riscv/insns/mul_s.h
index 5c1397c5a1c4f9a65623fb377da6c4318f72edbb..3a5905bf47a2c53d26d1e85f8737b67128b67b7d 100644 (file)
--- a/riscv/insns/mul_s.h
+++ b/riscv/insns/mul_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f32_mul(FRS1, FRS2);
+FRD = f32_mul(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/mul_s_rm.h b/riscv/insns/mul_s_rm.h
index a5bf23a9c1c55af90e38485b8c4df41635e4f24b..64755785991ec37d191962fc65975c854397a8ee 100644 (file)
--- a/riscv/insns/mul_s_rm.h
+++ b/riscv/insns/mul_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f32_mul(FRS1, FRS2);
+FRD = f32_mul(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/mulh.h b/riscv/insns/mulh.h
index c4fead2db2537d453494ca2b4dc73f24c988c6d8..ed9c1a822115c01a6a52836dc87e13fe7c244b9a 100644 (file)
--- a/riscv/insns/mulh.h
+++ b/riscv/insns/mulh.h
@@ -1,4 +1,4 @@
 require64;
 int64_t rb = RS1;
 int64_t ra = RS2;
-RDR = (int128_t(rb) * int128_t(ra)) >> 64;
+RD = (int128_t(rb) * int128_t(ra)) >> 64;

diff --git a/riscv/insns/mulhu.h b/riscv/insns/mulhu.h
index 1ce0252e942d8ff2fe143328473a10274292fc55..17c610d672936fbad51371c46ff89ef9a187a20b 100644 (file)
--- a/riscv/insns/mulhu.h
+++ b/riscv/insns/mulhu.h
@@ -1,2 +1,2 @@
 require64;
-RDR = (uint128_t(RS1) * uint128_t(RS2)) >> 64;
+RD = (uint128_t(RS1) * uint128_t(RS2)) >> 64;

diff --git a/riscv/insns/mulhuw.h b/riscv/insns/mulhuw.h
index c2a082d8adf33f5378d9c6569039a9733192dba9..9260a24be911bca1c6c11d016d1b702b68f2f078 100644 (file)
--- a/riscv/insns/mulhuw.h
+++ b/riscv/insns/mulhuw.h
@@ -1,2 +1,2 @@
-RDR = sext32((RS1 * RS2) >> 32);
+RD = sext32((RS1 * RS2) >> 32);
 

diff --git a/riscv/insns/mulhw.h b/riscv/insns/mulhw.h
index 7becbfeea07ec3c927250eceed6f3e6b0c9ca7d9..a47aa1ef557707c63b25a9feed9eefc0fdafbdf6 100644 (file)
--- a/riscv/insns/mulhw.h
+++ b/riscv/insns/mulhw.h
@@ -1,2 +1,2 @@
-RDR = sext32((sreg_t(RS1) * sreg_t(RS2)) >> 32);
+RD = sext32((sreg_t(RS1) * sreg_t(RS2)) >> 32);
 

diff --git a/riscv/insns/mulw.h b/riscv/insns/mulw.h
index c483fb6f87bcc8bbf868dfcaaa0c46d8a58beb72..81285a22cf11c6fcab64c57d7632671aac516d29 100644 (file)
--- a/riscv/insns/mulw.h
+++ b/riscv/insns/mulw.h
@@ -1,2 +1,2 @@
-RDR = sext32(RS1 * RS2);
+RD = sext32(RS1 * RS2);
 

diff --git a/riscv/insns/nmadd_d.h b/riscv/insns/nmadd_d.h
index 1cdebd32c1bf11172b42831b43099f00fcb96710..3d6ac527722db794299e7524851d498ac1e5fd91 100644 (file)
--- a/riscv/insns/nmadd_d.h
+++ b/riscv/insns/nmadd_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f64_mulAdd(FRS1, FRS2, FRS3) ^ (uint64_t)INT64_MIN;
+FRD = f64_mulAdd(FRS1, FRS2, FRS3) ^ (uint64_t)INT64_MIN;
 set_fp_exceptions;

diff --git a/riscv/insns/nmadd_d_rm.h b/riscv/insns/nmadd_d_rm.h
index 2d4022d60471a145b84cedfb9a4fca288be75bf2..1e2ee27a89db1a1a8bea846415e4fa07b341bfc9 100644 (file)
--- a/riscv/insns/nmadd_d_rm.h
+++ b/riscv/insns/nmadd_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f64_mulAdd(FRS1, FRS2, FRS3) ^ (uint64_t)INT64_MIN;
+FRD = f64_mulAdd(FRS1, FRS2, FRS3) ^ (uint64_t)INT64_MIN;
 set_fp_exceptions;

diff --git a/riscv/insns/nmadd_s.h b/riscv/insns/nmadd_s.h
index b0b70215f4db3a6a63e5f766650ace155be0cdf3..aa05b5098d1f520e22fd8fe02ab1129977c041f5 100644 (file)
--- a/riscv/insns/nmadd_s.h
+++ b/riscv/insns/nmadd_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f32_mulAdd(FRS1, FRS2, FRS3) ^ (uint32_t)INT32_MIN;
+FRD = f32_mulAdd(FRS1, FRS2, FRS3) ^ (uint32_t)INT32_MIN;
 set_fp_exceptions;

diff --git a/riscv/insns/nmadd_s_rm.h b/riscv/insns/nmadd_s_rm.h
index 611653c89ad2e5d8069872a5548af55e8d5e49ea..78abb78f11fc73a28eabf8d0d2da06e17f3dfa19 100644 (file)
--- a/riscv/insns/nmadd_s_rm.h
+++ b/riscv/insns/nmadd_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f32_mulAdd(FRS1, FRS2, FRS3) ^ (uint32_t)INT32_MIN;
+FRD = f32_mulAdd(FRS1, FRS2, FRS3) ^ (uint32_t)INT32_MIN;
 set_fp_exceptions;

diff --git a/riscv/insns/nmsub_d.h b/riscv/insns/nmsub_d.h
index 1e010c85bba1365983b995cbbd36a8390d72c268..fa4a862bb002567ee66e16195079adfc0417816d 100644 (file)
--- a/riscv/insns/nmsub_d.h
+++ b/riscv/insns/nmsub_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN;
+FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN;
 set_fp_exceptions;

diff --git a/riscv/insns/nmsub_d_rm.h b/riscv/insns/nmsub_d_rm.h
index df153b8ce198743f990ee8e29f2c6b57baa32d97..ae643a56be09b037b110d4e62096689a54b0edbb 100644 (file)
--- a/riscv/insns/nmsub_d_rm.h
+++ b/riscv/insns/nmsub_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN;
+FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN;
 set_fp_exceptions;

diff --git a/riscv/insns/nmsub_s.h b/riscv/insns/nmsub_s.h
index 9818dc76fe6d326d5988bac4dd0d259db199c8b4..98442f84364d57889d942fd0d8eadc7aed1aa6e2 100644 (file)
--- a/riscv/insns/nmsub_s.h
+++ b/riscv/insns/nmsub_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN;
+FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN;
 set_fp_exceptions;

diff --git a/riscv/insns/nmsub_s_rm.h b/riscv/insns/nmsub_s_rm.h
index 02216c95860998ad1c335df3293aa43084a040a4..cbb70ba35d7ad64f30afeed8c4d70a10ff308a89 100644 (file)
--- a/riscv/insns/nmsub_s_rm.h
+++ b/riscv/insns/nmsub_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN;
+FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN;
 set_fp_exceptions;

diff --git a/riscv/insns/nor.h b/riscv/insns/nor.h
index a3ba7d154c0a546956333e34533dfb4c227e1cda..553449f28d98bd265854a0037a482df209e145b9 100644 (file)
--- a/riscv/insns/nor.h
+++ b/riscv/insns/nor.h
@@ -1 +1 @@
-RDR = ~(RS1 | RS2);
+RD = ~(RS1 | RS2);

diff --git a/riscv/insns/or.h b/riscv/insns/or.h
index ef27ba6f25a0c27606ac9fa120200db9d021bc56..07bcac3555c41da7eacc84775e17b7bb4d5830a7 100644 (file)
--- a/riscv/insns/or.h
+++ b/riscv/insns/or.h
@@ -1 +1 @@
-RDR = RS1 | RS2;
+RD = RS1 | RS2;

diff --git a/riscv/insns/ori.h b/riscv/insns/ori.h
index 3ee429d00566fd6fc4fc4a0bb0869d419884e585..9561b971f4b92ffe63249b21a8e510314ca58a63 100644 (file)
--- a/riscv/insns/ori.h
+++ b/riscv/insns/ori.h
@@ -1 +1 @@
-RDI = SIMM | RS1;
+RD = SIMM | RS1;

diff --git a/riscv/insns/rdnpc.h b/riscv/insns/rdnpc.h
index 254512cc00ad00c06c34b5128e977886cd649d54..5525421fc435c2dfcfff7bcd8db3acb93314d51c 100644 (file)
--- a/riscv/insns/rdnpc.h
+++ b/riscv/insns/rdnpc.h
@@ -1 +1 @@
-RDR = npc;
+RD = npc;

diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h
index 9192428e37519adac62cd422e28490aa20a7f4c1..1c82b9589cb066a4410ff7b99bfb1b12f41e10b8 100644 (file)
--- a/riscv/insns/rem.h
+++ b/riscv/insns/rem.h
@@ -1,2 +1,2 @@
 require64;
-RDR = sreg_t(RS1) % sreg_t(RS2);
+RD = sreg_t(RS1) % sreg_t(RS2);

diff --git a/riscv/insns/remu.h b/riscv/insns/remu.h
index 2f40aaa7d6e018c5a046a423633dbc09d4d8d382..e6af5123ddb376cf0db848d356b876c41c826cae 100644 (file)
--- a/riscv/insns/remu.h
+++ b/riscv/insns/remu.h
@@ -1,2 +1,2 @@
 require64;
-RDR = RS1 % RS2;
+RD = RS1 % RS2;

diff --git a/riscv/insns/remuw.h b/riscv/insns/remuw.h
index 26decf20f286829ff1b1a8895f74dc3a442a1daa..0a7a1ba4f003962b08c59755e315ad423949d72a 100644 (file)
--- a/riscv/insns/remuw.h
+++ b/riscv/insns/remuw.h
@@ -1,2 +1,2 @@
-RDR = sext32(uint32_t(RS1) % uint32_t(RS2));
+RD = sext32(uint32_t(RS1) % uint32_t(RS2));
 

diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h
index 83bf1470265104267fb33ddc57b0aeea39855c81..0d67c882995d16abb273090353b42275a76b7421 100644 (file)
--- a/riscv/insns/remw.h
+++ b/riscv/insns/remw.h
@@ -1,2 +1,2 @@
-RDR = sext32(int32_t(RS1) % int32_t(RS2));
+RD = sext32(int32_t(RS1) % int32_t(RS2));
 

diff --git a/riscv/insns/s_d.h b/riscv/insns/s_d.h
index 4c9c466c653cd47c1766374c54c0b7ec5f7cf2e4..113398efa6a59cfb60ea6e157ce67e5381a02071 100644 (file)
--- a/riscv/insns/s_d.h
+++ b/riscv/insns/s_d.h
@@ -1,2 +1,2 @@
 require_fp;
-mmu.store_uint64(RS1+SIMM, FRS2);
+mmu.store_uint64(RS1+BIMM, FRS2);

diff --git a/riscv/insns/s_s.h b/riscv/insns/s_s.h
index 384246ffda7012bc759287d5674c98bf32895369..23d333300e38dd60ce2e1a7bb19105fc9983b16a 100644 (file)
--- a/riscv/insns/s_s.h
+++ b/riscv/insns/s_s.h
@@ -1,2 +1,2 @@
 require_fp;
-mmu.store_uint32(RS1+SIMM, FRS2);
+mmu.store_uint32(RS1+BIMM, FRS2);

diff --git a/riscv/insns/sb.h b/riscv/insns/sb.h
index 5a2110fccc4fe10e2595366674976d7e82d994f6..af5bd10240fb63d249915809bb9930b62b0fbf0a 100644 (file)
--- a/riscv/insns/sb.h
+++ b/riscv/insns/sb.h
@@ -1 +1 @@
-mmu.store_uint8(RS1+SIMM, RS2);
+mmu.store_uint8(RS1+BIMM, RS2);

diff --git a/riscv/insns/sd.h b/riscv/insns/sd.h
index 587df8df47ce21f621d1bb2203e85fb67e58550d..f4ece21e50f66811417ddc1399378f9284f27358 100644 (file)
--- a/riscv/insns/sd.h
+++ b/riscv/insns/sd.h
@@ -1,2 +1,2 @@
 require64;
-mmu.store_uint64(RS1+SIMM, RS2);
+mmu.store_uint64(RS1+BIMM, RS2);

diff --git a/riscv/insns/sgninj_d.h b/riscv/insns/sgninj_d.h
index b1722da9dea74fdd2fa7d26d73d4050c40a772ef..f66e804dccf3e6032467281f8fc1d8b995ea8014 100644 (file)
--- a/riscv/insns/sgninj_d.h
+++ b/riscv/insns/sgninj_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRDR = (FRS1 &~ INT64_MIN) | (FRS2 & INT64_MIN);
+FRD = (FRS1 &~ INT64_MIN) | (FRS2 & INT64_MIN);

diff --git a/riscv/insns/sgninj_s.h b/riscv/insns/sgninj_s.h
index 2df0b94a0e654535b2815f5c5e221cdb4606746f..35609ac41c22f8ab9122688e832555b3c31c3861 100644 (file)
--- a/riscv/insns/sgninj_s.h
+++ b/riscv/insns/sgninj_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRDR = (FRS1 &~ (uint32_t)INT32_MIN) | (FRS2 & (uint32_t)INT32_MIN);
+FRD = (FRS1 &~ (uint32_t)INT32_MIN) | (FRS2 & (uint32_t)INT32_MIN);

diff --git a/riscv/insns/sgninjn_d.h b/riscv/insns/sgninjn_d.h
index 90c7ae9bd9d2fae7744b274eb09e88aa1b13bd62..22de215b20adfe97a85d4a85513b38fb944ce5ba 100644 (file)
--- a/riscv/insns/sgninjn_d.h
+++ b/riscv/insns/sgninjn_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRDR = (FRS1 &~ INT64_MIN) | ((~FRS2) & INT64_MIN);
+FRD = (FRS1 &~ INT64_MIN) | ((~FRS2) & INT64_MIN);

diff --git a/riscv/insns/sgninjn_s.h b/riscv/insns/sgninjn_s.h
index 7be7b46623cacf406680306f65597947d84b3dae..dd66d71a73bb00f23827c4301afeb34b71ae44df 100644 (file)
--- a/riscv/insns/sgninjn_s.h
+++ b/riscv/insns/sgninjn_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRDR = (FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN);
+FRD = (FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN);

diff --git a/riscv/insns/sgnmul_d.h b/riscv/insns/sgnmul_d.h
index 8e558506c815daf54d24f950af90818b21326d92..331b6e4f4c8ac496b52dd16c2cba717d70f19d05 100644 (file)
--- a/riscv/insns/sgnmul_d.h
+++ b/riscv/insns/sgnmul_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRDR = FRS1 ^ (FRS2 & INT64_MIN);
+FRD = FRS1 ^ (FRS2 & INT64_MIN);

diff --git a/riscv/insns/sgnmul_s.h b/riscv/insns/sgnmul_s.h
index e651888f0d47035217273d07dda6da9a0c105497..b4554066e59de99f3c409da64039bdcfa52c35e9 100644 (file)
--- a/riscv/insns/sgnmul_s.h
+++ b/riscv/insns/sgnmul_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRDR = FRS1 ^ (FRS2 & (uint32_t)INT32_MIN);
+FRD = FRS1 ^ (FRS2 & (uint32_t)INT32_MIN);

diff --git a/riscv/insns/sh.h b/riscv/insns/sh.h
index bbc2bda3f8ca59f6e0bf544ea20a2a5984fce318..a484e1e81be056f8d221b4cc058c440e5d195753 100644 (file)
--- a/riscv/insns/sh.h
+++ b/riscv/insns/sh.h
@@ -1 +1 @@
-mmu.store_uint16(RS1+SIMM, RS2);
+mmu.store_uint16(RS1+BIMM, RS2);

diff --git a/riscv/insns/sll.h b/riscv/insns/sll.h
index 8b6bc700f0bbbcfd76a6b58607d7ba799c4c6889..ae38f16b67892b763bf8ca287c82dc1c66b5866a 100644 (file)
--- a/riscv/insns/sll.h
+++ b/riscv/insns/sll.h
@@ -1,2 +1,2 @@
 require64;
-RDR = RS1 << (RS2 & 0x3F);
+RD = RS1 << (RS2 & 0x3F);

diff --git a/riscv/insns/slli.h b/riscv/insns/slli.h
index 33e23aa39411bb525093f7274ace2f913da1acb1..f7ba310d3e3330192c9c9876214dd352081445ea 100644 (file)
--- a/riscv/insns/slli.h
+++ b/riscv/insns/slli.h
@@ -1,2 +1,2 @@
 require64;
-RDI = RS1 << SHAMT;
+RD = RS1 << SHAMT;

diff --git a/riscv/insns/slliw.h b/riscv/insns/slliw.h
index 85469772cb43fc0e9decd3fbab85e339cc1e89a9..41be30f5c7d0784f0ca511b5c5d2afab965e6916 100644 (file)
--- a/riscv/insns/slliw.h
+++ b/riscv/insns/slliw.h
@@ -1 +1 @@
-RDI = sext32(RS1 << SHAMTW);
+RD = sext32(RS1 << SHAMTW);

diff --git a/riscv/insns/sllw.h b/riscv/insns/sllw.h
index 521c0f7e5eb8b8f3f03adabd23fa2fce4fbff19d..90e5c4c9ed05dfbc1b56a459b8ff6372dbb665af 100644 (file)
--- a/riscv/insns/sllw.h
+++ b/riscv/insns/sllw.h
@@ -1 +1 @@
-RDR = sext32(RS1 << (RS2 & 0x1F));
+RD = sext32(RS1 << (RS2 & 0x1F));

diff --git a/riscv/insns/slt.h b/riscv/insns/slt.h
index 6511f42c838485013e8034f473fd034cc5d98597..5c50534a97b13500dc376a7f86ad14c1115b16c0 100644 (file)
--- a/riscv/insns/slt.h
+++ b/riscv/insns/slt.h
@@ -1 +1 @@
-RDR = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2));
+RD = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2));

diff --git a/riscv/insns/slti.h b/riscv/insns/slti.h
index 6204619a73c5cedf2e44dbbf757f7e3e5f5a2ed8..1dcd8927fac7dbc8fdbd87391fef1d816c44cd80 100644 (file)
--- a/riscv/insns/slti.h
+++ b/riscv/insns/slti.h
@@ -1 +1 @@
-RDI = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(SIMM));
+RD = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(SIMM));

diff --git a/riscv/insns/sltiu.h b/riscv/insns/sltiu.h
index b7c8ce64f10cd1c9e3bfb3c6242a8d56f66ce1aa..45e579b518d151d221769949df6510787c100eac 100644 (file)
--- a/riscv/insns/sltiu.h
+++ b/riscv/insns/sltiu.h
@@ -1 +1 @@
-RDI = cmp_trunc(RS1) < cmp_trunc(SIMM);
+RD = cmp_trunc(RS1) < cmp_trunc(SIMM);

diff --git a/riscv/insns/sltu.h b/riscv/insns/sltu.h
index 1d4ebe65f46d85c577bc3066d85c63736bf09ffe..2c5bdc33da9a0fd69e74ecb541509e212a57f763 100644 (file)
--- a/riscv/insns/sltu.h
+++ b/riscv/insns/sltu.h
@@ -1 +1 @@
-RDR = cmp_trunc(RS1) < cmp_trunc(RS2);
+RD = cmp_trunc(RS1) < cmp_trunc(RS2);

diff --git a/riscv/insns/sqrt_d.h b/riscv/insns/sqrt_d.h
index 99ffa18089203a510ab4dd86f34462d289f61073..e2a2014007210c23827cbbbc0ec74fe4fafff001 100644 (file)
--- a/riscv/insns/sqrt_d.h
+++ b/riscv/insns/sqrt_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f64_sqrt(FRS1);
+FRD = f64_sqrt(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/sqrt_d_rm.h b/riscv/insns/sqrt_d_rm.h
index 5e93b27640a0d91ea1e572914a608c1a1ea75a4b..7647c9c8d630f0dcf2b075998e3c881cbe241c28 100644 (file)
--- a/riscv/insns/sqrt_d_rm.h
+++ b/riscv/insns/sqrt_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f64_sqrt(FRS1);
+FRD = f64_sqrt(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/sqrt_s.h b/riscv/insns/sqrt_s.h
index 12c8160b6918c777eda9ad5df990f545a0430c2f..c491649a62333238e0c905c9bafd77995f30f270 100644 (file)
--- a/riscv/insns/sqrt_s.h
+++ b/riscv/insns/sqrt_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f32_sqrt(FRS1);
+FRD = f32_sqrt(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/sqrt_s_rm.h b/riscv/insns/sqrt_s_rm.h
index cb3ff53c3220c5b09d2c21c4cb885a8ae675396e..426f24171118de816f72a09c0ce16ef88d747c33 100644 (file)
--- a/riscv/insns/sqrt_s_rm.h
+++ b/riscv/insns/sqrt_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f32_sqrt(FRS1);
+FRD = f32_sqrt(FRS1);
 set_fp_exceptions;

diff --git a/riscv/insns/sra.h b/riscv/insns/sra.h
index f0919badbc7f5c045fa124f08dca96ab05e26016..4a789164d8fcecc9b257d09ab4005cea776a5acf 100644 (file)
--- a/riscv/insns/sra.h
+++ b/riscv/insns/sra.h
@@ -1,2 +1,2 @@
 require64;
-RDR = sreg_t(RS1) >> (RS2 & 0x3F);
+RD = sreg_t(RS1) >> (RS2 & 0x3F);

diff --git a/riscv/insns/srai.h b/riscv/insns/srai.h
index b2026bb5c9486899dbb41b1e91990e9f53fb73c1..1f0dde2acddfa386733c04b0479f84b2b69f86d5 100644 (file)
--- a/riscv/insns/srai.h
+++ b/riscv/insns/srai.h
@@ -1,2 +1,2 @@
 require64;
-RDI = sreg_t(RS1) >> SHAMT;
+RD = sreg_t(RS1) >> SHAMT;

diff --git a/riscv/insns/sraiw.h b/riscv/insns/sraiw.h
index 0831b1428d00d75caf01b371b02d7c1582b19a6a..24a9eae4c4b74079186f8d05d8045af4764ac2da 100644 (file)
--- a/riscv/insns/sraiw.h
+++ b/riscv/insns/sraiw.h
@@ -1 +1 @@
-RDI = sext32(sreg_t(RS1) >> SHAMTW);
+RD = sext32(sreg_t(RS1) >> SHAMTW);

diff --git a/riscv/insns/sraw.h b/riscv/insns/sraw.h
index a49ead6ff1ae3d67af28a45ce921d4b7de7091ad..f8946fbb3f2fd4d8b01c70c78cdea30dfc72d3f2 100644 (file)
--- a/riscv/insns/sraw.h
+++ b/riscv/insns/sraw.h
@@ -1 +1 @@
-RDR = sext32(sreg_t(RS1) >> (RS2 & 0x1F));
+RD = sext32(sreg_t(RS1) >> (RS2 & 0x1F));

diff --git a/riscv/insns/srl.h b/riscv/insns/srl.h
index fa17eb71eccae0159712beb743a81689eb2ff77d..87138dab4f2ee591a18054008a9a5e509f5108b9 100644 (file)
--- a/riscv/insns/srl.h
+++ b/riscv/insns/srl.h
@@ -1,2 +1,2 @@
 require64;
-RDR = RS1 >> (RS2 & 0x3F);
+RD = RS1 >> (RS2 & 0x3F);

diff --git a/riscv/insns/srli.h b/riscv/insns/srli.h
index 29a97a2e51254d0aced63050cbf5e1dc162048a4..e0d8ae079bf5541a470e36161c88404648ee22c6 100644 (file)
--- a/riscv/insns/srli.h
+++ b/riscv/insns/srli.h
@@ -1,2 +1,2 @@
 require64;
-RDI = RS1 >> SHAMT;
+RD = RS1 >> SHAMT;

diff --git a/riscv/insns/srliw.h b/riscv/insns/srliw.h
index 5513a5a403402e20db90e026ff236a5c837f223f..2a2bb31ee591616d14cb6e3abb29d779ff8ce613 100644 (file)
--- a/riscv/insns/srliw.h
+++ b/riscv/insns/srliw.h
@@ -1 +1 @@
-RDI = sext32((uint32_t)RS1 >> SHAMTW);
+RD = sext32((uint32_t)RS1 >> SHAMTW);

diff --git a/riscv/insns/srlw.h b/riscv/insns/srlw.h
index 7aa4bc6ea5c9ccf99466decca6f3274a0f9739dc..a0058ae04a24fd0d0085876d19b83280179ab4a0 100644 (file)
--- a/riscv/insns/srlw.h
+++ b/riscv/insns/srlw.h
@@ -1 +1 @@
-RDR = sext32((uint32_t)RS1 >> (RS2 & 0x1F));
+RD = sext32((uint32_t)RS1 >> (RS2 & 0x1F));

diff --git a/riscv/insns/sub.h b/riscv/insns/sub.h
index 005b66f4c3d9baae2749525b3e8d6338d696551c..e7736c9e448e169ed6a12e4066c99e1f80770ccc 100644 (file)
--- a/riscv/insns/sub.h
+++ b/riscv/insns/sub.h
@@ -1,2 +1,2 @@
 require64;
-RDR = RS1 - RS2;
+RD = RS1 - RS2;

diff --git a/riscv/insns/sub_d.h b/riscv/insns/sub_d.h
index 20997325c2f3c784cdbb47490fc45bd676ceb2b2..54630a278a92531177899ff293c4a29214e93e60 100644 (file)
--- a/riscv/insns/sub_d.h
+++ b/riscv/insns/sub_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f64_sub(FRS1, FRS2);
+FRD = f64_sub(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/sub_d_rm.h b/riscv/insns/sub_d_rm.h
index 85477efe31a5ac8a2ef789125ea36cfdf3e6c9c2..e25eebbdc281b86f4d5aad2974dfcee16be4789a 100644 (file)
--- a/riscv/insns/sub_d_rm.h
+++ b/riscv/insns/sub_d_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f64_sub(FRS1, FRS2);
+FRD = f64_sub(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/sub_s.h b/riscv/insns/sub_s.h
index e28f042dbfc5218020b7ce6ed92213859426e92b..142c7ab6e557b254d3429f3b39b8ee6f78aa6c40 100644 (file)
--- a/riscv/insns/sub_s.h
+++ b/riscv/insns/sub_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRDR = f32_sub(FRS1, FRS2);
+FRD = f32_sub(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/sub_s_rm.h b/riscv/insns/sub_s_rm.h
index 0e9ccf250cbd8cbf3ed1410c191a148b8b5c3d59..6c64d0435dff9f28e99c7d2d8dfec0c34a0e7674 100644 (file)
--- a/riscv/insns/sub_s_rm.h
+++ b/riscv/insns/sub_s_rm.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRDR = f32_sub(FRS1, FRS2);
+FRD = f32_sub(FRS1, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/subw.h b/riscv/insns/subw.h
index 9dd7114206908d739727e6c70b36c4943e05f222..958cc5d7a67b345d755c7a2615b0147ae35f6822 100644 (file)
--- a/riscv/insns/subw.h
+++ b/riscv/insns/subw.h
@@ -1,2 +1,2 @@
-RDR = sext32(RS1 - RS2);
+RD = sext32(RS1 - RS2);
 

diff --git a/riscv/insns/sw.h b/riscv/insns/sw.h
index e644e16d611a451c80938180aae24a2f1c390346..dbe260f59cc628ec4c467b1e879eda48de6694de 100644 (file)
--- a/riscv/insns/sw.h
+++ b/riscv/insns/sw.h
@@ -1 +1 @@
-mmu.store_uint32(RS1+SIMM, RS2);
+mmu.store_uint32(RS1+BIMM, RS2);

diff --git a/riscv/insns/xor.h b/riscv/insns/xor.h
index f11738a05b1e144c913a06a64994a5fc0f9fe881..49b178367e653c92de67124c76cbb748364df7cc 100644 (file)
--- a/riscv/insns/xor.h
+++ b/riscv/insns/xor.h
@@ -1 +1 @@
-RDR = RS1 ^ RS2;
+RD = RS1 ^ RS2;

diff --git a/riscv/insns/xori.h b/riscv/insns/xori.h
index 039e1b72abbc1a73f7f809120b3503d485816444..5852aaca4b8fb2d5505822e6b1dda2f5ddf4ade9 100644 (file)
--- a/riscv/insns/xori.h
+++ b/riscv/insns/xori.h
@@ -1 +1 @@
-RDI = SIMM ^ RS1;
+RD = SIMM ^ RS1;