Remove muxY and ffY for now

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 74bcbf451b75a59d5bd48070c52ca3fa93205ded..389f0cb568b7b396548faa32a9cef5be870aaf7d 100644 (file)
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -38,7 +38,7 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
        log("ffB:   %s\n", log_id(st.ffB, "--"));
        log("dsp:   %s\n", log_id(st.dsp, "--"));
        log("ffP:   %s\n", log_id(st.ffP, "--"));
-       log("muxP:  %s\n", log_id(st.muxP, "--"));
+       //log("muxP:  %s\n", log_id(st.muxP, "--"));
        log("sigPused: %s\n", log_signal(st.sigPused));
        log_module(pm.module);
 #endif
@@ -81,9 +81,9 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
                if (st.ffP) {
                        SigSpec P = cell->getPort("\\P");
                        SigSpec D;
-                       if (st.muxP)
-                               D = st.muxP->getPort("\\B");
-                       else
+                       //if (st.muxP)
+                       //      D = st.muxP->getPort("\\B");
+                       //else
                                D = st.ffP->getPort("\\D");
                        SigSpec Q = st.ffP->getPort("\\Q");
                        P.replace(pm.sigmap(D), Q);
@@ -107,7 +107,7 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
                        log(" ffB:%s", log_id(st.ffB));
 
                if (st.ffP)
-                       log(" ffY:%s", log_id(st.ffP));
+                       log(" ffP:%s", log_id(st.ffP));
 
                log("\n");
        }

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 8abae93163951b9a2c9ac6bb66bcaeab7a3c9a80..f95de94104c256b96a75e52eeb7746642563c9af 100644 (file)
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -47,11 +47,9 @@ endcode
 // (as opposed to being a dummy)
 code sigPused
        SigSpec P = port(dsp, \P);
-       int i;
-       for (i = GetSize(P); i > 0; i--)
-               if (nusers(P[i-1]) > 1)
-                       break;
-       sigPused = P.extract(0, i).remove_const();
+       for (int i = 0; i < GetSize(P); i++)
+               if (P[i].wire && nusers(P[i]) > 1)
+                       sigPused.append(P[i]);
 endcode
 
 match ffP
@@ -66,33 +64,33 @@ match ffP
        optional
 endmatch
 
-// $mux cell left behind by dff2dffe
-//   would prefer not to run 'opt_expr -mux_undef'
-//   since that would lose information helpful for
-//   efficient wide-mux inference
-match muxP
-       if !sigPused.empty() && !ffP
-       select muxP->type.in($mux)
-       select nusers(port(muxP, \B)) == 2
-       select port(muxP, \A).is_fully_undef()
-       filter param(muxP, \WIDTH).as_int() >= GetSize(sigPused)
-       filter includes(port(muxP, \B).to_sigbit_set(), sigPused.to_sigbit_set())
-       optional
-endmatch
-
-match ffY
-       if muxP
-       select ffY->type.in($dff, $dffe)
-       select nusers(port(ffY, \D)) == 2
-       // DSP48E1 does not support clock inversion
-       select param(ffY, \CLK_POLARITY).as_bool()
-       filter param(ffY, \WIDTH).as_int() >= GetSize(sigPused)
-       filter includes(port(ffY, \D).to_sigbit_set(), port(muxP, \Y).to_sigbit_set())
-endmatch
+//// $mux cell left behind by dff2dffe
+////   would prefer not to run 'opt_expr -mux_undef'
+////   since that would lose information helpful for
+////   efficient wide-mux inference
+//match muxP
+//     if !sigPused.empty() && !ffP
+//     select muxP->type.in($mux)
+//     select nusers(port(muxP, \B)) == 2
+//     select port(muxP, \A).is_fully_undef()
+//     filter param(muxP, \WIDTH).as_int() >= GetSize(sigPused)
+//     filter includes(port(muxP, \B).to_sigbit_set(), sigPused.to_sigbit_set())
+//     optional
+//endmatch
+//
+//match ffY
+//     if muxP
+//     select ffY->type.in($dff, $dffe)
+//     select nusers(port(ffY, \D)) == 2
+//     // DSP48E1 does not support clock inversion
+//     select param(ffY, \CLK_POLARITY).as_bool()
+//     filter param(ffY, \WIDTH).as_int() >= GetSize(sigPused)
+//     filter includes(port(ffY, \D).to_sigbit_set(), port(muxP, \Y).to_sigbit_set())
+//endmatch
 
 code ffP clock
-       if (ffY)
-               ffP = ffY;
+//     if (ffY)
+//             ffP = ffY;
 
        if (ffP) {
                SigBit c = port(ffP, \CLK).as_bit();