* PIPE_TRANSFER_DISCARD_RANGE are set.
*/
if (res->u.b.target == PIPE_BUFFER &&
- !util_ranges_intersect(&res->valid_buffer_range, xfer->base.box.x,
- xfer->base.box.x + xfer->base.box.width)) {
+ !util_ranges_intersect(&res->valid_buffer_range, xfer->base.box.x,
+ xfer->base.box.x + xfer->base.box.width) &&
+ likely(!(virgl_debug & VIRGL_DEBUG_XFER))) {
flush = false;
readback = false;
wait = false;
/* When the resource is busy but its content can be discarded, we can
* replace its HW resource or use a staging buffer to avoid waiting.
*/
- if (wait && (xfer->base.usage & (PIPE_TRANSFER_DISCARD_RANGE |
- PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE))) {
+ if (wait &&
+ (xfer->base.usage & (PIPE_TRANSFER_DISCARD_RANGE |
+ PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE)) &&
+ likely(!(virgl_debug & VIRGL_DEBUG_XFER))) {
bool can_realloc = false;
bool can_staging = false;
{ "emubgra", VIRGL_DEBUG_EMULATE_BGRA, "Enable tweak to emulate BGRA as RGBA on GLES hosts"},
{ "bgraswz", VIRGL_DEBUG_BGRA_DEST_SWIZZLE, "Enable tweak to swizzle emulated BGRA on GLES hosts" },
{ "sync", VIRGL_DEBUG_SYNC, "Sync after every flush" },
+ { "xfer", VIRGL_DEBUG_XFER, "Do not optimize for transfers" },
DEBUG_NAMED_VALUE_END
};
DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug, "VIRGL_DEBUG", debug_options, 0)
VIRGL_DEBUG_EMULATE_BGRA = 1 << 2,
VIRGL_DEBUG_BGRA_DEST_SWIZZLE = 1 << 3,
VIRGL_DEBUG_SYNC = 1 << 4,
+ VIRGL_DEBUG_XFER = 1 << 5,
};
extern int virgl_debug;