svp64_matrix.py svremap reduce to 7 args from 8 (again)

diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
index c15479db9a36055166b6b023c7495f9ca3637333..130f94720ec42bc1cef1fa478fe7571f0c95d7e6 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
@@ -93,13 +93,13 @@ class DecoderTestCase(FHDLTestCase):
 
     def test_sv_remap2(self):
         """>>> lst = ["svshape 5, 4, 3, 0, 0",
-                        "svremap 31, 1, 2, 3, 0, 0, 0, 0",
+                        "svremap 31, 1, 2, 3, 0, 0, 0",
                        "sv.fmadds 0.v, 8.v, 16.v, 0.v"
                         ]
                 REMAP fmadds FRT, FRA, FRC, FRB
         """
         lst = SVP64Asm(["svshape 4, 3, 3, 0, 0",
-                        "svremap 31, 1, 2, 3, 0, 0, 0, 0",
+                        "svremap 31, 1, 2, 3, 0, 0, 0",
                        "sv.fmadds 0.v, 16.v, 32.v, 0.v"
                         ])
         lst = list(lst)