examples/pytholite/basic: demonstrate conversion to Verilog

diff --git a/examples/pytholite/basic.py b/examples/pytholite/basic.py
index fa8ba9ba3d9d129c8fc34aa38ed6cc1ccc190226..91688dc028c200e9b84a73dcae729643dd1a4805 100644 (file)
--- a/examples/pytholite/basic.py
+++ b/examples/pytholite/basic.py
@@ -3,6 +3,7 @@ from migen.actorlib.sim import *
 from migen.pytholite.compiler import make_pytholite
 from migen.sim.generic import Simulator
 from migen.sim.icarus import Runner
+from migen.fhdl import verilog
 
 layout = [("r", BV(32))]
 
@@ -32,12 +33,15 @@ def run_sim(ng):
        del sim
 
 def main():
+       print("Simulating native Python:")
+       ng_native = SimActor(number_gen(), ("result", Source, layout))
+       run_sim(ng_native)
+       
        print("Simulating Pytholite:")
        ng_pytholite = make_pytholite(number_gen, dataflow=[("result", Source, layout)])
        run_sim(ng_pytholite)
        
-       print("Simulating native Python:")
-       ng_native = SimActor(number_gen(), ("result", Source, layout))
-       run_sim(ng_native)
+       print("Converting Pytholite to Verilog:")
+       print(verilog.convert(ng_pytholite.get_fragment()))
 
 main()