(no commit message)

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index ff535877aeb74e0b42c127894756c398d4279210..25daa1814038f35b389e771e5ef501277847da38 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -235,14 +235,14 @@ that the spec is shifted up by one bit
 
 Mode is an augmentation of SV behaviour.  Some of these alterations are element-based (saturation), others involve post-analysis (predicate result) and others are Vector-based (mapreduce, fail-on-first).
 
-| 0-1 |  2   3    4    description |
-| --- | ------------------ |
-| 00  |    M   sz   CRM  reduce mode (M=1). |
-| 01  |  inv CR-bit    Rc=1: ffirst CR sel |
-| 01  |   inv sz   dz   Rc=0: ffirst z/nonz |
-| 10  |   N   sz   dz   sat mode: N=0/1 u/s |
-| 11  |  inv CR-bit    Rc=1: pred-result CR sel |
-| 11  |  inv sz   dz   Rc=0: pred-result z/nonz |
+| 0-1 |  2  |  3   4  |  description              |
+| --- | --- |---------|-------------------------- |
+| 00  |   M |  sz CRM | reduce mode (M=1). |
+| 01  | inv | CR-bit  | Rc=1: ffirst CR sel |
+| 01  | inv | sz   dz |  Rc=0: ffirst z/nonz |
+| 10  |   N | sz   dz |  sat mode: N=0/1 u/s |
+| 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
+| 11  | inv | sz   dz |  Rc=0: pred-result z/nonz |
 
 Mode types: