(no commit message)

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index 87e084e9ae56cd5e4edcf4aaf1df6089e1dd9376..7582962632d936912ca8c8eb7af2d295217458be 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -218,7 +218,7 @@ standard vector instruction with Rc=1.
 # Register Profiles
 
 Instructions are broken down by Register Profiles as listed in the following auto-generated page:
-[[opcode_regs_deduped]].  "Non-SV" indicates that the operations with this Register Profile cannot be Vectorised (dcbz, twi)
+[[opcode_regs_deduped]].  "Non-SV" indicates that the operations with this Register Profile cannot be Vectorised (mtspr, bc, dcbz, twi)
 
 ## LDST-1R-1W-imm
 TBD
@@ -239,7 +239,7 @@ TBD
 ## LDST-3R-1W
 TBD
 ## CRi
-TBD
+non-SV
 ## CRio
 TBD
 ## CR=2R1W