Added english language description, spaces and brackets for ldu instruction

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index a87d6332b2c176356cdfe2492c40176e8c90159b..2ff1a3b0bd88398f41e3d56519481a0bdfee5af3 100644 (file)
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -542,6 +542,16 @@ Pseudo-code:
     RT <- MEM(EA, 8)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum
+    (RA)+ (DS||0b00). The doubleword in storage
+    addressed by EA is loaded into RT.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None