sim: mn10300: migrate to standard uintXX_t types

This old port setup its own uintXX types, but since we require C11
now, we can assume the standard uintXX_t types exist and use them.

diff --git a/sim/mn10300/am33-2.igen b/sim/mn10300/am33-2.igen
index bcf68b46e2b7a0cd2a1610d238e5db87f8ec33cd..40761b2a19d9c9bdaf06cf45fbb3b92a3dc1d035 100644 (file)
--- a/sim/mn10300/am33-2.igen
+++ b/sim/mn10300/am33-2.igen
@@ -98,7 +98,7 @@
 "bset"
 *am33_2
 {
-  unsigned32 temp;
+  uint32_t temp;
   int z;
   
   PC = cia;
@@ -115,7 +115,7 @@
 "bclr"
 *am33_2
 {
-  unsigned32 temp;
+  uint32_t temp;
   int z;
   
   PC = cia;
@@ -1114,7 +1114,7 @@
   else
     {
       int reg = translate_rreg (SD_, Rm);
-      unsigned32 val = State.regs[reg];
+      uint32_t val = State.regs[reg];
       FPCR = (val & (EC_MASK | EE_MASK | FCC_MASK))
        | ((FPCR & ~val) & EF_MASK);
     }
@@ -1147,7 +1147,7 @@
     fpu_disabled_exception (SD, CPU, cia);
   else
     {
-      unsigned32 val = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+      uint32_t val = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
       FPCR = (val & (EC_MASK | EE_MASK | FCC_MASK))
        | ((FPCR & ~val) & EF_MASK);
     }
@@ -1424,7 +1424,7 @@
     fpu_disabled_exception (SD, CPU, cia);
   else
     {
-      uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+      uint32_t imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 
       fpu_cmp (SD, CPU, cia, &XS2FS (Y,Sm), &imm, FP_SINGLE);
     }
@@ -1496,7 +1496,7 @@
     fpu_disabled_exception (SD, CPU, cia);
   else
     {
-      uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+      uint32_t imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 
       fpu_add (SD, CPU, cia,
               &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
@@ -1569,7 +1569,7 @@
     fpu_disabled_exception (SD, CPU, cia);
   else
     {
-      uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+      uint32_t imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 
       fpu_sub (SD, CPU, cia,
               &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);
@@ -1642,7 +1642,7 @@
     fpu_disabled_exception (SD, CPU, cia);
   else
     {
-      uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+      uint32_t imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 
       fpu_mul (SD, CPU, cia,
               &imm, &XS2FS (Y,Sm), &XS2FS (X,Sn), FP_SINGLE);
@@ -1715,7 +1715,7 @@
     fpu_disabled_exception (SD, CPU, cia);
   else
     {
-      uint32 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
+      uint32_t imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 
       fpu_div (SD, CPU, cia,
               &XS2FS (Y,Sm), &imm, &XS2FS (X,Sn), FP_SINGLE);

diff --git a/sim/mn10300/am33.igen b/sim/mn10300/am33.igen
index 5bc96aca6164efb19c08a24cc3870d144350a959..964f07521a8c64c40245a7b99cfcdfa12938a802 100644 (file)
--- a/sim/mn10300/am33.igen
+++ b/sim/mn10300/am33.igen
@@ -119,7 +119,7 @@
 *am33
 *am33_2
 {
-  unsigned32 sp, next_pc;
+  uint32_t sp, next_pc;
 
   PC = cia;
   sp = State.regs[REG_SP];
@@ -207,8 +207,8 @@
 *am33
 *am33_2
 {
-  unsigned32 usp = State.regs[REG_USP];
-  unsigned32 mask;
+  uint32_t usp = State.regs[REG_USP];
+  uint32_t mask;
 
   PC = cia;
   mask = REGS;
@@ -301,8 +301,8 @@
 *am33
 *am33_2
 {
-  unsigned32 usp = State.regs[REG_USP];
-  unsigned32 mask;
+  uint32_t usp = State.regs[REG_USP];
+  uint32_t mask;
 
   PC = cia;
   mask = REGS;
@@ -533,7 +533,7 @@
 {
   int srcreg, dstreg;
   int z, c, n, v;
-  unsigned32 reg1, reg2, sum;
+  uint32_t reg1, reg2, sum;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
@@ -577,7 +577,7 @@
 {
   int srcreg, dstreg;
   int z, c, n, v;
-  unsigned32 reg1, reg2, difference;
+  uint32_t reg1, reg2, difference;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
@@ -756,7 +756,7 @@
 *am33_2
 {
   int srcreg, dstreg;
-  signed32 temp;
+  int32_t temp;
   int c, z, n;
 
   PC = cia;
@@ -842,7 +842,7 @@
 {
   int dstreg;
   int c, n, z;
-  unsigned32 value;
+  uint32_t value;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
@@ -867,7 +867,7 @@
 {
   int dstreg;
   int c, n, z;
-  unsigned32 value;
+  uint32_t value;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
@@ -891,15 +891,15 @@
 *am33_2
 {
   int srcreg, dstreg;
-  unsigned64 temp;
+  uint64_t temp;
   int n, z;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
   dstreg = translate_rreg (SD_, RN0);
 
-  temp = ((signed64)(signed32)State.regs[dstreg]
-          *  (signed64)(signed32)State.regs[srcreg]);
+  temp = ((int64_t)(int32_t)State.regs[dstreg]
+          *  (int64_t)(int32_t)State.regs[srcreg]);
   State.regs[dstreg] = temp & 0xffffffff;
   State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
@@ -915,15 +915,15 @@
 *am33_2
 {
   int srcreg, dstreg;
-  unsigned64 temp;
+  uint64_t temp;
   int n, z;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
   dstreg = translate_rreg (SD_, RN0);
 
-  temp = ((unsigned64)State.regs[dstreg]
-          * (unsigned64)State.regs[srcreg]);
+  temp = ((uint64_t)State.regs[dstreg]
+          * (uint64_t)State.regs[srcreg]);
   State.regs[dstreg] = temp & 0xffffffff;
   State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
@@ -939,7 +939,7 @@
 *am33_2
 {
   int srcreg, dstreg;
-  signed64 temp;
+  int64_t temp;
   int n, z;
 
   PC = cia;
@@ -949,8 +949,8 @@
   temp = State.regs[REG_MDR];
   temp <<= 32;
   temp |= State.regs[dstreg];
-  State.regs[REG_MDR] = temp % (signed32)State.regs[srcreg];
-  temp /= (signed32)State.regs[srcreg];
+  State.regs[REG_MDR] = temp % (int32_t)State.regs[srcreg];
+  temp /= (int32_t)State.regs[srcreg];
   State.regs[dstreg] = temp & 0xffffffff;
   z = (State.regs[dstreg] == 0);
   n = (State.regs[dstreg] & 0x80000000) != 0;
@@ -965,7 +965,7 @@
 *am33_2
 {
   int srcreg, dstreg;
-  unsigned64 temp;
+  uint64_t temp;
   int n, z;
 
   PC = cia;
@@ -1215,15 +1215,15 @@
 *am33_2
 {
   int srcreg1, srcreg2;
-  signed64 temp, sum;
+  int64_t temp, sum;
   int c, v;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM2);
   srcreg2 = translate_rreg (SD_, RN0);
 
-  temp = ((signed64)(signed32)State.regs[srcreg2]
-          * (signed64)(signed32)State.regs[srcreg1]);
+  temp = ((int64_t)(int32_t)State.regs[srcreg2]
+          * (int64_t)(int32_t)State.regs[srcreg1]);
   sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
   c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
   State.regs[REG_MCRL] = sum;
@@ -1244,15 +1244,15 @@
 *am33_2
 {
   int srcreg1, srcreg2;
-  unsigned64 temp, sum;
+  uint64_t temp, sum;
   int c, v;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM2);
   srcreg2 = translate_rreg (SD_, RN0);
 
-  temp = ((unsigned64)State.regs[srcreg2]
-          * (unsigned64)State.regs[srcreg1]);
+  temp = ((uint64_t)State.regs[srcreg2]
+          * (uint64_t)State.regs[srcreg1]);
   sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
   c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
   State.regs[REG_MCRL] = sum;
@@ -1273,15 +1273,15 @@
 *am33_2
 {
   int srcreg1, srcreg2;
-  signed32 temp, sum;
+  int32_t temp, sum;
   int v;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM2);
   srcreg2 = translate_rreg (SD_, RN0);
 
-  temp = ((signed32)(signed8)(State.regs[srcreg2] & 0xff)
-          * (signed32)(signed8)(State.regs[srcreg1] & 0xff));
+  temp = ((int32_t)(int8_t)(State.regs[srcreg2] & 0xff)
+          * (int32_t)(int8_t)(State.regs[srcreg1] & 0xff));
   sum = State.regs[REG_MCRL] + temp;
   v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
         && (temp & 0x80000000) != (sum & 0x80000000));
@@ -1297,15 +1297,15 @@
 *am33_2
 {
   int srcreg1, srcreg2;
-  signed64 temp, sum;
+  int64_t temp, sum;
   int v;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM2);
   srcreg2 = translate_rreg (SD_, RN0);
 
-  temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
-          * (unsigned32)(State.regs[srcreg1] & 0xff));
+  temp = ((uint32_t)(State.regs[srcreg2] & 0xff)
+          * (uint32_t)(State.regs[srcreg1] & 0xff));
   sum = State.regs[REG_MCRL] + temp;
   v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
         && (temp & 0x80000000) != (sum & 0x80000000));
@@ -1321,15 +1321,15 @@
 *am33_2
 {
   int srcreg1, srcreg2;
-  signed64 temp, sum;
+  int64_t temp, sum;
   int c, v;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM2);
   srcreg2 = translate_rreg (SD_, RN0);
 
-  temp = ((unsigned64)(signed16)(State.regs[srcreg2] & 0xffff)
-          * (unsigned64)(signed16)(State.regs[srcreg1] & 0xffff));
+  temp = ((uint64_t)(int16_t)(State.regs[srcreg2] & 0xffff)
+          * (uint64_t)(int16_t)(State.regs[srcreg1] & 0xffff));
   sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
   c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
   State.regs[REG_MCRL] = sum;
@@ -1350,15 +1350,15 @@
 *am33_2
 {
   int srcreg1, srcreg2;
-  signed64 temp, sum;
+  int64_t temp, sum;
   int c, v;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM2);
   srcreg2 = translate_rreg (SD_, RN0);
 
-  temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
-          * (unsigned64)(State.regs[srcreg1] & 0xffff));
+  temp = ((uint64_t)(State.regs[srcreg2] & 0xffff)
+          * (uint64_t)(State.regs[srcreg1] & 0xffff));
   sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
   c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
   State.regs[REG_MCRL] = sum;
@@ -1379,17 +1379,17 @@
 *am33_2
 {
   int srcreg1, srcreg2;
-  signed32 temp, temp2, sum;
+  int32_t temp, temp2, sum;
   int v;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM2);
   srcreg2 = translate_rreg (SD_, RN0);
 
-  temp = ((signed32)(signed16)(State.regs[srcreg2] & 0xffff)
-          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
-  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
-          * (signed32)(signed16)((State.regs[srcreg2] >> 16) & 0xffff));
+  temp = ((int32_t)(int16_t)(State.regs[srcreg2] & 0xffff)
+          * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+  temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+          * (int32_t)(int16_t)((State.regs[srcreg2] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
   v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
         && (temp & 0x80000000) != (sum & 0x80000000));
@@ -1405,17 +1405,17 @@
 *am33_2
 {
   int srcreg1, srcreg2;
-  unsigned32 temp, temp2, sum;
+  uint32_t temp, temp2, sum;
   int v;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM2);
   srcreg2 = translate_rreg (SD_, RN0);
 
-  temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
-          * (unsigned32)(State.regs[srcreg1] & 0xffff));
-  temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
-          * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
+  temp = ((uint32_t)(State.regs[srcreg2] & 0xffff)
+          * (uint32_t)(State.regs[srcreg1] & 0xffff));
+  temp2 = ((uint32_t)((State.regs[srcreg1] >> 16) & 0xffff)
+          * (uint32_t)((State.regs[srcreg2] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
   v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
         && (temp & 0x80000000) != (sum & 0x80000000));
@@ -1431,17 +1431,17 @@
 *am33_2
 {
   int srcreg, dstreg;
-  signed32 temp;
+  int32_t temp;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
   dstreg = translate_rreg (SD_, RN0);
 
-  temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
-          * (signed32)(signed16)(State.regs[srcreg] & 0xffff));
+  temp = ((int32_t)(int16_t)(State.regs[dstreg] & 0xffff)
+          * (int32_t)(int16_t)(State.regs[srcreg] & 0xffff));
   State.regs[REG_MDRQ] = temp;
-  temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
-          * (signed32)(signed16)((State.regs[srcreg] >>16) & 0xffff));
+  temp = ((int32_t)(int16_t)((State.regs[dstreg] >> 16) & 0xffff)
+          * (int32_t)(int16_t)((State.regs[srcreg] >>16) & 0xffff));
   State.regs[dstreg] = temp;
 }
 
@@ -1452,17 +1452,17 @@
 *am33_2
 {
   int srcreg, dstreg;
-  unsigned32 temp;
+  uint32_t temp;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RM2);
   dstreg = translate_rreg (SD_, RN0);
 
-  temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
-          * (unsigned32)(State.regs[srcreg] & 0xffff));
+  temp = ((uint32_t)(State.regs[dstreg] & 0xffff)
+          * (uint32_t)(State.regs[srcreg] & 0xffff));
   State.regs[REG_MDRQ] = temp;
-  temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
-          * (unsigned32)((State.regs[srcreg] >>16) & 0xffff));
+  temp = ((uint32_t)((State.regs[dstreg] >> 16) & 0xffff)
+          * (uint32_t)((State.regs[srcreg] >>16) & 0xffff));
   State.regs[dstreg] = temp;
 }
 
@@ -1512,7 +1512,7 @@
   /* 32bit saturation.  */
   if (State.regs[srcreg] == 0x20)
     {
-      signed64 tmp;
+      int64_t tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -1528,7 +1528,7 @@
   /* 16bit saturation */
   else if (State.regs[srcreg] == 0x10)
     {
-      signed64 tmp;
+      int64_t tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -1544,7 +1544,7 @@
   /* 8 bit saturation */
   else if (State.regs[srcreg] == 0x8)
     {
-      signed64 tmp;
+      int64_t tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -1560,7 +1560,7 @@
   /* 9 bit saturation */
   else if (State.regs[srcreg] == 0x9)
     {
-      signed64 tmp;
+      int64_t tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -1576,7 +1576,7 @@
   /* 9 bit saturation */
   else if (State.regs[srcreg] == 0x30)
     {
-      signed64 tmp;
+      int64_t tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -1731,7 +1731,7 @@
 {
   int dstreg, imm;
   int z, c, n, v;
-  unsigned32 reg2, sum;
+  uint32_t reg2, sum;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
@@ -1774,7 +1774,7 @@
 {
   int imm, dstreg;
   int z, c, n, v;
-  unsigned32 reg2, difference;
+  uint32_t reg2, difference;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
@@ -1886,7 +1886,7 @@
 *am33_2
 {
   int dstreg;
-  signed32 temp;
+  int32_t temp;
   int c, z, n;
 
   PC = cia;
@@ -1948,14 +1948,14 @@
 *am33_2
 {
   int dstreg;
-  unsigned64 temp;
+  uint64_t temp;
   int z, n;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
 
-  temp = ((signed64)(signed32)State.regs[dstreg]
-          *  (signed64)(signed32)EXTEND8 (IMM8));
+  temp = ((int64_t)(int32_t)State.regs[dstreg]
+          *  (int64_t)(int32_t)EXTEND8 (IMM8));
   State.regs[dstreg] = temp & 0xffffffff;
   State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
@@ -1971,14 +1971,14 @@
 *am33_2
 {
   int dstreg;
-  unsigned64 temp;
+  uint64_t temp;
   int z, n;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
 
-  temp = ((unsigned64)State.regs[dstreg]
-          * (unsigned64)(IMM8 & 0xff));
+  temp = ((uint64_t)State.regs[dstreg]
+          * (uint64_t)(IMM8 & 0xff));
   State.regs[dstreg] = temp & 0xffffffff;
   State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
@@ -2231,14 +2231,14 @@
 *am33_2
 {
   int srcreg;
-  signed64 temp, sum;
+  int64_t temp, sum;
   int c, v;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RN2);
 
-  temp = ((signed64)(signed32)EXTEND8 (IMM8)
-          * (signed64)(signed32)State.regs[srcreg]);
+  temp = ((int64_t)(int32_t)EXTEND8 (IMM8)
+          * (int64_t)(int32_t)State.regs[srcreg]);
   sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
   c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
   State.regs[REG_MCRL] = sum;
@@ -2259,14 +2259,14 @@
 *am33_2
 {
   int srcreg;
-  signed64 temp, sum;
+  int64_t temp, sum;
   int c, v;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RN2);
 
-  temp = ((unsigned64) (IMM8)
-          * (unsigned64)State.regs[srcreg]);
+  temp = ((uint64_t) (IMM8)
+          * (uint64_t)State.regs[srcreg]);
   sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
   c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
   State.regs[REG_MCRL] = sum;
@@ -2287,14 +2287,14 @@
 *am33_2
 {
   int srcreg;
-  signed64 temp, sum;
+  int64_t temp, sum;
   int c, v;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RN2);
 
-  temp = ((signed64)(signed8)EXTEND8 (IMM8)
-          * (signed64)(signed8)State.regs[srcreg] & 0xff);
+  temp = ((int64_t)(int8_t)EXTEND8 (IMM8)
+          * (int64_t)(int8_t)State.regs[srcreg] & 0xff);
   sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
   c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
   State.regs[REG_MCRL] = sum;
@@ -2315,14 +2315,14 @@
 *am33_2
 {
   int srcreg;
-  signed64 temp, sum;
+  int64_t temp, sum;
   int c, v;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RN2);
 
-  temp = ((unsigned64) (IMM8)
-          * (unsigned64)State.regs[srcreg] & 0xff);
+  temp = ((uint64_t) (IMM8)
+          * (uint64_t)State.regs[srcreg] & 0xff);
   sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
   c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
   State.regs[REG_MCRL] = sum;
@@ -2343,14 +2343,14 @@
 *am33_2
 {
   int srcreg;
-  signed64 temp, sum;
+  int64_t temp, sum;
   int c, v;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RN2);
 
-  temp = ((signed64)(signed16)EXTEND8 (IMM8)
-          * (signed64)(signed16)State.regs[srcreg] & 0xffff);
+  temp = ((int64_t)(int16_t)EXTEND8 (IMM8)
+          * (int64_t)(int16_t)State.regs[srcreg] & 0xffff);
   sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
   c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
   State.regs[REG_MCRL] = sum;
@@ -2371,14 +2371,14 @@
 *am33_2
 {
   int srcreg;
-  signed64 temp, sum;
+  int64_t temp, sum;
   int c, v;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RN2);
 
-  temp = ((unsigned64) (IMM8)
-          * (unsigned64)State.regs[srcreg] & 0xffff);
+  temp = ((uint64_t) (IMM8)
+          * (uint64_t)State.regs[srcreg] & 0xffff);
   sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
   c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
   State.regs[REG_MCRL] = sum;
@@ -2409,7 +2409,7 @@
   /* 32bit saturation.  */
   if (IMM8 == 0x20)
     {
-      signed64 tmp;
+      int64_t tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -2425,7 +2425,7 @@
   /* 16bit saturation */
   else if (IMM8 == 0x10)
     {
-      signed64 tmp;
+      int64_t tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -2441,7 +2441,7 @@
   /* 8 bit saturation */
   else if (IMM8 == 0x8)
     {
-      signed64 tmp;
+      int64_t tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -2457,7 +2457,7 @@
   /* 9 bit saturation */
   else if (IMM8 == 0x9)
     {
-      signed64 tmp;
+      int64_t tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -2473,7 +2473,7 @@
   /* 9 bit saturation */
   else if (IMM8 == 0x30)
     {
-      signed64 tmp;
+      int64_t tmp;
 
       tmp = State.regs[REG_MCRH];
       tmp <<= 32;
@@ -2496,7 +2496,7 @@
 *am33_2
 {
   int z, c, n, v;
-  unsigned32 sum, source1, source2;
+  uint32_t sum, source1, source2;
   int srcreg1, srcreg2, dstreg;
 
   PC = cia;
@@ -2527,7 +2527,7 @@
 *am33_2
 {
   int z, c, n, v;
-  unsigned32 sum, source1, source2;
+  uint32_t sum, source1, source2;
   int srcreg1, srcreg2, dstreg;
 
   PC = cia;
@@ -2558,7 +2558,7 @@
 *am33_2
 {
   int z, c, n, v;
-  unsigned32 difference, source1, source2;
+  uint32_t difference, source1, source2;
   int srcreg1, srcreg2, dstreg;
 
   PC = cia;
@@ -2589,7 +2589,7 @@
 *am33_2
 {
   int z, c, n, v;
-  unsigned32 difference, source1, source2;
+  uint32_t difference, source1, source2;
   int srcreg1, srcreg2, dstreg;
 
   PC = cia;
@@ -2689,7 +2689,7 @@
 *am33_2
 {
   int z, c, n;
-  signed32 temp;
+  int32_t temp;
   int srcreg1, srcreg2, dstreg;
 
   PC = cia;
@@ -2763,7 +2763,7 @@
 *am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed64 temp;
+  int64_t temp;
   int n, z;
 
   PC = cia;
@@ -2772,8 +2772,8 @@
   dstreg1 = translate_rreg (SD_, RD0);
   dstreg2 = translate_rreg (SD_, RD2);
 
-  temp = ((signed64)(signed32)State.regs[srcreg1]
-          *  (signed64)(signed32)State.regs[srcreg2]);
+  temp = ((int64_t)(int32_t)State.regs[srcreg1]
+          *  (int64_t)(int32_t)State.regs[srcreg2]);
   State.regs[dstreg2] = temp & 0xffffffff;
   State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
 
@@ -2791,7 +2791,7 @@
 *am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed64 temp;
+  int64_t temp;
   int n, z;
 
   PC = cia;
@@ -2800,8 +2800,8 @@
   dstreg1 = translate_rreg (SD_, RD0);
   dstreg2 = translate_rreg (SD_, RD2);
 
-  temp = ((unsigned64)State.regs[srcreg1]
-          *  (unsigned64)State.regs[srcreg2]);
+  temp = ((uint64_t)State.regs[srcreg1]
+          *  (uint64_t)State.regs[srcreg2]);
   State.regs[dstreg2] = temp & 0xffffffff;
   State.regs[dstreg1] = (temp & 0xffffffff00000000LL) >> 32;
 
@@ -2987,8 +2987,8 @@
 *am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed64 temp;
-  unsigned32 sum;
+  int64_t temp;
+  uint32_t sum;
   int c, v;
 
   PC = cia;
@@ -2997,8 +2997,8 @@
   dstreg1 = translate_rreg (SD_, RD0);
   dstreg2 = translate_rreg (SD_, RD2);
 
-  temp = ((signed64)(signed32)State.regs[srcreg1]
-          *  (signed64)(signed32)State.regs[srcreg2]);
+  temp = ((int64_t)(int32_t)State.regs[srcreg1]
+          *  (int64_t)(int32_t)State.regs[srcreg2]);
 
   sum = State.regs[dstreg2] + (temp & 0xffffffff);
   c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
@@ -3024,8 +3024,8 @@
 *am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed64 temp;
-  unsigned32 sum;
+  int64_t temp;
+  uint32_t sum;
   int c, v;
 
   PC = cia;
@@ -3034,8 +3034,8 @@
   dstreg1 = translate_rreg (SD_, RD0);
   dstreg2 = translate_rreg (SD_, RD2);
 
-  temp = ((unsigned64)State.regs[srcreg1]
-          * (unsigned64)State.regs[srcreg2]);
+  temp = ((uint64_t)State.regs[srcreg1]
+          * (uint64_t)State.regs[srcreg2]);
 
   sum = State.regs[dstreg2] + (temp & 0xffffffff);
   c = (sum < State.regs[dstreg2]) || (sum < (temp & 0xffffffff));
@@ -3061,7 +3061,7 @@
 *am33_2
 {
   int srcreg1, srcreg2, dstreg;
-  signed32 temp, sum;
+  int32_t temp, sum;
   int v;
 
   PC = cia;
@@ -3069,8 +3069,8 @@
   srcreg2 = translate_rreg (SD_, RN0);
   dstreg = translate_rreg (SD_, RD0);
 
-  temp = ((signed32)(State.regs[srcreg2] & 0xff)
-          * (signed32)(State.regs[srcreg1] & 0xff));
+  temp = ((int32_t)(State.regs[srcreg2] & 0xff)
+          * (int32_t)(State.regs[srcreg1] & 0xff));
   sum = State.regs[dstreg] + temp;
   v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
         && (temp & 0x80000000) != (sum & 0x80000000));
@@ -3090,7 +3090,7 @@
 *am33_2
 {
   int srcreg1, srcreg2, dstreg;
-  signed32 temp, sum;
+  int32_t temp, sum;
   int v;
 
   PC = cia;
@@ -3098,8 +3098,8 @@
   srcreg2 = translate_rreg (SD_, RN0);
   dstreg = translate_rreg (SD_, RD0);
 
-  temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
-          * (unsigned32)(State.regs[srcreg1] & 0xff));
+  temp = ((uint32_t)(State.regs[srcreg2] & 0xff)
+          * (uint32_t)(State.regs[srcreg1] & 0xff));
   sum = State.regs[dstreg] + temp;
   v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
         && (temp & 0x80000000) != (sum & 0x80000000));
@@ -3119,7 +3119,7 @@
 *am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed64 temp, sum;
+  int64_t temp, sum;
   int v;
 
   PC = cia;
@@ -3128,8 +3128,8 @@
   dstreg1 = translate_rreg (SD_, RD0);
   dstreg2 = translate_rreg (SD_, RD0);
 
-  temp = ((signed32)(State.regs[srcreg2] & 0xffff)
-          * (signed32)(State.regs[srcreg1] & 0xffff));
+  temp = ((int32_t)(State.regs[srcreg2] & 0xffff)
+          * (int32_t)(State.regs[srcreg1] & 0xffff));
   State.regs[dstreg2] += (temp & 0xffffffff);
   sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
   v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
@@ -3150,7 +3150,7 @@
 *am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed64 temp, sum;
+  int64_t temp, sum;
   int v;
 
   PC = cia;
@@ -3159,8 +3159,8 @@
   dstreg1 = translate_rreg (SD_, RD0);
   dstreg2 = translate_rreg (SD_, RD0);
 
-  temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
-          * (unsigned32)(State.regs[srcreg1] & 0xffff));
+  temp = ((uint32_t)(State.regs[srcreg2] & 0xffff)
+          * (uint32_t)(State.regs[srcreg1] & 0xffff));
   State.regs[dstreg2] += (temp & 0xffffffff);
   sum = State.regs[dstreg1] + ((temp >> 32) & 0xffffffff);
   v = ((State.regs[dstreg1] & 0x80000000) == (temp & 0x80000000)
@@ -3181,7 +3181,7 @@
 *am33_2
 {
   int srcreg1, srcreg2, dstreg;
-  signed32 temp, temp2, sum;
+  int32_t temp, temp2, sum;
   int v;
 
   PC = cia;
@@ -3189,10 +3189,10 @@
   srcreg2 = translate_rreg (SD_, RN0);
   dstreg = translate_rreg (SD_, RD0);
 
-  temp = ((signed32)(State.regs[srcreg2] & 0xffff)
-          * (signed32)(State.regs[srcreg1] & 0xffff));
-  temp2 = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
-          * (signed32)((State.regs[srcreg2] >> 16) & 0xffff));
+  temp = ((int32_t)(State.regs[srcreg2] & 0xffff)
+          * (int32_t)(State.regs[srcreg1] & 0xffff));
+  temp2 = ((int32_t)((State.regs[srcreg1] >> 16) & 0xffff)
+          * (int32_t)((State.regs[srcreg2] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[dstreg];
   v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
         && (temp & 0x80000000) != (sum & 0x80000000));
@@ -3212,7 +3212,7 @@
 *am33_2
 {
   int srcreg1, srcreg2, dstreg;
-  signed32 temp, temp2, sum;
+  int32_t temp, temp2, sum;
   int v;
 
   PC = cia;
@@ -3220,10 +3220,10 @@
   srcreg2 = translate_rreg (SD_, RN0);
   dstreg = translate_rreg (SD_, RD0);
 
-  temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
-          * (unsigned32)(State.regs[srcreg1] & 0xffff));
-  temp2 = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
-          * (unsigned32)((State.regs[srcreg2] >> 16) & 0xffff));
+  temp = ((uint32_t)(State.regs[srcreg2] & 0xffff)
+          * (uint32_t)(State.regs[srcreg1] & 0xffff));
+  temp2 = ((uint32_t)((State.regs[srcreg1] >> 16) & 0xffff)
+          * (uint32_t)((State.regs[srcreg2] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[dstreg];
   v = ((State.regs[dstreg] & 0x80000000) == (temp & 0x80000000)
         && (temp & 0x80000000) != (sum & 0x80000000));
@@ -3243,7 +3243,7 @@
 *am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed64 temp;
+  int64_t temp;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM2);
@@ -3251,11 +3251,11 @@
   dstreg1 = translate_rreg (SD_, RD0);
   dstreg2 = translate_rreg (SD_, RD2);
 
-  temp = ((signed32)(State.regs[srcreg1] & 0xffff)
-          * (signed32)(State.regs[srcreg1] & 0xffff));
+  temp = ((int32_t)(State.regs[srcreg1] & 0xffff)
+          * (int32_t)(State.regs[srcreg1] & 0xffff));
   State.regs[dstreg2] = temp;
-  temp = ((signed32)((State.regs[srcreg1] >> 16) & 0xffff)
-          * (signed32)((State.regs[srcreg1] >>16) & 0xffff));
+  temp = ((int32_t)((State.regs[srcreg1] >> 16) & 0xffff)
+          * (int32_t)((State.regs[srcreg1] >>16) & 0xffff));
   State.regs[dstreg1] = temp;
 }
 
@@ -3266,7 +3266,7 @@
 *am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed64 temp;
+  int64_t temp;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM2);
@@ -3274,11 +3274,11 @@
   dstreg1 = translate_rreg (SD_, RD0);
   dstreg2 = translate_rreg (SD_, RD2);
 
-  temp = ((unsigned32)(State.regs[srcreg1] & 0xffff)
-          * (unsigned32)(State.regs[srcreg1] & 0xffff));
+  temp = ((uint32_t)(State.regs[srcreg1] & 0xffff)
+          * (uint32_t)(State.regs[srcreg1] & 0xffff));
   State.regs[dstreg2] = temp;
-  temp = ((unsigned32)((State.regs[srcreg1] >> 16) & 0xffff)
-          * (unsigned32)((State.regs[srcreg1] >>16) & 0xffff));
+  temp = ((uint32_t)((State.regs[srcreg1] >> 16) & 0xffff)
+          * (uint32_t)((State.regs[srcreg1] >>16) & 0xffff));
   State.regs[dstreg1] = temp;
 }
 
@@ -3396,7 +3396,7 @@
 *am33_2
 {
   int dstreg, z, n, c, v;
-  unsigned32 sum, imm, reg2;
+  uint32_t sum, imm, reg2;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
@@ -3437,7 +3437,7 @@
 *am33_2
 {
   int dstreg, z, n, c, v;
-  unsigned32 difference, imm, reg2;
+  uint32_t difference, imm, reg2;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
@@ -3549,7 +3549,7 @@
 *am33_2
 {
   int dstreg;
-  signed32 temp;
+  int32_t temp;
   int c, z, n;
 
   PC = cia;
@@ -3612,14 +3612,14 @@
 *am33_2
 {
   int dstreg;
-  unsigned64 temp;
+  uint64_t temp;
   int z, n;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
 
-  temp = ((signed64)(signed32)State.regs[dstreg]
-          *  (signed64)(signed32)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
+  temp = ((int64_t)(int32_t)State.regs[dstreg]
+          *  (int64_t)(int32_t)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
   State.regs[dstreg] = temp & 0xffffffff;
   State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
@@ -3635,14 +3635,14 @@
 *am33_2
 {
   int dstreg;
-  unsigned64 temp;
+  uint64_t temp;
   int z, n;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
 
-  temp = ((unsigned64)State.regs[dstreg]
-          *  (unsigned64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
+  temp = ((uint64_t)State.regs[dstreg]
+          *  (uint64_t)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)));
   State.regs[dstreg] = temp & 0xffffffff;
   State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
@@ -3909,14 +3909,14 @@
 *am33_2
 {
   int srcreg;
-  signed64 temp, sum;
+  int64_t temp, sum;
   int c, v;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RN2);
 
-  temp = ((signed64)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))
-          * (signed64)State.regs[srcreg]);
+  temp = ((int64_t)EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C))
+          * (int64_t)State.regs[srcreg]);
   sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
   c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
   State.regs[REG_MCRL] = sum;
@@ -3937,14 +3937,14 @@
 *am33_2
 {
   int srcreg;
-  signed64 temp, sum;
+  int64_t temp, sum;
   int c, v;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RN2);
 
-  temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
-          * (unsigned64)State.regs[srcreg]);
+  temp = ((uint64_t) (FETCH24 (IMM24A, IMM24B, IMM24C))
+          * (uint64_t)State.regs[srcreg]);
   sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
   c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
   State.regs[REG_MCRL] = sum;
@@ -3965,14 +3965,14 @@
 *am33_2
 {
   int srcreg;
-  signed64 temp, sum;
+  int64_t temp, sum;
   int c, v;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RN2);
 
-  temp = ((signed64)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
-          * (signed64)State.regs[srcreg] & 0xff);
+  temp = ((int64_t)EXTEND8 (FETCH24 (IMM24A, IMM24B, IMM24C))
+          * (int64_t)State.regs[srcreg] & 0xff);
   sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
   c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
   State.regs[REG_MCRL] = sum;
@@ -3993,14 +3993,14 @@
 *am33_2
 {
   int srcreg;
-  signed64 temp, sum;
+  int64_t temp, sum;
   int c, v;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RN2);
 
-  temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C))
-          * (unsigned64)State.regs[srcreg] & 0xff);
+  temp = ((uint64_t) (FETCH24 (IMM24A, IMM24B, IMM24C))
+          * (uint64_t)State.regs[srcreg] & 0xff);
   sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
   c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
   State.regs[REG_MCRL] = sum;
@@ -4021,14 +4021,14 @@
 *am33_2
 {
   int srcreg;
-  signed64 temp, sum;
+  int64_t temp, sum;
   int c, v;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RN2);
 
-  temp = ((signed64)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
-          * (signed64)State.regs[srcreg] & 0xffff);
+  temp = ((int64_t)EXTEND16 (FETCH24 (IMM24A, IMM24B, IMM24C))
+          * (int64_t)State.regs[srcreg] & 0xffff);
   sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
   c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
   State.regs[REG_MCRL] = sum;
@@ -4049,14 +4049,14 @@
 *am33_2
 {
   int srcreg;
-  signed64 temp, sum;
+  int64_t temp, sum;
   int c, v;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RN2);
 
-  temp = ((unsigned64) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
-          * (unsigned64)State.regs[srcreg] & 0xffff);
+  temp = ((uint64_t) (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffff)
+          * (uint64_t)State.regs[srcreg] & 0xffff);
   sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
   c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
   State.regs[REG_MCRL] = sum;
@@ -4197,7 +4197,7 @@
 *am33_2
 {
   int dstreg;
-  unsigned32 imm, reg2, sum;
+  uint32_t imm, reg2, sum;
   int z, n, c, v;
 
   PC = cia;
@@ -4239,7 +4239,7 @@
 *am33_2
 {
   int dstreg;
-  unsigned32 imm, reg2, difference;
+  uint32_t imm, reg2, difference;
   int z, n, c, v;
 
   PC = cia;
@@ -4352,7 +4352,7 @@
 *am33_2
 {
   int dstreg;
-  signed32 temp;
+  int32_t temp;
   int c, z, n;
 
   PC = cia;
@@ -4414,14 +4414,14 @@
 *am33_2
 {
   int dstreg;
-  unsigned64 temp;
+  uint64_t temp;
   int z, n;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
 
-  temp = ((signed64)(signed32)State.regs[dstreg]
-          *  (signed64)(signed32)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
+  temp = ((int64_t)(int32_t)State.regs[dstreg]
+          *  (int64_t)(int32_t)(FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
   State.regs[dstreg] = temp & 0xffffffff;
   State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
@@ -4437,14 +4437,14 @@
 *am33_2
 {
   int dstreg;
-  unsigned64 temp;
+  uint64_t temp;
   int z, n;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
 
-  temp = ((unsigned64)State.regs[dstreg]
-          *  (unsigned64) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
+  temp = ((uint64_t)State.regs[dstreg]
+          *  (uint64_t) (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D)));
   State.regs[dstreg] = temp & 0xffffffff;
   State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[dstreg] == 0);
@@ -4710,15 +4710,15 @@
 *am33_2
 {
   int srcreg, imm;
-  signed64 temp, sum;
+  int64_t temp, sum;
   int c, v;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RN0);
   imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 
-  temp = ((signed64)(signed32)State.regs[srcreg]
-          * (signed64)(signed32)imm);
+  temp = ((int64_t)(int32_t)State.regs[srcreg]
+          * (int64_t)(int32_t)imm);
   sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
   c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
   State.regs[REG_MCRL] = sum;
@@ -4739,15 +4739,15 @@
 *am33_2
 {
   int srcreg, imm;
-  signed64 temp, sum;
+  int64_t temp, sum;
   int c, v;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RN0);
   imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 
-  temp = ((unsigned64)State.regs[srcreg]
-          * (unsigned64)imm);
+  temp = ((uint64_t)State.regs[srcreg]
+          * (uint64_t)imm);
   sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
   c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
   State.regs[REG_MCRL] = sum;
@@ -4768,15 +4768,15 @@
 *am33_2
 {
   int srcreg, imm;
-  signed32 temp, sum;
+  int32_t temp, sum;
   int v;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RN0);
   imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 
-  temp = ((signed32)(signed8)(State.regs[srcreg] & 0xff)
-          * (signed32)(signed8)(imm & 0xff));
+  temp = ((int32_t)(int8_t)(State.regs[srcreg] & 0xff)
+          * (int32_t)(int8_t)(imm & 0xff));
   sum = State.regs[REG_MCRL] + temp;
   v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
         && (temp & 0x80000000) != (sum & 0x80000000));
@@ -4792,15 +4792,15 @@
 *am33_2
 {
   int srcreg, imm;
-  signed32 temp, sum;
+  int32_t temp, sum;
   int v;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RN0);
   imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 
-  temp = ((unsigned32)(State.regs[srcreg] & 0xff)
-          * (unsigned32)(imm & 0xff));
+  temp = ((uint32_t)(State.regs[srcreg] & 0xff)
+          * (uint32_t)(imm & 0xff));
   sum = State.regs[REG_MCRL] + temp;
   v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
         && (temp & 0x80000000) != (sum & 0x80000000));
@@ -4816,15 +4816,15 @@
 *am33_2
 {
   int srcreg, imm;
-  signed32 temp, sum;
+  int32_t temp, sum;
   int v;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RN0);
   imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 
-  temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
-          * (signed32)(signed16)(imm & 0xffff));
+  temp = ((int32_t)(int16_t)(State.regs[srcreg] & 0xffff)
+          * (int32_t)(int16_t)(imm & 0xffff));
   sum = State.regs[REG_MCRL] + temp;
   v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
         && (temp & 0x80000000) != (sum & 0x80000000));
@@ -4840,15 +4840,15 @@
 *am33_2
 {
   int srcreg, imm;
-  signed32 temp, sum;
+  int32_t temp, sum;
   int v;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RN0);
   imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 
-  temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
-          * (unsigned32)(imm & 0xffff));
+  temp = ((uint32_t)(State.regs[srcreg] & 0xffff)
+          * (uint32_t)(imm & 0xffff));
   sum = State.regs[REG_MCRL] + temp;
   v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
         && (temp & 0x80000000) != (sum & 0x80000000));
@@ -4864,17 +4864,17 @@
 *am33_2
 {
   int srcreg, imm;
-  signed32 temp, temp2, sum;
+  int32_t temp, temp2, sum;
   int v;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RN0);
   imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 
-  temp = ((signed32)(signed16)(State.regs[srcreg] & 0xffff)
-          * (signed32)(signed16)(imm & 0xffff));
-  temp2 = ((signed32)(signed16)((State.regs[srcreg] >> 16) & 0xffff)
-          * (signed32)(signed16)((imm >> 16) & 0xffff));
+  temp = ((int32_t)(int16_t)(State.regs[srcreg] & 0xffff)
+          * (int32_t)(int16_t)(imm & 0xffff));
+  temp2 = ((int32_t)(int16_t)((State.regs[srcreg] >> 16) & 0xffff)
+          * (int32_t)(int16_t)((imm >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
   v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
         && (temp & 0x80000000) != (sum & 0x80000000));
@@ -4890,17 +4890,17 @@
 *am33_2
 {
   int srcreg, imm;
-  signed32 temp, temp2, sum;
+  int32_t temp, temp2, sum;
   int v;
 
   PC = cia;
   srcreg = translate_rreg (SD_, RN0);
   imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 
-  temp = ((unsigned32)(State.regs[srcreg] & 0xffff)
-          * (unsigned32)(imm & 0xffff));
-  temp2 = ((unsigned32)((State.regs[srcreg] >> 16) & 0xffff)
-          * (unsigned32)((imm >> 16) & 0xffff));
+  temp = ((uint32_t)(State.regs[srcreg] & 0xffff)
+          * (uint32_t)(imm & 0xffff));
+  temp2 = ((uint32_t)((State.regs[srcreg] >> 16) & 0xffff)
+          * (uint32_t)((imm >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
   v = ((State.regs[REG_MCRL] & 0x80000000) == (temp & 0x80000000)
         && (temp & 0x80000000) != (sum & 0x80000000));
@@ -4916,17 +4916,17 @@
 *am33_2
 {
   int imm, dstreg;
-  signed32 temp;
+  int32_t temp;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
   imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 
-  temp = ((signed32)(signed16)(State.regs[dstreg] & 0xffff)
-          * (signed32)(signed16)(imm & 0xffff));
+  temp = ((int32_t)(int16_t)(State.regs[dstreg] & 0xffff)
+          * (int32_t)(int16_t)(imm & 0xffff));
   State.regs[REG_MDRQ] = temp;
-  temp = ((signed32)(signed16)((State.regs[dstreg] >> 16) & 0xffff)
-          * (signed32)(signed16)((imm>>16) & 0xffff));
+  temp = ((int32_t)(int16_t)((State.regs[dstreg] >> 16) & 0xffff)
+          * (int32_t)(int16_t)((imm>>16) & 0xffff));
   State.regs[dstreg] = temp;
 }
 
@@ -4937,17 +4937,17 @@
 *am33_2
 {
   int imm, dstreg;
-  signed32 temp;
+  int32_t temp;
 
   PC = cia;
   dstreg = translate_rreg (SD_, RN0);
   imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
 
-  temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
-          * (unsigned32)(imm & 0xffff));
+  temp = ((uint32_t)(State.regs[dstreg] & 0xffff)
+          * (uint32_t)(imm & 0xffff));
   State.regs[REG_MDRQ] = temp;
-  temp = ((unsigned32)((State.regs[dstreg] >> 16) & 0xffff)
-          * (unsigned32)((imm >>16) & 0xffff));
+  temp = ((uint32_t)((State.regs[dstreg] >> 16) & 0xffff)
+          * (uint32_t)((imm >>16) & 0xffff));
   State.regs[dstreg] = temp;
 }
 
@@ -7348,7 +7348,7 @@
 *am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed32 temp, temp2, sum;
+  int32_t temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7356,10 +7356,10 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
-          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
-  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
-           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+  temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+          * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+  temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+           * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
   State.regs[dstreg2] += State.regs[srcreg2];
@@ -7373,17 +7373,17 @@
 *am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed32 temp, temp2, sum;
+  int32_t temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
-          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
-  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
-           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+  temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+          * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+  temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+           * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
   State.regs[dstreg2] += EXTEND4 (IMM4);
@@ -7397,7 +7397,7 @@
 *am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed32 temp, temp2, sum;
+  int32_t temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7405,10 +7405,10 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
-          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
-  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
-           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+  temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+          * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+  temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+           * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
   State.regs[dstreg2] -= State.regs[srcreg2];
@@ -7422,17 +7422,17 @@
 *am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed32 temp, temp2, sum;
+  int32_t temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
-          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
-  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
-           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+  temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+          * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+  temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+           * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
   State.regs[dstreg2] -= EXTEND4 (IMM4);
@@ -7446,7 +7446,7 @@
 *am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed32 temp, temp2, sum;
+  int32_t temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7454,10 +7454,10 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
-          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
-  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
-           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+  temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+          * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+  temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+           * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
   genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
@@ -7471,17 +7471,17 @@
 *am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed32 temp, temp2, sum;
+  int32_t temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
-          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
-  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
-           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+  temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+          * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+  temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+           * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
   genericCmp (EXTEND4 (IMM4), State.regs[dstreg2]);
@@ -7495,7 +7495,7 @@
 *am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed32 temp, temp2, sum;
+  int32_t temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7503,10 +7503,10 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
-          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
-  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
-           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+  temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+          * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+  temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+           * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
   State.regs[dstreg2] = State.regs[srcreg2];
@@ -7520,17 +7520,17 @@
 *am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed32 temp, temp2, sum;
+  int32_t temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
-          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
-  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
-           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+  temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+          * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+  temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+           * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
   State.regs[dstreg2] = EXTEND4 (IMM4);
@@ -7544,7 +7544,7 @@
 *am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed32 temp, temp2, sum;
+  int32_t temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7552,10 +7552,10 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
-          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
-  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
-           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+  temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+          * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+  temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+           * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
   temp = State.regs[dstreg2];
@@ -7571,17 +7571,17 @@
 *am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed32 temp, temp2, sum;
+  int32_t temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
-          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
-  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
-           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+  temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+          * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+  temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+           * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
   temp = State.regs[dstreg2];
@@ -7597,7 +7597,7 @@
 *am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed32 temp, temp2, sum;
+  int32_t temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7605,10 +7605,10 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
-          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
-  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
-           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+  temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+          * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+  temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+           * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
   State.regs[dstreg2] >>= State.regs[srcreg2];
@@ -7622,17 +7622,17 @@
 *am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed32 temp, temp2, sum;
+  int32_t temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
-          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
-  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
-           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+  temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+          * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+  temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+           * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
   State.regs[dstreg2] >>= IMM4;
@@ -7647,7 +7647,7 @@
 *am33_2
 {
   int srcreg1, srcreg2, dstreg1, dstreg2;
-  signed32 temp, temp2, sum;
+  int32_t temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
@@ -7655,10 +7655,10 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
-          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
-  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
-           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+  temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+          * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+  temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+           * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
   State.regs[dstreg2] <<= State.regs[srcreg2];
@@ -7672,17 +7672,17 @@
 *am33_2
 {
   int srcreg1, dstreg1, dstreg2;
-  signed32 temp, temp2, sum;
+  int32_t temp, temp2, sum;
 
   PC = cia;
   srcreg1 = translate_rreg (SD_, RM1);
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  temp = ((signed32)(signed16)(State.regs[dstreg1] & 0xffff)
-          * (signed32)(signed16)(State.regs[srcreg1] & 0xffff));
-  temp2 = ((signed32)(signed16)((State.regs[srcreg1] >> 16) & 0xffff)
-           * (signed32)(signed16)((State.regs[dstreg1] >> 16) & 0xffff));
+  temp = ((int32_t)(int16_t)(State.regs[dstreg1] & 0xffff)
+          * (int32_t)(int16_t)(State.regs[srcreg1] & 0xffff));
+  temp2 = ((int32_t)(int16_t)((State.regs[srcreg1] >> 16) & 0xffff)
+           * (int32_t)(int16_t)((State.regs[dstreg1] >> 16) & 0xffff));
   sum = temp + temp2 + State.regs[REG_MCRL];
 
   State.regs[dstreg2] <<= IMM4;

diff --git a/sim/mn10300/dv-mn103cpu.c b/sim/mn10300/dv-mn103cpu.c
index c8e897ebbda646d29ea5178d12f888e3417408ad..b3640b93dacf164403026cdc3ea6201b00eff56c 100644 (file)
--- a/sim/mn10300/dv-mn103cpu.c
+++ b/sim/mn10300/dv-mn103cpu.c
@@ -113,9 +113,9 @@ struct mn103cpu {
   int pending_nmi;
   int pending_reset;
   /* the visible registers */
-  unsigned16 interrupt_vector[NR_VECTORS];
-  unsigned16 internal_memory_control;
-  unsigned16 cpu_mode;
+  uint16_t interrupt_vector[NR_VECTORS];
+  uint16_t internal_memory_control;
+  uint16_t cpu_mode;
 };
 
 
@@ -357,7 +357,7 @@ mn103cpu_io_read_buffer (struct hw *me,
                         unsigned nr_bytes)
 {
   struct mn103cpu *controller = hw_data (me);
-  unsigned16 val = 0;
+  uint16_t val = 0;
   enum mn103cpu_regs reg = decode_mn103cpu_addr (me, controller, base);
 
   switch (reg)
@@ -383,7 +383,7 @@ mn103cpu_io_read_buffer (struct hw *me,
     }
 
   if (nr_bytes == 2)
-    *(unsigned16*) dest = H2LE_2 (val);
+    *(uint16_t*) dest = H2LE_2 (val);
 
   return nr_bytes;
 }     
@@ -396,14 +396,14 @@ mn103cpu_io_write_buffer (struct hw *me,
                          unsigned nr_bytes)
 {
   struct mn103cpu *controller = hw_data (me);
-  unsigned16 val;
+  uint16_t val;
   enum mn103cpu_regs reg;
 
   if (nr_bytes != 2)
     hw_abort (me, "must be two byte write");
 
   reg = decode_mn103cpu_addr (me, controller, base);
-  val = LE2H_2 (* (unsigned16 *) source);
+  val = LE2H_2 (* (uint16_t *) source);
 
   switch (reg)
     {

diff --git a/sim/mn10300/dv-mn103int.c b/sim/mn10300/dv-mn103int.c
index 66df97a63c8dd7a019a6f24fbf721eab838b5c79..071d7e5389c7a0efb3fe90a9d96233dfeaae72cc 100644 (file)
--- a/sim/mn10300/dv-mn103int.c
+++ b/sim/mn10300/dv-mn103int.c
@@ -517,14 +517,14 @@ decode_group (struct hw *me,
   return &controller->group[gid];
 }
 
-static unsigned8
+static uint8_t
 read_icr (struct hw *me,
          struct mn103int *controller,
          unsigned_word base)
 {
   unsigned_word offset;
   struct mn103int_group *group = decode_group (me, controller, base, &offset);
-  unsigned8 val = 0;
+  uint8_t val = 0;
   switch (group->type)
     {
 
@@ -571,7 +571,7 @@ static void
 write_icr (struct hw *me,
           struct mn103int *controller,
           unsigned_word base,
-          unsigned8 val)
+          uint8_t val)
 {
   unsigned_word offset;
   struct mn103int_group *group = decode_group (me, controller, base, &offset);
@@ -632,12 +632,12 @@ write_icr (struct hw *me,
 
 /* Read the IAGR (Interrupt accepted group register) */
 
-static unsigned8
+static uint8_t
 read_iagr (struct hw *me,
           struct mn103int *controller,
           unsigned_word offset)
 {
-  unsigned8 val;
+  uint8_t val;
   switch (offset)
     {
     case 0:
@@ -687,13 +687,13 @@ external_group (struct mn103int *controller,
     }
 }
 
-static unsigned8
+static uint8_t
 read_extmd (struct hw *me,
            struct mn103int *controller,
            unsigned_word offset)
 {
   int gid;
-  unsigned8 val = 0;
+  uint8_t val = 0;
   struct mn103int_group *group = external_group (controller, offset);
   if (group != NULL)
     {
@@ -710,7 +710,7 @@ static void
 write_extmd (struct hw *me,
             struct mn103int *controller,
             unsigned_word offset,
-            unsigned8 val)
+            uint8_t val)
 {
   int gid;
   struct mn103int_group *group = external_group (controller, offset);
@@ -756,7 +756,7 @@ mn103int_io_read_buffer (struct hw *me,
                         unsigned nr_bytes)
 {
   struct mn103int *controller = hw_data (me);
-  unsigned8 *buf = dest;
+  uint8_t *buf = dest;
   unsigned byte;
   /* HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes)); */
   for (byte = 0; byte < nr_bytes; byte++)
@@ -789,7 +789,7 @@ mn103int_io_write_buffer (struct hw *me,
                          unsigned nr_bytes)
 {
   struct mn103int *controller = hw_data (me);
-  const unsigned8 *buf = source;
+  const uint8_t *buf = source;
   unsigned byte;
   /* HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes)); */
   for (byte = 0; byte < nr_bytes; byte++)

diff --git a/sim/mn10300/dv-mn103iop.c b/sim/mn10300/dv-mn103iop.c
index 2d86bfb171631c571eeee610f969bb8a771ed27c..515b977b08b25c7e56b5205c2a7e89291473bbc9 100644 (file)
--- a/sim/mn10300/dv-mn103iop.c
+++ b/sim/mn10300/dv-mn103iop.c
@@ -87,7 +87,7 @@ enum {
 };
 
 typedef struct _mn10300_ioport {
-  unsigned8 output, output_mode, control, pin;
+  uint8_t output, output_mode, control, pin;
   struct hw_event *event;
 } mn10300_ioport;
 
@@ -96,7 +96,7 @@ typedef struct _mn10300_ioport {
 struct mn103iop {
   struct mn103iop_block block[NR_BLOCKS];
   mn10300_ioport port[NR_PORTS];
-  unsigned8      p2ss, p4ss;
+  uint8_t      p2ss, p4ss;
 };
 
 
@@ -215,7 +215,7 @@ read_output_reg (struct hw *me,
 {
   if ( nr_bytes == 1 )
     {
-      *(unsigned8 *)dest = io_port->port[io_port_reg].output;
+      *(uint8_t *)dest = io_port->port[io_port_reg].output;
     }
   else
     {
@@ -236,7 +236,7 @@ read_output_mode_reg (struct hw *me,
     {
       /* check if there are fields which can't be written and
         take appropriate action depending what bits are set */
-      *(unsigned8 *)dest = io_port->port[io_port_reg].output_mode;
+      *(uint8_t *)dest = io_port->port[io_port_reg].output_mode;
     }
   else
     {
@@ -255,7 +255,7 @@ read_control_reg (struct hw *me,
 {
   if ( nr_bytes == 1 )
     {
-      *(unsigned8 *)dest = io_port->port[io_port_reg].control;
+      *(uint8_t *)dest = io_port->port[io_port_reg].control;
     }
   else
     {
@@ -274,7 +274,7 @@ read_pin_reg (struct hw *me,
 {
   if ( nr_bytes == 1 )
     {
-      *(unsigned8 *)dest = io_port->port[io_port_reg].pin;
+      *(uint8_t *)dest = io_port->port[io_port_reg].pin;
     }
   else
     {
@@ -296,11 +296,11 @@ read_dedicated_control_reg (struct hw *me,
       /* select on io_port_reg: */
       if ( io_port_reg == P2SS )
        {
-         *(unsigned8 *)dest = io_port->p2ss;
+         *(uint8_t *)dest = io_port->p2ss;
        }
       else
        {
-         *(unsigned8 *)dest = io_port->p4ss;
+         *(uint8_t *)dest = io_port->p4ss;
        }
     }
   else
@@ -375,7 +375,7 @@ write_output_reg (struct hw *me,
                  const void *source,
                  unsigned  nr_bytes)
 {
-  unsigned8 buf = *(unsigned8 *)source;
+  uint8_t buf = *(uint8_t *)source;
   if ( nr_bytes == 1 )
     {
       if ( io_port_reg == 3 && (buf & 0xfc) != 0 )
@@ -402,7 +402,7 @@ write_output_mode_reg (struct hw *me,
                       const void *source,
                       unsigned  nr_bytes)
 {
-  unsigned8 buf = *(unsigned8 *)source;
+  uint8_t buf = *(uint8_t *)source;
   if ( nr_bytes == 1 )
     {
       /* check if there are fields which can't be written and
@@ -432,7 +432,7 @@ write_control_reg (struct hw *me,
                   const void *source,
                   unsigned  nr_bytes)
 {
-  unsigned8 buf = *(unsigned8 *)source;
+  uint8_t buf = *(uint8_t *)source;
   if ( nr_bytes == 1 )
     {
       if ( io_port_reg == 3 && (buf & 0xfc) != 0 )
@@ -459,7 +459,7 @@ write_dedicated_control_reg (struct hw *me,
                             const void *source,
                             unsigned  nr_bytes)
 {
-  unsigned8 buf = *(unsigned8 *)source;
+  uint8_t buf = *(uint8_t *)source;
   if ( nr_bytes == 1 )
     {
       /* select on io_port_reg: */

diff --git a/sim/mn10300/dv-mn103ser.c b/sim/mn10300/dv-mn103ser.c
index b02f7d702758a6f97a97c2823faa21929d0ebcc2..c1a61c9798eb70e063e5a60a96f87a9694ef8479 100644 (file)
--- a/sim/mn10300/dv-mn103ser.c
+++ b/sim/mn10300/dv-mn103ser.c
@@ -81,8 +81,8 @@ enum serial_register_types {
 #define SIO_STAT_RRDY 0x0010
 
 typedef struct _mn10300_serial {
-  unsigned16 status, control;
-  unsigned8  txb, rxb, intmode;
+  uint16_t status, control;
+  uint8_t  txb, rxb, intmode;
   struct hw_event *event;
 } mn10300_serial;
 
@@ -91,7 +91,7 @@ typedef struct _mn10300_serial {
 struct mn103ser {
   struct mn103ser_block block;
   mn10300_serial device[NR_SERIAL_DEVS];
-  unsigned8      serial2_timer_reg;
+  uint8_t      serial2_timer_reg;
   do_hw_poll_read_method *reader;
 };
 
@@ -294,7 +294,7 @@ read_control_reg (struct hw *me,
   /* really allow 1 byte read, too */
   if ( nr_bytes == 2 )
     {
-      *(unsigned16 *)dest = H2LE_2 (serial->device[serial_reg].control);
+      *(uint16_t *)dest = H2LE_2 (serial->device[serial_reg].control);
     }
   else
     {
@@ -313,7 +313,7 @@ read_intmode_reg (struct hw *me,
 {
   if ( nr_bytes == 1 )
     {
-      *(unsigned8 *)dest = serial->device[serial_reg].intmode;
+      *(uint8_t *)dest = serial->device[serial_reg].intmode;
     }
   else
     {
@@ -332,7 +332,7 @@ read_txb (struct hw *me,
 {
   if ( nr_bytes == 1 )
     {
-      *(unsigned8 *)dest = serial->device[serial_reg].txb;
+      *(uint8_t *)dest = serial->device[serial_reg].txb;
     }
   else
     {
@@ -351,7 +351,7 @@ read_rxb (struct hw *me,
 {
   if ( nr_bytes == 1 )
     {
-      *(unsigned8 *)dest = serial->device[serial_reg].rxb;
+      *(uint8_t *)dest = serial->device[serial_reg].rxb;
       /* Reception buffer is now empty. */
       serial->device[serial_reg].status &= ~SIO_STAT_RRDY;
     }
@@ -429,11 +429,11 @@ read_status_reg (struct hw *me,
 
   if ( nr_bytes == 1 )
     {
-      *(unsigned8 *)dest = (unsigned8)serial->device[serial_reg].status;
+      *(uint8_t *)dest = (uint8_t)serial->device[serial_reg].status;
     }
   else if ( nr_bytes == 2 && serial_reg != SC2STR )
     {
-      *(unsigned16 *)dest = H2LE_2 (serial->device[serial_reg].status);
+      *(uint16_t *)dest = H2LE_2 (serial->device[serial_reg].status);
     }
   else
     {
@@ -451,7 +451,7 @@ read_serial2_timer_reg (struct hw *me,
 {
   if ( nr_bytes == 1 )
     {
-      * (unsigned8 *) dest = (unsigned8) serial->serial2_timer_reg;
+      * (uint8_t *) dest = (uint8_t) serial->serial2_timer_reg;
     }
   else
     {
@@ -480,7 +480,7 @@ mn103ser_io_read_buffer (struct hw *me,
     case SC2CTR:
       read_control_reg(me, serial, serial_reg-SC0CTR, dest, nr_bytes);
       HW_TRACE ((me, "read - ctrl reg%d has 0x%x\n", serial_reg-SC0CTR,
-                *(unsigned8 *)dest));
+                *(uint8_t *)dest));
       break;
 
     /* interrupt mode registers */
@@ -489,7 +489,7 @@ mn103ser_io_read_buffer (struct hw *me,
     case SC2ICR:
       read_intmode_reg(me, serial, serial_reg-SC0ICR, dest, nr_bytes);
       HW_TRACE ((me, "read - intmode reg%d has 0x%x\n", serial_reg-SC0ICR,
-                *(unsigned8 *)dest));
+                *(uint8_t *)dest));
       break;
 
     /* transmission buffers */
@@ -516,12 +516,12 @@ mn103ser_io_read_buffer (struct hw *me,
     case SC2STR: 
       read_status_reg(me, serial, serial_reg-SC0STR, dest, nr_bytes);
       HW_TRACE ((me, "read - status reg%d has 0x%x\n", serial_reg-SC0STR,
-                *(unsigned8 *)dest));
+                *(uint8_t *)dest));
       break;
 
     case SC2TIM:
       read_serial2_timer_reg(me, serial, dest, nr_bytes);
-      HW_TRACE ((me, "read - serial2 timer reg %d\n", *(unsigned8 *)dest));
+      HW_TRACE ((me, "read - serial2 timer reg %d\n", *(uint8_t *)dest));
       break;
 
     default:
@@ -539,7 +539,7 @@ write_control_reg (struct hw *me,
                   const void *source,
                   unsigned  nr_bytes)
 {
-  unsigned16 val = LE2H_2 (*(unsigned16 *)source);
+  uint16_t val = LE2H_2 (*(uint16_t *)source);
 
   /* really allow 1 byte write, too */
   if ( nr_bytes == 2 )
@@ -568,7 +568,7 @@ write_intmode_reg (struct hw *me,
                   const void *source,
                   unsigned  nr_bytes)
 {
-unsigned8 val = *(unsigned8 *)source;
+uint8_t val = *(uint8_t *)source;
 
   if ( nr_bytes == 1 )
     {
@@ -604,7 +604,7 @@ write_txb (struct hw *me,
       SIM_DESC sd = hw_system (me);
       int status;
 
-      serial->device[serial_reg].txb = *(unsigned8 *)source;
+      serial->device[serial_reg].txb = *(uint8_t *)source;
 
       status = dv_sockser_status (sd);
       if (!(status & DV_SOCKSER_DISCONNECTED))
@@ -635,7 +635,7 @@ write_serial2_timer_reg (struct hw *me,
 {
   if ( nr_bytes == 1 )
     {
-      serial->serial2_timer_reg = *(unsigned8 *)source;
+      serial->serial2_timer_reg = *(uint8_t *)source;
     }
   else
     {
@@ -663,7 +663,7 @@ mn103ser_io_write_buffer (struct hw *me,
     case SC1CTR:
     case SC2CTR:
       HW_TRACE ((me, "write - ctrl reg%d has 0x%x, nrbytes=%d.\n",
-                serial_reg-SC0CTR, *(unsigned8 *)source, nr_bytes));
+                serial_reg-SC0CTR, *(uint8_t *)source, nr_bytes));
       write_control_reg(me, serial, serial_reg-SC0CTR, source, nr_bytes);
       break;
 
@@ -672,7 +672,7 @@ mn103ser_io_write_buffer (struct hw *me,
     case SC1ICR:
     case SC2ICR:
       HW_TRACE ((me, "write - intmode reg%d has 0x%x, nrbytes=%d.\n",
-                serial_reg-SC0ICR, *(unsigned8 *)source, nr_bytes));
+                serial_reg-SC0ICR, *(uint8_t *)source, nr_bytes));
       write_intmode_reg(me, serial, serial_reg-SC0ICR, source, nr_bytes);
       break;
 
@@ -701,7 +701,7 @@ mn103ser_io_write_buffer (struct hw *me,
 
     case SC2TIM:
       HW_TRACE ((me, "read - serial2 timer reg %d (nrbytes=%d)\n",
-                *(unsigned8 *)source, nr_bytes));
+                *(uint8_t *)source, nr_bytes));
       write_serial2_timer_reg(me, serial, source, nr_bytes);
       break;
 

diff --git a/sim/mn10300/dv-mn103tim.c b/sim/mn10300/dv-mn103tim.c
index 969133cd46ce779cc109649b0cd5b11cb0b9c4f4..bfda142fd6e8999410ae651fa2181f264bdc21bb 100644 (file)
--- a/sim/mn10300/dv-mn103tim.c
+++ b/sim/mn10300/dv-mn103tim.c
@@ -97,12 +97,12 @@ enum timer_register_types {
 #define NR_TIMERS 7
 
 typedef struct _mn10300_timer_regs {
-  unsigned32 base;
-  unsigned8  mode;
+  uint32_t base;
+  uint8_t  mode;
 } mn10300_timer_regs;
 
 typedef struct _mn10300_timer {
-  unsigned32 div_ratio, start;
+  uint32_t div_ratio, start;
   struct hw_event *event;
 } mn10300_timer;
 
@@ -113,8 +113,8 @@ struct mn103tim {
   mn10300_timer timer[NR_TIMERS];
 
   /* treat timer 6 registers specially. */
-  unsigned16   tm6md0, tm6md1, tm6bc, tm6ca, tm6cb; 
-  unsigned8  tm6mda, tm6mdb;  /* compare/capture mode regs for timer 6 */
+  uint16_t   tm6md0, tm6md1, tm6bc, tm6ca, tm6cb; 
+  uint8_t  tm6mda, tm6mdb;  /* compare/capture mode regs for timer 6 */
 };
 
 /* output port ID's */
@@ -287,8 +287,8 @@ read_mode_reg (struct hw *me,
               void *dest,
               unsigned nr_bytes)
 {
-  unsigned16 val16;
-  unsigned32 val32;
+  uint16_t val16;
+  uint32_t val32;
 
   switch ( nr_bytes )
     {
@@ -296,24 +296,24 @@ read_mode_reg (struct hw *me,
       /* Accessing 1 byte is ok for all mode registers. */
       if ( timer_nr == 6 )
        {
-         *(unsigned8*)dest = timers->tm6md0;
+         *(uint8_t*)dest = timers->tm6md0;
        }
       else
        {
-         *(unsigned8*)dest = timers->reg[timer_nr].mode;
+         *(uint8_t*)dest = timers->reg[timer_nr].mode;
        }
       break;
 
     case 2:
       if ( timer_nr == 6 )
        {
-         *(unsigned16 *)dest = (timers->tm6md0 << 8) | timers->tm6md1;
+         *(uint16_t *)dest = (timers->tm6md0 << 8) | timers->tm6md1;
        }
       else if ( timer_nr == 0 || timer_nr == 2 )
        {
          val16 = (timers->reg[timer_nr].mode << 8)
            | timers->reg[timer_nr+1].mode;
-         *(unsigned16*)dest = val16;
+         *(uint16_t*)dest = val16;
        }
       else
        {
@@ -328,7 +328,7 @@ read_mode_reg (struct hw *me,
            | (timers->reg[1].mode << 16)
            | (timers->reg[2].mode << 8)
            | timers->reg[3].mode;
-         *(unsigned32*)dest = val32;
+         *(uint32_t*)dest = val32;
        }
       else
        {
@@ -350,8 +350,8 @@ read_base_reg (struct hw *me,
               void *dest,
               unsigned  nr_bytes)
 {
-  unsigned16 val16;
-  unsigned32 val32;
+  uint16_t val16;
+  uint32_t val32;
 
   /* Check nr_bytes: accesses of 1, 2 and 4 bytes allowed depending on timer. */
   switch ( nr_bytes )
@@ -360,7 +360,7 @@ read_base_reg (struct hw *me,
       /* Reading 1 byte is ok for all registers. */
       if ( timer_nr < NR_8BIT_TIMERS )
        {
-         *(unsigned8*)dest = timers->reg[timer_nr].base;
+         *(uint8_t*)dest = timers->reg[timer_nr].base;
        }
       break;
 
@@ -380,7 +380,7 @@ read_base_reg (struct hw *me,
            {
              val16 = timers->reg[timer_nr].base;
            }
-         *(unsigned16*)dest = val16;
+         *(uint16_t*)dest = val16;
        }
       break;
 
@@ -389,12 +389,12 @@ read_base_reg (struct hw *me,
        {
          val32 = (timers->reg[0].base << 24) | (timers->reg[1].base << 16)
            | (timers->reg[2].base << 8) | timers->reg[3].base;
-         *(unsigned32*)dest = val32;
+         *(uint32_t*)dest = val32;
        }
       else if ( timer_nr == 4 ) 
        {
          val32 = (timers->reg[4].base << 16) | timers->reg[5].base;
-         *(unsigned32*)dest = val32;
+         *(uint32_t*)dest = val32;
        }
       else
        {
@@ -416,7 +416,7 @@ read_counter (struct hw *me,
              void *dest,
              unsigned  nr_bytes)
 {
-  unsigned32 val;
+  uint32_t val;
 
   if ( NULL == timers->timer[timer_nr].event )
     {
@@ -449,15 +449,15 @@ read_counter (struct hw *me,
 
   switch (nr_bytes) {
   case 1:
-    *(unsigned8 *)dest = val;
+    *(uint8_t *)dest = val;
     break;
     
   case 2:
-    *(unsigned16 *)dest = val;
+    *(uint16_t *)dest = val;
     break;
 
   case 4:
-    *(unsigned32 *)dest = val;
+    *(uint32_t *)dest = val;
     break;
 
   default:
@@ -474,26 +474,26 @@ read_special_timer6_reg (struct hw *me,
                         void *dest,
                         unsigned  nr_bytes)
 {
-  unsigned32 val;
+  uint32_t val;
 
   switch (nr_bytes) {
   case 1:
     {
       switch ( timer_nr ) {
       case TM6MDA:
-       *(unsigned8 *)dest = timers->tm6mda;
+       *(uint8_t *)dest = timers->tm6mda;
        break;
     
       case TM6MDB:
-       *(unsigned8 *)dest = timers->tm6mdb;
+       *(uint8_t *)dest = timers->tm6mdb;
        break;
     
       case TM6CA:
-       *(unsigned8 *)dest = timers->tm6ca;
+       *(uint8_t *)dest = timers->tm6ca;
        break;
     
       case TM6CB:
-       *(unsigned8 *)dest = timers->tm6cb;
+       *(uint8_t *)dest = timers->tm6cb;
        break;
       
       default:
@@ -505,11 +505,11 @@ read_special_timer6_reg (struct hw *me,
   case 2:
     if ( timer_nr == TM6CA )
       {
-       *(unsigned16 *)dest = timers->tm6ca;
+       *(uint16_t *)dest = timers->tm6ca;
       }
     else if ( timer_nr == TM6CB )
       {
-       *(unsigned16 *)dest = timers->tm6cb;
+       *(uint16_t *)dest = timers->tm6cb;
       }
     else
       {
@@ -642,8 +642,8 @@ write_base_reg (struct hw *me,
                unsigned  nr_bytes)
 {
   unsigned i;
-  const unsigned8 *buf8 = source;
-  const unsigned16 *buf16 = source;
+  const uint8_t *buf8 = source;
+  const uint16_t *buf16 = source;
 
   /* If TMnCNE == 0 (counting is off),  writing to the base register
      (TMnBR) causes a simultaneous write to the counter reg (TMnBC).
@@ -713,8 +713,8 @@ write_mode_reg (struct hw *me,
      /* for timers 0 to 5 */
 {
   unsigned i;
-  unsigned8 mode_val, next_mode_val;
-  unsigned32 div_ratio;
+  uint8_t mode_val, next_mode_val;
+  uint32_t div_ratio;
 
   if ( nr_bytes != 1 )
     {
@@ -722,7 +722,7 @@ write_mode_reg (struct hw *me,
                timer_nr);
     }
 
-  mode_val = *(unsigned8 *)source;
+  mode_val = *(uint8_t *)source;
   timers->reg[timer_nr].mode = mode_val;
       
   if ( ( mode_val & count_and_load_mask ) == count_and_load_mask )
@@ -840,8 +840,8 @@ write_tm6md (struct hw *me,
             const void *source,
             unsigned nr_bytes)
 {
-  unsigned8 mode_val0 = 0x00, mode_val1 = 0x00;
-  unsigned32 div_ratio;
+  uint8_t mode_val0 = 0x00, mode_val1 = 0x00;
+  uint32_t div_ratio;
   long timer_nr = 6;
 
   unsigned_word offset = address - timers->block[0].base;
@@ -854,7 +854,7 @@ write_tm6md (struct hw *me,
   if ( offset == 0x84 )  /* address of TM6MD */
     {
       /*  Fill in first byte of mode */
-      mode_val0 = *(unsigned8 *)source;
+      mode_val0 = *(uint8_t *)source;
       timers->tm6md0 = mode_val0;
     
       if ( ( mode_val0 & 0x26 ) != 0 )
@@ -868,11 +868,11 @@ write_tm6md (struct hw *me,
       /*  Fill in second byte of mode */
       if ( nr_bytes == 2 )
        {
-         mode_val1 = *(unsigned8 *)source+1;
+         mode_val1 = *(uint8_t *)source+1;
        }
       else
        {
-         mode_val1 = *(unsigned8 *)source;
+         mode_val1 = *(uint8_t *)source;
        }
 
       timers->tm6md1 = mode_val1;
@@ -931,26 +931,26 @@ write_special_timer6_reg (struct hw *me,
                          const void *source,
                          unsigned  nr_bytes)
 {
-  unsigned32 val;
+  uint32_t val;
 
   switch (nr_bytes) {
   case 1:
     {
       switch ( timer_nr ) {
       case TM6MDA:
-       timers->tm6mda = *(unsigned8 *)source;
+       timers->tm6mda = *(uint8_t *)source;
        break;
     
       case TM6MDB:
-       timers->tm6mdb = *(unsigned8 *)source;
+       timers->tm6mdb = *(uint8_t *)source;
        break;
     
       case TM6CA:
-       timers->tm6ca = *(unsigned8 *)source;
+       timers->tm6ca = *(uint8_t *)source;
        break;
     
       case TM6CB:
-       timers->tm6cb = *(unsigned8 *)source;
+       timers->tm6cb = *(uint8_t *)source;
        break;
       
       default:
@@ -962,11 +962,11 @@ write_special_timer6_reg (struct hw *me,
   case 2:
     if ( timer_nr == TM6CA )
       {
-       timers->tm6ca = *(unsigned16 *)source;
+       timers->tm6ca = *(uint16_t *)source;
       }
     else if ( timer_nr == TM6CB )
       {
-       timers->tm6cb = *(unsigned16 *)source;
+       timers->tm6cb = *(uint16_t *)source;
       }
     else
       {
@@ -992,7 +992,7 @@ mn103tim_io_write_buffer (struct hw *me,
   enum timer_register_types timer_reg;
 
   HW_TRACE ((me, "write to 0x%08lx length %d with 0x%x", (long) base,
-            (int) nr_bytes, *(unsigned32 *)source));
+            (int) nr_bytes, *(uint32_t *)source));
 
   timer_reg = decode_addr (me, timers, base);
 

diff --git a/sim/mn10300/interp.c b/sim/mn10300/interp.c
index 551d17630082f5c1754191cb40c1ba0229c2829c..2e7fd1630479802d03e3d3c42e1623cbf34f619f 100644 (file)
--- a/sim/mn10300/interp.c
+++ b/sim/mn10300/interp.c
@@ -320,7 +320,7 @@ sim_create_inferior (SIM_DESC sd,
   } else {
     PC = 0;
   }
-  CPU_PC_SET (STATE_CPU (sd, 0), (unsigned64) PC);
+  CPU_PC_SET (STATE_CPU (sd, 0), (uint64_t) PC);
 
   if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33_2)
     PSW |= PSW_FE;
@@ -335,7 +335,7 @@ static int
 mn10300_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
 {
   reg_t reg = State.regs[rn];
-  uint8 *a = memory;
+  uint8_t *a = memory;
   a[0] = reg;
   a[1] = reg >> 8;
   a[2] = reg >> 16;
@@ -346,7 +346,7 @@ mn10300_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
 static int
 mn10300_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
 {
-  uint8 *a = memory;
+  uint8_t *a = memory;
   State.regs[rn] = (a[3] << 24) + (a[2] << 16) + (a[1] << 8) + a[0];
   return length;
 }

diff --git a/sim/mn10300/mn10300.igen b/sim/mn10300/mn10300.igen
index 9431c0b5179094692a9863a7c6dc0a1e402cdd49..6330d6f0090a873c14c33de502e3df75d4caed07 100644 (file)
--- a/sim/mn10300/mn10300.igen
+++ b/sim/mn10300/mn10300.igen
@@ -21,7 +21,7 @@
 *am33_2
 {
   /*  OP_8000 (); */
-  signed32 immed = EXTEND8 (IMM8);
+  int32_t immed = EXTEND8 (IMM8);
   State.regs[REG_D0+DN0] = immed;
   PC = cia;
 }
@@ -776,7 +776,7 @@
 
 {
   /* OP_2C0000 (); */
-  unsigned32 value;
+  uint32_t value;
 
   PC = cia;
   value = EXTEND16 (FETCH16(IMM16A, IMM16B));
@@ -794,7 +794,7 @@
 
 {
   /* OP_FCCC0000 (); */
-  unsigned32 value;
+  uint32_t value;
 
   PC = cia;
   value = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
@@ -812,7 +812,7 @@
 
 {
   /* OP_240000 (); */
-  unsigned32 value;
+  uint32_t value;
 
   PC = cia;
   value = FETCH16(IMM16A, IMM16B);
@@ -1734,7 +1734,7 @@
 
 {
   /* OP_F8FE00 (); */
-  unsigned32 imm;
+  uint32_t imm;
 
   /* Note: no PSW changes. */
   PC = cia;
@@ -1753,7 +1753,7 @@
 
 {
   /* OP_FAFE0000 (); */
-  unsigned32 imm;
+  uint32_t imm;
 
   /* Note: no PSW changes. */
   PC = cia;
@@ -1772,7 +1772,7 @@
 
 {
   /* OP_FCFE0000 (); */
-  unsigned32 imm;
+  uint32_t imm;
 
   /* Note: no PSW changes. */
   PC = cia;
@@ -1792,7 +1792,7 @@
 {
   /* OP_F140 (); */
   int z, c, n, v;
-  unsigned32 reg1, reg2, sum;
+  uint32_t reg1, reg2, sum;
 
   PC = cia;
   reg1 = State.regs[REG_D0 + DM1];
@@ -1912,7 +1912,7 @@
 {
   /* OP_F180 (); */
   int z, c, n, v;
-  unsigned32 reg1, reg2, difference;
+  uint32_t reg1, reg2, difference;
 
   PC = cia;
   reg1 = State.regs[REG_D0 + DM1];
@@ -1942,12 +1942,12 @@
 
 {
   /* OP_F240 (); */
-  unsigned64 temp;
+  uint64_t temp;
   int n, z;
 
   PC = cia;
-  temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
-          *  (signed64)(signed32)State.regs[REG_D0 + DM1]);
+  temp = ((int64_t)(int32_t)State.regs[REG_D0 + DN0]
+          *  (int64_t)(int32_t)State.regs[REG_D0 + DM1]);
   State.regs[REG_D0 + DN0] = temp & 0xffffffff;
   State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
   z = (State.regs[REG_D0 + DN0] == 0);
@@ -1967,12 +1967,12 @@
 
 {
   /* OP_F250 (); */
-  unsigned64 temp;
+  uint64_t temp;
   int n, z;
 
   PC = cia;
-  temp = ((unsigned64)State.regs[REG_D0 + DN0]
-          * (unsigned64)State.regs[REG_D0 + DM1]);
+  temp = ((uint64_t)State.regs[REG_D0 + DN0]
+          * (uint64_t)State.regs[REG_D0 + DM1]);
   State.regs[REG_D0 + DN0] = temp & 0xffffffff;
   State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
   z = (State.regs[REG_D0 + DN0] == 0);
@@ -1992,20 +1992,20 @@
 
 {
   /* OP_F260 (); */
-  signed64 temp;
-  signed32 denom;
+  int64_t temp;
+  int32_t denom;
   int n, z, v;
 
   PC = cia;
-  denom = (signed32)State.regs[REG_D0 + DM1];
+  denom = (int32_t)State.regs[REG_D0 + DM1];
 
   temp = State.regs[REG_MDR];
   temp <<= 32;
   temp |= State.regs[REG_D0 + DN0];
   if ( !(v = (0 == denom)) )
     {
-      State.regs[REG_MDR] = temp % (signed32)State.regs[REG_D0 + DM1];
-      temp /= (signed32)State.regs[REG_D0 + DM1];
+      State.regs[REG_MDR] = temp % (int32_t)State.regs[REG_D0 + DM1];
+      temp /= (int32_t)State.regs[REG_D0 + DM1];
       State.regs[REG_D0 + DN0] = temp & 0xffffffff;
     }
   else
@@ -2030,12 +2030,12 @@
 
 {
   /* OP_F270 (); */
-  unsigned64 temp;
-  unsigned32 denom;
+  uint64_t temp;
+  uint32_t denom;
   int n, z, v;
 
   PC = cia;
-  denom = (unsigned32)State.regs[REG_D0 + DM1];
+  denom = (uint32_t)State.regs[REG_D0 + DM1];
   temp = State.regs[REG_MDR];
   temp <<= 32;
   temp |= State.regs[REG_D0 + DN0];
@@ -2067,7 +2067,7 @@
 
 {
   /* OP_40 (); */
-  unsigned32 imm;
+  uint32_t imm;
 
   PC = cia;
   imm = 1;
@@ -2591,7 +2591,7 @@
 
 {
   /* OP_F080 (); */
-  unsigned32 temp;
+  uint32_t temp;
   int z;
 
   PC = cia;
@@ -2615,7 +2615,7 @@
 
 {
   /* OP_FE000000 (); */
-  unsigned32 temp;
+  uint32_t temp;
   int z;
 
   PC = cia;
@@ -2639,7 +2639,7 @@
 
 {
   /* OP_FAF00000 (); */
-  unsigned32 temp;
+  uint32_t temp;
   int z;
 
   PC = cia;
@@ -2662,7 +2662,7 @@
 
 {
   /* OP_F090 (); */
-  unsigned32 temp;
+  uint32_t temp;
   int z;
 
   PC = cia;
@@ -2686,7 +2686,7 @@
 
 {
   /* OP_FE010000 (); */
-  unsigned32 temp;
+  uint32_t temp;
   int z;
 
   PC = cia;
@@ -2710,7 +2710,7 @@
 
 {
   /* OP_FAF40000 (); */
-  unsigned32 temp;
+  uint32_t temp;
   int z;
 
   PC = cia;
@@ -2733,7 +2733,7 @@
 
 {
   /* OP_F2B0 (); */
-  signed32 temp;
+  int32_t temp;
   int z, n, c;
 
   PC = cia;
@@ -2758,7 +2758,7 @@
 
 {
   /* OP_F8C800 (); */
-  signed32 temp;
+  int32_t temp;
   int z, n, c;
 
   PC = cia;
@@ -2892,7 +2892,7 @@
 
 {
   /* OP_F284 (); */
-  unsigned32 value;
+  uint32_t value;
   int c,n,z;
 
   PC = cia;
@@ -2919,7 +2919,7 @@
 
 {
   /* OP_F280 (); */
-  unsigned32 value;
+  uint32_t value;
   int c,n,z;
 
   PC = cia;
@@ -3499,7 +3499,7 @@
 
 {
   /* OP_F0F0 (); */
-  unsigned32 next_pc, sp;
+  uint32_t next_pc, sp;
 
   PC = cia;
   sp = State.regs[REG_SP];
@@ -3521,7 +3521,7 @@
 
 {
   /* OP_FAFF0000 (); */
-  unsigned32 next_pc, sp;
+  uint32_t next_pc, sp;
 
   PC = cia;
   sp = State.regs[REG_SP];
@@ -3543,7 +3543,7 @@
 
 {
   /* OP_FCFF0000 (); */
-  unsigned32 next_pc, sp;
+  uint32_t next_pc, sp;
 
   PC = cia;
   sp = State.regs[REG_SP];
@@ -3565,7 +3565,7 @@
 
 {
   /* OP_F0FC (); */
-  unsigned32 sp;
+  uint32_t sp;
 
   sp = State.regs[REG_SP];
   State.regs[REG_PC] = load_word(sp);
@@ -3583,7 +3583,7 @@
 
 {
   /* OP_F0FD (); */
-  unsigned32 sp;
+  uint32_t sp;
 
   sp = State.regs[REG_SP];
   PSW = load_half(sp);
@@ -3603,7 +3603,7 @@
 
 {
   /* OP_F0FE (); */
-  unsigned32 sp, next_pc;
+  uint32_t sp, next_pc;
 
   PC = cia;
   sp = State.regs[REG_SP];
@@ -3685,12 +3685,12 @@
 
 {
   /* OP_F600 (); */
-  unsigned64 temp;
+  uint64_t temp;
   int n, z;
 
   PC = cia;
-  temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
-          *  (signed64)(signed32)State.regs[REG_D0 + DM1]);
+  temp = ((int64_t)(int32_t)State.regs[REG_D0 + DN0]
+          *  (int64_t)(int32_t)State.regs[REG_D0 + DM1]);
   State.regs[REG_D0 + DN0] = temp & 0xffffffff;
   State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
   z = (State.regs[REG_D0 + DN0] == 0);
@@ -3710,12 +3710,12 @@
 
 {
   /* OP_F90000 (); */
-  unsigned64 temp;
+  uint64_t temp;
   int n, z;
 
   PC = cia;
-  temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
-          * (signed64)(signed32)EXTEND8 (IMM8));
+  temp = ((int64_t)(int32_t)State.regs[REG_D0 + DN0]
+          * (int64_t)(int32_t)EXTEND8 (IMM8));
   State.regs[REG_D0 + DN0] = temp & 0xffffffff;
   State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
   z = (State.regs[REG_D0 + DN0] == 0);
@@ -3735,12 +3735,12 @@
 
 {
   /* OP_FB000000 (); */
-  unsigned64 temp;
+  uint64_t temp;
   int n, z;
 
   PC = cia;
-  temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
-          * (signed64)(signed32)EXTEND16 (FETCH16(IMM16A, IMM16B)));
+  temp = ((int64_t)(int32_t)State.regs[REG_D0 + DN0]
+          * (int64_t)(int32_t)EXTEND16 (FETCH16(IMM16A, IMM16B)));
   State.regs[REG_D0 + DN0] = temp & 0xffffffff;
   State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
   z = (State.regs[REG_D0 + DN0] == 0);
@@ -3760,12 +3760,12 @@
 
 {
   /* OP_FD000000 (); */
-  unsigned64 temp;
+  uint64_t temp;
   int n, z;
 
   PC = cia;
-  temp = ((signed64)(signed32)State.regs[REG_D0 + DN0]
-          * (signed64)(signed32)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
+  temp = ((int64_t)(int32_t)State.regs[REG_D0 + DN0]
+          * (int64_t)(int32_t)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
   State.regs[REG_D0 + DN0] = temp & 0xffffffff;
   State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
   z = (State.regs[REG_D0 + DN0] == 0);
@@ -3785,12 +3785,12 @@
 
 {
   /* OP_F610 (); */
-  unsigned64 temp;
+  uint64_t temp;
   int n, z;
 
   PC = cia;
-  temp = ((unsigned64) State.regs[REG_D0 + DN0]
-         * (unsigned64) State.regs[REG_D0 + DM1]);
+  temp = ((uint64_t) State.regs[REG_D0 + DN0]
+         * (uint64_t) State.regs[REG_D0 + DM1]);
   State.regs[REG_D0 + DN0] = temp & 0xffffffff;
   State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
   z = (State.regs[REG_D0 + DN0] == 0);
@@ -3810,12 +3810,12 @@
 
 {
   /* OP_F91400 (); */
-  unsigned64 temp;
+  uint64_t temp;
   int n, z;
 
   PC = cia;
-  temp = ((unsigned64)State.regs[REG_D0 + DN0]
-         * (unsigned64)EXTEND8 (IMM8));
+  temp = ((uint64_t)State.regs[REG_D0 + DN0]
+         * (uint64_t)EXTEND8 (IMM8));
   State.regs[REG_D0 + DN0] = temp & 0xffffffff;
   State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
   z = (State.regs[REG_D0 + DN0] == 0);
@@ -3835,12 +3835,12 @@
 
 {
   /* OP_FB140000 (); */
-  unsigned64 temp;
+  uint64_t temp;
   int n, z;
 
   PC = cia;
-  temp = ((unsigned64)State.regs[REG_D0 + DN0]
-         * (unsigned64) EXTEND16 (FETCH16(IMM16A, IMM16B)));
+  temp = ((uint64_t)State.regs[REG_D0 + DN0]
+         * (uint64_t) EXTEND16 (FETCH16(IMM16A, IMM16B)));
   State.regs[REG_D0 + DN0] = temp & 0xffffffff;
   State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
   z = (State.regs[REG_D0 + DN0] == 0);
@@ -3860,12 +3860,12 @@
 
 {
   /* OP_FD140000 (); */
-  unsigned64 temp;
+  uint64_t temp;
   int n, z;
 
   PC = cia;
-  temp = ((unsigned64)State.regs[REG_D0 + DN0]
-          * (unsigned64)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
+  temp = ((uint64_t)State.regs[REG_D0 + DN0]
+          * (uint64_t)(FETCH32(IMM32A, IMM32B, IMM32C, IMM32D)));
   State.regs[REG_D0 + DN0] = temp & 0xffffffff;
   State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
   z = (State.regs[REG_D0 + DN0] == 0);
@@ -3975,8 +3975,8 @@
 
 {
   /* OP_CE00 (); */
-  unsigned32 sp = State.regs[REG_SP];
-  unsigned32 mask;
+  uint32_t sp = State.regs[REG_SP];
+  uint32_t mask;
 
   PC = cia;
   mask = REGS;
@@ -4074,8 +4074,8 @@
 
 {
   /* OP_CF00 (); */
-  unsigned32 sp = State.regs[REG_SP];
-  unsigned32 mask;
+  uint32_t sp = State.regs[REG_SP];
+  uint32_t mask;
 
   PC = cia;
   mask = REGS;
@@ -4173,8 +4173,8 @@
 
 {
   /* OP_CD000000 (); */
-  unsigned32 next_pc, sp;
-  unsigned32 mask;
+  uint32_t next_pc, sp;
+  uint32_t mask;
 
   PC = cia;
   sp = State.regs[REG_SP];
@@ -4282,8 +4282,8 @@
 
 {
   /* OP_DD000000 (); */
-  unsigned32 next_pc, sp;
-  unsigned32 mask;
+  uint32_t next_pc, sp;
+  uint32_t mask;
 
   PC = cia;
   sp = State.regs[REG_SP];
@@ -4391,8 +4391,8 @@
 
 {
   /* OP_DF0000 (); */
-  unsigned32 sp, offset;
-  unsigned32 mask;
+  uint32_t sp, offset;
+  uint32_t mask;
 
   PC = cia;
   State.regs[REG_SP] += IMM8;
@@ -4496,8 +4496,8 @@
 
 {
   /* OP_DE0000 (); */
-  unsigned32 sp, offset;
-  unsigned32 mask;
+  uint32_t sp, offset;
+  uint32_t mask;
 
   PC = cia;
   State.regs[REG_SP] += IMM8;

diff --git a/sim/mn10300/mn10300_sim.h b/sim/mn10300/mn10300_sim.h
index 82306e667d2f1db02dad88bbc634f010a3062321..f1ab23ffe4fb2c7c4f55c7b06542fa6e0ecd599a 100644 (file)
--- a/sim/mn10300/mn10300_sim.h
+++ b/sim/mn10300/mn10300_sim.h
@@ -11,18 +11,11 @@
 
 extern SIM_DESC simulator;
 
-typedef unsigned8 uint8;
-typedef signed8 int8;
-typedef unsigned16 uint16;
-typedef signed16 int16;
-typedef unsigned32 uint32;
-typedef signed32 int32;
-
 typedef struct
 {
-  uint32 low, high;
+  uint32_t low, high;
 } dword;
-typedef uint32 reg_t;
+typedef uint32_t reg_t;
 
 struct simops 
 {
@@ -160,12 +153,12 @@ u642dw (sim_core_read_unaligned_8 (STATE_CPU (simulator, 0), \
                                   PC, read_map, (ADDR)))
 
 static INLINE2 dword
-u642dw (unsigned64 dw)
+u642dw (uint64_t dw)
 {
   dword r;
 
-  r.low = (unsigned32)dw;
-  r.high = (unsigned32)(dw >> 32);
+  r.low = (uint32_t)dw;
+  r.high = (uint32_t)(dw >> 32);
   return r;
 }
 
@@ -186,20 +179,20 @@ sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
 sim_core_write_unaligned_8 (STATE_CPU (simulator, 0), \
                            PC, write_map, (ADDR), dw2u64 (DATA))
 
-static INLINE2 unsigned64
+static INLINE2 uint64_t
 dw2u64 (dword data)
 {
-  return data.low | (((unsigned64)data.high) << 32);
+  return data.low | (((uint64_t)data.high) << 32);
 }
 
 /* Function declarations.  */
 
-INLINE_SIM_MAIN (void) genericAdd (unsigned32 source, unsigned32 destReg);
-INLINE_SIM_MAIN (void) genericSub (unsigned32 source, unsigned32 destReg);
-INLINE_SIM_MAIN (void) genericCmp (unsigned32 leftOpnd, unsigned32 rightOpnd);
-INLINE_SIM_MAIN (void) genericOr (unsigned32 source, unsigned32 destReg);
-INLINE_SIM_MAIN (void) genericXor (unsigned32 source, unsigned32 destReg);
-INLINE_SIM_MAIN (void) genericBtst (unsigned32 leftOpnd, unsigned32 rightOpnd);
+INLINE_SIM_MAIN (void) genericAdd (uint32_t source, uint32_t destReg);
+INLINE_SIM_MAIN (void) genericSub (uint32_t source, uint32_t destReg);
+INLINE_SIM_MAIN (void) genericCmp (uint32_t leftOpnd, uint32_t rightOpnd);
+INLINE_SIM_MAIN (void) genericOr (uint32_t source, uint32_t destReg);
+INLINE_SIM_MAIN (void) genericXor (uint32_t source, uint32_t destReg);
+INLINE_SIM_MAIN (void) genericBtst (uint32_t leftOpnd, uint32_t rightOpnd);
 INLINE_SIM_MAIN (void) do_syscall (SIM_DESC sd);
 void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig);
 

diff --git a/sim/mn10300/op_utils.c b/sim/mn10300/op_utils.c
index eb4439f5f09ce48345d8a4a042ad3b5b6a2f1d19..2fccf2da207fd58ec6af70ac15ac17665501a404 100644 (file)
--- a/sim/mn10300/op_utils.c
+++ b/sim/mn10300/op_utils.c
@@ -25,10 +25,10 @@
 
 
 INLINE_SIM_MAIN (void)
-genericAdd(unsigned32 source, unsigned32 destReg)
+genericAdd(uint32_t source, uint32_t destReg)
 {
   int z, c, n, v;
-  unsigned32 dest, sum;
+  uint32_t dest, sum;
 
   dest = State.regs[destReg];
   sum = source + dest;
@@ -49,10 +49,10 @@ genericAdd(unsigned32 source, unsigned32 destReg)
 
 
 INLINE_SIM_MAIN (void)
-genericSub(unsigned32 source, unsigned32 destReg)
+genericSub(uint32_t source, uint32_t destReg)
 {
   int z, c, n, v;
-  unsigned32 dest, difference;
+  uint32_t dest, difference;
 
   dest = State.regs[destReg];
   difference = dest - source;
@@ -70,10 +70,10 @@ genericSub(unsigned32 source, unsigned32 destReg)
 }
 
 INLINE_SIM_MAIN (void)
-genericCmp(unsigned32 leftOpnd, unsigned32 rightOpnd)
+genericCmp(uint32_t leftOpnd, uint32_t rightOpnd)
 {
   int z, c, n, v;
-  unsigned32 value;
+  uint32_t value;
 
   value = rightOpnd - leftOpnd;
 
@@ -90,7 +90,7 @@ genericCmp(unsigned32 leftOpnd, unsigned32 rightOpnd)
 
 
 INLINE_SIM_MAIN (void)
-genericOr(unsigned32 source, unsigned32 destReg)
+genericOr(uint32_t source, uint32_t destReg)
 {
   int n, z;
 
@@ -103,7 +103,7 @@ genericOr(unsigned32 source, unsigned32 destReg)
 
 
 INLINE_SIM_MAIN (void)
-genericXor(unsigned32 source, unsigned32 destReg)
+genericXor(uint32_t source, uint32_t destReg)
 {
   int n, z;
 
@@ -116,9 +116,9 @@ genericXor(unsigned32 source, unsigned32 destReg)
 
 
 INLINE_SIM_MAIN (void)
-genericBtst(unsigned32 leftOpnd, unsigned32 rightOpnd)
+genericBtst(uint32_t leftOpnd, uint32_t rightOpnd)
 {
-  unsigned32 temp;
+  uint32_t temp;
   int z, n;
 
   temp = rightOpnd;