fhdl.ir: don't crash propagataing ports in empty fragments.

diff --git a/nmigen/fhdl/ir.py b/nmigen/fhdl/ir.py
index 0945fcb5b4d85af3ba2dcb6b4af3ed526d663d3a..4676c48259dbb833190fc8c6e7eeb068765c4761 100644 (file)
--- a/nmigen/fhdl/ir.py
+++ b/nmigen/fhdl/ir.py
@@ -131,8 +131,8 @@ class Fragment:
     def _propagate_ports(self, ports):
         # Collect all signals we're driving (on LHS of statements), and signals we're using
         # (on RHS of statements, or in clock domains).
-        self_driven = union(s._lhs_signals() for s in self.statements)
-        self_used   = union(s._rhs_signals() for s in self.statements)
+        self_driven = union(s._lhs_signals() for s in self.statements) or ValueSet()
+        self_used   = union(s._rhs_signals() for s in self.statements) or ValueSet()
         for domain, _ in self.iter_sync():
             cd = self.domains[domain]
             self_used.add(cd.clk)

diff --git a/nmigen/test/test_fhdl_ir.py b/nmigen/test/test_fhdl_ir.py
index 86cd55ad38b221b88f83f73f81aed3a76334a7bc..2bf592bf25b577180fa63bb75dd79f7bf73f40a1 100644 (file)
--- a/nmigen/test/test_fhdl_ir.py
+++ b/nmigen/test/test_fhdl_ir.py
@@ -13,6 +13,14 @@ class FragmentPortsTestCase(FHDLTestCase):
         self.c2 = Signal()
         self.c3 = Signal()
 
+    def test_empty(self):
+        f = Fragment()
+
+        ins, outs = f._propagate_ports(ports=())
+        self.assertEqual(ins, ValueSet())
+        self.assertEqual(outs, ValueSet())
+        self.assertEqual(f.ports, ValueSet())
+
     def test_self_contained(self):
         f = Fragment()
         f.add_statements(