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diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index ecce194eeda43e9097801dd6daa532257c6fcbb4..60e865b96b123e2666961f98d9c02ffee725cc0b 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -305,4 +305,13 @@ Remarkably, very little: the devil is in the details though.
 It is only when looking slightly deeper into the Power ISA that
 certain things turn out to be missing, and this is down in part to IBM's
 primary focus on the 750 Packed SIMD opcodes at the expense of the 250 or
-so Scalar ones. 
+so Scalar ones.  Examples include that transfer operations between the
+Integer and Floating-point Scalar register files were dropped approximately
+a decade ago after the Packed SIMD variants were considered to be
+duplicates.  With it being completely inappropriate to attempt to Vectorise
+a Packed SIMD ISA designed 20 years ago with no Predication of any kind,
+the Scalar ISA, a much better all-round candidate for Vectorisation is
+left anaemic.  Fortunately, with the ISA Working Group being willing
+to consider RFCs (Requests For Change) these omissions have the potential
+to be corrected.
+