radv: tune primitive binning for small chips

Based on PAL and RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4144>

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index da83aa562bb600bfb5cfd94ac847c1acf063182a..7f32e135c63cea7091d17b7dcef40c972691c14b 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3477,8 +3477,13 @@ radv_get_binning_settings(const struct radv_physical_device *pdev)
 {
        struct radv_binning_settings settings;
        if (pdev->rad_info.has_dedicated_vram) {
-               settings.context_states_per_bin = 1;
-               settings.persistent_states_per_bin = 1;
+               if (pdev->rad_info.num_render_backends > 4) {
+                       settings.context_states_per_bin = 1;
+                       settings.persistent_states_per_bin = 1;
+               } else {
+                       settings.context_states_per_bin = 3;
+                       settings.persistent_states_per_bin = 8;
+               }
                settings.fpovs_per_batch = 63;
        } else {
                /* The context states are affected by the scissor bug. */