Add testcase for signal used as part input part output

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 6bdd3bc3206aa8eb6cad50a2cdcaed1eb42a9650..8314af211dc7b64607287a625fe309b38a74eaa1 100644 (file)
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -289,3 +289,8 @@ module abc9_test033(input clk, d, output reg q1, q2);
 always @(posedge clk) q1 <= d;
 always @(posedge clk) q2 <= q1;
 endmodule
+
+module abc9_test034(input clk, d, output reg [1:0] q);
+always @(posedge clk) q[0] <= d;
+always @(negedge clk) q[1] <= q[0];
+endmodule