Add support for DREG

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index d8213e02ff111682ee88cf0e413598addea9ce7c..547073aa6029b833ac25d4e7d14e8b0a29b33408 100644 (file)
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -38,6 +38,8 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
        log("ffAmux:     %s\n", log_id(st.ffAmux, "--"));
        log("ffB:        %s\n", log_id(st.ffB, "--"));
        log("ffBmux:     %s\n", log_id(st.ffBmux, "--"));
+       log("ffD:        %s\n", log_id(st.ffD, "--"));
+       log("ffDmux:     %s\n", log_id(st.ffDmux, "--"));
        log("dsp:        %s\n", log_id(st.dsp, "--"));
        log("ffM:        %s\n", log_id(st.ffM, "--"));
        log("ffMmux:     %s\n", log_id(st.ffMmux, "--"));
@@ -141,6 +143,17 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
 
                        cell->setParam("\\BREG", 1);
                }
+               if (st.ffD) {
+                       if (st.ffDmux) {
+                               SigSpec S = st.ffDmux->getPort("\\S");
+                               cell->setPort("\\CED", st.ffBenpol ? S : pm.module->Not(NEW_ID, S));
+                       }
+                       else
+                               cell->setPort("\\CED", State::S1);
+                       cell->setPort("\\D", st.sigD);
+
+                       cell->setParam("\\DREG", 1);
+               }
                if (st.ffM) {
                        if (st.ffMmux) {
                                SigSpec S = st.ffMmux->getPort("\\S");

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 7d943b16f67bd447d746b1e6bc69a5f709e75bf1..6cc42e2e1b8d42a7a5257b4ea583ca4b2953f823 100644 (file)
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -1,9 +1,9 @@
 pattern xilinx_dsp
 
 state <SigBit> clock
-state <SigSpec> sigA sigffAmuxY sigB sigffBmuxY sigC sigD sigM sigP
+state <SigSpec> sigA sigffAmuxY sigB sigffBmuxY sigC sigD sigffDmuxY sigM sigP
 state <IdString> postAddAB postAddMuxAB
-state <bool> ffAenpol ffADenpol ffBenpol ffMenpol ffPenpol
+state <bool> ffAenpol ffADenpol ffBenpol ffDenpol ffMenpol ffPenpol
 state <int> ffPoffset
 
 match dsp
@@ -236,6 +236,61 @@ match ffBmux
        optional
 endmatch
 
+match ffD
+       if param(dsp, \DREG).as_int() == 0
+       select ffD->type.in($dff)
+       // DSP48E1 does not support clock inversion
+       select param(ffD, \CLK_POLARITY).as_bool()
+       filter GetSize(port(ffD, \Q)) >= GetSize(sigD)
+       slice offset GetSize(port(ffD, \Q))
+       filter offset+GetSize(sigD) <= GetSize(port(ffD, \Q))
+       filter port(ffD, \Q).extract(offset, GetSize(sigD)) == sigD
+       optional
+endmatch
+
+code sigD sigffDmuxY clock
+       if (ffD) {
+               for (auto b : port(ffD, \Q))
+                       if (b.wire->get_bool_attribute(\keep))
+                               reject;
+
+               SigBit c = port(ffD, \CLK).as_bit();
+               if (clock != SigBit() && c != clock)
+                       reject;
+               clock = c;
+
+               SigSpec D = sigD;
+               D.replace(port(ffD, \Q), port(ffD, \D));
+               // Only search for ffBmux if ffB.Q has at
+               //   least 3 users (ffB, dsp, ffBmux) and
+               //   its ffB.D only has two (ffB, ffBmux)
+               if (nusers(sigD) >= 3 && nusers(D) == 2)
+                       sigffDmuxY = sigD;
+               sigD = std::move(D);
+       }
+endcode
+
+match ffDmux
+       if !sigffDmuxY.empty()
+       select ffDmux->type.in($mux)
+       index <SigSpec> port(ffDmux, \Y) === port(ffD, \D)
+       filter GetSize(port(ffDmux, \Y)) >= GetSize(sigD)
+       slice offset GetSize(port(ffDmux, \Y))
+       filter offset+GetSize(sigD) <= GetSize(port(ffDmux, \Y))
+       filter port(ffDmux, \Y).extract(offset, GetSize(sigB)) == sigD
+       choice <IdString> AB {\A, \B}
+       filter offset+GetSize(sigffDmuxY) <= GetSize(port(ffDmux, \Y))
+       filter port(ffDmux, AB).extract(offset, GetSize(sigffDmuxY)) == sigffDmuxY
+       define <bool> pol (AB == \A)
+       set ffDenpol pol
+       optional
+endmatch
+
+code sigD
+       if (ffDmux)
+               sigD.replace(port(ffDmux, \Y), port(ffDmux, ffDenpol ? \B : \A));
+endcode
+
 match ffMmux
        if param(dsp, \MREG).as_int() == 0
        if nusers(sigM) == 2