Closes #1714. Fix make failure when NDEBUG=1.

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 8f57184116145029a1208dcd830b7316b29f3314..54605f90e33d06e3a262257d13d218bff6045268 100644 (file)
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -752,13 +752,11 @@ void reintegrate(RTLIL::Module *module)
                                continue;
                        }
 
-#ifndef NDEBUG
                        RTLIL::Module* box_module = design->module(existing_cell->type);
                        IdString derived_type = box_module->derive(design, existing_cell->parameters);
                        RTLIL::Module* derived_module = design->module(derived_type);
                        log_assert(derived_module);
                        log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at("\\abc9_box_id").as_int()));
-#endif
                        mapped_cell->type = existing_cell->type;
 
                        RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);