#include "iris_screen.h"
#include "intel/compiler/brw_compiler.h"
+static void
+split_depth_stencil_resources(struct pipe_resource *res,
+ struct pipe_resource **out_z,
+ struct pipe_resource **out_s)
+{
+ const struct util_format_description *desc =
+ util_format_description(res->format);
+
+ if (util_format_has_depth(desc)) {
+ *out_z = res;
+ *out_s = iris_resource_get_separate_stencil(res);
+ } else {
+ assert(util_format_has_stencil(desc));
+ *out_z = NULL;
+ *out_s = res;
+ }
+}
+
/**
* The pipe->clear() driver hook.
*
if (buffers & PIPE_CLEAR_DEPTHSTENCIL) {
struct pipe_surface *psurf = cso_fb->zsbuf;
+ struct pipe_resource *z_res;
+ struct pipe_resource *stencil_res;
struct blorp_surf z_surf;
+ struct blorp_surf stencil_surf;
const unsigned num_layers =
psurf->u.tex.last_layer - psurf->u.tex.first_layer + 1;
- iris_blorp_surf_for_resource(&z_surf, psurf->texture,
- ISL_AUX_USAGE_NONE, true);
+ split_depth_stencil_resources(psurf->texture, &z_res, &stencil_res);
- blorp_clear_depth_stencil(&blorp_batch, &z_surf, NULL /* XXX */,
+ if (z_res) {
+ iris_blorp_surf_for_resource(&z_surf, z_res,
+ ISL_AUX_USAGE_NONE, true);
+ }
+
+ if (stencil_res) {
+ iris_blorp_surf_for_resource(&stencil_surf, stencil_res,
+ ISL_AUX_USAGE_NONE, true);
+ }
+
+ blorp_clear_depth_stencil(&blorp_batch, &z_surf, &stencil_surf,
psurf->u.tex.level, psurf->u.tex.first_layer,
num_layers, 0, 0, psurf->width, psurf->height,
- (buffers & PIPE_CLEAR_DEPTH) != 0,
- depth, 0 /* XXX */, stencil);
-
- if (buffers & PIPE_CLEAR_STENCIL)
- fprintf(stderr, "XXX: stencil clears not implemented\n");
+ (buffers & PIPE_CLEAR_DEPTH) != 0, depth,
+ (buffers & PIPE_CLEAR_STENCIL) ? 0xff : 0,
+ stencil);
}
if (buffers & PIPE_CLEAR_COLOR) {
return usage;
}
+struct pipe_resource *
+iris_resource_get_separate_stencil(struct pipe_resource *p_res)
+{
+ /* For packed depth-stencil, we treat depth as the primary resource
+ * and store S8 as the "second plane" resource.
+ */
+ return p_res->next;
+}
+
static void
iris_resource_destroy(struct pipe_screen *screen,
struct pipe_resource *resource)
struct iris_screen *screen = (struct iris_screen *)pscreen;
struct gen_device_info *devinfo = &screen->devinfo;
struct iris_resource *res = iris_alloc_resource(pscreen, templ);
+ const struct util_format_description *format_desc =
+ util_format_description(templ->format);
+
if (!res)
return NULL;
- bool depth_or_stencil = util_format_is_depth_or_stencil(templ->format);
-
+ const bool has_depth = util_format_has_depth(format_desc);
uint64_t modifier = DRM_FORMAT_MOD_INVALID;
if (modifiers_count == 0 || !modifiers) {
- if (depth_or_stencil) {
+ if (has_depth) {
modifier = I915_FORMAT_MOD_Y_TILED;
} else if (templ->bind & PIPE_BIND_DISPLAY_TARGET) {
/* Display is X-tiled for historical reasons. */
const struct isl_drm_modifier_info *mod_info =
isl_drm_modifier_get_info(modifier);
+ enum isl_tiling tiling = templ->format == PIPE_FORMAT_S8_UINT ?
+ ISL_TILING_W : mod_info->tiling;
+
isl_surf_usage_flags_t usage = pipe_bind_to_isl_usage(templ->bind);
if (templ->target == PIPE_TEXTURE_CUBE ||
templ->target == PIPE_TEXTURE_CUBE_ARRAY)
usage |= ISL_SURF_USAGE_CUBE_BIT;
- if (depth_or_stencil && templ->usage != PIPE_USAGE_STAGING)
- usage |= ISL_SURF_USAGE_DEPTH_BIT;
+ if (templ->usage != PIPE_USAGE_STAGING) {
+ if (templ->format == PIPE_FORMAT_S8_UINT)
+ usage |= ISL_SURF_USAGE_STENCIL_BIT;
+ else if (has_depth)
+ usage |= ISL_SURF_USAGE_DEPTH_BIT;
+ }
enum pipe_format pfmt = templ->format;
.min_alignment_B = 0,
.row_pitch_B = 0,
.usage = usage,
- .tiling_flags = 1 << mod_info->tiling);
+ .tiling_flags = 1 << tiling);
assert(isl_surf_created_successfully);
enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER;