arm: Eliminate the MustBeOne ARM specific request flag.

This flag makes constructing a generic Request object for ARM
impossible, since generic consumers won't know to set that flag to one.

As a principle, Request flags should change the behavior of a request
away from whatever the default/typical behavior is in the current
context, so flags set to zero means no special behavior.

Change-Id: Id606dc0bf42210218e1745585327671a98a8dba4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26546
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc
index 125e0f8ff7a3e933c7978c69400ce0beeb09b4dc..211a17626116bfc3ff4ce1c36f0a3e73fd8b7857 100644 (file)
--- a/src/arch/arm/insts/macromem.cc
+++ b/src/arch/arm/insts/macromem.cc
@@ -472,7 +472,7 @@ VldMultOp::VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
 
     RegIndex rMid = deinterleave ? VecSpecialElem : vd * 2;
 
-    uint32_t noAlign = TLB::MustBeOne;
+    uint32_t noAlign = 0;
 
     unsigned uopIdx = 0;
     switch (regs) {
@@ -833,7 +833,7 @@ VstMultOp::VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
     if (interleave) numMicroops += (regs / elems);
     microOps = new StaticInstPtr[numMicroops];
 
-    uint32_t noAlign = TLB::MustBeOne;
+    uint32_t noAlign = 0;
 
     RegIndex rMid = interleave ? VecSpecialElem : vd * 2;
 
@@ -1143,8 +1143,7 @@ VldMultOp64::VldMultOp64(const char *mnem, ExtMachInst machInst,
 
     microOps = new StaticInstPtr[numMicroops];
     unsigned uopIdx = 0;
-    uint32_t memaccessFlags = TLB::MustBeOne | (TLB::ArmFlags) eSize |
-        TLB::AllowUnaligned;
+    uint32_t memaccessFlags = (TLB::ArmFlags)eSize | TLB::AllowUnaligned;
 
     int i = 0;
     for (; i < numMemMicroops - 1; ++i) {
@@ -1251,8 +1250,7 @@ VstMultOp64::VstMultOp64(const char *mnem, ExtMachInst machInst,
         }
     }
 
-    uint32_t memaccessFlags = TLB::MustBeOne | (TLB::ArmFlags) eSize |
-        TLB::AllowUnaligned;
+    uint32_t memaccessFlags = (TLB::ArmFlags)eSize | TLB::AllowUnaligned;
 
     int i = 0;
     for (; i < numMemMicroops - 1; ++i) {
@@ -1319,8 +1317,7 @@ VldSingleOp64::VldSingleOp64(const char *mnem, ExtMachInst machInst,
     microOps = new StaticInstPtr[numMicroops];
     unsigned uopIdx = 0;
 
-    uint32_t memaccessFlags = TLB::MustBeOne | (TLB::ArmFlags) eSize |
-        TLB::AllowUnaligned;
+    uint32_t memaccessFlags = (TLB::ArmFlags)eSize | TLB::AllowUnaligned;
 
     int i = 0;
     for (; i < numMemMicroops - 1; ++i) {
@@ -1398,8 +1395,7 @@ VstSingleOp64::VstSingleOp64(const char *mnem, ExtMachInst machInst,
             numStructElems, index, i /* step */, replicate);
     }
 
-    uint32_t memaccessFlags = TLB::MustBeOne | (TLB::ArmFlags) eSize |
-        TLB::AllowUnaligned;
+    uint32_t memaccessFlags = (TLB::ArmFlags)eSize | TLB::AllowUnaligned;
 
     int i = 0;
     for (; i < numMemMicroops - 1; ++i) {

diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh
index b3ba76dd45133f8e54785279d7e1752861539bd7..94a3e0fd196a1f467c941bf52cafa2296485546e 100644 (file)
--- a/src/arch/arm/insts/macromem.hh
+++ b/src/arch/arm/insts/macromem.hh
@@ -118,8 +118,7 @@ class MicroNeonMemOp : public MicroOp
     MicroNeonMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
                    RegIndex _dest, RegIndex _ura, uint32_t _imm)
             : MicroOp(mnem, machInst, __opClass),
-              dest(_dest), ura(_ura), imm(_imm),
-              memAccessFlags(TLB::MustBeOne)
+              dest(_dest), ura(_ura), imm(_imm), memAccessFlags()
     {
     }
 };
@@ -393,7 +392,7 @@ class MicroMemOp : public MicroIntImmOp
     MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
                RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm)
             : MicroIntImmOp(mnem, machInst, __opClass, _ura, _urb, _imm),
-              up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord)
+              up(_up), memAccessFlags(TLB::AlignWord)
     {
     }
 
@@ -414,7 +413,7 @@ class MicroMemPairOp : public MicroOp
             bool _up, uint8_t _imm)
         : MicroOp(mnem, machInst, __opClass),
         dest(_dreg1), dest2(_dreg2), urb(_base), up(_up), imm(_imm),
-        memAccessFlags(TLB::MustBeOne | TLB::AlignWord)
+        memAccessFlags(TLB::AlignWord)
     {
     }
 

diff --git a/src/arch/arm/insts/sve_mem.hh b/src/arch/arm/insts/sve_mem.hh
index 7625374fb257ba8bc1476c9778e675dbbce85699..48651136c0648eba0180230134d65c9cf5b8b428 100644 (file)
--- a/src/arch/arm/insts/sve_mem.hh
+++ b/src/arch/arm/insts/sve_mem.hh
@@ -61,7 +61,7 @@ class SveMemVecFillSpill : public ArmStaticInst
                        IntRegIndex _base, uint64_t _imm)
         : ArmStaticInst(mnem, _machInst, __opClass),
           dest(_dest), base(_base), imm(_imm),
-          memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
+          memAccessFlags(ArmISA::TLB::AllowUnaligned)
     {
         baseIsSP = isSP(_base);
     }
@@ -86,7 +86,7 @@ class SveMemPredFillSpill : public ArmStaticInst
                         IntRegIndex _base, uint64_t _imm)
         : ArmStaticInst(mnem, _machInst, __opClass),
           dest(_dest), base(_base), imm(_imm),
-          memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
+          memAccessFlags(ArmISA::TLB::AllowUnaligned)
     {
         baseIsSP = isSP(_base);
     }
@@ -112,7 +112,7 @@ class SveContigMemSS : public ArmStaticInst
                    IntRegIndex _offset)
         : ArmStaticInst(mnem, _machInst, __opClass),
           dest(_dest), gp(_gp), base(_base), offset(_offset),
-          memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
+          memAccessFlags(ArmISA::TLB::AllowUnaligned)
     {
         baseIsSP = isSP(_base);
     }
@@ -138,7 +138,7 @@ class SveContigMemSI : public ArmStaticInst
                    uint64_t _imm)
         : ArmStaticInst(mnem, _machInst, __opClass),
           dest(_dest), gp(_gp), base(_base), imm(_imm),
-          memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
+          memAccessFlags(ArmISA::TLB::AllowUnaligned)
     {
         baseIsSP = isSP(_base);
     }

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b2175cb493851b9a4836d66b31fd8cc528cc57f0..2cc0f950c14e4ea2ce6535b46b3c10721493bb13 100644 (file)
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1680,60 +1680,54 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
               Fault fault;
               switch(misc_reg) {
                 case MISCREG_ATS1CPR:
-                  flags    = TLB::MustBeOne;
                   tranType = TLB::S1CTran;
                   mode     = BaseTLB::Read;
                   break;
                 case MISCREG_ATS1CPW:
-                  flags    = TLB::MustBeOne;
                   tranType = TLB::S1CTran;
                   mode     = BaseTLB::Write;
                   break;
                 case MISCREG_ATS1CUR:
-                  flags    = TLB::MustBeOne | TLB::UserMode;
+                  flags    = TLB::UserMode;
                   tranType = TLB::S1CTran;
                   mode     = BaseTLB::Read;
                   break;
                 case MISCREG_ATS1CUW:
-                  flags    = TLB::MustBeOne | TLB::UserMode;
+                  flags    = TLB::UserMode;
                   tranType = TLB::S1CTran;
                   mode     = BaseTLB::Write;
                   break;
                 case MISCREG_ATS12NSOPR:
                   if (!haveSecurity)
                       panic("Security Extensions required for ATS12NSOPR");
-                  flags    = TLB::MustBeOne;
                   tranType = TLB::S1S2NsTran;
                   mode     = BaseTLB::Read;
                   break;
                 case MISCREG_ATS12NSOPW:
                   if (!haveSecurity)
                       panic("Security Extensions required for ATS12NSOPW");
-                  flags    = TLB::MustBeOne;
                   tranType = TLB::S1S2NsTran;
                   mode     = BaseTLB::Write;
                   break;
                 case MISCREG_ATS12NSOUR:
                   if (!haveSecurity)
                       panic("Security Extensions required for ATS12NSOUR");
-                  flags    = TLB::MustBeOne | TLB::UserMode;
+                  flags    = TLB::UserMode;
                   tranType = TLB::S1S2NsTran;
                   mode     = BaseTLB::Read;
                   break;
                 case MISCREG_ATS12NSOUW:
                   if (!haveSecurity)
                       panic("Security Extensions required for ATS12NSOUW");
-                  flags    = TLB::MustBeOne | TLB::UserMode;
+                  flags    = TLB::UserMode;
                   tranType = TLB::S1S2NsTran;
                   mode     = BaseTLB::Write;
                   break;
                 case MISCREG_ATS1HR: // only really useful from secure mode.
-                  flags    = TLB::MustBeOne;
                   tranType = TLB::HypMode;
                   mode     = BaseTLB::Read;
                   break;
                 case MISCREG_ATS1HW:
-                  flags    = TLB::MustBeOne;
                   tranType = TLB::HypMode;
                   mode     = BaseTLB::Write;
                   break;
@@ -1947,62 +1941,54 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
                 Fault fault;
                 switch(misc_reg) {
                   case MISCREG_AT_S1E1R_Xt:
-                    flags    = TLB::MustBeOne;
                     tranType = TLB::S1E1Tran;
                     mode     = BaseTLB::Read;
                     break;
                   case MISCREG_AT_S1E1W_Xt:
-                    flags    = TLB::MustBeOne;
                     tranType = TLB::S1E1Tran;
                     mode     = BaseTLB::Write;
                     break;
                   case MISCREG_AT_S1E0R_Xt:
-                    flags    = TLB::MustBeOne | TLB::UserMode;
+                    flags    = TLB::UserMode;
                     tranType = TLB::S1E0Tran;
                     mode     = BaseTLB::Read;
                     break;
                   case MISCREG_AT_S1E0W_Xt:
-                    flags    = TLB::MustBeOne | TLB::UserMode;
+                    flags    = TLB::UserMode;
                     tranType = TLB::S1E0Tran;
                     mode     = BaseTLB::Write;
                     break;
                   case MISCREG_AT_S1E2R_Xt:
-                    flags    = TLB::MustBeOne;
                     tranType = TLB::S1E2Tran;
                     mode     = BaseTLB::Read;
                     break;
                   case MISCREG_AT_S1E2W_Xt:
-                    flags    = TLB::MustBeOne;
                     tranType = TLB::S1E2Tran;
                     mode     = BaseTLB::Write;
                     break;
                   case MISCREG_AT_S12E0R_Xt:
-                    flags    = TLB::MustBeOne | TLB::UserMode;
+                    flags    = TLB::UserMode;
                     tranType = TLB::S12E0Tran;
                     mode     = BaseTLB::Read;
                     break;
                   case MISCREG_AT_S12E0W_Xt:
-                    flags    = TLB::MustBeOne | TLB::UserMode;
+                    flags    = TLB::UserMode;
                     tranType = TLB::S12E0Tran;
                     mode     = BaseTLB::Write;
                     break;
                   case MISCREG_AT_S12E1R_Xt:
-                    flags    = TLB::MustBeOne;
                     tranType = TLB::S12E1Tran;
                     mode     = BaseTLB::Read;
                     break;
                   case MISCREG_AT_S12E1W_Xt:
-                    flags    = TLB::MustBeOne;
                     tranType = TLB::S12E1Tran;
                     mode     = BaseTLB::Write;
                     break;
                   case MISCREG_AT_S1E3R_Xt:
-                    flags    = TLB::MustBeOne;
                     tranType = TLB::S1E3Tran;
                     mode     = BaseTLB::Read;
                     break;
                   case MISCREG_AT_S1E3W_Xt:
-                    flags    = TLB::MustBeOne;
                     tranType = TLB::S1E3Tran;
                     mode     = BaseTLB::Write;
                     break;

diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index 0b99cc6c37e4c79473487626a3a2499b6297fa25..de0fdd2700206342a309a09220d92f876f508639 100644 (file)
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -141,7 +141,7 @@ let {{
                                                  bits(machInst, 22) << 4);
         const uint32_t type = bits(machInst, 11, 8);
         uint32_t size = 0;
-        uint32_t align = TLB::MustBeOne;
+        uint32_t align = 0;
         unsigned inc = 1;
         unsigned regs = 1;
         unsigned lane = 0;

diff --git a/src/arch/arm/isa/insts/amo64.isa b/src/arch/arm/isa/insts/amo64.isa
index 86ee7ba040c729a70e8d111e79b5c961c6273c8f..6d3a5151e2f26a1a9dece2d80f6abdd875754a1a 100644 (file)
--- a/src/arch/arm/isa/insts/amo64.isa
+++ b/src/arch/arm/isa/insts/amo64.isa
@@ -75,7 +75,7 @@ let {{
             self.top = top
             self.paired = paired
 
-            self.memFlags = ["ArmISA::TLB::MustBeOne"]
+            self.memFlags = []
             self.instFlags = ["IsAtomic"]
             self.codeBlobs = { "postacc_code" : "" }
             self.codeBlobs['usrDecl'] = ""

diff --git a/src/arch/arm/isa/insts/branch.isa b/src/arch/arm/isa/insts/branch.isa
index 69a220ea041dab0f1152e689462f665349625b0b..f61d0c56a5acf840da4ef219e34bf1416a108689 100644 (file)
--- a/src/arch/arm/isa/insts/branch.isa
+++ b/src/arch/arm/isa/insts/branch.isa
@@ -188,8 +188,7 @@ let {{
         if isTbh:
             eaCode = '''
             unsigned memAccessFlags = ArmISA::TLB::AllowUnaligned |
-                                      ArmISA::TLB::AlignHalfWord |
-                                      ArmISA::TLB::MustBeOne;
+                                      ArmISA::TLB::AlignHalfWord;
             EA = Op1 + Op2 * 2
             '''
             accCode = 'NPC = PC + 2 * (Mem_uh);\n'
@@ -197,8 +196,7 @@ let {{
         else:
             eaCode = '''
             unsigned memAccessFlags = ArmISA::TLB::AllowUnaligned |
-                                      ArmISA::TLB::AlignByte |
-                                      ArmISA::TLB::MustBeOne;
+                                      ArmISA::TLB::AlignByte;
             EA = Op1 + Op2
             '''
             accCode = 'NPC = PC + 2 * (Mem_ub)'

diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa
index 16b3c5733eccd84b0f304dfcc16326d5efbd29bb..3c1e941537522351fa86070e068846685c10fe6b 100644 (file)
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -386,8 +386,7 @@ let {{
 
     msrdczva_ea_code = msr_check_code
     msrdczva_ea_code += '''
-           Request::Flags memAccessFlags = Request::CACHE_BLOCK_ZERO |
-               ArmISA::TLB::MustBeOne;
+           Request::Flags memAccessFlags = Request::CACHE_BLOCK_ZERO;
            EA = XBase;
            assert(!(Dczid & 0x10));
            uint64_t op_size = power(2, Dczid + 2);
@@ -418,8 +417,7 @@ let {{
 
     msrdccvau_ea_code = msr_check_code
     msrdccvau_ea_code += '''
-           Request::Flags memAccessFlags = Request::CLEAN | Request::DST_POU |
-              ArmISA::TLB::MustBeOne;
+           Request::Flags memAccessFlags = Request::CLEAN | Request::DST_POU;
            EA = XBase;
            faultAddr = EA;
            System *sys = xc->tcBase()->getSystemPtr();
@@ -443,8 +441,7 @@ let {{
 
     msrdccvac_ea_code = msr_check_code
     msrdccvac_ea_code += '''
-           Request::Flags memAccessFlags = Request::CLEAN | Request::DST_POC |
-              ArmISA::TLB::MustBeOne;
+           Request::Flags memAccessFlags = Request::CLEAN | Request::DST_POC;
            EA = XBase;
            faultAddr = EA;
            System *sys = xc->tcBase()->getSystemPtr();
@@ -469,7 +466,7 @@ let {{
     msrdccivac_ea_code = msr_check_code
     msrdccivac_ea_code += '''
            Request::Flags memAccessFlags = Request::CLEAN |
-              Request::INVALIDATE | Request::DST_POC | ArmISA::TLB::MustBeOne;
+              Request::INVALIDATE | Request::DST_POC;
            EA = XBase;
            faultAddr = EA;
            System *sys = xc->tcBase()->getSystemPtr();
@@ -494,7 +491,7 @@ let {{
     msrdcivac_ea_code = msr_check_code
     msrdcivac_ea_code += '''
            Request::Flags memAccessFlags = Request::INVALIDATE |
-              Request::DST_POC | ArmISA::TLB::MustBeOne;
+              Request::DST_POC;
            EA = XBase;
            faultAddr = EA;
            HCR hcr = Hcr64;

diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index cab3cff3c9f4830f44646d992040f38490f9dcb4..dc1d650218d080c65152d4eff37dceaaabadb819 100644 (file)
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -64,10 +64,11 @@ let {{
             else:
                 self.op = " -"
 
-            self.memFlags = ["ArmISA::TLB::MustBeOne"]
+            self.memFlags = []
             self.codeBlobs = {"postacc_code" : ""}
 
-        def emitHelper(self, base = 'Memory', wbDecl = None, instFlags = [], pcDecl = None):
+        def emitHelper(self, base='Memory', wbDecl=None, instFlags=[],
+                       pcDecl=None):
 
             global header_output, decoder_output, exec_output
 

diff --git a/src/arch/arm/isa/insts/ldr64.isa b/src/arch/arm/isa/insts/ldr64.isa
index 96bf64297eec7cdefec5959fe94fb7f0733578de..4f1250938ed58df6d7d4ac6ea2078d6ab21a4ef7 100644 (file)
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -58,7 +58,7 @@ let {{
             self.flavor = flavor
             self.top = top
 
-            self.memFlags = ["ArmISA::TLB::MustBeOne"]
+            self.memFlags = []
             self.instFlags = []
             self.codeBlobs = {"postacc_code" : ""}
 

diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 03401ca3258460bde2a05fe086d01269fcae3cc7..396930f178a8cd5d433ab8291340e0b89fdbfbd2 100644 (file)
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -1120,8 +1120,7 @@ let {{
     '''
 
     McrDcimvacCode = '''
-        const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
-                                            Request::INVALIDATE |
+        const Request::Flags memAccessFlags(Request::INVALIDATE |
                                             Request::DST_POC);
         EA = Op1;
     '''
@@ -1139,8 +1138,7 @@ let {{
                    Mcr15CompleteAcc.subst(McrDcimvacIop)
 
     McrDccmvacCode = '''
-        const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
-                                            Request::CLEAN |
+        const Request::Flags memAccessFlags(Request::CLEAN |
                                             Request::DST_POC);
         EA = Op1;
     '''
@@ -1158,8 +1156,7 @@ let {{
                    Mcr15CompleteAcc.subst(McrDccmvacIop)
 
     McrDccmvauCode = '''
-        const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
-                                            Request::CLEAN |
+        const Request::Flags memAccessFlags(Request::CLEAN |
                                             Request::DST_POU);
         EA = Op1;
     '''
@@ -1177,8 +1174,7 @@ let {{
                    Mcr15CompleteAcc.subst(McrDccmvauIop)
 
     McrDccimvacCode = '''
-        const Request::Flags memAccessFlags(ArmISA::TLB::MustBeOne |
-                                            Request::CLEAN |
+        const Request::Flags memAccessFlags(Request::CLEAN |
                                             Request::INVALIDATE |
                                             Request::DST_POC);
         EA = Op1;

diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index 38c1ccb86b4d848587296c3e8a497e64d7aa52bc..f5424789c1cef0b40ff1e09347bf82cd06020179 100644 (file)
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -63,7 +63,7 @@ let {{
             else:
                 self.op = " -"
 
-            self.memFlags = ["ArmISA::TLB::MustBeOne"]
+            self.memFlags = []
             self.codeBlobs = { "postacc_code" : "" }
 
         def emitHelper(self, base = 'Memory', wbDecl = None):
@@ -137,8 +137,7 @@ let {{
             (newHeader,
              newDecoder,
              newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
-                 ["ArmISA::TLB::AlignWord", "ArmISA::TLB::MustBeOne"], [],
-                 'SrsOp', wbDecl)
+                 ["ArmISA::TLB::AlignWord"], [], 'SrsOp', wbDecl)
 
             header_output += newHeader
             decoder_output += newDecoder

diff --git a/src/arch/arm/isa/insts/str64.isa b/src/arch/arm/isa/insts/str64.isa
index 58ca3dfcc017f0d0836b01fbb8b6550902c3b633..22d1456611698232756ec39ac744f7722222ac67 100644 (file)
--- a/src/arch/arm/isa/insts/str64.isa
+++ b/src/arch/arm/isa/insts/str64.isa
@@ -56,7 +56,7 @@ let {{
             self.flavor = flavor
             self.top = top
 
-            self.memFlags = ["ArmISA::TLB::MustBeOne"]
+            self.memFlags = []
             self.instFlags = []
             self.codeBlobs = { "postacc_code" : "" }
 

diff --git a/src/arch/arm/isa/templates/sve_mem.isa b/src/arch/arm/isa/templates/sve_mem.isa
index bd9cb83aaaba739c5531590ced9dd3592bfe51d4..fc31b2de2f5d1f93ecbb806ac26f1e036f6ae585 100644 (file)
--- a/src/arch/arm/isa/templates/sve_mem.isa
+++ b/src/arch/arm/isa/templates/sve_mem.isa
@@ -408,8 +408,7 @@ def template SveIndexedMemVIMicroopDeclare {{
               dest(_dest), gp(_gp), base(_base), imm(_imm),
               elemIndex(_elemIndex), numElems(_numElems),
               firstFault(_firstFault),
-              memAccessFlags(ArmISA::TLB::AllowUnaligned |
-                             ArmISA::TLB::MustBeOne)
+              memAccessFlags(ArmISA::TLB::AllowUnaligned)
         {
             %(constructor)s;
             if (_opClass == MemReadOp && elemIndex == 0) {
@@ -488,8 +487,7 @@ def template SveIndexedMemSVMicroopDeclare {{
               offsetIs32(_offsetIs32), offsetIsSigned(_offsetIsSigned),
               offsetIsScaled(_offsetIsScaled), elemIndex(_elemIndex),
               numElems(_numElems), firstFault(_firstFault),
-              memAccessFlags(ArmISA::TLB::AllowUnaligned |
-                             ArmISA::TLB::MustBeOne)
+              memAccessFlags(ArmISA::TLB::AllowUnaligned)
         {
             %(constructor)s;
             if (_opClass == MemReadOp && elemIndex == 0) {
@@ -847,8 +845,7 @@ def template SveStructMemSIMicroopDeclare {{
             : %(base_class)s(mnem, machInst, %(op_class)s),
               dest(_dest), gp(_gp), base(_base), imm(_imm),
               numRegs(_numRegs), regIndex(_regIndex),
-              memAccessFlags(ArmISA::TLB::AllowUnaligned |
-                             ArmISA::TLB::MustBeOne)
+              memAccessFlags(ArmISA::TLB::AllowUnaligned)
         {
             %(constructor)s;
             baseIsSP = isSP(_base);
@@ -1111,8 +1108,7 @@ def template SveStructMemSSMicroopDeclare {{
             : %(base_class)s(mnem, machInst, %(op_class)s),
               dest(_dest), gp(_gp), base(_base), offset(_offset),
               numRegs(_numRegs), regIndex(_regIndex),
-              memAccessFlags(ArmISA::TLB::AllowUnaligned |
-                             ArmISA::TLB::MustBeOne)
+              memAccessFlags(ArmISA::TLB::AllowUnaligned)
         {
             %(constructor)s;
             baseIsSP = isSP(_base);

diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 89eb9c70c4c717503c59738cb93abaefaf870e08..51bb8ec13babdce23b9b05c3e95510a9f6bfcaf7 100644 (file)
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -2014,7 +2014,6 @@ TableWalker::fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes,
     // check here.
     if (currState->stage2Req) {
         Fault fault;
-        flags = flags | TLB::MustBeOne;
 
         if (isTiming) {
             Stage2MMU::Stage2Translation *tran = new

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 31836e1546ffbb5e0bfe1243c6f3dc872821b57c..5a92a0c33ac77981bbfd0defbeb6d1e6c652264c 100644 (file)
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -549,7 +549,6 @@ TLB::translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode,
     bool is_write = (mode == Write);
 
     if (!is_fetch) {
-        assert(flags & MustBeOne || req->isPrefetch());
         if (sctlr.a || !(flags & AllowUnaligned)) {
             if (vaddr & mask(flags & AlignmentMask)) {
                 // LPAE is always disabled in SE mode
@@ -1165,7 +1164,6 @@ TLB::translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode,
         req->setFlags(Request::STRICT_ORDER);
     }
     if (!is_fetch) {
-        assert(flags & MustBeOne || req->isPrefetch());
         if (sctlr.a || !(flags & AllowUnaligned)) {
             if (vaddr & mask(flags & AlignmentMask)) {
                 alignFaults++;

diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 428a4452b134a4d262e27426e34cef2769db044e..4efbe02869025a332dd6b0c643a0b0b327793efd 100644 (file)
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -113,11 +113,7 @@ class TLB : public BaseTLB
 
         AllowUnaligned = 0x8,
         // Priv code operating as if it wasn't
-        UserMode = 0x10,
-        // Because zero otherwise looks like a valid setting and may be used
-        // accidentally, this bit must be non-zero to show it was used on
-        // purpose.
-        MustBeOne = 0x40
+        UserMode = 0x10
     };
 
     enum ArmTranslationType {

diff --git a/src/arch/arm/tracers/tarmac_parser.cc b/src/arch/arm/tracers/tarmac_parser.cc
index 8f1974d144b2d531ccd7d3226cf22551f00c5655..a5fc32dbbfbfd54a7d2b802207c8cd10bb33347a 100644 (file)
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -873,8 +873,7 @@ TarmacParserRecord::dump()
     ostream &outs = Trace::output();
 
     uint64_t written_data = 0;
-    unsigned mem_flags = ArmISA::TLB::MustBeOne | 3 |
-        ArmISA::TLB::AllowUnaligned;
+    unsigned mem_flags = 3 | ArmISA::TLB::AllowUnaligned;
 
     ISetState isetstate;