build/sim: allow configuring verilator optimization level

diff --git a/litex/build/sim/core/Makefile b/litex/build/sim/core/Makefile
index 149789d8cb5bf16d96e270cdb9dffd015e30f7aa..e34e456e0557423adf5842c5fbf5e422349e938f 100644 (file)
--- a/litex/build/sim/core/Makefile
+++ b/litex/build/sim/core/Makefile
@@ -1,7 +1,7 @@
 include variables.mak
 
 CC = gcc
-CFLAGS = -Wall -O0 -ggdb $(if $(COVERAGE), -DVM_COVERAGE)
+CFLAGS = -Wall -$(OPT_LEVEL) -ggdb $(if $(COVERAGE), -DVM_COVERAGE)
 LDFLAGS = -lpthread -ljson-c -lm -lstdc++ -ldl -levent
 
 CC_SRCS ?= "--cc dut.v"

diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py
index 8d6a9a48f815c676ba48022c51c3d8eb559689cc..0bb35e2dd54a62c90f24b78c6fef6f3c1988d3de 100644 (file)
--- a/litex/build/sim/verilator.py
+++ b/litex/build/sim/verilator.py
@@ -117,19 +117,20 @@ def _generate_sim_config(config):
     tools.write_to_file("sim_config.js", content)
 
 
-def _build_sim(build_name, sources, threads, coverage):
+def _build_sim(build_name, sources, threads, coverage, opt_level="O3"):
     makefile = os.path.join(core_directory, 'Makefile')
     cc_srcs = []
     for filename, language, library in sources:
         cc_srcs.append("--cc " + filename + " ")
     build_script_contents = """\
 rm -rf obj_dir/
-make -C . -f {} {} {} {}
+make -C . -f {} {} {} {} {}
 mkdir -p modules && cp obj_dir/*.so modules
 """.format(makefile,
     "CC_SRCS=\"{}\"".format("".join(cc_srcs)),
     "THREADS={}".format(threads) if int(threads) > 1 else "",
     "COVERAGE=1" if coverage else "",
+    "OPT_LEVEL={}".format(opt_level),
     )
     build_script_file = "build_" + build_name + ".sh"
     tools.write_to_file(build_script_file, build_script_contents, force_unix=True)
@@ -169,7 +170,7 @@ def _run_sim(build_name, as_root=False):
 class SimVerilatorToolchain:
     def build(self, platform, fragment, build_dir="build", build_name="dut",
             toolchain_path=None, serial="console", build=True, run=True, threads=1,
-            verbose=True, sim_config=None, coverage=False,
+            verbose=True, sim_config=None, coverage=False, opt_level="O0",
             trace=False, trace_start=0, trace_end=-1):
 
         # create build directory
@@ -200,7 +201,7 @@ class SimVerilatorToolchain:
                 _generate_sim_config(sim_config)
 
             # build
-            _build_sim(build_name, platform.sources, threads, coverage)
+            _build_sim(build_name, platform.sources, threads, coverage, opt_level)
 
         # run
         if run:

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 01bab977abeba925c1c5eb36df65d9e3d6d315bb..1c0769aef9afbf91995b446feaf5cf497c372c07 100755 (executable)
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -204,6 +204,8 @@ def main():
                         help="cycle to start VCD tracing")
     parser.add_argument("--trace-end", default=-1,
                         help="cycle to end VCD tracing")
+    parser.add_argument("--opt-level", default="O3",
+                        help="compilation optimization level")
     args = parser.parse_args()
 
     soc_kwargs = soc_sdram_argdict(args)
@@ -242,10 +244,12 @@ def main():
     builder_kwargs["csr_csv"] = "csr.csv"
     builder = Builder(soc, **builder_kwargs)
     vns = builder.build(run=False, threads=args.threads, sim_config=sim_config,
+        opt_level=args.opt_level,
         trace=args.trace, trace_start=int(args.trace_start), trace_end=int(args.trace_end))
     if args.with_analyzer:
         soc.analyzer.export_csv(vns, "analyzer.csv")
     builder.build(build=False, threads=args.threads, sim_config=sim_config,
+        opt_level=args.opt_level,
         trace=args.trace, trace_start=int(args.trace_start), trace_end=int(args.trace_end))