ppc/svp64: support avgadd instructions

diff --git a/gas/testsuite/gas/ppc/avgadd.d b/gas/testsuite/gas/ppc/avgadd.d
new file mode 100644 (file)
index 0000000..062e783
--- /dev/null
+++ b/gas/testsuite/gas/ppc/avgadd.d
@@ -0,0 +1,14 @@
+#as: -mlibresoc
+#objdump: -dr -Mlibresoc
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+0+ <\.text>:
+.*:\s+(5b e0 06 9c|9c 06 e0 5b)\s+avgadd\s+r31,r0,r0
+.*:\s+(58 1f 06 9c|9c 06 1f 58)\s+avgadd\s+r0,r31,r0
+.*:\s+(58 00 fe 9c|9c fe 00 58)\s+avgadd\s+r0,r0,r31
+.*:\s+(5b e0 06 9d|9d 06 e0 5b)\s+avgadd.\s+r31,r0,r0
+.*:\s+(58 1f 06 9d|9d 06 1f 58)\s+avgadd.\s+r0,r31,r0
+.*:\s+(58 00 fe 9d|9d fe 00 58)\s+avgadd.\s+r0,r0,r31

diff --git a/gas/testsuite/gas/ppc/avgadd.s b/gas/testsuite/gas/ppc/avgadd.s
new file mode 100644 (file)
index 0000000..92d2480
--- /dev/null
+++ b/gas/testsuite/gas/ppc/avgadd.s
@@ -0,0 +1,6 @@
+avgadd 31,0,0
+avgadd 0,31,0
+avgadd 0,0,31
+avgadd. 31,0,0
+avgadd. 0,31,0
+avgadd. 0,0,31

diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index 63503b66788bf066dc9fbaa71d39ef079bc93ff8..370b126c3d2ec7d3a532020480abbb3bb00c4740 100644 (file)
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -163,3 +163,4 @@ run_dump_test "svremap"
 run_dump_test "svindex"
 run_dump_test "fmvis"
 run_dump_test "fishmv"
+run_dump_test "avgadd"

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 3cfb95a5999c97d5ed660c01b35c10d8068ec76c..22125adbde8b1ddf6e861cb98fb22e9ab77e24d6 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -7032,6 +7032,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"svremap",    SVRM(22,57),    SVRM_MASK,      SVP64,  PPCVLE, {SVme, mi0, mi1, mi2, mo0, mo1, pst}},
 
+{"avgadd",     XRC(22,846,0),  X_MASK, SVP64,  PPCVLE, {RT, RA, RB}},
+{"avgadd.",    XRC(22,846,1),  X_MASK, SVP64,  PPCVLE, {RT, RA, RB}},
+
 {"rotlw",      MME(23,31,0),   MMBME_MASK,  PPCCOM,    PPCVLE|EXT,     {RA, RS, RB}},
 {"rlwnm",      M(23,0),        M_MASK,      PPCCOM,    PPCVLE,         {RA, RS, RB, MBE, ME}},
 {"rlnm",       M(23,0),        M_MASK,      PWRCOM,    PPCVLE,         {RA, RS, RB, MBE, ME}},