bank: fix csrgen address decoder

diff --git a/migen/bank/csrgen.py b/migen/bank/csrgen.py
index e605415b14e0bd20bba07145957d51e510169600..460966b46af6d40d3ef8418aeec7063837d502f3 100644 (file)
--- a/migen/bank/csrgen.py
+++ b/migen/bank/csrgen.py
@@ -16,7 +16,7 @@ class Bank:
                comb = []
                sync = []
                
-               comb.append(a(self._sel, self.interface.a_i[12:] == f.Constant(self.address, f.BV(4))))
+               comb.append(a(self._sel, self.interface.a_i[10:] == f.Constant(self.address, f.BV(4))))
                
                nregs = len(self.description)
                nbits = f.BitsFor(nregs-1)