```
FRS <- FPADD32(FRT, FRB)
- FRT <- FPMULADD32(FRT, FRA, FRB, 1, -1)
+ sub <- FPSUB32(FRT, FRB)
+ FRT <- FPMUL32(FRA, sub)
```
+The two IEEE754-FP32 operations
+
+```
+ FRS <- [(FRT) + (FRB)]
+ FRT <- [(FRT) - (FRB)] * (FRA)
+```
+
+are simultaneously performed.
+
The Floating-Point operand in register FRT is added to the floating-point
operand in register FRB and the result stored in FRS.
the result then multiplied by FRA to create an intermediate result that
is stored in FRT.
-The add into FRS is treated exactly as `fadd`. The creation of the
-result FRT is exact!y that of `fmsub`. The creation of FRS and FRT are
-treated as parallel independent operations which occur at the same time.
+The add into FRS is treated exactly as `fadds`. The creation of the
+result FRT is **not** the same as that of `fmsubs`.
+The creation of FRS and FRT are treated as parallel independent operations
+which occur at the same time.
Note that if Rc=1 an Illegal Instruction is raised. Rc=1 is `RESERVED`
```
FRS <- FPADD64(FRT, FRB)
- FRT <- FPMULADD64(FRT, FRA, FRB, 1, -1)
+ sub <- FPSUB64(FRT, FRB)
+ FRT <- FPMUL64(FRA, sub)
```
+The two IEEE754-FP64 operations
+
+```
+ FRS <- [(FRT) + (FRB)]
+ FRT <- [(FRT) - (FRB)] * (FRA)
+```
+
+are simultaneously performed.
+
The Floating-Point operand in register FRT is added to the floating-point
operand in register FRB and the result stored in FRS.
is stored in FRT.
The add into FRS is treated exactly as `fadd`. The creation of the
-result FRT is exact!y that of `fmsub`. The creation of FRS and FRT are
-treated as parallel independent operations which occur at the same time.
+result FRT is **not** the same as that of `fmsub`.
+The creation of FRS and FRT are treated as parallel independent operations
+which occur at the same time.
Note that if Rc=1 an Illegal Instruction is raised. Rc=1 is `RESERVED`