wishbone/wishbone2csr: use wishbone.sel on CSR write.

CSR write is only done if wishbone.sel != 0. This should avoid the need for 64-bit
CSR alignment on 64-bit CPUs since a 64-bit Wishbone write access targeting only the
32-bit LSB or MSB will be splitted in 2x32-bit accesses: one with sel=0xf, one with sel=0.

diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py
index be2f9f8df9029b60f27bf94a97eb3d43a7660c40..75ed6f6494be1cfe205f389ae58217efbd8e9047 100644 (file)
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@@ -387,7 +387,7 @@ class Wishbone2CSR(Module):
         fsm.act("WRITE-READ",
             If(self.wishbone.cyc & self.wishbone.stb,
                 self.csr.adr.eq(self.wishbone.adr),
-                self.csr.we.eq(self.wishbone.we),
+                self.csr.we.eq(self.wishbone.we & (self.wishbone.sel != 0)),
                 NextState("ACK")
             )
         )