Use migen.fhdl.std

diff --git a/README b/README
index 09e29e1d4150777db9d903e7fc714e9c4717a84d..d649b4b192b532bb66be4a3f3236bc547b347f63 100644 (file)
--- a/README
+++ b/README
@@ -3,8 +3,7 @@ Mibuild (Milkymist Build system)
 
 Quick intro:
 
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 from mibuild.platforms import m1
 plat = m1.Platform()
 led = plat.request("user_led")

diff --git a/mibuild/crg.py b/mibuild/crg.py
index 7b5799f36556a3e89ff8d37771ea6e60774d3a95..5d51a13b9d754dd5348bdeb664ca97ef3be3c8fd 100644 (file)
--- a/mibuild/crg.py
+++ b/mibuild/crg.py
@@ -1,5 +1,4 @@
-from migen.fhdl.structure import *
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
 
 class SimpleCRG(Module):
        def __init__(self, platform, clk_name, rst_name, rst_invert=False):

diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py
index 3ff2f02e76febd7aa44f4a64c1e69034e43430ce..2ce4673bdaeae2d63dbdca70fdfb08d74d75d52f 100644 (file)
--- a/mibuild/generic_platform.py
+++ b/mibuild/generic_platform.py
@@ -1,7 +1,7 @@
 from copy import copy
 import os, argparse
 
-from migen.fhdl.structure import *
+from migen.fhdl.std import *
 from migen.genlib.record import Record
 from migen.fhdl import verilog
 

diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py
index d6ac47291a3c0e127487a14f50b0506a96f68311..c5273cabd39e77de80a1cb4cacfe1698ca821217 100644 (file)
--- a/mibuild/xilinx_ise.py
+++ b/mibuild/xilinx_ise.py
@@ -1,9 +1,8 @@
 import os, struct, subprocess, sys
 from decimal import Decimal
 
-from migen.fhdl.structure import *
-from migen.fhdl.specials import Instance, SynthesisDirective
-from migen.fhdl.module import Module
+from migen.fhdl.std import *
+from migen.fhdl.specials import SynthesisDirective
 from migen.genlib.cdc import *
 
 from mibuild.generic_platform import *