+++ /dev/null
-# Copyright (c) 2012 ARM Limited
-# All rights reserved.
-#
-# The license below extends only to copyright in the software and shall
-# not be construed as granting a license to any other intellectual
-# property including but not limited to intellectual property relating
-# to a hardware implementation of the functionality of the software
-# licensed hereunder. You may use the software subject to the license
-# terms below provided that you ensure that this notice is replicated
-# unmodified and in its entirety in all distributions of the software,
-# modified or unmodified, in source code or in binary form.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Andreas Sandberg
-
-from m5.params import *
-from m5.proxy import *
-from m5.objects.BaseISA import BaseISA
-
-class AlphaISA(BaseISA):
- type = 'AlphaISA'
- cxx_class = 'AlphaISA::ISA'
- cxx_header = "arch/alpha/isa.hh"
-
- system = Param.System(Parent.any, "System this ISA object belongs to")
+++ /dev/null
-# Copyright (c) 2008 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black
-
-from m5.objects.BaseInterrupts import BaseInterrupts
-
-class AlphaInterrupts(BaseInterrupts):
- type = 'AlphaInterrupts'
- cxx_class = 'AlphaISA::Interrupts'
- cxx_header = "arch/alpha/interrupts.hh"
+++ /dev/null
-# Copyright (c) 2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Nathan Binkert
-
-from m5.params import *
-from m5.proxy import *
-
-from m5.objects.System import System
-
-class AlphaSystem(System):
- type = 'AlphaSystem'
- cxx_header = "arch/alpha/system.hh"
- console = Param.String("file that contains the console code")
- pal = Param.String("file that contains palcode")
- system_type = Param.UInt64("Type of system we are emulating")
- system_rev = Param.UInt64("Revision of system we are emulating")
- load_addr_mask = 0xffffffffff
-
-class LinuxAlphaSystem(AlphaSystem):
- type = 'LinuxAlphaSystem'
- cxx_header = "arch/alpha/linux/system.hh"
- system_type = 34
- system_rev = 1 << 10
-
- boot_cpu_frequency = Param.Frequency(Self.cpu[0].clk_domain.clock[0]
- .frequency,
- "boot processor frequency")
-
-class FreebsdAlphaSystem(AlphaSystem):
- type = 'FreebsdAlphaSystem'
- cxx_header = "arch/alpha/freebsd/system.hh"
- system_type = 34
- system_rev = 1 << 10
+++ /dev/null
-# Copyright (c) 2005-2007 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Nathan Binkert
-
-from m5.SimObject import SimObject
-from m5.params import *
-
-from m5.objects.BaseTLB import BaseTLB
-
-class AlphaTLB(BaseTLB):
- type = 'AlphaTLB'
- cxx_class = 'AlphaISA::TLB'
- cxx_header = "arch/alpha/tlb.hh"
- size = Param.Int("TLB size")
-
-class AlphaDTB(AlphaTLB):
- size = 64
-
-class AlphaITB(AlphaTLB):
- size = 48
+++ /dev/null
-# -*- mode:python -*-
-
-# Copyright (c) 2004-2005 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Gabe Black
-# Steve Reinhardt
-
-Import('*')
-
-if env['TARGET_ISA'] == 'alpha':
- Source('decoder.cc')
- Source('ev5.cc')
- Source('faults.cc')
- Source('freebsd/system.cc')
- Source('idle_event.cc')
- Source('interrupts.cc')
- Source('ipr.cc')
- Source('isa.cc')
- Source('kernel_stats.cc')
- Source('linux/linux.cc')
- Source('linux/process.cc')
- Source('linux/system.cc')
- Source('osfpal.cc')
- Source('pagetable.cc')
- Source('process.cc')
- Source('regredir.cc')
- Source('remote_gdb.cc')
- Source('stacktrace.cc')
- Source('system.cc')
- Source('tlb.cc')
- Source('utility.cc')
- Source('vtophys.cc')
-
- SimObject('AlphaInterrupts.py')
- SimObject('AlphaISA.py')
- SimObject('AlphaSystem.py')
- SimObject('AlphaTLB.py')
-
- # Add in files generated by the ISA description.
- ISADesc('isa/main.isa')
+++ /dev/null
-# -*- mode:python -*-
-
-# Copyright (c) 2004-2005 The Regents of The University of Michigan
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Nathan Binkert
-
-Import('*')
-
-all_isa_list.append('alpha')
+++ /dev/null
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- * Nathan Binkert
- */
-
-#ifndef __AOUT_MACHDEP_H__
-#define __AOUT_MACHDEP_H__
-
-///
-/// Funky Alpha 64-bit a.out header used for PAL code.
-///
-struct aout_exechdr {
- uint16_t magic; ///< magic number
- uint16_t vstamp; ///< version stamp?
- uint16_t bldrev; ///< ???
- uint16_t padcell; ///< padding
- uint64_t tsize; ///< text segment size
- uint64_t dsize; ///< data segment size
- uint64_t bsize; ///< bss segment size
- uint64_t entry; ///< entry point
- uint64_t text_start; ///< text base address
- uint64_t data_start; ///< data base address
- uint64_t bss_start; ///< bss base address
- uint32_t gprmask; ///< GPR mask (unused, AFAIK)
- uint32_t fprmask; ///< FPR mask (unused, AFAIK)
- uint64_t gp_value; ///< global pointer reg value
-};
-
-#define AOUT_LDPGSZ 8192
-
-#define N_GETMAGIC(ex) ((ex).magic)
-
-#define N_BADMAX
-
-#define N_TXTADDR(ex) ((ex).text_start)
-#define N_DATADDR(ex) ((ex).data_start)
-#define N_BSSADDR(ex) ((ex).bss_start)
-
-#define N_TXTOFF(ex) \
- (N_GETMAGIC(ex) == ZMAGIC ? 0 : sizeof(struct aout_exechdr))
-
-#define N_DATOFF(ex) N_ALIGN(ex, N_TXTOFF(ex) + (ex).tsize)
-
-#endif /* !__AOUT_MACHDEP_H__*/
+++ /dev/null
-/*
- * Copyright (c) 2011 Google
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#include "arch/alpha/decoder.hh"
-
-namespace AlphaISA
-{
-
-GenericISA::BasicDecodeCache Decoder::defaultCache;
-
-}
+++ /dev/null
-/*
- * Copyright (c) 2012 Google
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#ifndef __ARCH_ALPHA_DECODER_HH__
-#define __ARCH_ALPHA_DECODER_HH__
-
-#include "arch/generic/decode_cache.hh"
-#include "arch/types.hh"
-#include "cpu/static_inst.hh"
-#include "sim/full_system.hh"
-
-namespace AlphaISA
-{
-
-class ISA;
-class Decoder
-{
- protected:
- // The extended machine instruction being generated
- ExtMachInst ext_inst;
- bool instDone;
-
- public:
- Decoder(ISA* isa = nullptr) : instDone(false)
- {}
-
- void
- process()
- { }
-
- void
- reset()
- {
- instDone = false;
- }
-
- // Use this to give data to the predecoder. This should be used
- // when there is control flow.
- void
- moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
- {
- ext_inst = letoh(inst);
- instDone = true;
- if (FullSystem)
- ext_inst |= (static_cast<ExtMachInst>(pc.pc() & 0x1) << 32);
- }
-
- bool
- needMoreBytes()
- {
- return true;
- }
-
- bool
- instReady()
- {
- return instDone;
- }
-
- void takeOverFrom(Decoder * old) {}
-
- protected:
- /// A cache of decoded instruction objects.
- static GenericISA::BasicDecodeCache defaultCache;
-
- public:
- StaticInstPtr decodeInst(ExtMachInst mach_inst);
-
- /// Decode a machine instruction.
- /// @param mach_inst The binary instruction to decode.
- /// @retval A pointer to the corresponding StaticInst object.
- StaticInstPtr
- decode(ExtMachInst mach_inst, Addr addr)
- {
- return defaultCache.decode(this, mach_inst, addr);
- }
-
- StaticInstPtr
- decode(AlphaISA::PCState &nextPC)
- {
- if (!instDone)
- return NULL;
- instDone = false;
- return decode(ext_inst, nextPC.instAddr());
- }
-};
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_DECODER_HH__
+++ /dev/null
-/*
- * Taken from NetBSD arch/alpha/ecoff_machdep.h
- */
-
-/* $NetBSD: ecoff_machdep.h,v 1.5 1999/04/27 02:32:33 cgd Exp $ */
-
-/*
- * Copyright (c) 1994 Adam Glass
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by Adam Glass.
- * 4. The name of the Author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY Adam Glass ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL Adam Glass BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-//
-// Define COFF/ECOFF integer type sizes
-//
-typedef int16_t coff_short;
-typedef uint16_t coff_ushort;
-typedef int32_t coff_int;
-typedef uint32_t coff_uint;
-typedef int64_t coff_long;
-typedef uint64_t coff_ulong;
-typedef uint64_t coff_addr;
-
-#define ECOFF_LDPGSZ 4096
-
-#define ECOFF_PAD \
- coff_ushort bldrev; /* XXX */
-
-#define ECOFF_MACHDEP \
- coff_uint gprmask; \
- coff_uint fprmask; \
- coff_ulong gp_value
-
-#define ECOFF_MAGIC_ALPHA 0603
-#define ECOFF_MAGIC_NETBSD_ALPHA 0605
-#define ECOFF_BADMAG(ep) \
- ((ep)->f.f_magic != ECOFF_MAGIC_ALPHA && \
- (ep)->f.f_magic != ECOFF_MAGIC_NETBSD_ALPHA)
-
-#define ECOFF_FLAG_EXEC 0002
-#define ECOFF_SEGMENT_ALIGNMENT(ep) \
- (((ep)->f.f_flags & ECOFF_FLAG_EXEC) == 0 ? 8 : 16)
-
-#define ECOFF_FLAG_OBJECT_TYPE_MASK 0x3000
-#define ECOFF_OBJECT_TYPE_NO_SHARED 0x1000
-#define ECOFF_OBJECT_TYPE_SHARABLE 0x2000
-#define ECOFF_OBJECT_TYPE_CALL_SHARED 0x3000
-
+++ /dev/null
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- * Nathan Binkert
- */
-
-#include "arch/alpha/faults.hh"
-#include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/kernel_stats.hh"
-#include "arch/alpha/osfpal.hh"
-#include "arch/alpha/tlb.hh"
-#include "base/cp_annotate.hh"
-#include "base/debug.hh"
-#include "cpu/base.hh"
-#include "cpu/simple_thread.hh"
-#include "cpu/thread_context.hh"
-#include "sim/sim_exit.hh"
-
-namespace AlphaISA {
-
-template<typename T>
-TLB *
-getITBPtr(T *tc)
-{
- auto tlb = dynamic_cast<TLB *>(tc->getITBPtr());
- assert(tlb);
- return tlb;
-}
-
-template<typename T>
-TLB *
-getDTBPtr(T *tc)
-{
- auto tlb = dynamic_cast<TLB *>(tc->getDTBPtr());
- assert(tlb);
- return tlb;
-}
-
-////////////////////////////////////////////////////////////////////////
-//
-//
-//
-void
-initIPRs(ThreadContext *tc, int cpuId)
-{
- for (int i = 0; i < NumInternalProcRegs; ++i) {
- tc->setMiscRegNoEffect(i, 0);
- }
-
- tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase);
- tc->setMiscRegNoEffect(IPR_MCSR, 0x6);
- tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
-}
-
-RegVal
-ISA::readIpr(int idx, ThreadContext *tc)
-{
- uint64_t retval = 0; // return value, default 0
-
- switch (idx) {
- case IPR_PALtemp0:
- case IPR_PALtemp1:
- case IPR_PALtemp2:
- case IPR_PALtemp3:
- case IPR_PALtemp4:
- case IPR_PALtemp5:
- case IPR_PALtemp6:
- case IPR_PALtemp7:
- case IPR_PALtemp8:
- case IPR_PALtemp9:
- case IPR_PALtemp10:
- case IPR_PALtemp11:
- case IPR_PALtemp12:
- case IPR_PALtemp13:
- case IPR_PALtemp14:
- case IPR_PALtemp15:
- case IPR_PALtemp16:
- case IPR_PALtemp17:
- case IPR_PALtemp18:
- case IPR_PALtemp19:
- case IPR_PALtemp20:
- case IPR_PALtemp21:
- case IPR_PALtemp22:
- case IPR_PALtemp23:
- case IPR_PAL_BASE:
-
- case IPR_IVPTBR:
- case IPR_DC_MODE:
- case IPR_MAF_MODE:
- case IPR_ISR:
- case IPR_EXC_ADDR:
- case IPR_IC_PERR_STAT:
- case IPR_DC_PERR_STAT:
- case IPR_MCSR:
- case IPR_ASTRR:
- case IPR_ASTER:
- case IPR_SIRR:
- case IPR_ICSR:
- case IPR_ICM:
- case IPR_DTB_CM:
- case IPR_IPLR:
- case IPR_INTID:
- case IPR_PMCTR:
- // no side-effect
- retval = ipr[idx];
- break;
-
- case IPR_CC:
- retval |= ipr[idx] & ULL(0xffffffff00000000);
- retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
- break;
-
- case IPR_VA:
- retval = ipr[idx];
- break;
-
- case IPR_VA_FORM:
- case IPR_MM_STAT:
- case IPR_IFAULT_VA_FORM:
- case IPR_EXC_MASK:
- case IPR_EXC_SUM:
- retval = ipr[idx];
- break;
-
- case IPR_DTB_PTE:
- {
- TlbEntry &entry = getDTBPtr(tc)->index(1);
-
- retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32;
- retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8;
- retval |= ((uint64_t)entry.xwe & ULL(0xf)) << 12;
- retval |= ((uint64_t)entry.fonr & ULL(0x1)) << 1;
- retval |= ((uint64_t)entry.fonw & ULL(0x1))<< 2;
- retval |= ((uint64_t)entry.asma & ULL(0x1)) << 4;
- retval |= ((uint64_t)entry.asn & ULL(0x7f)) << 57;
- }
- break;
-
- // write only registers
- case IPR_HWINT_CLR:
- case IPR_SL_XMIT:
- case IPR_DC_FLUSH:
- case IPR_IC_FLUSH:
- case IPR_ALT_MODE:
- case IPR_DTB_IA:
- case IPR_DTB_IAP:
- case IPR_ITB_IA:
- case IPR_ITB_IAP:
- panic("Tried to read write only register %d\n", idx);
- break;
-
- default:
- // invalid IPR
- panic("Tried to read from invalid ipr %d\n", idx);
- break;
- }
-
- return retval;
-}
-
-// Cause the simulator to break when changing to the following IPL
-int break_ipl = -1;
-
-void
-ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
-{
- auto *stats = dynamic_cast<AlphaISA::Kernel::Statistics *>(
- tc->getKernelStats());
- assert(stats || !tc->getKernelStats());
- switch (idx) {
- case IPR_PALtemp0:
- case IPR_PALtemp1:
- case IPR_PALtemp2:
- case IPR_PALtemp3:
- case IPR_PALtemp4:
- case IPR_PALtemp5:
- case IPR_PALtemp6:
- case IPR_PALtemp7:
- case IPR_PALtemp8:
- case IPR_PALtemp9:
- case IPR_PALtemp10:
- case IPR_PALtemp11:
- case IPR_PALtemp12:
- case IPR_PALtemp13:
- case IPR_PALtemp14:
- case IPR_PALtemp15:
- case IPR_PALtemp16:
- case IPR_PALtemp17:
- case IPR_PALtemp18:
- case IPR_PALtemp19:
- case IPR_PALtemp20:
- case IPR_PALtemp21:
- case IPR_PALtemp22:
- case IPR_PAL_BASE:
- case IPR_IC_PERR_STAT:
- case IPR_DC_PERR_STAT:
- case IPR_PMCTR:
- // write entire quad w/ no side-effect
- ipr[idx] = val;
- break;
-
- case IPR_CC_CTL:
- // This IPR resets the cycle counter. We assume this only
- // happens once... let's verify that.
- assert(ipr[idx] == 0);
- ipr[idx] = 1;
- break;
-
- case IPR_CC:
- // This IPR only writes the upper 64 bits. It's ok to write
- // all 64 here since we mask out the lower 32 in rpcc (see
- // isa_desc).
- ipr[idx] = val;
- break;
-
- case IPR_PALtemp23:
- // write entire quad w/ no side-effect
- if (stats)
- stats->context(ipr[idx], val, tc);
- ipr[idx] = val;
- break;
-
- case IPR_DTB_PTE:
- // write entire quad w/ no side-effect, tag is forthcoming
- ipr[idx] = val;
- break;
-
- case IPR_EXC_ADDR:
- // second least significant bit in PC is always zero
- ipr[idx] = val & ~2;
- break;
-
- case IPR_ASTRR:
- case IPR_ASTER:
- // only write least significant four bits - privilege mask
- ipr[idx] = val & 0xf;
- break;
-
- case IPR_IPLR:
- // only write least significant five bits - interrupt level
- ipr[idx] = val & 0x1f;
- if (stats)
- stats->swpipl(ipr[idx]);
- break;
-
- case IPR_DTB_CM:
- if (val & 0x18) {
- if (stats)
- stats->mode(Kernel::user, tc);
- } else {
- if (stats)
- stats->mode(Kernel::kernel, tc);
- }
- M5_FALLTHROUGH;
-
- case IPR_ICM:
- // only write two mode bits - processor mode
- ipr[idx] = val & 0x18;
- break;
-
- case IPR_ALT_MODE:
- // only write two mode bits - processor mode
- ipr[idx] = val & 0x18;
- break;
-
- case IPR_MCSR:
- // more here after optimization...
- ipr[idx] = val;
- break;
-
- case IPR_SIRR:
- // only write software interrupt mask
- ipr[idx] = val & 0x7fff0;
- break;
-
- case IPR_ICSR:
- ipr[idx] = val & ULL(0xffffff0300);
- break;
-
- case IPR_IVPTBR:
- case IPR_MVPTBR:
- ipr[idx] = val & ULL(0xffffffffc0000000);
- break;
-
- case IPR_DC_TEST_CTL:
- ipr[idx] = val & 0x1ffb;
- break;
-
- case IPR_DC_MODE:
- case IPR_MAF_MODE:
- ipr[idx] = val & 0x3f;
- break;
-
- case IPR_ITB_ASN:
- ipr[idx] = val & 0x7f0;
- break;
-
- case IPR_DTB_ASN:
- ipr[idx] = val & ULL(0xfe00000000000000);
- break;
-
- case IPR_EXC_SUM:
- case IPR_EXC_MASK:
- // any write to this register clears it
- ipr[idx] = 0;
- break;
-
- case IPR_INTID:
- case IPR_SL_RCV:
- case IPR_MM_STAT:
- case IPR_ITB_PTE_TEMP:
- case IPR_DTB_PTE_TEMP:
- // read-only registers
- panic("Tried to write read only ipr %d\n", idx);
-
- case IPR_HWINT_CLR:
- case IPR_SL_XMIT:
- case IPR_DC_FLUSH:
- case IPR_IC_FLUSH:
- // the following are write only
- ipr[idx] = val;
- break;
-
- case IPR_DTB_IA:
- // really a control write
- ipr[idx] = 0;
-
- getDTBPtr(tc)->flushAll();
- break;
-
- case IPR_DTB_IAP:
- // really a control write
- ipr[idx] = 0;
-
- getDTBPtr(tc)->flushProcesses();
- break;
-
- case IPR_DTB_IS:
- // really a control write
- ipr[idx] = val;
-
- getDTBPtr(tc)->flushAddr(val, DTB_ASN_ASN(ipr[IPR_DTB_ASN]));
- break;
-
- case IPR_DTB_TAG: {
- struct TlbEntry entry;
-
- // FIXME: granularity hints NYI...
- if (DTB_PTE_GH(ipr[IPR_DTB_PTE]) != 0)
- panic("PTE GH field != 0");
-
- // write entire quad
- ipr[idx] = val;
-
- // construct PTE for new entry
- entry.ppn = DTB_PTE_PPN(ipr[IPR_DTB_PTE]);
- entry.xre = DTB_PTE_XRE(ipr[IPR_DTB_PTE]);
- entry.xwe = DTB_PTE_XWE(ipr[IPR_DTB_PTE]);
- entry.fonr = DTB_PTE_FONR(ipr[IPR_DTB_PTE]);
- entry.fonw = DTB_PTE_FONW(ipr[IPR_DTB_PTE]);
- entry.asma = DTB_PTE_ASMA(ipr[IPR_DTB_PTE]);
- entry.asn = DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
-
- // insert new TAG/PTE value into data TLB
- getDTBPtr(tc)->insert(val, entry);
- }
- break;
-
- case IPR_ITB_PTE: {
- struct TlbEntry entry;
-
- // FIXME: granularity hints NYI...
- if (ITB_PTE_GH(val) != 0)
- panic("PTE GH field != 0");
-
- // write entire quad
- ipr[idx] = val;
-
- // construct PTE for new entry
- entry.ppn = ITB_PTE_PPN(val);
- entry.xre = ITB_PTE_XRE(val);
- entry.xwe = 0;
- entry.fonr = ITB_PTE_FONR(val);
- entry.fonw = ITB_PTE_FONW(val);
- entry.asma = ITB_PTE_ASMA(val);
- entry.asn = ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
-
- // insert new TAG/PTE value into data TLB
- getITBPtr(tc)->insert(ipr[IPR_ITB_TAG], entry);
- }
- break;
-
- case IPR_ITB_IA:
- // really a control write
- ipr[idx] = 0;
-
- getITBPtr(tc)->flushAll();
- break;
-
- case IPR_ITB_IAP:
- // really a control write
- ipr[idx] = 0;
-
- getITBPtr(tc)->flushProcesses();
- break;
-
- case IPR_ITB_IS:
- // really a control write
- ipr[idx] = val;
-
- getITBPtr(tc)->flushAddr(val, ITB_ASN_ASN(ipr[IPR_ITB_ASN]));
- break;
-
- default:
- // invalid IPR
- panic("Tried to write to invalid ipr %d\n", idx);
- }
-
- // no error...
-}
-
-void
-copyIprs(ThreadContext *src, ThreadContext *dest)
-{
- for (int i = 0; i < NumInternalProcRegs; ++i)
- dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
-}
-
-} // namespace AlphaISA
+++ /dev/null
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- * Nathan Binkert
- * Ali Saidi
- */
-
-#ifndef __ARCH_ALPHA_EV5_HH__
-#define __ARCH_ALPHA_EV5_HH__
-
-#include "arch/alpha/isa_traits.hh"
-
-class ThreadContext;
-
-namespace AlphaISA {
-
-const uint64_t AsnMask = ULL(0xff);
-const int VAddrImplBits = 43;
-const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
-const Addr VAddrUnImplMask = ~VAddrImplMask;
-inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
-inline Addr VAddrVPN(Addr a) { return a >> PageShift; }
-inline Addr VAddrOffset(Addr a) { return a & PageOffset; }
-inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
-inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
-
-inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); }
-const int PAddrImplBits = 44; // for Tsunami
-const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1;
-const Addr PAddrUncachedBit39 = ULL(0x8000000000);
-const Addr PAddrUncachedBit40 = ULL(0x10000000000);
-const Addr PAddrUncachedBit43 = ULL(0x80000000000);
-const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35>
-
-inline Addr
-Phys2K0Seg(Addr addr)
-{
- if (addr & PAddrUncachedBit43) {
- addr &= PAddrUncachedMask;
- addr |= PAddrUncachedBit40;
- }
- return addr | K0SegBase;
-}
-
-inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
-inline Addr DTB_PTE_PPN(uint64_t reg)
-{ return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
-inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
-inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
-inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
-inline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
-inline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
-inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
-
-inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
-inline Addr ITB_PTE_PPN(uint64_t reg)
-{ return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
-inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
-inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
-inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
-inline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
-inline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
-
-inline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; }
-
-inline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; }
-inline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; }
-inline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; }
-
-inline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; }
-inline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
-inline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
-
-const uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020);
-const uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010);
-const uint64_t MM_STAT_FONW_MASK = ULL(0x0008);
-const uint64_t MM_STAT_FONR_MASK = ULL(0x0004);
-const uint64_t MM_STAT_ACV_MASK = ULL(0x0002);
-const uint64_t MM_STAT_WR_MASK = ULL(0x0001);
-inline int Opcode(MachInst inst) { return inst >> 26 & 0x3f; }
-inline int Ra(MachInst inst) { return inst >> 21 & 0x1f; }
-
-const Addr PalBase = 0x4000;
-const Addr PalMax = 0x10000;
-
-void copyIprs(ThreadContext *src, ThreadContext *dest);
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_EV5_HH__
+++ /dev/null
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- * Kevin Lim
- */
-
-#include "arch/alpha/faults.hh"
-
-#include "arch/alpha/ev5.hh"
-#include "arch/alpha/tlb.hh"
-#include "base/trace.hh"
-#include "cpu/base.hh"
-#include "cpu/thread_context.hh"
-#include "mem/page_table.hh"
-#include "sim/full_system.hh"
-#include "sim/process.hh"
-
-namespace AlphaISA {
-
-FaultName MachineCheckFault::_name = "mchk";
-FaultVect MachineCheckFault::_vect = 0x0401;
-FaultStat MachineCheckFault::_count;
-
-FaultName AlignmentFault::_name = "unalign";
-FaultVect AlignmentFault::_vect = 0x0301;
-FaultStat AlignmentFault::_count;
-
-FaultName ResetFault::_name = "reset";
-FaultVect ResetFault::_vect = 0x0001;
-FaultStat ResetFault::_count;
-
-FaultName ArithmeticFault::_name = "arith";
-FaultVect ArithmeticFault::_vect = 0x0501;
-FaultStat ArithmeticFault::_count;
-
-FaultName InterruptFault::_name = "interrupt";
-FaultVect InterruptFault::_vect = 0x0101;
-FaultStat InterruptFault::_count;
-
-FaultName NDtbMissFault::_name = "dtb_miss_single";
-FaultVect NDtbMissFault::_vect = 0x0201;
-FaultStat NDtbMissFault::_count;
-
-FaultName PDtbMissFault::_name = "dtb_miss_double";
-FaultVect PDtbMissFault::_vect = 0x0281;
-FaultStat PDtbMissFault::_count;
-
-FaultName DtbPageFault::_name = "dtb_page_fault";
-FaultVect DtbPageFault::_vect = 0x0381;
-FaultStat DtbPageFault::_count;
-
-FaultName DtbAcvFault::_name = "dtb_acv_fault";
-FaultVect DtbAcvFault::_vect = 0x0381;
-FaultStat DtbAcvFault::_count;
-
-FaultName DtbAlignmentFault::_name = "unalign";
-FaultVect DtbAlignmentFault::_vect = 0x0301;
-FaultStat DtbAlignmentFault::_count;
-
-FaultName ItbPageFault::_name = "itbmiss";
-FaultVect ItbPageFault::_vect = 0x0181;
-FaultStat ItbPageFault::_count;
-
-FaultName ItbAcvFault::_name = "iaccvio";
-FaultVect ItbAcvFault::_vect = 0x0081;
-FaultStat ItbAcvFault::_count;
-
-FaultName UnimplementedOpcodeFault::_name = "opdec";
-FaultVect UnimplementedOpcodeFault::_vect = 0x0481;
-FaultStat UnimplementedOpcodeFault::_count;
-
-FaultName FloatEnableFault::_name = "fen";
-FaultVect FloatEnableFault::_vect = 0x0581;
-FaultStat FloatEnableFault::_count;
-
-/* We use the same fault vector, as for the guest system these should be the
- * same, but for host purposes, having differentiation is helpful for
- * debug/monitorization purposes. */
-FaultName VectorEnableFault::_name = "ven";
-FaultVect VectorEnableFault::_vect = 0x0581;
-FaultStat VectorEnableFault::_count;
-
-FaultName PalFault::_name = "pal";
-FaultVect PalFault::_vect = 0x2001;
-FaultStat PalFault::_count;
-
-FaultName IntegerOverflowFault::_name = "intover";
-FaultVect IntegerOverflowFault::_vect = 0x0501;
-FaultStat IntegerOverflowFault::_count;
-
-void
-AlphaFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
-{
- FaultBase::invoke(tc);
- if (!FullSystem)
- return;
- countStat()++;
-
- PCState pc = tc->pcState();
-
- // exception restart address
- if (setRestartAddress() || !(pc.pc() & 0x3))
- tc->setMiscRegNoEffect(IPR_EXC_ADDR, pc.pc());
-
- if (skipFaultingInstruction()) {
- // traps... skip faulting instruction.
- tc->setMiscRegNoEffect(IPR_EXC_ADDR,
- tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4);
- }
-
- pc.set(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect());
- tc->pcState(pc);
-}
-
-void
-ArithmeticFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
-{
- FaultBase::invoke(tc);
- if (!FullSystem)
- return;
- panic("Arithmetic traps are unimplemented!");
-}
-
-void
-DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
-{
- if (FullSystem) {
- // Set fault address and flags. Even though we're modeling an
- // EV5, we use the EV6 technique of not latching fault registers
- // on VPTE loads (instead of locking the registers until IPR_VA is
- // read, like the EV5). The EV6 approach is cleaner and seems to
- // work with EV5 PAL code, but not the other way around.
- if (reqFlags.noneSet(AlphaRequestFlags::VPTE | Request::PREFETCH)) {
- // set VA register with faulting address
- tc->setMiscRegNoEffect(IPR_VA, vaddr);
-
- // set MM_STAT register flags
- MachInst machInst = inst->machInst;
- tc->setMiscRegNoEffect(IPR_MM_STAT,
- (((Opcode(machInst) & 0x3f) << 11) |
- ((Ra(machInst) & 0x1f) << 6) |
- (flags & 0x3f)));
-
- // set VA_FORM register with faulting formatted address
- tc->setMiscRegNoEffect(IPR_VA_FORM,
- tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3));
- }
- }
-
- AlphaFault::invoke(tc);
-}
-
-void
-ItbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
-{
- if (FullSystem) {
- tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
- tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
- tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
- }
-
- AlphaFault::invoke(tc);
-}
-
-void
-ItbPageFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
-{
- if (FullSystem) {
- ItbFault::invoke(tc);
- return;
- }
-
- Process *p = tc->getProcessPtr();
- const EmulationPageTable::Entry *pte = p->pTable->lookup(pc);
- panic_if(!pte, "Tried to execute unmapped address %#x.\n", pc);
-
- VAddr vaddr(pc);
- TlbEntry entry(p->pTable->pid(), vaddr.page(), pte->paddr,
- pte->flags & EmulationPageTable::Uncacheable,
- pte->flags & EmulationPageTable::ReadOnly);
- dynamic_cast<TLB *>(tc->getITBPtr())->insert(vaddr.page(), entry);
-}
-
-void
-NDtbMissFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
-{
- if (FullSystem) {
- DtbFault::invoke(tc, inst);
- return;
- }
-
- Process *p = tc->getProcessPtr();
- const EmulationPageTable::Entry *pte = p->pTable->lookup(vaddr);
- if (!pte && p->fixupStackFault(vaddr))
- pte = p->pTable->lookup(vaddr);
- panic_if(!pte, "Tried to access unmapped address %#x.\n", (Addr)vaddr);
- TlbEntry entry(p->pTable->pid(), vaddr.page(), pte->paddr,
- pte->flags & EmulationPageTable::Uncacheable,
- pte->flags & EmulationPageTable::ReadOnly);
- dynamic_cast<TLB *>(tc->getDTBPtr())->insert(vaddr.page(), entry);
-}
-
-} // namespace AlphaISA
-
+++ /dev/null
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- * Kevin Lim
- */
-
-#ifndef __ARCH_ALPHA_FAULTS_HH__
-#define __ARCH_ALPHA_FAULTS_HH__
-
-#include "arch/alpha/pagetable.hh"
-#include "mem/request.hh"
-#include "sim/faults.hh"
-
-// The design of the "name" and "vect" functions is in sim/faults.hh
-
-namespace AlphaISA {
-
-typedef Addr FaultVect;
-
-class AlphaFault : public FaultBase
-{
- protected:
- virtual bool skipFaultingInstruction() {return false;}
- virtual bool setRestartAddress() {return true;}
- public:
- virtual ~AlphaFault() {}
- void invoke(ThreadContext * tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr);
- virtual FaultVect vect() = 0;
- virtual FaultStat & countStat() = 0;
-};
-
-class MachineCheckFault : public AlphaFault
-{
- private:
- static FaultName _name;
- static FaultVect _vect;
- static FaultStat _count;
-
- public:
- FaultName name() const {return _name;}
- FaultVect vect() {return _vect;}
- FaultStat & countStat() {return _count;}
-};
-
-class AlignmentFault : public AlphaFault
-{
- private:
- static FaultName _name;
- static FaultVect _vect;
- static FaultStat _count;
-
- public:
- FaultName name() const {return _name;}
- FaultVect vect() {return _vect;}
- FaultStat & countStat() {return _count;}
- bool isAlignmentFault() const {return true;}
-};
-
-class ResetFault : public AlphaFault
-{
- private:
- static FaultName _name;
- static FaultVect _vect;
- static FaultStat _count;
-
- public:
- FaultName name() const {return _name;}
- FaultVect vect() {return _vect;}
- FaultStat & countStat() {return _count;}
-};
-
-class ArithmeticFault : public AlphaFault
-{
- private:
- static FaultName _name;
- static FaultVect _vect;
- static FaultStat _count;
-
- protected:
- bool skipFaultingInstruction() {return true;}
-
- public:
- FaultName name() const {return _name;}
- FaultVect vect() {return _vect;}
- FaultStat & countStat() {return _count;}
- void invoke(ThreadContext * tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr);
-};
-
-class InterruptFault : public AlphaFault
-{
- private:
- static FaultName _name;
- static FaultVect _vect;
- static FaultStat _count;
-
- protected:
- bool setRestartAddress() {return false;}
-
- public:
- FaultName name() const {return _name;}
- FaultVect vect() {return _vect;}
- FaultStat & countStat() {return _count;}
-};
-
-class DtbFault : public AlphaFault
-{
- protected:
- VAddr vaddr;
- Request::Flags reqFlags;
- uint64_t flags;
-
- public:
- DtbFault(VAddr _vaddr, Request::Flags _reqFlags, uint64_t _flags)
- : vaddr(_vaddr), reqFlags(_reqFlags), flags(_flags)
- { }
- FaultName name() const = 0;
- FaultVect vect() = 0;
- FaultStat & countStat() = 0;
- void invoke(ThreadContext * tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr);
-};
-
-class NDtbMissFault : public DtbFault
-{
- private:
- static FaultName _name;
- static FaultVect _vect;
- static FaultStat _count;
-
- public:
- NDtbMissFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags)
- : DtbFault(vaddr, reqFlags, flags)
- { }
- FaultName name() const {return _name;}
- FaultVect vect() {return _vect;}
- FaultStat & countStat() {return _count;}
- void invoke(ThreadContext * tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr);
-};
-
-class PDtbMissFault : public DtbFault
-{
- private:
- static FaultName _name;
- static FaultVect _vect;
- static FaultStat _count;
-
- public:
- PDtbMissFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags)
- : DtbFault(vaddr, reqFlags, flags)
- { }
- FaultName name() const {return _name;}
- FaultVect vect() {return _vect;}
- FaultStat & countStat() {return _count;}
-};
-
-class DtbPageFault : public DtbFault
-{
- private:
- static FaultName _name;
- static FaultVect _vect;
- static FaultStat _count;
-
- public:
- DtbPageFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags)
- : DtbFault(vaddr, reqFlags, flags)
- { }
- FaultName name() const {return _name;}
- FaultVect vect() {return _vect;}
- FaultStat & countStat() {return _count;}
-};
-
-class DtbAcvFault : public DtbFault
-{
- private:
- static FaultName _name;
- static FaultVect _vect;
- static FaultStat _count;
-
- public:
- DtbAcvFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags)
- : DtbFault(vaddr, reqFlags, flags)
- { }
- FaultName name() const {return _name;}
- FaultVect vect() {return _vect;}
- FaultStat & countStat() {return _count;}
-};
-
-class DtbAlignmentFault : public DtbFault
-{
- private:
- static FaultName _name;
- static FaultVect _vect;
- static FaultStat _count;
-
- public:
- DtbAlignmentFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags)
- : DtbFault(vaddr, reqFlags, flags)
- { }
- FaultName name() const {return _name;}
- FaultVect vect() {return _vect;}
- FaultStat & countStat() {return _count;}
-};
-
-class ItbFault : public AlphaFault
-{
- protected:
- Addr pc;
-
- public:
- ItbFault(Addr _pc) : pc(_pc) { }
- FaultName name() const = 0;
- FaultVect vect() = 0;
- FaultStat & countStat() = 0;
- void invoke(ThreadContext * tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr);
-};
-
-class ItbPageFault : public ItbFault
-{
- private:
- static FaultName _name;
- static FaultVect _vect;
- static FaultStat _count;
-
- public:
- ItbPageFault(Addr pc) : ItbFault(pc) { }
- FaultName name() const {return _name;}
- FaultVect vect() {return _vect;}
- FaultStat & countStat() {return _count;}
- void invoke(ThreadContext * tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr);
-};
-
-class ItbAcvFault : public ItbFault
-{
- private:
- static FaultName _name;
- static FaultVect _vect;
- static FaultStat _count;
-
- public:
- ItbAcvFault(Addr pc) : ItbFault(pc) { }
- FaultName name() const {return _name;}
- FaultVect vect() {return _vect;}
- FaultStat & countStat() {return _count;}
-};
-
-class UnimplementedOpcodeFault : public AlphaFault
-{
- private:
- static FaultName _name;
- static FaultVect _vect;
- static FaultStat _count;
-
- public:
- FaultName name() const {return _name;}
- FaultVect vect() {return _vect;}
- FaultStat & countStat() {return _count;}
-};
-
-class FloatEnableFault : public AlphaFault
-{
- private:
- static FaultName _name;
- static FaultVect _vect;
- static FaultStat _count;
-
- public:
- FaultName name() const {return _name;}
- FaultVect vect() {return _vect;}
- FaultStat & countStat() {return _count;}
-};
-
-class VectorEnableFault : public AlphaFault
-{
- private:
- static FaultName _name;
- static FaultVect _vect;
- static FaultStat _count;
-
- public:
- FaultName name() const {return _name;}
- FaultVect vect() {return _vect;}
- FaultStat & countStat() {return _count;}
-};
-
-class PalFault : public AlphaFault
-{
- private:
- static FaultName _name;
- static FaultVect _vect;
- static FaultStat _count;
-
- protected:
- bool skipFaultingInstruction() {return true;}
-
- public:
- FaultName name() const {return _name;}
- FaultVect vect() {return _vect;}
- FaultStat & countStat() {return _count;}
-};
-
-class IntegerOverflowFault : public AlphaFault
-{
- private:
- static FaultName _name;
- static FaultVect _vect;
- static FaultStat _count;
-
- public:
- FaultName name() const {return _name;}
- FaultVect vect() {return _vect;}
- FaultStat & countStat() {return _count;}
-};
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_FAULTS_HH__
+++ /dev/null
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ben Nash
- */
-
-/**
- * @file
- * Modifications for the FreeBSD kernel.
- * Based on kern/linux/linux_system.cc.
- *
- */
-
-#include "arch/alpha/freebsd/system.hh"
-
-#include "arch/alpha/system.hh"
-#include "arch/isa_traits.hh"
-#include "arch/vtophys.hh"
-#include "base/loader/symtab.hh"
-#include "cpu/thread_context.hh"
-#include "mem/fs_translating_port_proxy.hh"
-#include "sim/byteswap.hh"
-
-#define TIMER_FREQUENCY 1193180
-
-using namespace std;
-using namespace AlphaISA;
-
-FreebsdAlphaSystem::FreebsdAlphaSystem(Params *p)
- : AlphaSystem(p)
-{
- /**
- * Any time DELAY is called just skip the function.
- * Shouldn't we actually emulate the delay?
- */
- skipDelayEvent = addKernelFuncEvent<SkipFuncEvent>("DELAY");
- skipCalibrateClocks =
- addKernelFuncEvent<SkipCalibrateClocksEvent>("calibrate_clocks");
-}
-
-FreebsdAlphaSystem::~FreebsdAlphaSystem()
-{
- delete skipDelayEvent;
- delete skipCalibrateClocks;
-}
-
-void
-FreebsdAlphaSystem::doCalibrateClocks(ThreadContext *tc)
-{
- Addr ppc_vaddr = 0;
- Addr timer_vaddr = 0;
-
- ppc_vaddr = (Addr)tc->readIntReg(17);
- timer_vaddr = (Addr)tc->readIntReg(18);
-
- virtProxy.write(ppc_vaddr, (uint32_t)SimClock::Frequency);
- virtProxy.write(timer_vaddr, (uint32_t)TIMER_FREQUENCY);
-}
-
-void
-FreebsdAlphaSystem::SkipCalibrateClocksEvent::process(ThreadContext *tc)
-{
- SkipFuncEvent::process(tc);
- ((FreebsdAlphaSystem *)tc->getSystemPtr())->doCalibrateClocks(tc);
-}
-
-FreebsdAlphaSystem *
-FreebsdAlphaSystemParams::create()
-{
- return new FreebsdAlphaSystem(this);
-}
+++ /dev/null
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ben Nash
- */
-
-#ifndef __ARCH_ALPHA_FREEBSD_SYSTEM_HH__
-#define __ARCH_ALPHA_FREEBSD_SYSTEM_HH__
-
-#include "arch/alpha/system.hh"
-#include "kern/system_events.hh"
-#include "params/FreebsdAlphaSystem.hh"
-#include "sim/system.hh"
-
-class FreebsdAlphaSystem : public AlphaSystem
-{
- private:
- class SkipCalibrateClocksEvent : public SkipFuncEvent
- {
- public:
- SkipCalibrateClocksEvent(PCEventScope *s, const std::string &desc,
- Addr addr)
- : SkipFuncEvent(s, desc, addr) {}
- virtual void process(ThreadContext *tc);
- };
-
- SkipFuncEvent *skipDelayEvent;
- SkipCalibrateClocksEvent *skipCalibrateClocks;
-
- public:
- typedef FreebsdAlphaSystemParams Params;
- FreebsdAlphaSystem(Params *p);
- ~FreebsdAlphaSystem();
-
- void doCalibrateClocks(ThreadContext *tc);
-};
-
-#endif // __ARCH_ALPHA_FREEBSD_SYSTEM_HH__
+++ /dev/null
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Lisa Hsu
- * Nathan Binkert
- */
-
-#include "arch/alpha/idle_event.hh"
-
-#include "arch/alpha/kernel_stats.hh"
-#include "cpu/thread_context.hh"
-
-using namespace AlphaISA;
-
-void
-IdleStartEvent::process(ThreadContext *tc)
-{
- if (tc->getKernelStats()) {
- RegVal val = tc->readMiscRegNoEffect(IPR_PALtemp23);
- auto *stats = dynamic_cast<AlphaISA::Kernel::Statistics *>(
- tc->getKernelStats());
- assert(stats);
- stats->setIdleProcess(val, tc);
- }
- remove();
-}
+++ /dev/null
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- * Lisa Hsu
- * Ali Saidi
- */
-
-#ifndef __KERN_ALPHA_IDLE_EVENT_HH__
-#define __KERN_ALPHA_IDLE_EVENT_HH__
-
-#include "cpu/pc_event.hh"
-
-class IdleStartEvent : public PCEvent
-{
- public:
- IdleStartEvent(PCEventScope *s, const std::string &desc, Addr addr)
- : PCEvent(s, desc, addr)
- {}
- virtual void process(ThreadContext *tc);
-};
-
-#endif // __KERN_ALPHA_IDLE_EVENT_HH__
+++ /dev/null
-/*
- * Copyright (c) 2008 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#include "arch/alpha/interrupts.hh"
-
-AlphaISA::Interrupts *
-AlphaInterruptsParams::create()
-{
- return new AlphaISA::Interrupts(this);
-}
+++ /dev/null
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- * Kevin Lim
- */
-
-#ifndef __ARCH_ALPHA_INTERRUPT_HH__
-#define __ARCH_ALPHA_INTERRUPT_HH__
-
-#include <memory>
-
-#include "arch/alpha/faults.hh"
-#include "arch/alpha/isa_traits.hh"
-#include "arch/generic/interrupts.hh"
-#include "base/compiler.hh"
-#include "base/trace.hh"
-#include "cpu/thread_context.hh"
-#include "debug/Flow.hh"
-#include "debug/Interrupt.hh"
-#include "params/AlphaInterrupts.hh"
-
-namespace AlphaISA {
-
-class Interrupts : public BaseInterrupts
-{
- private:
- bool newInfoSet;
- int newIpl;
- int newSummary;
- BaseCPU * cpu;
-
- protected:
- uint64_t interrupts[NumInterruptLevels];
- uint64_t intstatus;
-
- public:
- typedef AlphaInterruptsParams Params;
-
- const Params *
- params() const
- {
- return dynamic_cast<const Params *>(_params);
- }
-
- Interrupts(Params * p) : BaseInterrupts(p), cpu(NULL)
- {
- memset(interrupts, 0, sizeof(interrupts));
- intstatus = 0;
- newInfoSet = false;
- }
-
- void
- setCPU(BaseCPU * _cpu)
- {
- cpu = _cpu;
- }
-
- void
- post(int int_num, int index)
- {
- DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
-
- if (int_num < 0 || int_num >= NumInterruptLevels)
- panic("int_num out of bounds\n");
-
- if (index < 0 || index >= (int)sizeof(uint64_t) * 8)
- panic("int_num out of bounds\n");
-
- interrupts[int_num] |= 1 << index;
- intstatus |= (ULL(1) << int_num);
- }
-
- void
- clear(int int_num, int index)
- {
- DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
-
- if (int_num < 0 || int_num >= NumInterruptLevels)
- panic("int_num out of bounds\n");
-
- if (index < 0 || index >= (int)sizeof(uint64_t) * 8)
- panic("int_num out of bounds\n");
-
- interrupts[int_num] &= ~(1 << index);
- if (interrupts[int_num] == 0)
- intstatus &= ~(ULL(1) << int_num);
- }
-
- void
- clearAll()
- {
- DPRINTF(Interrupt, "Interrupts all cleared\n");
-
- memset(interrupts, 0, sizeof(interrupts));
- intstatus = 0;
- }
-
- void
- serialize(CheckpointOut &cp) const
- {
- SERIALIZE_ARRAY(interrupts, NumInterruptLevels);
- SERIALIZE_SCALAR(intstatus);
- }
-
- void
- unserialize(CheckpointIn &cp)
- {
- UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels);
- UNSERIALIZE_SCALAR(intstatus);
- }
-
- bool
- checkInterrupts(ThreadContext *tc) const
- {
- if (intstatus == 0)
- return false;
-
- if (tc->pcState().pc() & 0x3)
- return false;
-
- if (tc->readMiscRegNoEffect(IPR_ASTRR))
- panic("asynchronous traps not implemented\n");
-
- uint64_t ipl = 0;
- uint64_t summary = 0;
-
- if (tc->readMiscRegNoEffect(IPR_SIRR)) {
- for (uint64_t i = INTLEVEL_SOFTWARE_MIN;
- i < INTLEVEL_SOFTWARE_MAX; i++) {
- if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
- // See table 4-19 of 21164 hardware reference
- ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
- summary |= (ULL(1) << i);
- }
- }
- }
-
- for (uint64_t i = INTLEVEL_EXTERNAL_MIN; i < INTLEVEL_EXTERNAL_MAX;
- i++) {
- if (intstatus & (ULL(1) << i)) {
- // See table 4-19 of 21164 hardware reference
- ipl = i;
- summary |= (ULL(1) << i);
- }
- }
-
- return ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR);
- }
-
- Fault
- getInterrupt(ThreadContext *tc)
- {
- assert(checkInterrupts(tc));
-
- uint64_t ipl = 0;
- uint64_t summary = 0;
- if (tc->readMiscRegNoEffect(IPR_SIRR)) {
- for (uint64_t i = INTLEVEL_SOFTWARE_MIN;
- i < INTLEVEL_SOFTWARE_MAX; i++) {
- if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
- // See table 4-19 of 21164 hardware reference
- ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
- summary |= (ULL(1) << i);
- }
- }
- }
-
- for (uint64_t i = INTLEVEL_EXTERNAL_MIN; i < INTLEVEL_EXTERNAL_MAX;
- i++) {
- if (intstatus & (ULL(1) << i)) {
- // See table 4-19 of 21164 hardware reference
- ipl = i;
- summary |= (ULL(1) << i);
- }
- }
-
- newIpl = ipl;
- newSummary = summary;
- newInfoSet = true;
- DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
- tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
-
- return std::make_shared<InterruptFault>();
- }
-
- void
- updateIntrInfo(ThreadContext *tc)
- {
- assert(newInfoSet);
- tc->setMiscRegNoEffect(IPR_ISR, newSummary);
- tc->setMiscRegNoEffect(IPR_INTID, newIpl);
- newInfoSet = false;
- }
-};
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_INTERRUPT_HH__
-
+++ /dev/null
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#include "arch/alpha/ipr.hh"
-
-#include <cassert>
-#include <cstring>
-
-namespace AlphaISA {
-
-md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs] = {
-
- //Write only
- RAW_IPR_HWINT_CLR, // H/W interrupt clear register
- RAW_IPR_SL_XMIT, // serial line transmit register
- RAW_IPR_DC_FLUSH,
- RAW_IPR_IC_FLUSH, // instruction cache flush control
- RAW_IPR_ALT_MODE, // alternate mode register
- RAW_IPR_DTB_IA, // DTLB invalidate all register
- RAW_IPR_DTB_IAP, // DTLB invalidate all process register
- RAW_IPR_ITB_IA, // ITLB invalidate all register
- RAW_IPR_ITB_IAP, // ITLB invalidate all process register
-
- //Read only
- RAW_IPR_INTID, // interrupt ID register
- RAW_IPR_SL_RCV, // serial line receive register
- RAW_IPR_MM_STAT, // data MMU fault status register
- RAW_IPR_ITB_PTE_TEMP, // ITLB page table entry temp register
- RAW_IPR_DTB_PTE_TEMP, // DTLB page table entry temporary register
-
- RAW_IPR_ISR, // interrupt summary register
- RAW_IPR_ITB_TAG, // ITLB tag register
- RAW_IPR_ITB_PTE, // ITLB page table entry register
- RAW_IPR_ITB_ASN, // ITLB address space register
- RAW_IPR_ITB_IS, // ITLB invalidate select register
- RAW_IPR_SIRR, // software interrupt request register
- RAW_IPR_ASTRR, // asynchronous system trap request register
- RAW_IPR_ASTER, // asynchronous system trap enable register
- RAW_IPR_EXC_ADDR, // exception address register
- RAW_IPR_EXC_SUM, // exception summary register
- RAW_IPR_EXC_MASK, // exception mask register
- RAW_IPR_PAL_BASE, // PAL base address register
- RAW_IPR_ICM, // instruction current mode
- RAW_IPR_IPLR, // interrupt priority level register
- RAW_IPR_IFAULT_VA_FORM, // formatted faulting virtual addr register
- RAW_IPR_IVPTBR, // virtual page table base register
- RAW_IPR_ICSR, // instruction control and status register
- RAW_IPR_IC_PERR_STAT, // inst cache parity error status register
- RAW_IPR_PMCTR, // performance counter register
-
- // PAL temporary registers...
- // register meanings gleaned from osfpal.s source code
- RAW_IPR_PALtemp0, // local scratch
- RAW_IPR_PALtemp1, // local scratch
- RAW_IPR_PALtemp2, // entUna
- RAW_IPR_PALtemp3, // CPU specific impure area pointer
- RAW_IPR_PALtemp4, // memory management temp
- RAW_IPR_PALtemp5, // memory management temp
- RAW_IPR_PALtemp6, // memory management temp
- RAW_IPR_PALtemp7, // entIF
- RAW_IPR_PALtemp8, // intmask
- RAW_IPR_PALtemp9, // entSys
- RAW_IPR_PALtemp10, // ??
- RAW_IPR_PALtemp11, // entInt
- RAW_IPR_PALtemp12, // entArith
- RAW_IPR_PALtemp13, // reserved for platform specific PAL
- RAW_IPR_PALtemp14, // reserved for platform specific PAL
- RAW_IPR_PALtemp15, // reserved for platform specific PAL
- RAW_IPR_PALtemp16, // scratch / whami<7:0> / mces<4:0>
- RAW_IPR_PALtemp17, // sysval
- RAW_IPR_PALtemp18, // usp
- RAW_IPR_PALtemp19, // ksp
- RAW_IPR_PALtemp20, // PTBR
- RAW_IPR_PALtemp21, // entMM
- RAW_IPR_PALtemp22, // kgp
- RAW_IPR_PALtemp23, // PCBB
-
- RAW_IPR_DTB_ASN, // DTLB address space number register
- RAW_IPR_DTB_CM, // DTLB current mode register
- RAW_IPR_DTB_TAG, // DTLB tag register
- RAW_IPR_DTB_PTE, // DTLB page table entry register
-
- RAW_IPR_VA, // fault virtual address register
- RAW_IPR_VA_FORM, // formatted virtual address register
- RAW_IPR_MVPTBR, // MTU virtual page table base register
- RAW_IPR_DTB_IS, // DTLB invalidate single register
- RAW_IPR_CC, // cycle counter register
- RAW_IPR_CC_CTL, // cycle counter control register
- RAW_IPR_MCSR, // MTU control register
-
- RAW_IPR_DC_PERR_STAT, // Dcache parity error status register
- RAW_IPR_DC_TEST_CTL, // Dcache test tag control register
- RAW_IPR_DC_TEST_TAG, // Dcache test tag register
- RAW_IPR_DC_TEST_TAG_TEMP, // Dcache test tag temporary register
- RAW_IPR_DC_MODE, // Dcache mode register
- RAW_IPR_MAF_MODE // miss address file mode register
-};
-
-int IprToMiscRegIndex[MaxInternalProcRegs];
-
-void
-initializeIprTable()
-{
- static bool initialized = false;
- if (initialized)
- return;
-
- memset(IprToMiscRegIndex, -1, MaxInternalProcRegs * sizeof(int));
-
- for (int x = 0; x < NumInternalProcRegs; x++)
- IprToMiscRegIndex[MiscRegIndexToIpr[x]] = x;
-}
-
-} // namespace AlphaISA
-
+++ /dev/null
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- * Gabe Black
- */
-
-#ifndef __ARCH_ALPHA_IPR_HH__
-#define __ARCH_ALPHA_IPR_HH__
-
-namespace AlphaISA {
-
-////////////////////////////////////////////////////////////////////////
-//
-// Internal Processor Reigsters
-//
-enum md_ipr_names {
- RAW_IPR_ISR = 0x100, // interrupt summary
- RAW_IPR_ITB_TAG = 0x101, // ITLB tag
- RAW_IPR_ITB_PTE = 0x102, // ITLB page table entry
- RAW_IPR_ITB_ASN = 0x103, // ITLB address space
- RAW_IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp
- RAW_IPR_ITB_IA = 0x105, // ITLB invalidate all
- RAW_IPR_ITB_IAP = 0x106, // ITLB invalidate all process
- RAW_IPR_ITB_IS = 0x107, // ITLB invalidate select
- RAW_IPR_SIRR = 0x108, // software interrupt request
- RAW_IPR_ASTRR = 0x109, // asynchronous system trap request
- RAW_IPR_ASTER = 0x10a, // asynchronous system trap enable
- RAW_IPR_EXC_ADDR = 0x10b, // exception address
- RAW_IPR_EXC_SUM = 0x10c, // exception summary
- RAW_IPR_EXC_MASK = 0x10d, // exception mask
- RAW_IPR_PAL_BASE = 0x10e, // PAL base address
- RAW_IPR_ICM = 0x10f, // instruction current mode
- RAW_IPR_IPLR = 0x110, // interrupt priority level
- RAW_IPR_INTID = 0x111, // interrupt ID
- RAW_IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr
- RAW_IPR_IVPTBR = 0x113, // virtual page table base
- RAW_IPR_HWINT_CLR = 0x115, // H/W interrupt clear
- RAW_IPR_SL_XMIT = 0x116, // serial line transmit
- RAW_IPR_SL_RCV = 0x117, // serial line receive
- RAW_IPR_ICSR = 0x118, // instruction control and status
- RAW_IPR_IC_FLUSH = 0x119, // instruction cache flush control
- RAW_IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status
- RAW_IPR_PMCTR = 0x11c, // performance counter
-
- // PAL temporary registers...
- // register meanings gleaned from osfpal.s source code
- RAW_IPR_PALtemp0 = 0x140, // local scratch
- RAW_IPR_PALtemp1 = 0x141, // local scratch
- RAW_IPR_PALtemp2 = 0x142, // entUna
- RAW_IPR_PALtemp3 = 0x143, // CPU specific impure area pointer
- RAW_IPR_PALtemp4 = 0x144, // memory management temp
- RAW_IPR_PALtemp5 = 0x145, // memory management temp
- RAW_IPR_PALtemp6 = 0x146, // memory management temp
- RAW_IPR_PALtemp7 = 0x147, // entIF
- RAW_IPR_PALtemp8 = 0x148, // intmask
- RAW_IPR_PALtemp9 = 0x149, // entSys
- RAW_IPR_PALtemp10 = 0x14a, // ??
- RAW_IPR_PALtemp11 = 0x14b, // entInt
- RAW_IPR_PALtemp12 = 0x14c, // entArith
- RAW_IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL
- RAW_IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL
- RAW_IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL
- RAW_IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0>
- RAW_IPR_PALtemp17 = 0x151, // sysval
- RAW_IPR_PALtemp18 = 0x152, // usp
- RAW_IPR_PALtemp19 = 0x153, // ksp
- RAW_IPR_PALtemp20 = 0x154, // PTBR
- RAW_IPR_PALtemp21 = 0x155, // entMM
- RAW_IPR_PALtemp22 = 0x156, // kgp
- RAW_IPR_PALtemp23 = 0x157, // PCBB
-
- RAW_IPR_DTB_ASN = 0x200, // DTLB address space number
- RAW_IPR_DTB_CM = 0x201, // DTLB current mode
- RAW_IPR_DTB_TAG = 0x202, // DTLB tag
- RAW_IPR_DTB_PTE = 0x203, // DTLB page table entry
- RAW_IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary
-
- RAW_IPR_MM_STAT = 0x205, // data MMU fault status
- RAW_IPR_VA = 0x206, // fault virtual address
- RAW_IPR_VA_FORM = 0x207, // formatted virtual address
- RAW_IPR_MVPTBR = 0x208, // MTU virtual page table base
- RAW_IPR_DTB_IAP = 0x209, // DTLB invalidate all process
- RAW_IPR_DTB_IA = 0x20a, // DTLB invalidate all
- RAW_IPR_DTB_IS = 0x20b, // DTLB invalidate single
- RAW_IPR_ALT_MODE = 0x20c, // alternate mode
- RAW_IPR_CC = 0x20d, // cycle counter
- RAW_IPR_CC_CTL = 0x20e, // cycle counter control
- RAW_IPR_MCSR = 0x20f, // MTU control
-
- RAW_IPR_DC_FLUSH = 0x210,
- RAW_IPR_DC_PERR_STAT = 0x212, // Dcache parity error status
- RAW_IPR_DC_TEST_CTL = 0x213, // Dcache test tag control
- RAW_IPR_DC_TEST_TAG = 0x214, // Dcache test tag
- RAW_IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary
- RAW_IPR_DC_MODE = 0x216, // Dcache mode
- RAW_IPR_MAF_MODE = 0x217, // miss address file mode
-
- MaxInternalProcRegs // number of IPRs
-};
-
-enum MiscRegIpr
-{
- //Write only
- MinWriteOnlyIpr,
- IPR_HWINT_CLR = MinWriteOnlyIpr,
- IPR_SL_XMIT,
- IPR_DC_FLUSH,
- IPR_IC_FLUSH,
- IPR_ALT_MODE,
- IPR_DTB_IA,
- IPR_DTB_IAP,
- IPR_ITB_IA,
- MaxWriteOnlyIpr,
- IPR_ITB_IAP = MaxWriteOnlyIpr,
-
- //Read only
- MinReadOnlyIpr,
- IPR_INTID = MinReadOnlyIpr,
- IPR_SL_RCV,
- IPR_MM_STAT,
- IPR_ITB_PTE_TEMP,
- MaxReadOnlyIpr,
- IPR_DTB_PTE_TEMP = MaxReadOnlyIpr,
-
- IPR_ISR,
- IPR_ITB_TAG,
- IPR_ITB_PTE,
- IPR_ITB_ASN,
- IPR_ITB_IS,
- IPR_SIRR,
- IPR_ASTRR,
- IPR_ASTER,
- IPR_EXC_ADDR,
- IPR_EXC_SUM,
- IPR_EXC_MASK,
- IPR_PAL_BASE,
- IPR_ICM,
- IPR_IPLR,
- IPR_IFAULT_VA_FORM,
- IPR_IVPTBR,
- IPR_ICSR,
- IPR_IC_PERR_STAT,
- IPR_PMCTR,
-
- // PAL temporary registers...
- // register meanings gleaned from osfpal.s source code
- IPR_PALtemp0,
- IPR_PALtemp1,
- IPR_PALtemp2,
- IPR_PALtemp3,
- IPR_PALtemp4,
- IPR_PALtemp5,
- IPR_PALtemp6,
- IPR_PALtemp7,
- IPR_PALtemp8,
- IPR_PALtemp9,
- IPR_PALtemp10,
- IPR_PALtemp11,
- IPR_PALtemp12,
- IPR_PALtemp13,
- IPR_PALtemp14,
- IPR_PALtemp15,
- IPR_PALtemp16,
- IPR_PALtemp17,
- IPR_PALtemp18,
- IPR_PALtemp19,
- IPR_PALtemp20,
- IPR_PALtemp21,
- IPR_PALtemp22,
- IPR_PALtemp23,
-
- IPR_DTB_ASN,
- IPR_DTB_CM,
- IPR_DTB_TAG,
- IPR_DTB_PTE,
-
- IPR_VA,
- IPR_VA_FORM,
- IPR_MVPTBR,
- IPR_DTB_IS,
- IPR_CC,
- IPR_CC_CTL,
- IPR_MCSR,
-
- IPR_DC_PERR_STAT,
- IPR_DC_TEST_CTL,
- IPR_DC_TEST_TAG,
- IPR_DC_TEST_TAG_TEMP,
- IPR_DC_MODE,
- IPR_MAF_MODE,
-
- NumInternalProcRegs // number of IPR registers
-};
-
-inline bool
-IprIsWritable(int index)
-{
- return index < MinReadOnlyIpr || index > MaxReadOnlyIpr;
-}
-
-inline bool
-IprIsReadable(int index)
-{
- return index < MinWriteOnlyIpr || index > MaxWriteOnlyIpr;
-}
-
-extern md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs];
-extern int IprToMiscRegIndex[MaxInternalProcRegs];
-
-void initializeIprTable();
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_IPR_HH__
+++ /dev/null
-/*
- * Copyright (c) 2009 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#include "arch/alpha/isa.hh"
-
-#include <cassert>
-
-#include "base/logging.hh"
-#include "cpu/thread_context.hh"
-#include "params/AlphaISA.hh"
-#include "sim/serialize.hh"
-
-namespace AlphaISA
-{
-
-ISA::ISA(Params *p) : BaseISA(p), system(p->system)
-{
- clear();
- initializeIprTable();
-}
-
-const AlphaISAParams *
-ISA::params() const
-{
- return dynamic_cast<const Params *>(_params);
-}
-
-void
-ISA::serialize(CheckpointOut &cp) const
-{
- SERIALIZE_SCALAR(fpcr);
- SERIALIZE_SCALAR(uniq);
- SERIALIZE_SCALAR(lock_flag);
- SERIALIZE_SCALAR(lock_addr);
- SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
-}
-
-void
-ISA::unserialize(CheckpointIn &cp)
-{
- UNSERIALIZE_SCALAR(fpcr);
- UNSERIALIZE_SCALAR(uniq);
- UNSERIALIZE_SCALAR(lock_flag);
- UNSERIALIZE_SCALAR(lock_addr);
- UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
-}
-
-
-RegVal
-ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
-{
- switch (misc_reg) {
- case MISCREG_FPCR:
- return fpcr;
- case MISCREG_UNIQ:
- return uniq;
- case MISCREG_LOCKFLAG:
- return lock_flag;
- case MISCREG_LOCKADDR:
- return lock_addr;
- case MISCREG_INTR:
- return intr_flag;
- default:
- assert(misc_reg < NumInternalProcRegs);
- return ipr[misc_reg];
- }
-}
-
-RegVal
-ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
-{
- switch (misc_reg) {
- case MISCREG_FPCR:
- return fpcr;
- case MISCREG_UNIQ:
- return uniq;
- case MISCREG_LOCKFLAG:
- return lock_flag;
- case MISCREG_LOCKADDR:
- return lock_addr;
- case MISCREG_INTR:
- return intr_flag;
- default:
- return readIpr(misc_reg, tc);
- }
-}
-
-void
-ISA::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
-{
- switch (misc_reg) {
- case MISCREG_FPCR:
- fpcr = val;
- return;
- case MISCREG_UNIQ:
- uniq = val;
- return;
- case MISCREG_LOCKFLAG:
- lock_flag = val;
- return;
- case MISCREG_LOCKADDR:
- lock_addr = val;
- return;
- case MISCREG_INTR:
- intr_flag = val;
- return;
- default:
- assert(misc_reg < NumInternalProcRegs);
- ipr[misc_reg] = val;
- return;
- }
-}
-
-void
-ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid)
-{
- switch (misc_reg) {
- case MISCREG_FPCR:
- fpcr = val;
- return;
- case MISCREG_UNIQ:
- uniq = val;
- return;
- case MISCREG_LOCKFLAG:
- lock_flag = val;
- return;
- case MISCREG_LOCKADDR:
- lock_addr = val;
- return;
- case MISCREG_INTR:
- intr_flag = val;
- return;
- default:
- setIpr(misc_reg, val, tc);
- return;
- }
-}
-
-}
-
-AlphaISA::ISA *
-AlphaISAParams::create()
-{
- return new AlphaISA::ISA(this);
-}
+++ /dev/null
-/*
- * Copyright (c) 2009 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#ifndef __ARCH_ALPHA_ISA_HH__
-#define __ARCH_ALPHA_ISA_HH__
-
-#include <cstring>
-#include <iostream>
-#include <string>
-
-#include "arch/alpha/registers.hh"
-#include "arch/alpha/types.hh"
-#include "arch/generic/isa.hh"
-#include "base/types.hh"
-#include "cpu/reg_class.hh"
-#include "sim/sim_object.hh"
-#include "sim/system.hh"
-
-struct AlphaISAParams;
-class BaseCPU;
-class Checkpoint;
-class EventManager;
-class ThreadContext;
-
-namespace AlphaISA
-{
- class ISA : public BaseISA
- {
- public:
- typedef uint64_t InternalProcReg;
- typedef AlphaISAParams Params;
-
- protected:
- // Parent system
- System *system;
-
- uint64_t fpcr; // floating point condition codes
- uint64_t uniq; // process-unique register
- bool lock_flag; // lock flag for LL/SC
- Addr lock_addr; // lock address for LL/SC
- int intr_flag;
-
- InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
-
- protected:
- InternalProcReg readIpr(int idx, ThreadContext *tc);
- void setIpr(int idx, InternalProcReg val, ThreadContext *tc);
-
- public:
-
- RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
- RegVal readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
-
- void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0);
- void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc,
- ThreadID tid=0);
-
- void
- clear()
- {
- fpcr = 0;
- uniq = 0;
- lock_flag = 0;
- lock_addr = 0;
- intr_flag = 0;
- memset(ipr, 0, sizeof(ipr));
- }
-
- void serialize(CheckpointOut &cp) const override;
- void unserialize(CheckpointIn &cp) override;
-
- RegId flattenRegId(const RegId& regId) const { return regId; }
-
- int
- flattenIntIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenFloatIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenVecIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenVecElemIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenVecPredIndex(int reg) const
- {
- return reg;
- }
-
- // dummy
- int
- flattenCCIndex(int reg) const
- {
- return reg;
- }
-
- int
- flattenMiscIndex(int reg) const
- {
- return reg;
- }
-
- const Params *params() const;
-
- ISA(Params *p);
-
- void startup(ThreadContext *tc) {}
-
- /// Explicitly import the otherwise hidden startup
- using BaseISA::startup;
- };
-}
-
-#endif
+++ /dev/null
-// -*- mode:c++ -*-
-
-// Copyright (c) 2003-2005 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Steve Reinhardt
-
-////////////////////////////////////////////////////////////////////
-//
-// Control transfer instructions
-//
-
-output header {{
-
- /**
- * Base class for instructions whose disassembly is not purely a
- * function of the machine instruction (i.e., it depends on the
- * PC). This class overrides the disassemble() method to check
- * the PC and symbol table values before re-using a cached
- * disassembly string. This is necessary for branches and jumps,
- * where the disassembly string includes the target address (which
- * may depend on the PC and/or symbol table).
- */
- class PCDependentDisassembly : public AlphaStaticInst
- {
- protected:
- /// Cached program counter from last disassembly
- mutable Addr cachedPC;
- /// Cached symbol table pointer from last disassembly
- mutable const SymbolTable *cachedSymtab;
-
- /// Constructor
- PCDependentDisassembly(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass)
- : AlphaStaticInst(mnem, _machInst, __opClass),
- cachedPC(0), cachedSymtab(0)
- {
- }
-
- const std::string &
- disassemble(Addr pc, const SymbolTable *symtab) const;
- };
-
- /**
- * Base class for branches (PC-relative control transfers),
- * conditional or unconditional.
- */
- class Branch : public PCDependentDisassembly
- {
- protected:
- /// Displacement to target address (signed).
- int32_t disp;
-
- /// Constructor.
- Branch(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
- : PCDependentDisassembly(mnem, _machInst, __opClass),
- disp(BRDISP << 2)
- {
- }
-
- AlphaISA::PCState branchTarget(
- const AlphaISA::PCState &branchPC) const override;
-
- /// Explicitly import the otherwise hidden branchTarget
- using StaticInst::branchTarget;
-
- std::string generateDisassembly(
- Addr pc, const SymbolTable *symtab) const override;
- };
-
- /**
- * Base class for jumps (register-indirect control transfers). In
- * the Alpha ISA, these are always unconditional.
- */
- class Jump : public PCDependentDisassembly
- {
- protected:
-
- /// Displacement to target address (signed).
- int32_t disp;
-
- public:
- /// Constructor
- Jump(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
- : PCDependentDisassembly(mnem, _machInst, __opClass),
- disp(BRDISP)
- {
- }
-
- AlphaISA::PCState branchTarget(ThreadContext *tc) const override;
-
- /// Explicitly import the otherwise hidden branchTarget
- using StaticInst::branchTarget;
-
- std::string generateDisassembly(
- Addr pc, const SymbolTable *symtab) const override;
- };
-}};
-
-output decoder {{
- AlphaISA::PCState
- Branch::branchTarget(const AlphaISA::PCState &branchPC) const
- {
- return branchPC.pc() + 4 + disp;
- }
-
- AlphaISA::PCState
- Jump::branchTarget(ThreadContext *tc) const
- {
- PCState pc = tc->pcState();
- uint64_t Rb = tc->readIntReg(_srcRegIdx[0].index());
- pc.set((Rb & ~3) | (pc.pc() & 1));
- return pc;
- }
-
- const std::string &
- PCDependentDisassembly::disassemble(Addr pc,
- const SymbolTable *symtab) const
- {
- if (!cachedDisassembly ||
- pc != cachedPC || symtab != cachedSymtab)
- {
- if (cachedDisassembly)
- delete cachedDisassembly;
-
- cachedDisassembly =
- new std::string(generateDisassembly(pc, symtab));
- cachedPC = pc;
- cachedSymtab = symtab;
- }
-
- return *cachedDisassembly;
- }
-
- std::string
- Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- std::stringstream ss;
-
- ccprintf(ss, "%-10s ", mnemonic);
-
- // There's only one register arg (RA), but it could be
- // either a source (the condition for conditional
- // branches) or a destination (the link reg for
- // unconditional branches)
- if (_numSrcRegs > 0) {
- printReg(ss, _srcRegIdx[0]);
- ss << ",";
- }
- else if (_numDestRegs > 0) {
- printReg(ss, _destRegIdx[0]);
- ss << ",";
- }
-
- Addr target = pc + 4 + disp;
-
- std::string str;
- if (symtab && symtab->findSymbol(target, str))
- ss << str;
- else
- ccprintf(ss, "0x%x", target);
-
- return ss.str();
- }
-
- std::string
- Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- std::stringstream ss;
-
- ccprintf(ss, "%-10s ", mnemonic);
-
- if (_numDestRegs > 0) {
- printReg(ss, _destRegIdx[0]);
- ss << ",";
- }
-
- ccprintf(ss, "(r%d)", RB);
-
- return ss.str();
- }
-}};
-
-def template JumpOrBranchDecode {{
- return (RA == 31)
- ? (StaticInst *)new %(class_name)s(machInst)
- : (StaticInst *)new %(class_name)sAndLink(machInst);
-}};
-
-def format CondBranch(code) {{
- code = '''
- bool cond;
- %(code)s;
- if (cond)
- NPC = NPC + disp;
- else
- NPC = NPC;
- ''' % { "code" : code }
- iop = InstObjParams(name, Name, 'Branch', code,
- ('IsDirectControl', 'IsCondControl'))
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
-}};
-
-let {{
-def UncondCtrlBase(name, Name, base_class, npc_expr, flags):
- # Declare basic control transfer w/o link (i.e. link reg is R31)
- nolink_code = 'NPC = %s;\n' % npc_expr
- nolink_iop = InstObjParams(name, Name, base_class,
- nolink_code, flags)
- header_output = BasicDeclare.subst(nolink_iop)
- decoder_output = BasicConstructor.subst(nolink_iop)
- exec_output = BasicExecute.subst(nolink_iop)
-
- # Generate declaration of '*AndLink' version, append to decls
- link_code = 'Ra = NPC & ~3;\n' + nolink_code
- link_iop = InstObjParams(name, Name + 'AndLink', base_class,
- link_code, flags)
- header_output += BasicDeclare.subst(link_iop)
- decoder_output += BasicConstructor.subst(link_iop)
- exec_output += BasicExecute.subst(link_iop)
-
- # need to use link_iop for the decode template since it is expecting
- # the shorter version of class_name (w/o "AndLink")
-
- return (header_output, decoder_output,
- JumpOrBranchDecode.subst(nolink_iop), exec_output)
-}};
-
-def format UncondBranch(*flags) {{
- flags += ('IsUncondControl', 'IsDirectControl')
- (header_output, decoder_output, decode_block, exec_output) = \
- UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags)
-}};
-
-def format Jump(*flags) {{
- flags += ('IsUncondControl', 'IsIndirectControl')
- (header_output, decoder_output, decode_block, exec_output) = \
- UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags)
-}};
-
-
+++ /dev/null
-// -*- mode:c++ -*-
-
-// Copyright (c) 2013 ARM Limited
-// All rights reserved
-//
-// The license below extends only to copyright in the software and shall
-// not be construed as granting a license to any other intellectual
-// property including but not limited to intellectual property relating
-// to a hardware implementation of the functionality of the software
-// licensed hereunder. You may use the software subject to the license
-// terms below provided that you ensure that this notice is replicated
-// unmodified and in its entirety in all distributions of the software,
-// modified or unmodified, in source code or in binary form.
-//
-// Copyright (c) 2003-2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Steve Reinhardt
-
-////////////////////////////////////////////////////////////////////
-//
-// The actual decoder specification
-//
-
-decode OPCODE default Unknown::unknown() {
-
- format LoadAddress {
- 0x08: lda({{ Ra = Rb + disp; }});
- 0x09: ldah({{ Ra = Rb + (disp << 16); }});
- }
-
- format LoadOrNop {
- 0x0a: ldbu({{ Ra_uq = Mem_ub; }});
- 0x0c: ldwu({{ Ra_uq = Mem_uw; }});
- 0x0b: ldq_u({{ Ra = Mem_uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
- 0x23: ldt({{ Fa = Mem_df; }});
- 0x2a: ldl_l({{ Ra_sl = Mem_sl; }}, mem_flags = LLSC);
- 0x2b: ldq_l({{ Ra_uq = Mem_uq; }}, mem_flags = LLSC);
- }
-
- format LoadOrPrefetch {
- 0x28: ldl({{ Ra_sl = Mem_sl; }});
- 0x29: ldq({{ Ra_uq = Mem_uq; }}, pf_flags = EVICT_NEXT);
- // IsFloating flag on lds gets the prefetch to disassemble
- // using f31 instead of r31... funcitonally it's unnecessary
- 0x22: lds({{ Fa_uq = s_to_t(Mem_ul); }},
- pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating);
- }
-
- format Store {
- 0x0e: stb({{ Mem_ub = Ra<7:0>; }});
- 0x0d: stw({{ Mem_uw = Ra<15:0>; }});
- 0x2c: stl({{ Mem_ul = Ra<31:0>; }});
- 0x2d: stq({{ Mem_uq = Ra_uq; }});
- 0x0f: stq_u({{ Mem_uq = Ra_uq; }}, {{ EA = (Rb + disp) & ~7; }});
- 0x26: sts({{ Mem_ul = t_to_s(Fa_uq); }});
- 0x27: stt({{ Mem_df = Fa; }});
- }
-
- format StoreCond {
- 0x2e: stl_c({{ Mem_ul = Ra<31:0>; }},
- {{
- uint64_t tmp = write_result;
- // see stq_c
- Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
- if (tmp == 1) {
- xc->setStCondFailures(0);
- }
- }}, mem_flags = LLSC, inst_flags = IsStoreConditional);
- 0x2f: stq_c({{ Mem_uq = Ra; }},
- {{
- uint64_t tmp = write_result;
- // If the write operation returns 0 or 1, then
- // this was a conventional store conditional,
- // and the value indicates the success/failure
- // of the operation. If another value is
- // returned, then this was a Turbolaser
- // mailbox access, and we don't update the
- // result register at all.
- Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
- if (tmp == 1) {
- // clear failure counter... this is
- // non-architectural and for debugging
- // only.
- xc->setStCondFailures(0);
- }
- }}, mem_flags = LLSC, inst_flags = IsStoreConditional);
- }
-
- format IntegerOperate {
-
- 0x10: decode INTFUNC { // integer arithmetic operations
-
- 0x00: addl({{ Rc_sl = Ra_sl + Rb_or_imm_sl; }});
- 0x40: addlv({{
- int32_t tmp = Ra_sl + Rb_or_imm_sl;
- // signed overflow occurs when operands have same sign
- // and sign of result does not match.
- if (Ra_sl<31:> == Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>)
- fault = std::make_shared<IntegerOverflowFault>();
- Rc_sl = tmp;
- }});
- 0x02: s4addl({{ Rc_sl = (Ra_sl << 2) + Rb_or_imm_sl; }});
- 0x12: s8addl({{ Rc_sl = (Ra_sl << 3) + Rb_or_imm_sl; }});
-
- 0x20: addq({{ Rc = Ra + Rb_or_imm; }});
- 0x60: addqv({{
- uint64_t tmp = Ra + Rb_or_imm;
- // signed overflow occurs when operands have same sign
- // and sign of result does not match.
- if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
- fault = std::make_shared<IntegerOverflowFault>();
- Rc = tmp;
- }});
- 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
- 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }});
-
- 0x09: subl({{ Rc_sl = Ra_sl - Rb_or_imm_sl; }});
- 0x49: sublv({{
- int32_t tmp = Ra_sl - Rb_or_imm_sl;
- // signed overflow detection is same as for add,
- // except we need to look at the *complemented*
- // sign bit of the subtrahend (Rb), i.e., if the initial
- // signs are the *same* then no overflow can occur
- if (Ra_sl<31:> != Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>)
- fault = std::make_shared<IntegerOverflowFault>();
- Rc_sl = tmp;
- }});
- 0x0b: s4subl({{ Rc_sl = (Ra_sl << 2) - Rb_or_imm_sl; }});
- 0x1b: s8subl({{ Rc_sl = (Ra_sl << 3) - Rb_or_imm_sl; }});
-
- 0x29: subq({{ Rc = Ra - Rb_or_imm; }});
- 0x69: subqv({{
- uint64_t tmp = Ra - Rb_or_imm;
- // signed overflow detection is same as for add,
- // except we need to look at the *complemented*
- // sign bit of the subtrahend (Rb), i.e., if the initial
- // signs are the *same* then no overflow can occur
- if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
- fault = std::make_shared<IntegerOverflowFault>();
- Rc = tmp;
- }});
- 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
- 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }});
-
- 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }});
- 0x6d: cmple({{ Rc = (Ra_sq <= Rb_or_imm_sq); }});
- 0x4d: cmplt({{ Rc = (Ra_sq < Rb_or_imm_sq); }});
- 0x3d: cmpule({{ Rc = (Ra_uq <= Rb_or_imm_uq); }});
- 0x1d: cmpult({{ Rc = (Ra_uq < Rb_or_imm_uq); }});
-
- 0x0f: cmpbge({{
- int hi = 7;
- int lo = 0;
- uint64_t tmp = 0;
- for (int i = 0; i < 8; ++i) {
- tmp |= (Ra_uq<hi:lo> >= Rb_or_imm_uq<hi:lo>) << i;
- hi += 8;
- lo += 8;
- }
- Rc = tmp;
- }});
- }
-
- 0x11: decode INTFUNC { // integer logical operations
-
- 0x00: and({{ Rc = Ra & Rb_or_imm; }});
- 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }});
- 0x20: bis({{ Rc = Ra | Rb_or_imm; }});
- 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }});
- 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }});
- 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }});
-
- // conditional moves
- 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }});
- 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }});
- 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }});
- 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }});
- 0x44: cmovlt({{ Rc = (Ra_sq < 0) ? Rb_or_imm : Rc; }});
- 0x46: cmovge({{ Rc = (Ra_sq >= 0) ? Rb_or_imm : Rc; }});
- 0x64: cmovle({{ Rc = (Ra_sq <= 0) ? Rb_or_imm : Rc; }});
- 0x66: cmovgt({{ Rc = (Ra_sq > 0) ? Rb_or_imm : Rc; }});
-
- // For AMASK, RA must be R31.
- 0x61: decode RA {
- 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }});
- }
-
- // For IMPLVER, RA must be R31 and the B operand
- // must be the immediate value 1.
- 0x6c: decode RA {
- 31: decode IMM {
- 1: decode INTIMM {
- // return EV5 for FullSystem and EV6 otherwise
- 1: implver({{ Rc = FullSystem ? 1 : 2 }});
- }
- }
- }
-
- // The mysterious 11.25...
- 0x25: WarnUnimpl::eleven25();
- }
-
- 0x12: decode INTFUNC {
- 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }});
- 0x34: srl({{ Rc = Ra_uq >> Rb_or_imm<5:0>; }});
- 0x3c: sra({{ Rc = Ra_sq >> Rb_or_imm<5:0>; }});
-
- 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }});
- 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }});
- 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }});
- 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }});
-
- 0x52: mskwh({{
- int bv = Rb_or_imm<2:0>;
- Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra;
- }});
- 0x62: msklh({{
- int bv = Rb_or_imm<2:0>;
- Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra;
- }});
- 0x72: mskqh({{
- int bv = Rb_or_imm<2:0>;
- Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra;
- }});
-
- 0x06: extbl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }});
- 0x16: extwl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<15:0>; }});
- 0x26: extll({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<31:0>; }});
- 0x36: extql({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8)); }});
-
- 0x5a: extwh({{
- Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }});
- 0x6a: extlh({{
- Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }});
- 0x7a: extqh({{
- Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }});
-
- 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }});
- 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }});
- 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }});
- 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }});
-
- 0x57: inswh({{
- int bv = Rb_or_imm<2:0>;
- Rc = bv ? (Ra_uq<15:0> >> (64 - 8 * bv)) : 0;
- }});
- 0x67: inslh({{
- int bv = Rb_or_imm<2:0>;
- Rc = bv ? (Ra_uq<31:0> >> (64 - 8 * bv)) : 0;
- }});
- 0x77: insqh({{
- int bv = Rb_or_imm<2:0>;
- Rc = bv ? (Ra_uq >> (64 - 8 * bv)) : 0;
- }});
-
- 0x30: zap({{
- uint64_t zapmask = 0;
- for (int i = 0; i < 8; ++i) {
- if (Rb_or_imm<i:>)
- zapmask |= (mask(8) << (i * 8));
- }
- Rc = Ra & ~zapmask;
- }});
- 0x31: zapnot({{
- uint64_t zapmask = 0;
- for (int i = 0; i < 8; ++i) {
- if (!Rb_or_imm<i:>)
- zapmask |= (mask(8) << (i * 8));
- }
- Rc = Ra & ~zapmask;
- }});
- }
-
- 0x13: decode INTFUNC { // integer multiplies
- 0x00: mull({{ Rc_sl = Ra_sl * Rb_or_imm_sl; }}, IntMultOp);
- 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp);
- 0x30: umulh({{
- uint64_t hi, lo;
- mul128(Ra, Rb_or_imm, hi, lo);
- Rc = hi;
- }}, IntMultOp);
- 0x40: mullv({{
- // 32-bit multiply with trap on overflow
- int64_t Rax = Ra_sl; // sign extended version of Ra_sl
- int64_t Rbx = Rb_or_imm_sl;
- int64_t tmp = Rax * Rbx;
- // To avoid overflow, all the upper 32 bits must match
- // the sign bit of the lower 32. We code this as
- // checking the upper 33 bits for all 0s or all 1s.
- uint64_t sign_bits = tmp<63:31>;
- if (sign_bits != 0 && sign_bits != mask(33))
- fault = std::make_shared<IntegerOverflowFault>();
- Rc_sl = tmp<31:0>;
- }}, IntMultOp);
- 0x60: mulqv({{
- // 64-bit multiply with trap on overflow
- uint64_t hi, lo;
- mul128(Ra, Rb_or_imm, hi, lo);
- // all the upper 64 bits must match the sign bit of
- // the lower 64
- if (!((hi == 0 && lo<63:> == 0) ||
- (hi == mask(64) && lo<63:> == 1)))
- fault = std::make_shared<IntegerOverflowFault>();
- Rc = lo;
- }}, IntMultOp);
- }
-
- 0x1c: decode INTFUNC {
- 0x00: decode RA { 31: sextb({{ Rc_sb = Rb_or_imm< 7:0>; }}); }
- 0x01: decode RA { 31: sextw({{ Rc_sw = Rb_or_imm<15:0>; }}); }
-
- 0x30: ctpop({{
- uint64_t count = 0;
- for (int i = 0; Rb<63:i>; ++i) {
- if (Rb<i:i> == 0x1)
- ++count;
- }
- Rc = count;
- }}, IntAluOp);
-
- 0x31: perr({{
- uint64_t temp = 0;
- int hi = 7;
- int lo = 0;
- for (int i = 0; i < 8; ++i) {
- uint8_t ra_ub = Ra_uq<hi:lo>;
- uint8_t rb_ub = Rb_uq<hi:lo>;
- temp += (ra_ub >= rb_ub) ?
- (ra_ub - rb_ub) : (rb_ub - ra_ub);
- hi += 8;
- lo += 8;
- }
- Rc = temp;
- }});
-
- 0x32: ctlz({{
- uint64_t count = 0;
- uint64_t temp = Rb;
- if (temp<63:32>) temp >>= 32; else count += 32;
- if (temp<31:16>) temp >>= 16; else count += 16;
- if (temp<15:8>) temp >>= 8; else count += 8;
- if (temp<7:4>) temp >>= 4; else count += 4;
- if (temp<3:2>) temp >>= 2; else count += 2;
- if (temp<1:1>) temp >>= 1; else count += 1;
- if ((temp<0:0>) != 0x1) count += 1;
- Rc = count;
- }}, IntAluOp);
-
- 0x33: cttz({{
- uint64_t count = 0;
- uint64_t temp = Rb;
- if (!(temp<31:0>)) { temp >>= 32; count += 32; }
- if (!(temp<15:0>)) { temp >>= 16; count += 16; }
- if (!(temp<7:0>)) { temp >>= 8; count += 8; }
- if (!(temp<3:0>)) { temp >>= 4; count += 4; }
- if (!(temp<1:0>)) { temp >>= 2; count += 2; }
- if (!(temp<0:0> & ULL(0x1))) {
- temp >>= 1; count += 1;
- }
- if (!(temp<0:0> & ULL(0x1))) count += 1;
- Rc = count;
- }}, IntAluOp);
-
-
- 0x34: unpkbw({{
- Rc = (Rb_uq<7:0>
- | (Rb_uq<15:8> << 16)
- | (Rb_uq<23:16> << 32)
- | (Rb_uq<31:24> << 48));
- }}, IntAluOp);
-
- 0x35: unpkbl({{
- Rc = (Rb_uq<7:0> | (Rb_uq<15:8> << 32));
- }}, IntAluOp);
-
- 0x36: pkwb({{
- Rc = (Rb_uq<7:0>
- | (Rb_uq<23:16> << 8)
- | (Rb_uq<39:32> << 16)
- | (Rb_uq<55:48> << 24));
- }}, IntAluOp);
-
- 0x37: pklb({{
- Rc = (Rb_uq<7:0> | (Rb_uq<39:32> << 8));
- }}, IntAluOp);
-
- 0x38: minsb8({{
- uint64_t temp = 0;
- int hi = 63;
- int lo = 56;
- for (int i = 7; i >= 0; --i) {
- int8_t ra_sb = Ra_uq<hi:lo>;
- int8_t rb_sb = Rb_uq<hi:lo>;
- temp = ((temp << 8)
- | ((ra_sb < rb_sb) ? Ra_uq<hi:lo>
- : Rb_uq<hi:lo>));
- hi -= 8;
- lo -= 8;
- }
- Rc = temp;
- }});
-
- 0x39: minsw4({{
- uint64_t temp = 0;
- int hi = 63;
- int lo = 48;
- for (int i = 3; i >= 0; --i) {
- int16_t ra_sw = Ra_uq<hi:lo>;
- int16_t rb_sw = Rb_uq<hi:lo>;
- temp = ((temp << 16)
- | ((ra_sw < rb_sw) ? Ra_uq<hi:lo>
- : Rb_uq<hi:lo>));
- hi -= 16;
- lo -= 16;
- }
- Rc = temp;
- }});
-
- 0x3a: minub8({{
- uint64_t temp = 0;
- int hi = 63;
- int lo = 56;
- for (int i = 7; i >= 0; --i) {
- uint8_t ra_ub = Ra_uq<hi:lo>;
- uint8_t rb_ub = Rb_uq<hi:lo>;
- temp = ((temp << 8)
- | ((ra_ub < rb_ub) ? Ra_uq<hi:lo>
- : Rb_uq<hi:lo>));
- hi -= 8;
- lo -= 8;
- }
- Rc = temp;
- }});
-
- 0x3b: minuw4({{
- uint64_t temp = 0;
- int hi = 63;
- int lo = 48;
- for (int i = 3; i >= 0; --i) {
- uint16_t ra_sw = Ra_uq<hi:lo>;
- uint16_t rb_sw = Rb_uq<hi:lo>;
- temp = ((temp << 16)
- | ((ra_sw < rb_sw) ? Ra_uq<hi:lo>
- : Rb_uq<hi:lo>));
- hi -= 16;
- lo -= 16;
- }
- Rc = temp;
- }});
-
- 0x3c: maxub8({{
- uint64_t temp = 0;
- int hi = 63;
- int lo = 56;
- for (int i = 7; i >= 0; --i) {
- uint8_t ra_ub = Ra_uq<hi:lo>;
- uint8_t rb_ub = Rb_uq<hi:lo>;
- temp = ((temp << 8)
- | ((ra_ub > rb_ub) ? Ra_uq<hi:lo>
- : Rb_uq<hi:lo>));
- hi -= 8;
- lo -= 8;
- }
- Rc = temp;
- }});
-
- 0x3d: maxuw4({{
- uint64_t temp = 0;
- int hi = 63;
- int lo = 48;
- for (int i = 3; i >= 0; --i) {
- uint16_t ra_uw = Ra_uq<hi:lo>;
- uint16_t rb_uw = Rb_uq<hi:lo>;
- temp = ((temp << 16)
- | ((ra_uw > rb_uw) ? Ra_uq<hi:lo>
- : Rb_uq<hi:lo>));
- hi -= 16;
- lo -= 16;
- }
- Rc = temp;
- }});
-
- 0x3e: maxsb8({{
- uint64_t temp = 0;
- int hi = 63;
- int lo = 56;
- for (int i = 7; i >= 0; --i) {
- int8_t ra_sb = Ra_uq<hi:lo>;
- int8_t rb_sb = Rb_uq<hi:lo>;
- temp = ((temp << 8)
- | ((ra_sb > rb_sb) ? Ra_uq<hi:lo>
- : Rb_uq<hi:lo>));
- hi -= 8;
- lo -= 8;
- }
- Rc = temp;
- }});
-
- 0x3f: maxsw4({{
- uint64_t temp = 0;
- int hi = 63;
- int lo = 48;
- for (int i = 3; i >= 0; --i) {
- int16_t ra_sw = Ra_uq<hi:lo>;
- int16_t rb_sw = Rb_uq<hi:lo>;
- temp = ((temp << 16)
- | ((ra_sw > rb_sw) ? Ra_uq<hi:lo>
- : Rb_uq<hi:lo>));
- hi -= 16;
- lo -= 16;
- }
- Rc = temp;
- }});
-
- format BasicOperateWithNopCheck {
- 0x70: decode RB {
- 31: ftoit({{ Rc = Fa_uq; }}, FloatCvtOp);
- }
- 0x78: decode RB {
- 31: ftois({{ Rc_sl = t_to_s(Fa_uq); }},
- FloatCvtOp);
- }
- }
- }
- }
-
- // Conditional branches.
- format CondBranch {
- 0x39: beq({{ cond = (Ra == 0); }});
- 0x3d: bne({{ cond = (Ra != 0); }});
- 0x3e: bge({{ cond = (Ra_sq >= 0); }});
- 0x3f: bgt({{ cond = (Ra_sq > 0); }});
- 0x3b: ble({{ cond = (Ra_sq <= 0); }});
- 0x3a: blt({{ cond = (Ra_sq < 0); }});
- 0x38: blbc({{ cond = ((Ra & 1) == 0); }});
- 0x3c: blbs({{ cond = ((Ra & 1) == 1); }});
-
- 0x31: fbeq({{ cond = (Fa == 0); }});
- 0x35: fbne({{ cond = (Fa != 0); }});
- 0x36: fbge({{ cond = (Fa >= 0); }});
- 0x37: fbgt({{ cond = (Fa > 0); }});
- 0x33: fble({{ cond = (Fa <= 0); }});
- 0x32: fblt({{ cond = (Fa < 0); }});
- }
-
- // unconditional branches
- format UncondBranch {
- 0x30: br();
- 0x34: bsr(IsCall);
- }
-
- // indirect branches
- 0x1a: decode JMPFUNC {
- format Jump {
- 0: jmp();
- 1: jsr(IsCall);
- 2: ret(IsReturn);
- 3: jsr_coroutine(IsCall, IsReturn);
- }
- }
-
- // Square root and integer-to-FP moves
- 0x14: decode FP_SHORTFUNC {
- // Integer to FP register moves must have RB == 31
- 0x4: decode RB {
- 31: decode FP_FULLFUNC {
- format BasicOperateWithNopCheck {
- 0x004: itofs({{ Fc_uq = s_to_t(Ra_ul); }}, FloatCvtOp);
- 0x024: itoft({{ Fc_uq = Ra_uq; }}, FloatCvtOp);
- 0x014: FailUnimpl::itoff(); // VAX-format conversion
- }
- }
- }
-
- // Square root instructions must have FA == 31
- 0xb: decode FA {
- 31: decode FP_TYPEFUNC {
- format FloatingPointOperate {
- 0x0b: sqrts({{
- if (Fb_sf < 0.0)
- fault = std::make_shared<ArithmeticFault>();
- Fc_sf = sqrt(Fb_sf);
- }}, FloatSqrtOp);
- 0x2b: sqrtt({{
- if (Fb < 0.0)
- fault = std::make_shared<ArithmeticFault>();
- Fc = sqrt(Fb);
- }}, FloatSqrtOp);
- }
- }
- }
-
- // VAX-format sqrtf and sqrtg are not implemented
- 0xa: FailUnimpl::sqrtfg();
- }
-
- // IEEE floating point
- 0x16: decode FP_SHORTFUNC_TOP2 {
- // The top two bits of the short function code break this
- // space into four groups: binary ops, compares, reserved, and
- // conversions. See Table 4-12 of AHB. There are different
- // special cases in these different groups, so we decode on
- // these top two bits first just to select a decode strategy.
- // Most of these instructions may have various trapping and
- // rounding mode flags set; these are decoded in the
- // FloatingPointDecode template used by the
- // FloatingPointOperate format.
-
- // add/sub/mul/div: just decode on the short function code
- // and source type. All valid trapping and rounding modes apply.
- 0: decode FP_TRAPMODE {
- // check for valid trapping modes here
- 0,1,5,7: decode FP_TYPEFUNC {
- format FloatingPointOperate {
- 0x00: adds({{ Fc_sf = Fa_sf + Fb_sf; }});
- 0x01: subs({{ Fc_sf = Fa_sf - Fb_sf; }});
- 0x02: muls({{ Fc_sf = Fa_sf * Fb_sf; }}, FloatMultOp);
- 0x03: divs({{ Fc_sf = Fa_sf / Fb_sf; }}, FloatDivOp);
-
- 0x20: addt({{ Fc = Fa + Fb; }});
- 0x21: subt({{ Fc = Fa - Fb; }});
- 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp);
- 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp);
- }
- }
- }
-
- // Floating-point compare instructions must have the default
- // rounding mode, and may use the default trapping mode or
- // /SU. Both trapping modes are treated the same by M5; the
- // only difference on the real hardware (as far a I can tell)
- // is that without /SU you'd get an imprecise trap if you
- // tried to compare a NaN with something else (instead of an
- // "unordered" result).
- 1: decode FP_FULLFUNC {
- format BasicOperateWithNopCheck {
- 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }},
- FloatCmpOp);
- 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }},
- FloatCmpOp);
- 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }},
- FloatCmpOp);
- 0x0a4, 0x5a4: cmptun({{ // unordered
- Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0;
- }}, FloatCmpOp);
- }
- }
-
- // The FP-to-integer and integer-to-FP conversion insts
- // require that FA be 31.
- 3: decode FA {
- 31: decode FP_TYPEFUNC {
- format FloatingPointOperate {
- 0x2f: decode FP_ROUNDMODE {
- format FPFixedRounding {
- // "chopped" i.e. round toward zero
- 0: cvttq({{ Fc_sq = (int64_t)trunc(Fb); }},
- Chopped);
- // round to minus infinity
- 1: cvttq({{ Fc_sq = (int64_t)floor(Fb); }},
- MinusInfinity);
- }
- default: cvttq({{ Fc_sq = (int64_t)nearbyint(Fb); }});
- }
-
- // The cvtts opcode is overloaded to be cvtst if the trap
- // mode is 2 or 6 (which are not valid otherwise)
- 0x2c: decode FP_FULLFUNC {
- format BasicOperateWithNopCheck {
- // trap on denorm version "cvtst/s" is
- // simulated same as cvtst
- 0x2ac, 0x6ac: cvtst({{ Fc = Fb_sf; }});
- }
- default: cvtts({{ Fc_sf = Fb; }});
- }
-
- // The trapping mode for integer-to-FP conversions
- // must be /SUI or nothing; /U and /SU are not
- // allowed. The full set of rounding modes are
- // supported though.
- 0x3c: decode FP_TRAPMODE {
- 0,7: cvtqs({{ Fc_sf = Fb_sq; }});
- }
- 0x3e: decode FP_TRAPMODE {
- 0,7: cvtqt({{ Fc = Fb_sq; }});
- }
- }
- }
- }
- }
-
- // misc FP operate
- 0x17: decode FP_FULLFUNC {
- format BasicOperateWithNopCheck {
- 0x010: cvtlq({{
- Fc_sl = (Fb_uq<63:62> << 30) | Fb_uq<58:29>;
- }});
- 0x030: cvtql({{
- Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29);
- }});
-
- // We treat the precise & imprecise trapping versions of
- // cvtql identically.
- 0x130, 0x530: cvtqlv({{
- // To avoid overflow, all the upper 32 bits must match
- // the sign bit of the lower 32. We code this as
- // checking the upper 33 bits for all 0s or all 1s.
- uint64_t sign_bits = Fb_uq<63:31>;
- if (sign_bits != 0 && sign_bits != mask(33))
- fault = std::make_shared<IntegerOverflowFault>();
- Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29);
- }});
-
- 0x020: cpys({{ // copy sign
- Fc_uq = (Fa_uq<63:> << 63) | Fb_uq<62:0>;
- }});
- 0x021: cpysn({{ // copy sign negated
- Fc_uq = (~Fa_uq<63:> << 63) | Fb_uq<62:0>;
- }});
- 0x022: cpyse({{ // copy sign and exponent
- Fc_uq = (Fa_uq<63:52> << 52) | Fb_uq<51:0>;
- }});
-
- 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }});
- 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }});
- 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }});
- 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }});
- 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
- 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
-
- 0x024: mt_fpcr({{ FPCR = Fa_uq; }}, IsIprAccess);
- 0x025: mf_fpcr({{ Fa_uq = FPCR; }}, IsIprAccess);
- }
- }
-
- // miscellaneous mem-format ops
- 0x18: decode MEMFUNC {
- format WarnUnimpl {
- 0x8000: fetch();
- 0xa000: fetch_m();
- 0xe800: ecb();
- }
-
- format MiscPrefetch {
- 0xf800: wh64({{ EA = Rb & ~ULL(63); }},
- {{ ; }},
- mem_flags = PREFETCH);
- }
-
- format BasicOperate {
- 0xc000: rpcc({{
- /* Rb is a fake dependency so here is a fun way to get
- * the parser to understand that.
- */
- uint64_t unused_var M5_VAR_USED = Rb;
- Ra = FullSystem ? xc->readMiscReg(IPR_CC) : curTick();
- }}, IsUnverifiable);
-
- // All of the barrier instructions below do nothing in
- // their execute() methods (hence the empty code blocks).
- // All of their functionality is hard-coded in the
- // pipeline based on the flags IsSerializing,
- // IsMemBarrier, and IsWriteBarrier. In the current
- // detailed CPU model, the execute() function only gets
- // called at fetch, so there's no way to generate pipeline
- // behavior at any other stage. Once we go to an
- // exec-in-exec CPU model we should be able to get rid of
- // these flags and implement this behavior via the
- // execute() methods.
-
- // trapb is just a barrier on integer traps, where excb is
- // a barrier on integer and FP traps. "EXCB is thus a
- // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
- // them the same though.
- 0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
- 0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
- 0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
- 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
- }
-
- 0xe000: decode FullSystemInt {
- 0: FailUnimpl::rc_se();
- default: BasicOperate::rc({{
- Ra = IntrFlag;
- IntrFlag = 0;
- }}, IsNonSpeculative, IsUnverifiable);
- }
- 0xf000: decode FullSystemInt {
- 0: FailUnimpl::rs_se();
- default: BasicOperate::rs({{
- Ra = IntrFlag;
- IntrFlag = 1;
- }}, IsNonSpeculative, IsUnverifiable);
- }
- }
-
- 0x00: decode FullSystemInt {
- 0: decode PALFUNC {
- format EmulatedCallPal {
- 0x00: halt ({{
- exitSimLoop("halt instruction encountered");
- }}, IsNonSpeculative);
- 0x83: callsys({{
- xc->syscall(&fault);
- }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
- // Read uniq reg into ABI return value register (r0)
- 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
- // Write uniq reg with value from ABI arg register (r16)
- 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
- }
- }
- default: CallPal::call_pal({{
- if (!palValid ||
- (palPriv
- && xc->readMiscReg(IPR_ICM) != mode_kernel)) {
- // invalid pal function code, or attempt to do privileged
- // PAL call in non-kernel mode
- fault = std::make_shared<UnimplementedOpcodeFault>();
- } else {
- // check to see if simulator wants to do something special
- // on this PAL call (including maybe suppress it)
- bool dopal = true;
- ThreadContext *tc = xc->tcBase();
- auto *base_stats = tc->getKernelStats();
- auto *stats = dynamic_cast<AlphaISA::Kernel::Statistics *>(
- base_stats);
- assert(stats || !base_stats);
- if (stats)
- stats->callpal(palFunc, tc);
-
- System *sys = tc->getSystemPtr();
-
- switch (palFunc) {
- case PAL::halt:
- xc->tcBase()->halt();
- if (--System::numSystemsRunning == 0)
- exitSimLoop("all cpus halted");
- break;
-
- case PAL::bpt:
- case PAL::bugchk:
- if (sys->breakpoint())
- dopal = false;
- break;
- }
-
- if (dopal) {
- xc->setMiscReg(IPR_EXC_ADDR, NPC);
- NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset;
- }
- }
- }}, IsNonSpeculative);
- }
-
- 0x1b: decode PALMODE {
- 0: OpcdecFault::hw_st_quad();
- 1: decode HW_LDST_QUAD {
- format HwLoad {
- 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem_ul; }},
- L, IsSerializing, IsSerializeBefore);
- 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem_uq; }},
- Q, IsSerializing, IsSerializeBefore);
- }
- }
- }
-
- 0x1f: decode PALMODE {
- 0: OpcdecFault::hw_st_cond();
- format HwStore {
- 1: decode HW_LDST_COND {
- 0: decode HW_LDST_QUAD {
- 0: hw_st({{ EA = (Rb + disp) & ~3; }},
- {{ Mem_ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore);
- 1: hw_st({{ EA = (Rb + disp) & ~7; }},
- {{ Mem_uq = Ra_uq; }}, Q, IsSerializing, IsSerializeBefore);
- }
-
- 1: FailUnimpl::hw_st_cond();
- }
- }
- }
-
- 0x19: decode PALMODE {
- 0: OpcdecFault::hw_mfpr();
- format HwMoveIPR {
- 1: hw_mfpr({{
- int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
- IprToMiscRegIndex[ipr_index] : -1;
- if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) ||
- miscRegIndex >= NumInternalProcRegs)
- fault = std::make_shared<UnimplementedOpcodeFault>();
- else
- Ra = xc->readMiscReg(miscRegIndex);
- }}, IsIprAccess);
- }
- }
-
- 0x1d: decode PALMODE {
- 0: OpcdecFault::hw_mtpr();
- format HwMoveIPR {
- 1: hw_mtpr({{
- int miscRegIndex = (ipr_index < MaxInternalProcRegs) ?
- IprToMiscRegIndex[ipr_index] : -1;
- if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) ||
- miscRegIndex >= NumInternalProcRegs)
- fault = std::make_shared<UnimplementedOpcodeFault>();
- else
- xc->setMiscReg(miscRegIndex, Ra);
- if (traceData) { traceData->setData(Ra); }
- }}, IsIprAccess);
- }
- }
-
- 0x1e: decode PALMODE {
- 0: OpcdecFault::hw_rei();
- format BasicOperate {
- 1: hw_rei({{
- Addr pc = PC;
- if (!(pc & 0x3))
- return std::make_shared<UnimplementedOpcodeFault>();
-
- LockFlag = false;
- NPC = IprExcAddr;
-
- ThreadContext *tc = xc->tcBase();
- auto *base_stats = tc->getKernelStats();
- auto *stats = dynamic_cast<AlphaISA::Kernel::Statistics *>(
- base_stats);
- assert(stats || !base_stats);
- if (stats)
- stats->hwrei();
-
- CPA::cpa()->swAutoBegin(tc, IprExcAddr);
- }}, IsSerializing, IsSerializeBefore);
- }
- }
-
- format BasicOperate {
- // M5 special opcodes use the reserved 0x01 opcode space
- 0x01: decode M5FUNC {
- 0x00: arm({{
- PseudoInst::arm(xc->tcBase());
- }}, IsNonSpeculative);
- 0x01: quiesce({{
- // Don't sleep if (unmasked) interrupts are pending
- BaseInterrupts* interrupts =
- xc->tcBase()->getCpuPtr()->getInterruptController(0);
- if (interrupts->checkInterrupts(xc->tcBase())) {
- PseudoInst::quiesceSkip(xc->tcBase());
- } else {
- PseudoInst::quiesce(xc->tcBase());
- }
- }}, IsNonSpeculative, IsQuiesce);
- 0x02: quiesceNs({{
- PseudoInst::quiesceNs(xc->tcBase(), R16);
- }}, IsNonSpeculative, IsQuiesce);
- 0x03: quiesceCycles({{
- PseudoInst::quiesceCycles(xc->tcBase(), R16);
- }}, IsNonSpeculative, IsQuiesce, IsUnverifiable);
- 0x04: quiesceTime({{
- R0 = PseudoInst::quiesceTime(xc->tcBase());
- }}, IsNonSpeculative, IsUnverifiable);
- 0x07: rpns({{
- R0 = PseudoInst::rpns(xc->tcBase());
- }}, IsNonSpeculative, IsUnverifiable);
- 0x09: wakeCPU({{
- PseudoInst::wakeCPU(xc->tcBase(), R16);
- }}, IsNonSpeculative, IsUnverifiable);
- 0x10: deprecated_ivlb({{
- warn_once("Obsolete M5 ivlb instruction encountered.\n");
- }});
- 0x11: deprecated_ivle({{
- warn_once("Obsolete M5 ivlb instruction encountered.\n");
- }});
- 0x20: deprecated_exit ({{
- warn_once("deprecated M5 exit instruction encountered.\n");
- PseudoInst::m5exit(xc->tcBase(), 0);
- }}, No_OpClass, IsNonSpeculative);
- 0x21: m5exit({{
- PseudoInst::m5exit(xc->tcBase(), R16);
- }}, No_OpClass, IsNonSpeculative);
- 0x31: loadsymbol({{
- PseudoInst::loadsymbol(xc->tcBase());
- }}, No_OpClass, IsNonSpeculative);
- 0x30: initparam({{
- Ra = PseudoInst::initParam(xc->tcBase(), R16, R17);
- }});
- 0x40: resetstats({{
- PseudoInst::resetstats(xc->tcBase(), R16, R17);
- }}, IsNonSpeculative);
- 0x41: dumpstats({{
- PseudoInst::dumpstats(xc->tcBase(), R16, R17);
- }}, IsNonSpeculative);
- 0x42: dumpresetstats({{
- PseudoInst::dumpresetstats(xc->tcBase(), R16, R17);
- }}, IsNonSpeculative);
- 0x43: m5checkpoint({{
- PseudoInst::m5checkpoint(xc->tcBase(), R16, R17);
- }}, IsNonSpeculative);
- 0x50: m5readfile({{
- R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18);
- }}, IsNonSpeculative);
- 0x51: m5break({{
- PseudoInst::debugbreak(xc->tcBase());
- }}, IsNonSpeculative);
- 0x52: m5switchcpu({{
- PseudoInst::switchcpu(xc->tcBase());
- }}, IsNonSpeculative);
- 0x53: m5addsymbol({{
- PseudoInst::addsymbol(xc->tcBase(), R16, R17);
- }}, IsNonSpeculative);
- 0x54: m5panic({{
- panic("M5 panic instruction called at pc = %#x.", PC);
- }}, IsNonSpeculative);
-#define CPANN(lbl) CPA::cpa()->lbl(xc->tcBase())
- 0x55: decode RA {
- 0x00: m5a_old({{
- panic("Deprecated M5 annotate instruction executed "
- "at pc = %#x\n", PC);
- }}, IsNonSpeculative);
- 0x01: m5a_bsm({{
- CPANN(swSmBegin);
- }}, IsNonSpeculative);
- 0x02: m5a_esm({{
- CPANN(swSmEnd);
- }}, IsNonSpeculative);
- 0x03: m5a_begin({{
- CPANN(swExplictBegin);
- }}, IsNonSpeculative);
- 0x04: m5a_end({{
- CPANN(swEnd);
- }}, IsNonSpeculative);
- 0x06: m5a_q({{
- CPANN(swQ);
- }}, IsNonSpeculative);
- 0x07: m5a_dq({{
- CPANN(swDq);
- }}, IsNonSpeculative);
- 0x08: m5a_wf({{
- CPANN(swWf);
- }}, IsNonSpeculative);
- 0x09: m5a_we({{
- CPANN(swWe);
- }}, IsNonSpeculative);
- 0x0C: m5a_sq({{
- CPANN(swSq);
- }}, IsNonSpeculative);
- 0x0D: m5a_aq({{
- CPANN(swAq);
- }}, IsNonSpeculative);
- 0x0E: m5a_pq({{
- CPANN(swPq);
- }}, IsNonSpeculative);
- 0x0F: m5a_l({{
- CPANN(swLink);
- }}, IsNonSpeculative);
- 0x10: m5a_identify({{
- CPANN(swIdentify);
- }}, IsNonSpeculative);
- 0x11: m5a_getid({{
- R0 = CPANN(swGetId);
- }}, IsNonSpeculative);
- 0x13: m5a_scl({{
- CPANN(swSyscallLink);
- }}, IsNonSpeculative);
- 0x14: m5a_rq({{
- CPANN(swRq);
- }}, IsNonSpeculative);
- } // M5 Annotate Operations
-#undef CPANN
- 0x56: m5reserved2({{
- warn("M5 reserved opcode ignored");
- }}, IsNonSpeculative);
- 0x57: m5reserved3({{
- warn("M5 reserved opcode ignored");
- }}, IsNonSpeculative);
- 0x58: m5reserved4({{
- warn("M5 reserved opcode ignored");
- }}, IsNonSpeculative);
- 0x59: m5reserved5({{
- warn("M5 reserved opcode ignored");
- }}, IsNonSpeculative);
- }
- }
-}
+++ /dev/null
-// -*- mode:c++ -*-
-
-// Copyright (c) 2003-2005 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Steve Reinhardt
-
-////////////////////////////////////////////////////////////////////
-//
-// Floating-point instructions
-//
-// Note that many FP-type instructions which do not support all the
-// various rounding & trapping modes use the simpler format
-// BasicOperateWithNopCheck.
-//
-
-output exec {{
- /// Check "FP enabled" machine status bit. Called when executing any FP
- /// instruction in full-system mode.
- /// @retval Full-system mode: NoFault if FP is enabled, FenFault
- /// if not. Non-full-system mode: always returns NoFault.
- inline Fault checkFpEnableFault(ExecContext *xc)
- {
- Fault fault = NoFault; // dummy... this ipr access should not fault
- if (FullSystem && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
- fault = std::make_shared<FloatEnableFault>();
- }
- return fault;
- }
- inline Fault checkVectorEnableFault(ExecContext *xc) {
- return std::make_shared<VectorEnableFault>();
- }
-}};
-
-output header {{
- /**
- * Base class for general floating-point instructions. Includes
- * support for various Alpha rounding and trapping modes. Only FP
- * instructions that require this support are derived from this
- * class; the rest derive directly from AlphaStaticInst.
- */
- class AlphaFP : public AlphaStaticInst
- {
- public:
- /// Alpha FP rounding modes.
- enum RoundingMode {
- Chopped = 0, ///< round toward zero
- Minus_Infinity = 1, ///< round toward minus infinity
- Normal = 2, ///< round to nearest (default)
- Dynamic = 3, ///< use FPCR setting (in instruction)
- Plus_Infinity = 3 ///< round to plus inifinity (in FPCR)
- };
-
- /// Alpha FP trapping modes.
- /// For instructions that produce integer results, the
- /// "Underflow Enable" modes really mean "Overflow Enable", and
- /// the assembly modifier is V rather than U.
- enum TrappingMode {
- /// default: nothing enabled
- Imprecise = 0, ///< no modifier
- /// underflow/overflow traps enabled, inexact disabled
- Underflow_Imprecise = 1, ///< /U or /V
- Underflow_Precise = 5, ///< /SU or /SV
- /// underflow/overflow and inexact traps enabled
- Underflow_Inexact_Precise = 7 ///< /SUI or /SVI
- };
-
- protected:
- /// Map Alpha rounding mode to C99 constants from <fenv.h>.
- static const int alphaToC99RoundingMode[];
-
- /// Map enum RoundingMode values to disassembly suffixes.
- static const char *roundingModeSuffix[];
- /// Map enum TrappingMode values to FP disassembly suffixes.
- static const char *fpTrappingModeSuffix[];
- /// Map enum TrappingMode values to integer disassembly suffixes.
- static const char *intTrappingModeSuffix[];
-
- /// This instruction's rounding mode.
- RoundingMode roundingMode;
- /// This instruction's trapping mode.
- TrappingMode trappingMode;
-
- /// Have we warned about this instruction's unsupported
- /// rounding mode (if applicable)?
- mutable bool warnedOnRounding;
-
- /// Have we warned about this instruction's unsupported
- /// trapping mode (if applicable)?
- mutable bool warnedOnTrapping;
-
- /// Constructor
- AlphaFP(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
- : AlphaStaticInst(mnem, _machInst, __opClass),
- roundingMode((enum RoundingMode)FP_ROUNDMODE),
- trappingMode((enum TrappingMode)FP_TRAPMODE),
- warnedOnRounding(false),
- warnedOnTrapping(false)
- {
- }
-
- int getC99RoundingMode(uint64_t fpcr_val) const;
-
- // This differs from the AlphaStaticInst version only in
- // printing suffixes for non-default rounding & trapping modes.
- std::string generateDisassembly(
- Addr pc, const SymbolTable *symtab) const override;
- };
-
-}};
-
-
-output decoder {{
- int
- AlphaFP::getC99RoundingMode(uint64_t fpcr_val) const
- {
- if (roundingMode == Dynamic) {
- return alphaToC99RoundingMode[bits(fpcr_val, 59, 58)];
- }
- else {
- return alphaToC99RoundingMode[roundingMode];
- }
- }
-
- std::string
- AlphaFP::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- std::string mnem_str(mnemonic);
-
- std::string suffix("");
- suffix += ((_destRegIdx[0].isFloatReg())
- ? fpTrappingModeSuffix[trappingMode]
- : intTrappingModeSuffix[trappingMode]);
- suffix += roundingModeSuffix[roundingMode];
-
- if (suffix != "") {
- mnem_str = csprintf("%s/%s", mnemonic, suffix);
- }
-
- std::stringstream ss;
- ccprintf(ss, "%-10s ", mnem_str.c_str());
-
- // just print the first two source regs... if there's
- // a third one, it's a read-modify-write dest (Rc),
- // e.g. for CMOVxx
- if (_numSrcRegs > 0) {
- printReg(ss, _srcRegIdx[0]);
- }
- if (_numSrcRegs > 1) {
- ss << ",";
- printReg(ss, _srcRegIdx[1]);
- }
-
- // just print the first dest... if there's a second one,
- // it's generally implicit
- if (_numDestRegs > 0) {
- if (_numSrcRegs > 0)
- ss << ",";
- printReg(ss, _destRegIdx[0]);
- }
-
- return ss.str();
- }
-
- const int AlphaFP::alphaToC99RoundingMode[] = {
- M5_FE_TOWARDZERO, // Chopped
- M5_FE_DOWNWARD, // Minus_Infinity
- M5_FE_TONEAREST, // Normal
- M5_FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR
- };
-
- const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };
- // mark invalid trapping modes, but don't fail on them, because
- // you could decode anything on a misspeculated path
- const char *AlphaFP::fpTrappingModeSuffix[] =
- { "", "u", "INVTM2", "INVTM3", "INVTM4", "su", "INVTM6", "sui" };
- const char *AlphaFP::intTrappingModeSuffix[] =
- { "", "v", "INVTM2", "INVTM3", "INVTM4", "sv", "INVTM6", "svi" };
-}};
-
-// FP instruction class execute method template. Handles non-standard
-// rounding modes.
-def template FloatingPointExecute {{
- Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
- {
- if (trappingMode != Imprecise && !warnedOnTrapping) {
- warn("%s: non-standard trapping mode not supported",
- generateDisassembly(0, NULL));
- warnedOnTrapping = true;
- }
-
- Fault fault = NoFault;
-
- %(fp_enable_check)s;
- %(op_decl)s;
- %(op_rd)s;
-#if USE_FENV
- if (roundingMode == Normal) {
- %(code)s;
- } else {
- m5_fesetround(getC99RoundingMode(
- xc->readMiscReg(MISCREG_FPCR)));
- %(code)s;
- m5_fesetround(M5_FE_TONEAREST);
- }
-#else
- if (roundingMode != Normal && !warnedOnRounding) {
- warn("%s: non-standard rounding mode not supported",
- generateDisassembly(0, NULL));
- warnedOnRounding = true;
- }
- %(code)s;
-#endif
-
- if (fault == NoFault) {
- %(op_wb)s;
- }
-
- return fault;
- }
-}};
-
-// FP instruction class execute method template where no dynamic
-// rounding mode control is needed. Like BasicExecute, but includes
-// check & warning for non-standard trapping mode.
-def template FPFixedRoundingExecute {{
- Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
- {
- if (trappingMode != Imprecise && !warnedOnTrapping) {
- warn("%s: non-standard trapping mode not supported",
- generateDisassembly(0, NULL));
- warnedOnTrapping = true;
- }
-
- Fault fault = NoFault;
-
- %(fp_enable_check)s;
- %(op_decl)s;
- %(op_rd)s;
- %(code)s;
-
- if (fault == NoFault) {
- %(op_wb)s;
- }
-
- return fault;
- }
-}};
-
-def template FloatingPointDecode {{
- {
- AlphaStaticInst *i = new %(class_name)s(machInst);
- if (FC == 31) {
- i = makeNop(i);
- }
- return i;
- }
-}};
-
-// General format for floating-point operate instructions:
-// - Checks trapping and rounding mode flags. Trapping modes
-// currently unimplemented (will fail).
-// - Generates NOP if FC == 31.
-def format FloatingPointOperate(code, *opt_args) {{
- iop = InstObjParams(name, Name, 'AlphaFP', code, opt_args)
- decode_block = FloatingPointDecode.subst(iop)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- exec_output = FloatingPointExecute.subst(iop)
-}};
-
-// Special format for cvttq where rounding mode is pre-decoded
-def format FPFixedRounding(code, class_suffix, *opt_args) {{
- Name += class_suffix
- iop = InstObjParams(name, Name, 'AlphaFP', code, opt_args)
- decode_block = FloatingPointDecode.subst(iop)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- exec_output = FPFixedRoundingExecute.subst(iop)
-}};
-
+++ /dev/null
-// -*- mode:c++ -*-
-
-// Copyright (c) 2003-2005 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Steve Reinhardt
-
-////////////////////////////////////////////////////////////////////
-//
-// Integer operate instructions
-//
-
-output header {{
- /**
- * Base class for integer immediate instructions.
- */
- class IntegerImm : public AlphaStaticInst
- {
- protected:
- /// Immediate operand value (unsigned 8-bit int).
- uint8_t imm;
-
- /// Constructor
- IntegerImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
- : AlphaStaticInst(mnem, _machInst, __opClass), imm(INTIMM)
- {
- }
-
- std::string generateDisassembly(
- Addr pc, const SymbolTable *symtab) const override;
- };
-}};
-
-output decoder {{
- std::string
- IntegerImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- std::stringstream ss;
-
- ccprintf(ss, "%-10s ", mnemonic);
-
- // just print the first source reg... if there's
- // a second one, it's a read-modify-write dest (Rc),
- // e.g. for CMOVxx
- if (_numSrcRegs > 0) {
- printReg(ss, _srcRegIdx[0]);
- ss << ",";
- }
-
- ss << (int)imm;
-
- if (_numDestRegs > 0) {
- ss << ",";
- printReg(ss, _destRegIdx[0]);
- }
-
- return ss.str();
- }
-}};
-
-
-def template RegOrImmDecode {{
- {
- AlphaStaticInst *i =
- (IMM) ? (AlphaStaticInst *)new %(class_name)sImm(machInst)
- : (AlphaStaticInst *)new %(class_name)s(machInst);
- if (RC == 31) {
- i = makeNop(i);
- }
- return i;
- }
-}};
-
-// Primary format for integer operate instructions:
-// - Generates both reg-reg and reg-imm versions if Rb_or_imm is used.
-// - Generates NOP if RC == 31.
-def format IntegerOperate(code, *opt_flags) {{
- # If the code block contains 'Rb_or_imm', we define two instructions,
- # one using 'Rb' and one using 'imm', and have the decoder select
- # the right one.
- uses_imm = (code.find('Rb_or_imm') != -1)
- if uses_imm:
- orig_code = code
- # base code is reg version:
- # rewrite by substituting 'Rb' for 'Rb_or_imm'
- code = re.sub(r'Rb_or_imm', 'Rb', orig_code)
- # generate immediate version by substituting 'imm'
- # note that imm takes no extenstion, so we extend
- # the regexp to replace any extension as well
- imm_code = re.sub(r'Rb_or_imm(_\w+)?', 'imm', orig_code)
-
- # generate declaration for register version
- iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- exec_output = BasicExecute.subst(iop)
-
- if uses_imm:
- # append declaration for imm version
- imm_iop = InstObjParams(name, Name + 'Imm', 'IntegerImm', imm_code,
- opt_flags)
- header_output += BasicDeclare.subst(imm_iop)
- decoder_output += BasicConstructor.subst(imm_iop)
- exec_output += BasicExecute.subst(imm_iop)
- # decode checks IMM bit to pick correct version
- decode_block = RegOrImmDecode.subst(iop)
- else:
- # no imm version: just check for nop
- decode_block = OperateNopCheckDecode.subst(iop)
-}};
+++ /dev/null
-// -*- mode:c++ -*-
-
-// Copyright (c) 2003-2005 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Steve Reinhardt
-
-////////////////////////////////////////////////////////////////////
-//
-// Alpha ISA description file.
-//
-////////////////////////////////////////////////////////////////////
-
-
-////////////////////////////////////////////////////////////////////
-//
-// Output include file directives.
-//
-
-output header {{
-#include <iomanip>
-#include <iostream>
-#include <sstream>
-
-#include "arch/alpha/faults.hh"
-#include "arch/alpha/types.hh"
-#include "cpu/static_inst.hh"
-#include "mem/packet.hh"
-#include "mem/request.hh" // some constructors use MemReq flags
-#include "sim/byteswap.hh"
-
-}};
-
-output decoder {{
-#include <cmath>
-
-#include "arch/alpha/decoder.hh"
-#include "arch/alpha/registers.hh"
-#include "arch/alpha/regredir.hh"
-#include "base/cprintf.hh"
-#include "base/fenv.hh"
-#include "base/loader/symtab.hh"
-#include "cpu/thread_context.hh" // for Jump::branchTarget()
-#include "mem/packet.hh"
-#include "sim/full_system.hh"
-
-using namespace AlphaISA;
-}};
-
-output exec {{
-#include <cmath>
-
-#include "arch/alpha/decoder.hh"
-#include "arch/alpha/kernel_stats.hh"
-#include "arch/alpha/osfpal.hh"
-#include "arch/alpha/registers.hh"
-#include "arch/alpha/regredir.hh"
-#include "arch/generic/memhelpers.hh"
-#include "base/cp_annotate.hh"
-#include "base/fenv.hh"
-#include "cpu/base.hh"
-#include "cpu/exetrace.hh"
-#include "mem/packet.hh"
-#include "mem/packet_access.hh"
-#include "sim/full_system.hh"
-#include "sim/pseudo_inst.hh"
-#include "sim/sim_exit.hh"
-
-using namespace AlphaISA;
-}};
-
-////////////////////////////////////////////////////////////////////
-//
-// Namespace statement. Everything below this line will be in the
-// AlphaISAInst namespace.
-//
-
-
-namespace AlphaISA;
-
-////////////////////////////////////////////////////////////////////
-//
-// Bitfield definitions.
-//
-
-// Universal (format-independent) fields
-def bitfield PALMODE <32:32>;
-def bitfield OPCODE <31:26>;
-def bitfield RA <25:21>;
-def bitfield RB <20:16>;
-
-// Memory format
-def signed bitfield MEMDISP <15: 0>; // displacement
-def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
-
-// Memory-format jumps
-def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
-def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
-
-// Branch format
-def signed bitfield BRDISP <20: 0>; // displacement
-
-// Integer operate format(s>;
-def bitfield INTIMM <20:13>; // integer immediate (literal)
-def bitfield IMM <12:12>; // immediate flag
-def bitfield INTFUNC <11: 5>; // function code
-def bitfield RC < 4: 0>; // dest reg
-
-// Floating-point operate format
-def bitfield FA <25:21>;
-def bitfield FB <20:16>;
-def bitfield FP_FULLFUNC <15: 5>; // complete function code
- def bitfield FP_TRAPMODE <15:13>; // trapping mode
- def bitfield FP_ROUNDMODE <12:11>; // rounding mode
- def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
- def bitfield FP_SRCTYPE <10: 9>; // source reg type
- def bitfield FP_SHORTFUNC < 8: 5>; // short function code
- def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
-def bitfield FC < 4: 0>; // dest reg
-
-// PALcode format
-def bitfield PALFUNC <25: 0>; // function code
-
-// EV5 PAL instructions:
-// HW_LD/HW_ST
-def bitfield HW_LDST_PHYS <15>; // address is physical
-def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
-def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
-def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
-def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
-def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
-def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
-def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
-
-// HW_REI
-def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
-def bitfield HW_REI_MBZ <13: 0>; // must be zero
-
-// HW_MTPR/MW_MFPR
-def bitfield HW_IPR_IDX <15:0>; // IPR index
-
-// M5 instructions
-def bitfield M5FUNC <7:0>;
-
-def operand_types {{
- 'sb' : 'int8_t',
- 'ub' : 'uint8_t',
- 'sw' : 'int16_t',
- 'uw' : 'uint16_t',
- 'sl' : 'int32_t',
- 'ul' : 'uint32_t',
- 'sq' : 'int64_t',
- 'uq' : 'uint64_t',
- 'sf' : 'float',
- 'df' : 'double'
-}};
-
-def operands {{
- # Int regs default to unsigned, but code should not count on this.
- # For clarity, descriptions that depend on unsigned behavior should
- # explicitly specify '_uq'.
- 'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA',
- 'IsInteger', 1),
- 'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB',
- 'IsInteger', 2),
- 'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC',
- 'IsInteger', 3),
- 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
- 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
- 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
- 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
- 'PC': ('PCState', 'uq', 'pc', ( None, None, 'IsControl' ), 4),
- 'NPC': ('PCState', 'uq', 'npc', ( None, None, 'IsControl' ), 4),
- 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
- 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
- 'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
- 'LockFlag': ('ControlReg', 'uq', 'MISCREG_LOCKFLAG', None, 1),
- 'IprExcAddr': ('ControlReg', 'uq', 'IPR_EXC_ADDR', None, 1),
- # The next two are hacks for non-full-system call-pal emulation
- 'R0': ('IntReg', 'uq', '0', None, 1),
- 'R16': ('IntReg', 'uq', '16', None, 1),
- 'R17': ('IntReg', 'uq', '17', None, 1),
- 'R18': ('IntReg', 'uq', '18', None, 1)
-}};
-
-////////////////////////////////////////////////////////////////////
-//
-// Basic instruction classes/templates/formats etc.
-//
-
-output header {{
- /**
- * Base class for all Alpha static instructions.
- */
- class AlphaStaticInst : public StaticInst
- {
- protected:
- /// Constructor.
- AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass)
- : StaticInst(mnem, _machInst, __opClass)
- {
- }
-
- /// Print a register name for disassembly given the unique
- /// dependence tag number (FP or int).
- void printReg(std::ostream &os, RegId reg) const;
-
- std::string generateDisassembly(
- Addr pc, const SymbolTable *symtab) const override;
-
- void
- advancePC(AlphaISA::PCState &pcState) const override
- {
- pcState.advance();
- }
-
- public:
- size_t
- asBytes(void *buf, size_t max_size) override
- {
- return simpleAsBytes(buf, max_size, machInst);
- }
- };
-}};
-
-output decoder {{
- void
- AlphaStaticInst::printReg(std::ostream &os, RegId reg) const
- {
- if (reg.isIntReg()) {
- ccprintf(os, "r%d", reg.index());
- }
- else {
- ccprintf(os, "f%d", reg.index());
- }
- }
-
- std::string
- AlphaStaticInst::generateDisassembly(
- Addr pc, const SymbolTable *symtab) const
- {
- std::stringstream ss;
-
- ccprintf(ss, "%-10s ", mnemonic);
-
- // just print the first two source regs... if there's
- // a third one, it's a read-modify-write dest (Rc),
- // e.g. for CMOVxx
- if (_numSrcRegs > 0) {
- printReg(ss, _srcRegIdx[0]);
- }
- if (_numSrcRegs > 1) {
- ss << ",";
- printReg(ss, _srcRegIdx[1]);
- }
-
- // just print the first dest... if there's a second one,
- // it's generally implicit
- if (_numDestRegs > 0) {
- if (_numSrcRegs > 0)
- ss << ",";
- printReg(ss, _destRegIdx[0]);
- }
-
- return ss.str();
- }
-}};
-
-// Basic instruction class declaration template.
-def template BasicDeclare {{
- /**
- * Static instruction class for "%(mnemonic)s".
- */
- class %(class_name)s : public %(base_class)s
- {
- public:
- /// Constructor.
- %(class_name)s(ExtMachInst machInst);
-
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- };
-}};
-
-// Basic instruction class constructor template.
-def template BasicConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst)
- : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
- {
- %(constructor)s;
- }
-}};
-
-// Basic instruction class execute method template.
-def template BasicExecute {{
- Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
- {
- Fault fault = NoFault;
-
- %(fp_enable_check)s;
- %(op_decl)s;
- %(op_rd)s;
- %(code)s;
-
- if (fault == NoFault) {
- %(op_wb)s;
- }
-
- return fault;
- }
-}};
-
-// Basic decode template.
-def template BasicDecode {{
- return new %(class_name)s(machInst);
-}};
-
-// Basic decode template, passing mnemonic in as string arg to constructor.
-def template BasicDecodeWithMnemonic {{
- return new %(class_name)s("%(mnemonic)s", machInst);
-}};
-
-// The most basic instruction format... used only for a few misc. insts
-def format BasicOperate(code, *flags) {{
- iop = InstObjParams(name, Name, 'AlphaStaticInst', code, flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
-}};
-
-
-
-////////////////////////////////////////////////////////////////////
-//
-// Nop
-//
-
-output header {{
- /**
- * Static instruction class for no-ops. This is a leaf class.
- */
- class Nop : public AlphaStaticInst
- {
- /// Disassembly of original instruction.
- const std::string originalDisassembly;
-
- public:
- /// Constructor
- Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
- : AlphaStaticInst("nop", _machInst, No_OpClass),
- originalDisassembly(_originalDisassembly)
- {
- flags[IsNop] = true;
- }
-
- ~Nop() { }
-
- std::string generateDisassembly(
- Addr pc, const SymbolTable *symtab) const override;
-
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- };
-
- /// Helper function for decoding nops. Substitute Nop object
- /// for original inst passed in as arg (and delete latter).
- static inline
- AlphaStaticInst *
- makeNop(AlphaStaticInst *inst)
- {
- AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
- delete inst;
- return nop;
- }
-}};
-
-output decoder {{
- std::string Nop::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- return csprintf("%-10s (%s)", "nop", originalDisassembly);
- }
-}};
-
-output exec {{
- Fault
- Nop::execute(ExecContext *, Trace::InstRecord *) const
- {
- return NoFault;
- }
-}};
-
-// integer & FP operate instructions use Rc as dest, so check for
-// Rc == 31 to detect nops
-def template OperateNopCheckDecode {{
- {
- AlphaStaticInst *i = new %(class_name)s(machInst);
- if (RC == 31) {
- i = makeNop(i);
- }
- return i;
- }
-}};
-
-// Like BasicOperate format, but generates NOP if RC/FC == 31
-def format BasicOperateWithNopCheck(code, *opt_args) {{
- iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_args)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = OperateNopCheckDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
-}};
-
-// Integer instruction templates, formats, etc.
-##include "int.isa"
-
-// Floating-point instruction templates, formats, etc.
-##include "fp.isa"
-
-// Memory instruction templates, formats, etc.
-##include "mem.isa"
-
-// Branch/jump instruction templates, formats, etc.
-##include "branch.isa"
-
-// PAL instruction templates, formats, etc.
-##include "pal.isa"
-
-// Opcdec fault instruction templates, formats, etc.
-##include "opcdec.isa"
-
-// Unimplemented instruction templates, formats, etc.
-##include "unimp.isa"
-
-// Unknown instruction templates, formats, etc.
-##include "unknown.isa"
-
-// Execution utility functions
-##include "util.isa"
-
-// The actual decoder
-##include "decoder.isa"
+++ /dev/null
-// -*- mode:c++ -*-
-
-// Copyright (c) 2003-2005 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Steve Reinhardt
-// Kevin Lim
-
-////////////////////////////////////////////////////////////////////
-//
-// Memory-format instructions: LoadAddress, Load, Store
-//
-
-output header {{
- /**
- * Base class for general Alpha memory-format instructions.
- */
- class Memory : public AlphaStaticInst
- {
- protected:
-
- /// Memory request flags. See mem_req_base.hh.
- Request::Flags memAccessFlags;
-
- /// Constructor
- Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
- : AlphaStaticInst(mnem, _machInst, __opClass)
- {
- }
-
- std::string generateDisassembly(
- Addr pc, const SymbolTable *symtab) const override;
- };
-
- /**
- * Base class for memory-format instructions using a 32-bit
- * displacement (i.e. most of them).
- */
- class MemoryDisp32 : public Memory
- {
- protected:
- /// Displacement for EA calculation (signed).
- int32_t disp;
-
- /// Constructor.
- MemoryDisp32(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
- : Memory(mnem, _machInst, __opClass),
- disp(MEMDISP)
- {
- }
- };
-
-
- /**
- * Base class for a few miscellaneous memory-format insts
- * that don't interpret the disp field: wh64, fetch, fetch_m, ecb.
- * None of these instructions has a destination register either.
- */
- class MemoryNoDisp : public Memory
- {
- protected:
- /// Constructor
- MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
- : Memory(mnem, _machInst, __opClass)
- {
- }
-
- std::string generateDisassembly(
- Addr pc, const SymbolTable *symtab) const override;
- };
-}};
-
-
-output decoder {{
- std::string
- Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
- flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
- }
-
- std::string
- MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- return csprintf("%-10s (r%d)", mnemonic, RB);
- }
-}};
-
-def format LoadAddress(code) {{
- iop = InstObjParams(name, Name, 'MemoryDisp32', code)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
-}};
-
-
-def template LoadStoreDeclare {{
- /**
- * Static instruction class for "%(mnemonic)s".
- */
- class %(class_name)s : public %(base_class)s
- {
- public:
-
- /// Constructor.
- %(class_name)s(ExtMachInst machInst);
-
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
- Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
- };
-}};
-
-def template LoadStoreConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst)
- : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
- {
- %(constructor)s;
- }
-}};
-
-
-def template LoadExecute {{
- Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
- {
- Addr EA;
- Fault fault = NoFault;
-
- %(fp_enable_check)s;
- %(op_decl)s;
- %(op_rd)s;
- %(ea_code)s;
-
- if (fault == NoFault) {
- fault = readMemAtomicLE(xc, traceData, EA, Mem, memAccessFlags);
- %(memacc_code)s;
- }
-
- if (fault == NoFault) {
- %(op_wb)s;
- }
-
- return fault;
- }
-}};
-
-
-def template LoadInitiateAcc {{
- Fault %(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
- {
- Addr EA;
- Fault fault = NoFault;
-
- %(fp_enable_check)s;
- %(op_src_decl)s;
- %(op_rd)s;
- %(ea_code)s;
-
- if (fault == NoFault) {
- fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags);
- }
-
- return fault;
- }
-}};
-
-
-def template LoadCompleteAcc {{
- Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
- {
- Fault fault = NoFault;
-
- %(fp_enable_check)s;
- %(op_decl)s;
-
- getMemLE(pkt, Mem, traceData);
-
- if (fault == NoFault) {
- %(memacc_code)s;
- }
-
- if (fault == NoFault) {
- %(op_wb)s;
- }
-
- return fault;
- }
-}};
-
-
-def template StoreExecute {{
- Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
- {
- Addr EA;
- Fault fault = NoFault;
-
- %(fp_enable_check)s;
- %(op_decl)s;
- %(op_rd)s;
- %(ea_code)s;
-
- if (fault == NoFault) {
- %(memacc_code)s;
- }
-
- if (fault == NoFault) {
- fault = writeMemAtomicLE(xc, traceData, Mem, EA,
- memAccessFlags, NULL);
- }
-
- if (fault == NoFault) {
- %(postacc_code)s;
- }
-
- if (fault == NoFault) {
- %(op_wb)s;
- }
-
- return fault;
- }
-}};
-
-def template StoreCondExecute {{
- Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
- {
- Addr EA;
- Fault fault = NoFault;
- uint64_t write_result = 0;
-
- %(fp_enable_check)s;
- %(op_decl)s;
- %(op_rd)s;
- %(ea_code)s;
-
- if (fault == NoFault) {
- %(memacc_code)s;
- }
-
- if (fault == NoFault) {
- fault = writeMemAtomicLE(xc, traceData, Mem, EA,
- memAccessFlags, &write_result);
- }
-
- if (fault == NoFault) {
- %(postacc_code)s;
- }
-
- if (fault == NoFault) {
- %(op_wb)s;
- }
-
- return fault;
- }
-}};
-
-def template StoreInitiateAcc {{
- Fault %(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
- {
- Addr EA;
- Fault fault = NoFault;
-
- %(fp_enable_check)s;
- %(op_decl)s;
- %(op_rd)s;
- %(ea_code)s;
-
- if (fault == NoFault) {
- %(memacc_code)s;
- }
-
- if (fault == NoFault) {
- fault = writeMemTimingLE(xc, traceData, Mem, EA,
- memAccessFlags, NULL);
- }
-
- return fault;
- }
-}};
-
-
-def template StoreCompleteAcc {{
- Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
- {
- return NoFault;
- }
-}};
-
-
-def template StoreCondCompleteAcc {{
- Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
- {
- Fault fault = NoFault;
-
- %(fp_enable_check)s;
- %(op_dest_decl)s;
-
- uint64_t write_result = pkt->req->getExtraData();
-
- if (fault == NoFault) {
- %(postacc_code)s;
- }
-
- if (fault == NoFault) {
- %(op_wb)s;
- }
-
- return fault;
- }
-}};
-
-
-def template MiscExecute {{
- Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
- {
- Addr EA M5_VAR_USED;
- Fault fault = NoFault;
-
- %(fp_enable_check)s;
- %(op_decl)s;
- %(op_rd)s;
- %(ea_code)s;
-
- warn_once("Prefetch instructions in Alpha do not do anything\n");
- if (fault == NoFault) {
- %(memacc_code)s;
- }
-
- return NoFault;
- }
-}};
-
-// Prefetches in Alpha don't actually do anything
-// They just build an effective address and complete
-def template MiscInitiateAcc {{
- Fault %(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
- {
- warn("initiateAcc undefined: Misc instruction does not support split "
- "access method!");
- return NoFault;
- }
-}};
-
-
-def template MiscCompleteAcc {{
- Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
- {
- warn("completeAcc undefined: Misc instruction does not support split "
- "access method!");
-
- return NoFault;
- }
-}};
-
-
-// load instructions use Ra as dest, so check for
-// Ra == 31 to detect nops
-def template LoadNopCheckDecode {{
- {
- AlphaStaticInst *i = new %(class_name)s(machInst);
- if (RA == 31) {
- i = makeNop(i);
- }
- return i;
- }
-}};
-
-
-// for some load instructions, Ra == 31 indicates a prefetch (not a nop)
-def template LoadPrefetchCheckDecode {{
- {
- if (RA != 31) {
- return new %(class_name)s(machInst);
- }
- else {
- return new %(class_name)sPrefetch(machInst);
- }
- }
-}};
-
-
-let {{
-def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
- postacc_code = '', base_class = 'MemoryDisp32',
- decode_template = BasicDecode, exec_template_base = ''):
- # Make sure flags are in lists (convert to lists if not).
- mem_flags = makeList(mem_flags)
- inst_flags = makeList(inst_flags)
-
- iop = InstObjParams(name, Name, base_class,
- { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code },
- inst_flags)
-
- if mem_flags:
- mem_flags = [ 'Request::%s' % flag for flag in mem_flags ]
- s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
- iop.constructor += s
-
- # select templates
-
- # The InitiateAcc template is the same for StoreCond templates as the
- # corresponding Store template..
- StoreCondInitiateAcc = StoreInitiateAcc
-
- fullExecTemplate = eval(exec_template_base + 'Execute')
- initiateAccTemplate = eval(exec_template_base + 'InitiateAcc')
- completeAccTemplate = eval(exec_template_base + 'CompleteAcc')
-
- # (header_output, decoder_output, decode_block, exec_output)
- return (LoadStoreDeclare.subst(iop),
- LoadStoreConstructor.subst(iop),
- decode_template.subst(iop),
- fullExecTemplate.subst(iop)
- + initiateAccTemplate.subst(iop)
- + completeAccTemplate.subst(iop))
-}};
-
-def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }},
- mem_flags = [], inst_flags = []) {{
- (header_output, decoder_output, decode_block, exec_output) = \
- LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
- decode_template = LoadNopCheckDecode,
- exec_template_base = 'Load')
-}};
-
-
-// Note that the flags passed in apply only to the prefetch version
-def format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }},
- mem_flags = [], pf_flags = [], inst_flags = []) {{
- # declare the load instruction object and generate the decode block
- (header_output, decoder_output, decode_block, exec_output) = \
- LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
- decode_template = LoadPrefetchCheckDecode,
- exec_template_base = 'Load')
-
- # Declare the prefetch instruction object.
-
- # Make sure flag args are lists so we can mess with them.
- mem_flags = makeList(mem_flags)
- pf_flags = makeList(pf_flags)
- inst_flags = makeList(inst_flags)
-
- pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
- pf_inst_flags = inst_flags
-
- (pf_header_output, pf_decoder_output, _, pf_exec_output) = \
- LoadStoreBase(name, Name + 'Prefetch', ea_code, ';',
- pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
-
- header_output += pf_header_output
- decoder_output += pf_decoder_output
- exec_output += pf_exec_output
-}};
-
-
-def format Store(memacc_code, ea_code = {{ EA = Rb + disp; }},
- mem_flags = [], inst_flags = []) {{
- (header_output, decoder_output, decode_block, exec_output) = \
- LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
- exec_template_base = 'Store')
-}};
-
-
-def format StoreCond(memacc_code, postacc_code,
- ea_code = {{ EA = Rb + disp; }},
- mem_flags = [], inst_flags = []) {{
- (header_output, decoder_output, decode_block, exec_output) = \
- LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
- postacc_code, exec_template_base = 'StoreCond')
-}};
-
-
-// Use 'MemoryNoDisp' as base: for wh64, fetch, ecb
-def format MiscPrefetch(ea_code, memacc_code,
- mem_flags = [], inst_flags = []) {{
- (header_output, decoder_output, decode_block, exec_output) = \
- LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
- base_class = 'MemoryNoDisp', exec_template_base = 'Misc')
-}};
-
-
+++ /dev/null
-// -*- mode:c++ -*-
-
-// Copyright (c) 2003-2005 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Kevin Lim
-
-////////////////////////////////////////////////////////////////////
-//
-// OPCDEC fault instructions
-//
-
-output header {{
- /**
- * Static instruction class for instructions that cause an OPCDEC fault
- * when executed. This is currently only for PAL mode instructions
- * executed in non-PAL mode.
- */
- class OpcdecFault : public AlphaStaticInst
- {
- public:
- /// Constructor
- OpcdecFault(ExtMachInst _machInst)
- : AlphaStaticInst("opcdec fault", _machInst, No_OpClass)
- {
- }
-
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
-
- std::string generateDisassembly(
- Addr pc, const SymbolTable *symtab) const override;
- };
-}};
-
-output decoder {{
- std::string
- OpcdecFault::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
- " OPCDEC fault", machInst, OPCODE);
- }
-}};
-
-output exec {{
- Fault
- OpcdecFault::execute(ExecContext *xc, Trace::InstRecord *traceData) const
- {
- return std::make_shared<UnimplementedOpcodeFault>();
- }
-}};
-
-def format OpcdecFault() {{
- decode_block = 'return new OpcdecFault(machInst);\n'
-}};
-
+++ /dev/null
-// -*- mode:c++ -*-
-
-// Copyright (c) 2003-2005 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Steve Reinhardt
-
-////////////////////////////////////////////////////////////////////
-//
-// PAL calls & PAL-specific instructions
-//
-
-output header {{
- /**
- * Base class for emulated call_pal calls (used only in
- * non-full-system mode).
- */
- class EmulatedCallPal : public AlphaStaticInst
- {
- protected:
-
- /// Constructor.
- EmulatedCallPal(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass)
- : AlphaStaticInst(mnem, _machInst, __opClass)
- {
- }
-
- std::string generateDisassembly(
- Addr pc, const SymbolTable *symtab) const override;
- };
-}};
-
-output decoder {{
- std::string
- EmulatedCallPal::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- return csprintf("%-10s %s", "call_pal", mnemonic);
- }
-}};
-
-def format EmulatedCallPal(code, *flags) {{
- iop = InstObjParams(name, Name, 'EmulatedCallPal', code, flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
-}};
-
-output header {{
- /**
- * Base class for full-system-mode call_pal instructions.
- * Probably could turn this into a leaf class and get rid of the
- * parser template.
- */
- class CallPalBase : public AlphaStaticInst
- {
- protected:
- int palFunc; ///< Function code part of instruction
- int palOffset; ///< Target PC, offset from IPR_PAL_BASE
- bool palValid; ///< is the function code valid?
- bool palPriv; ///< is this call privileged?
-
- /// Constructor.
- CallPalBase(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass);
-
- std::string generateDisassembly(
- Addr pc, const SymbolTable *symtab) const override;
- };
-}};
-
-output decoder {{
- inline
- CallPalBase::CallPalBase(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass)
- : AlphaStaticInst(mnem, _machInst, __opClass),
- palFunc(PALFUNC)
- {
- // From the 21164 HRM (paraphrased):
- // Bit 7 of the function code (mask 0x80) indicates
- // whether the call is privileged (bit 7 == 0) or
- // unprivileged (bit 7 == 1). The privileged call table
- // starts at 0x2000, the unprivielged call table starts at
- // 0x3000. Bits 5-0 (mask 0x3f) are used to calculate the
- // offset.
- const int palPrivMask = 0x80;
- const int palOffsetMask = 0x3f;
-
- // Pal call is invalid unless all other bits are 0
- palValid = ((machInst & ~(palPrivMask | palOffsetMask)) == 0);
- palPriv = ((machInst & palPrivMask) == 0);
- int shortPalFunc = (machInst & palOffsetMask);
- // Add 1 to base to set pal-mode bit
- palOffset = (palPriv ? 0x2001 : 0x3001) + (shortPalFunc << 6);
- }
-
- std::string
- CallPalBase::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- return csprintf("%-10s %#x", "call_pal", palFunc);
- }
-}};
-
-def format CallPal(code, *flags) {{
- iop = InstObjParams(name, Name, 'CallPalBase', code, flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
-}};
-
-////////////////////////////////////////////////////////////////////
-//
-// hw_ld, hw_st
-//
-
-output header {{
- /**
- * Base class for hw_ld and hw_st.
- */
- class HwLoadStore : public Memory
- {
- protected:
-
- /// Displacement for EA calculation (signed).
- int16_t disp;
-
- /// Constructor
- HwLoadStore(const char *mnem, ExtMachInst _machInst, OpClass __opClass);
-
- std::string generateDisassembly(
- Addr pc, const SymbolTable *symtab) const override;
- };
-}};
-
-
-output decoder {{
- inline
- HwLoadStore::HwLoadStore(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass)
- : Memory(mnem, _machInst, __opClass), disp(HW_LDST_DISP)
- {
- memAccessFlags.clear();
- if (HW_LDST_PHYS) memAccessFlags.set(Request::PHYSICAL);
- if (HW_LDST_ALT) memAccessFlags.set(AlphaRequestFlags::ALTMODE);
- if (HW_LDST_VPTE) memAccessFlags.set(AlphaRequestFlags::VPTE);
- if (HW_LDST_LOCK) memAccessFlags.set(Request::LLSC);
- }
-
- std::string
- HwLoadStore::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- // HW_LDST_LOCK and HW_LDST_COND are the same bit.
- const char *lock_str =
- (HW_LDST_LOCK) ? (flags[IsLoad] ? ",LOCK" : ",COND") : "";
-
- return csprintf("%-10s r%d,%d(r%d)%s%s%s%s%s",
- mnemonic, RA, disp, RB,
- HW_LDST_PHYS ? ",PHYS" : "",
- HW_LDST_ALT ? ",ALT" : "",
- HW_LDST_QUAD ? ",QUAD" : "",
- HW_LDST_VPTE ? ",VPTE" : "",
- lock_str);
- }
-}};
-
-def format HwLoad(ea_code, memacc_code, class_ext, *flags) {{
- (header_output, decoder_output, decode_block, exec_output) = \
- LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
- mem_flags = [], inst_flags = flags,
- base_class = 'HwLoadStore', exec_template_base = 'Load')
-}};
-
-
-def format HwStore(ea_code, memacc_code, class_ext, *flags) {{
- (header_output, decoder_output, decode_block, exec_output) = \
- LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
- mem_flags = [], inst_flags = flags,
- base_class = 'HwLoadStore', exec_template_base = 'Store')
-}};
-
-
-def format HwStoreCond(ea_code, memacc_code, postacc_code, class_ext,
- *flags) {{
- (header_output, decoder_output, decode_block, exec_output) = \
- LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
- postacc_code, mem_flags = [], inst_flags = flags,
- base_class = 'HwLoadStore')
-}};
-
-
-output header {{
- /**
- * Base class for hw_mfpr and hw_mtpr.
- */
- class HwMoveIPR : public AlphaStaticInst
- {
- protected:
- /// Index of internal processor register.
- int ipr_index;
-
- /// Constructor
- HwMoveIPR(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
- : AlphaStaticInst(mnem, _machInst, __opClass),
- ipr_index(HW_IPR_IDX)
- {
- }
-
- std::string generateDisassembly(
- Addr pc, const SymbolTable *symtab) const override;
- };
-}};
-
-output decoder {{
- std::string
- HwMoveIPR::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- if (_numSrcRegs > 0) {
- // must be mtpr
- return csprintf("%-10s r%d,IPR(%#x)",
- mnemonic, RA, ipr_index);
- }
- else {
- // must be mfpr
- return csprintf("%-10s IPR(%#x),r%d",
- mnemonic, ipr_index, RA);
- }
- }
-}};
-
-def format HwMoveIPR(code, *flags) {{
- all_flags = ['IprAccessOp']
- all_flags += flags
- iop = InstObjParams(name, Name, 'HwMoveIPR', code, all_flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
-}};
-
-
+++ /dev/null
-// -*- mode:c++ -*-
-
-// Copyright (c) 2003-2005 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Steve Reinhardt
-
-////////////////////////////////////////////////////////////////////
-//
-// Unimplemented instructions
-//
-
-output header {{
- /**
- * Static instruction class for unimplemented instructions that
- * cause simulator termination. Note that these are recognized
- * (legal) instructions that the simulator does not support; the
- * 'Unknown' class is used for unrecognized/illegal instructions.
- * This is a leaf class.
- */
- class FailUnimplemented : public AlphaStaticInst
- {
- public:
- /// Constructor
- FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst)
- : AlphaStaticInst(_mnemonic, _machInst, No_OpClass)
- {
- // don't call execute() (which panics) if we're on a
- // speculative path
- flags[IsNonSpeculative] = true;
- }
-
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
-
- std::string generateDisassembly(
- Addr pc, const SymbolTable *symtab) const override;
- };
-
- /**
- * Base class for unimplemented instructions that cause a warning
- * to be printed (but do not terminate simulation). This
- * implementation is a little screwy in that it will print a
- * warning for each instance of a particular unimplemented machine
- * instruction, not just for each unimplemented opcode. Should
- * probably make the 'warned' flag a static member of the derived
- * class.
- */
- class WarnUnimplemented : public AlphaStaticInst
- {
- private:
- /// Have we warned on this instruction yet?
- mutable bool warned;
-
- public:
- /// Constructor
- WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst)
- : AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false)
- {
- // don't call execute() (which panics) if we're on a
- // speculative path
- flags[IsNonSpeculative] = true;
- }
-
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
-
- std::string generateDisassembly(
- Addr pc, const SymbolTable *symtab) const override;
- };
-}};
-
-output decoder {{
- std::string
- FailUnimplemented::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- return csprintf("%-10s (unimplemented)", mnemonic);
- }
-
- std::string
- WarnUnimplemented::generateDisassembly(Addr pc,
- const SymbolTable *symtab) const
- {
- return csprintf("%-10s (unimplemented)", mnemonic);
- }
-}};
-
-output exec {{
- Fault
- FailUnimplemented::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
- {
- panic("attempt to execute unimplemented instruction '%s' "
- "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
- return std::make_shared<UnimplementedOpcodeFault>();
- }
-
- Fault
- WarnUnimplemented::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
- {
- if (!warned) {
- warn("instruction '%s' unimplemented\n", mnemonic);
- warned = true;
- }
-
- return NoFault;
- }
-}};
-
-
-def format FailUnimpl() {{
- iop = InstObjParams(name, 'FailUnimplemented')
- decode_block = BasicDecodeWithMnemonic.subst(iop)
-}};
-
-def format WarnUnimpl() {{
- iop = InstObjParams(name, 'WarnUnimplemented')
- decode_block = BasicDecodeWithMnemonic.subst(iop)
-}};
-
-output header {{
- /**
- * Static instruction class for unknown (illegal) instructions.
- * These cause simulator termination if they are executed in a
- * non-speculative mode. This is a leaf class.
- */
- class Unknown : public AlphaStaticInst
- {
- public:
- /// Constructor
- Unknown(ExtMachInst _machInst)
- : AlphaStaticInst("unknown", _machInst, No_OpClass)
- {
- // don't call execute() (which panics) if we're on a
- // speculative path
- flags[IsNonSpeculative] = true;
- }
-
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
-
- std::string generateDisassembly(
- Addr pc, const SymbolTable *symtab) const override;
- };
-}};
-
+++ /dev/null
-// -*- mode:c++ -*-
-
-// Copyright (c) 2003-2005 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Steve Reinhardt
-
-////////////////////////////////////////////////////////////////////
-//
-// Unknown instructions
-//
-
-output decoder {{
- std::string
- Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- return csprintf("%-10s (inst 0x%x, opcode 0x%x)",
- "unknown", machInst, OPCODE);
- }
-}};
-
-output exec {{
- Fault
- Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const
- {
- panic("attempt to execute unknown instruction "
- "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
- return std::make_shared<UnimplementedOpcodeFault>();
- }
-}};
-
-def format Unknown() {{
- decode_block = 'return new Unknown(machInst);\n'
-}};
-
+++ /dev/null
-// -*- mode:c++ -*-
-
-// Copyright (c) 2003-2005 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Steve Reinhardt
-
-////////////////////////////////////////////////////////////////////
-//
-// Utility functions for execute methods
-//
-
-output exec {{
-
- /// Return opa + opb, summing carry into third arg.
- inline uint64_t
- addc(uint64_t opa, uint64_t opb, int &carry)
- {
- uint64_t res = opa + opb;
- if (res < opa || res < opb)
- ++carry;
- return res;
- }
-
- /// Multiply two 64-bit values (opa * opb), returning the 128-bit
- /// product in res_hi and res_lo.
- inline void
- mul128(uint64_t opa, uint64_t opb, uint64_t &res_hi, uint64_t &res_lo)
- {
- // do a 64x64 --> 128 multiply using four 32x32 --> 64 multiplies
- uint64_t opa_hi = opa<63:32>;
- uint64_t opa_lo = opa<31:0>;
- uint64_t opb_hi = opb<63:32>;
- uint64_t opb_lo = opb<31:0>;
-
- res_lo = opa_lo * opb_lo;
-
- // The middle partial products logically belong in bit
- // positions 95 to 32. Thus the lower 32 bits of each product
- // sum into the upper 32 bits of the low result, while the
- // upper 32 sum into the low 32 bits of the upper result.
- uint64_t partial1 = opa_hi * opb_lo;
- uint64_t partial2 = opa_lo * opb_hi;
-
- uint64_t partial1_lo = partial1<31:0> << 32;
- uint64_t partial1_hi = partial1<63:32>;
- uint64_t partial2_lo = partial2<31:0> << 32;
- uint64_t partial2_hi = partial2<63:32>;
-
- // Add partial1_lo and partial2_lo to res_lo, keeping track
- // of any carries out
- int carry_out = 0;
- res_lo = addc(partial1_lo, res_lo, carry_out);
- res_lo = addc(partial2_lo, res_lo, carry_out);
-
- // Now calculate the high 64 bits...
- res_hi = (opa_hi * opb_hi) + partial1_hi + partial2_hi + carry_out;
- }
-
- /// Map 8-bit S-floating exponent to 11-bit T-floating exponent.
- /// See Table 2-2 of Alpha AHB.
- inline int
- map_s(int old_exp)
- {
- int hibit = old_exp<7:>;
- int lobits = old_exp<6:0>;
-
- if (hibit == 1) {
- return (lobits == 0x7f) ? 0x7ff : (0x400 | lobits);
- }
- else {
- return (lobits == 0) ? 0 : (0x380 | lobits);
- }
- }
-
- /// Convert a 32-bit S-floating value to the equivalent 64-bit
- /// representation to be stored in an FP reg.
- inline uint64_t
- s_to_t(uint32_t s_val)
- {
- uint64_t tmp = s_val;
- return (tmp<31:> << 63 // sign bit
- | (uint64_t)map_s(tmp<30:23>) << 52 // exponent
- | tmp<22:0> << 29); // fraction
- }
-
- /// Convert a 64-bit T-floating value to the equivalent 32-bit
- /// S-floating representation to be stored in memory.
- inline int32_t
- t_to_s(uint64_t t_val)
- {
- return (t_val<63:62> << 30 // sign bit & hi exp bit
- | t_val<58:29>); // rest of exp & fraction
- }
-}};
-
+++ /dev/null
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- * Gabe Black
- */
-
-#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__
-#define __ARCH_ALPHA_ISA_TRAITS_HH__
-
-#include "arch/alpha/ipr.hh"
-#include "arch/alpha/types.hh"
-#include "base/types.hh"
-#include "cpu/static_inst_fwd.hh"
-
-namespace AlphaISA {
-
-const ByteOrder GuestByteOrder = LittleEndianByteOrder;
-
-StaticInstPtr decodeInst(ExtMachInst);
-
-const Addr PageShift = 13;
-const Addr PageBytes = ULL(1) << PageShift;
-const Addr PageMask = ~(PageBytes - 1);
-const Addr PageOffset = PageBytes - 1;
-
-////////////////////////////////////////////////////////////////////////
-//
-// Translation stuff
-//
-
-const Addr PteShift = 3;
-const Addr NPtePageShift = PageShift - PteShift;
-const Addr NPtePage = ULL(1) << NPtePageShift;
-const Addr PteMask = NPtePage - 1;
-
-// User Virtual
-const Addr USegBase = ULL(0x0);
-const Addr USegEnd = ULL(0x000003ffffffffff);
-
-// Kernel Direct Mapped
-const Addr K0SegBase = ULL(0xfffffc0000000000);
-const Addr K0SegEnd = ULL(0xfffffdffffffffff);
-
-// Kernel Virtual
-const Addr K1SegBase = ULL(0xfffffe0000000000);
-const Addr K1SegEnd = ULL(0xffffffffffffffff);
-
-////////////////////////////////////////////////////////////////////////
-//
-// Interrupt levels
-//
-enum InterruptLevels
-{
- INTLEVEL_SOFTWARE_MIN = 4,
- INTLEVEL_SOFTWARE_MAX = 19,
-
- INTLEVEL_EXTERNAL_MIN = 20,
- INTLEVEL_EXTERNAL_MAX = 34,
-
- INTLEVEL_IRQ0 = 20,
- INTLEVEL_IRQ1 = 21,
- INTINDEX_ETHERNET = 0,
- INTINDEX_SCSI = 1,
- INTLEVEL_IRQ2 = 22,
- INTLEVEL_IRQ3 = 23,
-
- INTLEVEL_SERIAL = 33,
-
- NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
-};
-
-// EV5 modes
-enum mode_type
-{
- mode_kernel = 0, // kernel
- mode_executive = 1, // executive (unused by unix)
- mode_supervisor = 2, // supervisor (unused by unix)
- mode_user = 3, // user mode
- mode_number // number of modes
-};
-
-const int MachineBytes = 8;
-
-// Memory accesses cannot be unaligned
-const bool HasUnalignedMemAcc = false;
-
-const bool CurThreadInfoImplemented = true;
-const int CurThreadInfoReg = AlphaISA::IPR_PALtemp23;
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
+++ /dev/null
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Lisa Hsu
- * Nathan Binkert
- */
-
-#include "arch/alpha/kernel_stats.hh"
-
-#include <map>
-#include <stack>
-#include <string>
-
-#include "arch/alpha/osfpal.hh"
-#include "arch/generic/linux/threadinfo.hh"
-#include "base/trace.hh"
-#include "cpu/thread_context.hh"
-#include "debug/Context.hh"
-#include "sim/system.hh"
-
-using namespace std;
-using namespace Stats;
-
-namespace AlphaISA {
-namespace Kernel {
-
-const char *modestr[] = { "kernel", "user", "idle" };
-
-Statistics::Statistics()
- : ::Kernel::Statistics(),
- idleProcess((Addr)-1), themode(kernel), lastModeTick(0),
- iplLast(0), iplLastTick(0)
-{
-}
-
-void
-Statistics::regStats(const string &_name)
-{
- ::Kernel::Statistics::regStats(_name);
-
- _callpal
- .init(256)
- .name(name() + ".callpal")
- .desc("number of callpals executed")
- .flags(total | pdf | nozero | nonan)
- ;
-
- for (int i = 0; i < PAL::NumCodes; ++i) {
- const char *str = PAL::name(i);
- if (str)
- _callpal.subname(i, str);
- }
-
- _hwrei
- .name(name() + ".inst.hwrei")
- .desc("number of hwrei instructions executed")
- ;
-
- _mode
- .init(cpu_mode_num)
- .name(name() + ".mode_switch")
- .desc("number of protection mode switches")
- ;
-
- for (int i = 0; i < cpu_mode_num; ++i)
- _mode.subname(i, modestr[i]);
-
- _modeGood
- .init(cpu_mode_num)
- .name(name() + ".mode_good")
- ;
-
- for (int i = 0; i < cpu_mode_num; ++i)
- _modeGood.subname(i, modestr[i]);
-
- _modeFraction
- .name(name() + ".mode_switch_good")
- .desc("fraction of useful protection mode switches")
- .flags(total)
- ;
-
- for (int i = 0; i < cpu_mode_num; ++i)
- _modeFraction.subname(i, modestr[i]);
-
- _modeFraction = _modeGood / _mode;
-
- _modeTicks
- .init(cpu_mode_num)
- .name(name() + ".mode_ticks")
- .desc("number of ticks spent at the given mode")
- .flags(pdf)
- ;
- for (int i = 0; i < cpu_mode_num; ++i)
- _modeTicks.subname(i, modestr[i]);
-
- _swap_context
- .name(name() + ".swap_context")
- .desc("number of times the context was actually changed")
- ;
-
- _iplCount
- .init(32)
- .name(name() + ".ipl_count")
- .desc("number of times we switched to this ipl")
- .flags(total | pdf | nozero | nonan)
- ;
-
- _iplGood
- .init(32)
- .name(name() + ".ipl_good")
- .desc("number of times we switched to this ipl from a different ipl")
- .flags(total | pdf | nozero | nonan)
- ;
-
- _iplTicks
- .init(32)
- .name(name() + ".ipl_ticks")
- .desc("number of cycles we spent at this ipl")
- .flags(total | pdf | nozero | nonan)
- ;
-
- _iplUsed
- .name(name() + ".ipl_used")
- .desc("fraction of swpipl calls that actually changed the ipl")
- .flags(total | nozero | nonan)
- ;
-
- _iplUsed = _iplGood / _iplCount;
-}
-
-void
-Statistics::setIdleProcess(Addr idlepcbb, ThreadContext *tc)
-{
- assert(themode == kernel);
- idleProcess = idlepcbb;
- themode = idle;
- changeMode(themode, tc);
-}
-
-void
-Statistics::changeMode(cpu_mode newmode, ThreadContext *tc)
-{
- _mode[newmode]++;
-
- if (newmode == themode)
- return;
-
- DPRINTF(Context, "old mode=%s new mode=%s pid=%d\n",
- modestr[themode], modestr[newmode],
- Linux::ThreadInfo(tc).curTaskPID());
-
- _modeGood[newmode]++;
- _modeTicks[themode] += curTick() - lastModeTick;
-
- lastModeTick = curTick();
- themode = newmode;
-}
-
-void
-Statistics::mode(cpu_mode newmode, ThreadContext *tc)
-{
- Addr pcbb = tc->readMiscRegNoEffect(IPR_PALtemp23);
-
- if (newmode == kernel && pcbb == idleProcess)
- newmode = idle;
-
- changeMode(newmode, tc);
-}
-
-void
-Statistics::context(Addr oldpcbb, Addr newpcbb, ThreadContext *tc)
-{
- assert(themode != user);
-
- _swap_context++;
- changeMode(newpcbb == idleProcess ? idle : kernel, tc);
-
- DPRINTF(Context, "Context Switch old pid=%d new pid=%d\n",
- Linux::ThreadInfo(tc, oldpcbb).curTaskPID(),
- Linux::ThreadInfo(tc, newpcbb).curTaskPID());
-}
-
-void
-Statistics::callpal(int code, ThreadContext *tc)
-{
- if (!PAL::name(code))
- return;
-
- _callpal[code]++;
-}
-
-void
-Statistics::swpipl(int ipl)
-{
- assert(ipl >= 0 && ipl <= 0x1f && "invalid IPL\n");
-
- _iplCount[ipl]++;
-
- if (ipl == iplLast)
- return;
-
- _iplGood[ipl]++;
- _iplTicks[iplLast] += curTick() - iplLastTick;
- iplLastTick = curTick();
- iplLast = ipl;
-}
-
-void
-Statistics::serialize(CheckpointOut &cp) const
-{
- ::Kernel::Statistics::serialize(cp);
- int exemode = themode;
- SERIALIZE_SCALAR(exemode);
- SERIALIZE_SCALAR(idleProcess);
- SERIALIZE_SCALAR(lastModeTick);
- SERIALIZE_SCALAR(iplLast);
- SERIALIZE_SCALAR(iplLastTick);
-}
-
-void
-Statistics::unserialize(CheckpointIn &cp)
-{
- ::Kernel::Statistics::unserialize(cp);
- int exemode;
- UNSERIALIZE_SCALAR(exemode);
- UNSERIALIZE_SCALAR(idleProcess);
- UNSERIALIZE_SCALAR(lastModeTick);
- themode = (cpu_mode)exemode;
- UNSERIALIZE_SCALAR(iplLast);
- UNSERIALIZE_SCALAR(iplLastTick);
-}
-
-} // namespace Kernel
-} // namespace AlphaISA
+++ /dev/null
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Lisa Hsu
- * Nathan Binkert
- */
-
-#ifndef __ARCH_ALPHA_KERNEL_STATS_HH__
-#define __ARCH_ALPHA_KERNEL_STATS_HH__
-
-#include <map>
-#include <stack>
-#include <string>
-#include <vector>
-
-#include "cpu/static_inst.hh"
-#include "kern/kernel_stats.hh"
-
-class ThreadContext;
-
-namespace AlphaISA {
-namespace Kernel {
-
-enum cpu_mode { kernel, user, idle, cpu_mode_num };
-extern const char *modestr[];
-
-class Statistics : public ::Kernel::Statistics
-{
- protected:
- Addr idleProcess;
- cpu_mode themode;
- Tick lastModeTick;
-
- void changeMode(cpu_mode newmode, ThreadContext *tc);
-
- private:
- Stats::Vector _callpal;
-
- Stats::Scalar _hwrei;
-
- Stats::Vector _mode;
- Stats::Vector _modeGood;
- Stats::Formula _modeFraction;
- Stats::Vector _modeTicks;
-
- Stats::Scalar _swap_context;
-
- Stats::Vector _iplCount;
- Stats::Vector _iplGood;
- Stats::Vector _iplTicks;
- Stats::Formula _iplUsed;
-
- private:
- int iplLast;
- Tick iplLastTick;
-
- public:
- Statistics();
-
- void regStats(const std::string &name) override;
-
- public:
- void mode(cpu_mode newmode, ThreadContext *tc);
- void context(Addr oldpcbb, Addr newpcbb, ThreadContext *tc);
- void callpal(int code, ThreadContext *tc);
- void hwrei() { _hwrei++; }
- void swpipl(int ipl);
-
- void setIdleProcess(Addr idle, ThreadContext *tc);
-
- public:
- void serialize(CheckpointOut &cp) const override;
- void unserialize(CheckpointIn &cp) override;
-};
-
-} // namespace Kernel
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_KERNEL_STATS_HH__
+++ /dev/null
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Korey Sewell
- */
-
-#include "arch/alpha/linux/linux.hh"
-
-#include <fcntl.h>
-#include <sys/mman.h>
-
-#define TARGET AlphaLinux
-#include "kern/linux/flag_tables.hh"
+++ /dev/null
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Korey Sewell
- */
-
-#ifndef __ALPHA_ALPHA_LINUX_LINUX_HH__
-#define __ALPHA_ALPHA_LINUX_LINUX_HH__
-
-#include "arch/alpha/utility.hh"
-#include "kern/linux/linux.hh"
-
-/* AlphaLinux class contains static constants/definitions/misc.
- * structures which are specific to the Linux OS AND the Alpha
- * architecture
- */
-class AlphaLinux : public Linux
-{
- public:
-
- static const ByteOrder byteOrder = LittleEndianByteOrder;
-
- static const int TGT_SIGHUP = 0x000001;
- static const int TGT_SIGINT = 0x000002;
- static const int TGT_SIGQUIT = 0x000003;
- static const int TGT_SIGILL = 0x000004;
- static const int TGT_SIGTRAP = 0x000005;
- static const int TGT_SIGABRT = 0x000006;
- static const int TGT_SIGEMT = 0x000007;
- static const int TGT_SIGFPE = 0x000008;
- static const int TGT_SIGKILL = 0x000009;
- static const int TGT_SIGBUS = 0x00000a;
- static const int TGT_SIGSEGV = 0x00000b;
- static const int TGT_SIGSYS = 0x00000c;
- static const int TGT_SIGPIPE = 0x00000d;
- static const int TGT_SIGALRM = 0x00000e;
- static const int TGT_SIGTERM = 0x00000f;
- static const int TGT_SIGURG = 0x000010;
- static const int TGT_SIGSTOP = 0x000011;
- static const int TGT_SIGTSTP = 0x000012;
- static const int TGT_SIGCONT = 0x000013;
- static const int TGT_SIGCHLD = 0x000014;
- static const int TGT_SIGTTIN = 0x000015;
- static const int TGT_SIGTTOU = 0x000016;
- static const int TGT_SIGIO = 0x000017;
- static const int TGT_SIGXCPU = 0x000018;
- static const int TGT_SIGXFSZ = 0x000019;
- static const int TGT_SIGVTALRM = 0x00001a;
- static const int TGT_SIGPROF = 0x00001b;
- static const int TGT_SIGWINCH = 0x00001c;
- static const int TGT_SIGINFO = 0x00001d;
- static const int TGT_SIGUSR1 = 0x00001e;
- static const int TGT_SIGUSR2 = 0x00001f;
-
- /// This table maps the target open() flags to the corresponding
- /// host open() flags.
- static SyscallFlagTransTable openFlagTable[];
-
- /// Number of entries in openFlagTable[].
- static const int NUM_OPEN_FLAGS;
-
- //@{
- /// open(2) flag values.
- static const int TGT_O_RDONLY = 000000000; //!< O_RDONLY
- static const int TGT_O_WRONLY = 000000001; //!< O_WRONLY
- static const int TGT_O_RDWR = 000000002; //!< O_RDWR
- static const int TGT_O_CREAT = 000001000; //!< O_CREAT
- static const int TGT_O_EXCL = 000004000; //!< O_EXCL
- static const int TGT_O_NOCTTY = 000010000; //!< O_NOCTTY
- static const int TGT_O_TRUNC = 000002000; //!< O_TRUNC
- static const int TGT_O_APPEND = 000000010; //!< O_APPEND
- static const int TGT_O_NONBLOCK = 000000004; //!< O_NONBLOCK
- static const int TGT_O_DSYNC = 000040000; //!< O_DSYNC
- static const int TGT_FASYNC = 000020000; //!< FASYNC
- static const int TGT_O_DIRECT = 002000000; //!< O_DIRECT
- static const int TGT_O_LARGEFILE = 000400000; //!< O_LARGEFILE
- static const int TGT_O_DIRECTORY = 000100000; //!< O_DIRECTORY
- static const int TGT_O_NOFOLLOW = 000200000; //!< O_NOFOLLOW
- static const int TGT_O_NOATIME = 004000000; //!< O_NOATIME
- static const int TGT_O_CLOEXEC = 010000000; //!< O_CLOEXEC
- static const int TGT_O_SYNC = 020040000; //!< O_SYNC
- static const int TGT_O_PATH = 040000000; //!< O_PATH
- //@}
-
- static const unsigned TGT_MAP_SHARED = 0x000001;
- static const unsigned TGT_MAP_PRIVATE = 0x000002;
- static const unsigned TGT_MAP_ANON = 0x000010;
- static const unsigned TGT_MAP_DENYWRITE = 0x002000;
- static const unsigned TGT_MAP_EXECUTABLE = 0x004000;
- static const unsigned TGT_MAP_FILE = 0x000000;
- static const unsigned TGT_MAP_GROWSDOWN = 0x001000;
- static const unsigned TGT_MAP_HUGETLB = 0x100000;
- static const unsigned TGT_MAP_LOCKED = 0x008000;
- static const unsigned TGT_MAP_NONBLOCK = 0x040000;
- static const unsigned TGT_MAP_NORESERVE = 0x010000;
- static const unsigned TGT_MAP_POPULATE = 0x020000;
- static const unsigned TGT_MAP_STACK = 0x080000;
- static const unsigned TGT_MAP_ANONYMOUS = 0x000010;
- static const unsigned TGT_MAP_FIXED = 0x000100;
-
- static const unsigned NUM_MMAP_FLAGS;
-
- //@{
- /// For getsysinfo().
- static const unsigned GSI_PLATFORM_NAME = 103; //!< platform name as string
- static const unsigned GSI_CPU_INFO = 59; //!< CPU information
- static const unsigned GSI_PROC_TYPE = 60; //!< get proc_type
- static const unsigned GSI_MAX_CPU = 30; //!< max # CPUs on machine
- static const unsigned GSI_CPUS_IN_BOX = 55; //!< number of CPUs in system
- static const unsigned GSI_PHYSMEM = 19; //!< Physical memory in KB
- static const unsigned GSI_CLK_TCK = 42; //!< clock freq in Hz
- static const unsigned GSI_IEEE_FP_CONTROL = 45;
- //@}
-
- //@{
- /// For setsysinfo().
- static const unsigned SSI_IEEE_FP_CONTROL = 14; //!< ieee_set_fp_control()
- //@}
-
- //@{
- /// ioctl() command codes.
- static const unsigned TGT_TIOCGETP = 0x40067408;
- static const unsigned TGT_TIOCSETP = 0x80067409;
- static const unsigned TGT_TIOCSETN = 0x8006740a;
- static const unsigned TGT_TIOCSETC = 0x80067411;
- static const unsigned TGT_TIOCGETC = 0x40067412;
- static const unsigned TGT_FIONREAD = 0x4004667f;
- static const unsigned TGT_TCGETS = 0x402c7413;
- static const unsigned TGT_TCGETA = 0x40127417;
- static const unsigned TGT_TCSETAW = 0x80147419; // 2.6.15 kernel
- //@}
-
- static bool
- isTtyReq(unsigned req)
- {
- switch (req) {
- case TGT_TIOCGETP:
- case TGT_TIOCSETP:
- case TGT_TIOCSETN:
- case TGT_TIOCSETC:
- case TGT_TIOCGETC:
- case TGT_TCGETS:
- case TGT_TCGETA:
- case TGT_TCSETAW:
- return true;
- default:
- return false;
- }
- }
-
- /// For table().
- static const int TBL_SYSINFO = 12;
-
- /// Resource constants for getrlimit() (overide some generics).
- static const unsigned TGT_RLIMIT_NPROC = 8;
- static const unsigned TGT_RLIMIT_AS = 7;
- static const unsigned TGT_RLIMIT_NOFILE = 6;
- static const unsigned TGT_RLIMIT_MEMLOCK = 9;
-
- typedef struct {
- int64_t uptime; /* Seconds since boot */
- uint64_t loads[3]; /* 1, 5, and 15 minute load averages */
- uint64_t totalram; /* Total usable main memory size */
- uint64_t freeram; /* Available memory size */
- uint64_t sharedram; /* Amount of shared memory */
- uint64_t bufferram; /* Memory used by buffers */
- uint64_t totalswap; /* Total swap space size */
- uint64_t freeswap; /* swap space still available */
- uint16_t procs; /* Number of current processes */
- uint64_t totalhigh; /* Total high memory size */
- uint64_t freehigh; /* Available high memory size */
- uint64_t mem_unit; /* Memory unit size in bytes */
- } tgt_sysinfo;
-
- // For futex system call
- static const unsigned TGT_EAGAIN = 35;
- static const unsigned TGT_EWOULDBLOCK = TGT_EAGAIN;
-
- static void
- archClone(uint64_t flags,
- Process *pp, Process *cp,
- ThreadContext *ptc, ThreadContext *ctc,
- uint64_t stack, uint64_t tls)
- {
- AlphaISA::copyMiscRegs(ptc, ctc);
- if (stack)
- ctc->setIntReg(AlphaISA::StackPointerReg, stack);
- }
-};
-
-#endif // __ALPHA_ALPHA_LINUX_LINUX_HH__
+++ /dev/null
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- * Ali Saidi
- */
-
-#include "arch/alpha/linux/process.hh"
-
-#include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/linux/linux.hh"
-#include "base/loader/object_file.hh"
-#include "base/trace.hh"
-#include "cpu/thread_context.hh"
-#include "debug/SyscallVerbose.hh"
-#include "kern/linux/linux.hh"
-#include "sim/process.hh"
-#include "sim/syscall_desc.hh"
-#include "sim/syscall_emul.hh"
-
-using namespace std;
-using namespace AlphaISA;
-
-namespace
-{
-
-class AlphaLinuxObjectFileLoader : public Process::Loader
-{
- public:
- Process *
- load(ProcessParams *params, ObjectFile *obj_file) override
- {
- if (obj_file->getArch() != ObjectFile::Alpha)
- return nullptr;
-
- auto opsys = obj_file->getOpSys();
-
- if (opsys == ObjectFile::UnknownOpSys) {
- warn("Unknown operating system; assuming Linux.");
- opsys = ObjectFile::Linux;
- }
-
- if (opsys != ObjectFile::Linux)
- return nullptr;
-
- return new AlphaLinuxProcess(params, obj_file);
- }
-};
-
-AlphaLinuxObjectFileLoader loader;
-
-} // anonymous namespace
-
-/// Target uname() handler.
-static SyscallReturn
-unameFunc(SyscallDesc *desc, int callnum, ThreadContext *tc)
-{
- int index = 0;
- auto process = tc->getProcessPtr();
- TypedBufferArg<Linux::utsname> name(process->getSyscallArg(tc, index));
-
- strcpy(name->sysname, "Linux");
- strcpy(name->nodename, "sim.gem5.org");
- strcpy(name->release, process->release.c_str());
- strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
- strcpy(name->machine, "alpha");
-
- name.copyOut(tc->getVirtProxy());
- return 0;
-}
-
-/// Target osf_getsysyinfo() handler. Even though this call is
-/// borrowed from Tru64, the subcases that get used appear to be
-/// different in practice from those used by Tru64 processes.
-static SyscallReturn
-osf_getsysinfoFunc(SyscallDesc *desc, int callnum, ThreadContext *tc)
-{
- int index = 0;
- auto process = tc->getProcessPtr();
- unsigned op = process->getSyscallArg(tc, index);
- Addr bufPtr = process->getSyscallArg(tc, index);
- // unsigned nbytes = process->getSyscallArg(tc, 2);
-
- switch (op) {
-
- case 45: { // GSI_IEEE_FP_CONTROL
- TypedBufferArg<uint64_t> fpcr(bufPtr);
- // I don't think this exactly matches the HW FPCR
- *fpcr = 0;
- fpcr.copyOut(tc->getVirtProxy());
- return 0;
- }
-
- default:
- cerr << "osf_getsysinfo: unknown op " << op << endl;
- abort();
- break;
- }
-
- return 1;
-}
-
-/// Target osf_setsysinfo() handler.
-static SyscallReturn
-osf_setsysinfoFunc(SyscallDesc *desc, int callnum, ThreadContext *tc)
-{
- int index = 0;
- auto process = tc->getProcessPtr();
- unsigned op = process->getSyscallArg(tc, index);
- Addr bufPtr = process->getSyscallArg(tc, index);
- // unsigned nbytes = process->getSyscallArg(tc, 2);
-
- switch (op) {
-
- case 14: { // SSI_IEEE_FP_CONTROL
- TypedBufferArg<uint64_t> fpcr(bufPtr);
- // I don't think this exactly matches the HW FPCR
- fpcr.copyIn(tc->getVirtProxy());
- DPRINTFR(SyscallVerbose, "osf_setsysinfo(SSI_IEEE_FP_CONTROL): "
- " setting FPCR to 0x%x\n", letoh(*(uint64_t*)fpcr));
- return 0;
- }
-
- default:
- cerr << "osf_setsysinfo: unknown op " << op << endl;
- abort();
- break;
- }
-
- return 1;
-}
-
-
-SyscallDescABI<DefaultSyscallABI> AlphaLinuxProcess::syscallDescs[] = {
- /* 0 */ { "osf_syscall" },
- /* 1 */ { "exit", exitFunc },
- /* 2 */ { "fork" },
- /* 3 */ { "read", readFunc<AlphaLinux> },
- /* 4 */ { "write", writeFunc<AlphaLinux> },
- /* 5 */ { "osf_old_open" },
- /* 6 */ { "close", closeFunc },
- /* 7 */ { "osf_wait4" },
- /* 8 */ { "osf_old_creat" },
- /* 9 */ { "link" },
- /* 10 */ { "unlink", unlinkFunc },
- /* 11 */ { "osf_execve" },
- /* 12 */ { "chdir" },
- /* 13 */ { "fchdir" },
- /* 14 */ { "mknod" },
- /* 15 */ { "chmod", chmodFunc<AlphaLinux> },
- /* 16 */ { "chown", chownFunc },
- /* 17 */ { "brk", brkFunc },
- /* 18 */ { "osf_getfsstat" },
- /* 19 */ { "lseek", lseekFunc },
- /* 20 */ { "getxpid", getpidPseudoFunc },
- /* 21 */ { "osf_mount" },
- /* 22 */ { "umount" },
- /* 23 */ { "setuid", ignoreFunc },
- /* 24 */ { "getxuid", getuidPseudoFunc },
- /* 25 */ { "exec_with_loader" },
- /* 26 */ { "osf_ptrace" },
- /* 27 */ { "osf_nrecvmsg" },
- /* 28 */ { "osf_nsendmsg" },
- /* 29 */ { "osf_nrecvfrom" },
- /* 30 */ { "osf_naccept" },
- /* 31 */ { "osf_ngetpeername" },
- /* 32 */ { "osf_ngetsockname" },
- /* 33 */ { "access" },
- /* 34 */ { "osf_chflags" },
- /* 35 */ { "osf_fchflags" },
- /* 36 */ { "sync" },
- /* 37 */ { "kill" },
- /* 38 */ { "osf_old_stat" },
- /* 39 */ { "setpgid" },
- /* 40 */ { "osf_old_lstat" },
- /* 41 */ { "dup", dupFunc },
- /* 42 */ { "pipe", pipePseudoFunc },
- /* 43 */ { "osf_set_program_attributes" },
- /* 44 */ { "osf_profil" },
- /* 45 */ { "open", openFunc<AlphaLinux> },
- /* 46 */ { "osf_old_sigaction" },
- /* 47 */ { "getxgid", getgidPseudoFunc },
- /* 48 */ { "osf_sigprocmask", ignoreFunc },
- /* 49 */ { "osf_getlogin" },
- /* 50 */ { "osf_setlogin" },
- /* 51 */ { "acct" },
- /* 52 */ { "sigpending" },
- /* 53 */ { "osf_classcntl" },
- /* 54 */ { "ioctl", ioctlFunc<AlphaLinux> },
- /* 55 */ { "osf_reboot" },
- /* 56 */ { "osf_revoke" },
- /* 57 */ { "symlink" },
- /* 58 */ { "readlink", readlinkFunc },
- /* 59 */ { "execve" },
- /* 60 */ { "umask", umaskFunc },
- /* 61 */ { "chroot" },
- /* 62 */ { "osf_old_fstat" },
- /* 63 */ { "getpgrp" },
- /* 64 */ { "getpagesize", getpagesizeFunc },
- /* 65 */ { "osf_mremap" },
- /* 66 */ { "vfork" },
- /* 67 */ { "stat", statFunc<AlphaLinux> },
- /* 68 */ { "lstat", lstatFunc<AlphaLinux> },
- /* 69 */ { "osf_sbrk" },
- /* 70 */ { "osf_sstk" },
- /* 71 */ { "mmap", mmapFunc<AlphaLinux> },
- /* 72 */ { "osf_old_vadvise" },
- /* 73 */ { "munmap", munmapFunc },
- /* 74 */ { "mprotect", ignoreFunc },
- /* 75 */ { "madvise" },
- /* 76 */ { "vhangup" },
- /* 77 */ { "osf_kmodcall" },
- /* 78 */ { "osf_mincore" },
- /* 79 */ { "getgroups" },
- /* 80 */ { "setgroups" },
- /* 81 */ { "osf_old_getpgrp" },
- /* 82 */ { "setpgrp" },
- /* 83 */ { "osf_setitimer" },
- /* 84 */ { "osf_old_wait" },
- /* 85 */ { "osf_table" },
- /* 86 */ { "osf_getitimer" },
- /* 87 */ { "gethostname", gethostnameFunc },
- /* 88 */ { "sethostname" },
- /* 89 */ { "getdtablesize" },
- /* 90 */ { "dup2" },
- /* 91 */ { "fstat", fstatFunc<AlphaLinux> },
- /* 92 */ { "fcntl", fcntlFunc },
- /* 93 */ { "osf_select" },
- /* 94 */ { "poll" },
- /* 95 */ { "fsync" },
- /* 96 */ { "setpriority" },
- /* 97 */ { "socket" },
- /* 98 */ { "connect" },
- /* 99 */ { "accept" },
- /* 100 */ { "getpriority" },
- /* 101 */ { "send" },
- /* 102 */ { "recv" },
- /* 103 */ { "sigreturn" },
- /* 104 */ { "bind" },
- /* 105 */ { "setsockopt" },
- /* 106 */ { "listen" },
- /* 107 */ { "osf_plock" },
- /* 108 */ { "osf_old_sigvec" },
- /* 109 */ { "osf_old_sigblock" },
- /* 110 */ { "osf_old_sigsetmask" },
- /* 111 */ { "sigsuspend" },
- /* 112 */ { "osf_sigstack", ignoreFunc },
- /* 113 */ { "recvmsg" },
- /* 114 */ { "sendmsg" },
- /* 115 */ { "osf_old_vtrace" },
- /* 116 */ { "osf_gettimeofday" },
- /* 117 */ { "osf_getrusage" },
- /* 118 */ { "getsockopt" },
- /* 119 */ { "numa_syscalls" },
- /* 120 */ { "readv" },
- /* 121 */ { "writev", writevFunc<AlphaLinux> },
- /* 122 */ { "osf_settimeofday" },
- /* 123 */ { "fchown", fchownFunc },
- /* 124 */ { "fchmod", fchmodFunc<AlphaLinux> },
- /* 125 */ { "recvfrom" },
- /* 126 */ { "setreuid" },
- /* 127 */ { "setregid" },
- /* 128 */ { "rename", renameFunc },
- /* 129 */ { "truncate", truncateFunc },
- /* 130 */ { "ftruncate", ftruncateFunc },
- /* 131 */ { "flock" },
- /* 132 */ { "setgid" },
- /* 133 */ { "sendto" },
- /* 134 */ { "shutdown" },
- /* 135 */ { "socketpair" },
- /* 136 */ { "mkdir", mkdirFunc },
- /* 137 */ { "rmdir" },
- /* 138 */ { "osf_utimes" },
- /* 139 */ { "osf_old_sigreturn" },
- /* 140 */ { "osf_adjtime" },
- /* 141 */ { "getpeername" },
- /* 142 */ { "osf_gethostid" },
- /* 143 */ { "osf_sethostid" },
- /* 144 */ { "getrlimit", getrlimitFunc<AlphaLinux> },
- /* 145 */ { "setrlimit", ignoreFunc },
- /* 146 */ { "osf_old_killpg" },
- /* 147 */ { "setsid" },
- /* 148 */ { "quotactl" },
- /* 149 */ { "osf_oldquota" },
- /* 150 */ { "getsockname" },
- /* 151 */ { "osf_pread" },
- /* 152 */ { "osf_pwrite" },
- /* 153 */ { "osf_pid_block" },
- /* 154 */ { "osf_pid_unblock" },
- /* 155 */ { "osf_signal_urti" },
- /* 156 */ { "sigaction", ignoreFunc },
- /* 157 */ { "osf_sigwaitprim" },
- /* 158 */ { "osf_nfssvc" },
- /* 159 */ { "osf_getdirentries" },
- /* 160 */ { "osf_statfs" },
- /* 161 */ { "osf_fstatfs" },
- /* 162 */ { "unknown #162" },
- /* 163 */ { "osf_async_daemon" },
- /* 164 */ { "osf_getfh" },
- /* 165 */ { "osf_getdomainname" },
- /* 166 */ { "setdomainname" },
- /* 167 */ { "unknown #167" },
- /* 168 */ { "unknown #168" },
- /* 169 */ { "osf_exportfs" },
- /* 170 */ { "unknown #170" },
- /* 171 */ { "unknown #171" },
- /* 172 */ { "unknown #172" },
- /* 173 */ { "unknown #173" },
- /* 174 */ { "unknown #174" },
- /* 175 */ { "unknown #175" },
- /* 176 */ { "unknown #176" },
- /* 177 */ { "unknown #177" },
- /* 178 */ { "unknown #178" },
- /* 179 */ { "unknown #179" },
- /* 180 */ { "unknown #180" },
- /* 181 */ { "osf_alt_plock" },
- /* 182 */ { "unknown #182" },
- /* 183 */ { "unknown #183" },
- /* 184 */ { "osf_getmnt" },
- /* 185 */ { "unknown #185" },
- /* 186 */ { "unknown #186" },
- /* 187 */ { "osf_alt_sigpending" },
- /* 188 */ { "osf_alt_setsid" },
- /* 189 */ { "unknown #189" },
- /* 190 */ { "unknown #190" },
- /* 191 */ { "unknown #191" },
- /* 192 */ { "unknown #192" },
- /* 193 */ { "unknown #193" },
- /* 194 */ { "unknown #194" },
- /* 195 */ { "unknown #195" },
- /* 196 */ { "unknown #196" },
- /* 197 */ { "unknown #197" },
- /* 198 */ { "unknown #198" },
- /* 199 */ { "osf_swapon" },
- /* 200 */ { "msgctl" },
- /* 201 */ { "msgget" },
- /* 202 */ { "msgrcv" },
- /* 203 */ { "msgsnd" },
- /* 204 */ { "semctl" },
- /* 205 */ { "semget" },
- /* 206 */ { "semop" },
- /* 207 */ { "osf_utsname" },
- /* 208 */ { "lchown" },
- /* 209 */ { "osf_shmat" },
- /* 210 */ { "shmctl" },
- /* 211 */ { "shmdt" },
- /* 212 */ { "shmget" },
- /* 213 */ { "osf_mvalid" },
- /* 214 */ { "osf_getaddressconf" },
- /* 215 */ { "osf_msleep" },
- /* 216 */ { "osf_mwakeup" },
- /* 217 */ { "msync" },
- /* 218 */ { "osf_signal" },
- /* 219 */ { "osf_utc_gettime" },
- /* 220 */ { "osf_utc_adjtime" },
- /* 221 */ { "unknown #221" },
- /* 222 */ { "osf_security" },
- /* 223 */ { "osf_kloadcall" },
- /* 224 */ { "unknown #224" },
- /* 225 */ { "unknown #225" },
- /* 226 */ { "unknown #226" },
- /* 227 */ { "unknown #227" },
- /* 228 */ { "unknown #228" },
- /* 229 */ { "unknown #229" },
- /* 230 */ { "unknown #230" },
- /* 231 */ { "unknown #231" },
- /* 232 */ { "unknown #232" },
- /* 233 */ { "getpgid" },
- /* 234 */ { "getsid" },
- /* 235 */ { "sigaltstack", ignoreFunc },
- /* 236 */ { "osf_waitid" },
- /* 237 */ { "osf_priocntlset" },
- /* 238 */ { "osf_sigsendset" },
- /* 239 */ { "osf_set_speculative" },
- /* 240 */ { "osf_msfs_syscall" },
- /* 241 */ { "osf_sysinfo" },
- /* 242 */ { "osf_uadmin" },
- /* 243 */ { "osf_fuser" },
- /* 244 */ { "osf_proplist_syscall" },
- /* 245 */ { "osf_ntp_adjtime" },
- /* 246 */ { "osf_ntp_gettime" },
- /* 247 */ { "osf_pathconf" },
- /* 248 */ { "osf_fpathconf" },
- /* 249 */ { "unknown #249" },
- /* 250 */ { "osf_uswitch" },
- /* 251 */ { "osf_usleep_thread" },
- /* 252 */ { "osf_audcntl" },
- /* 253 */ { "osf_audgen" },
- /* 254 */ { "sysfs" },
- /* 255 */ { "osf_subsys_info" },
- /* 256 */ { "osf_getsysinfo", osf_getsysinfoFunc },
- /* 257 */ { "osf_setsysinfo", osf_setsysinfoFunc },
- /* 258 */ { "osf_afs_syscall" },
- /* 259 */ { "osf_swapctl" },
- /* 260 */ { "osf_memcntl" },
- /* 261 */ { "osf_fdatasync" },
- /* 262 */ { "unknown #262" },
- /* 263 */ { "unknown #263" },
- /* 264 */ { "unknown #264" },
- /* 265 */ { "unknown #265" },
- /* 266 */ { "unknown #266" },
- /* 267 */ { "unknown #267" },
- /* 268 */ { "unknown #268" },
- /* 269 */ { "unknown #269" },
- /* 270 */ { "unknown #270" },
- /* 271 */ { "unknown #271" },
- /* 272 */ { "unknown #272" },
- /* 273 */ { "unknown #273" },
- /* 274 */ { "unknown #274" },
- /* 275 */ { "unknown #275" },
- /* 276 */ { "unknown #276" },
- /* 277 */ { "unknown #277" },
- /* 278 */ { "unknown #278" },
- /* 279 */ { "unknown #279" },
- /* 280 */ { "unknown #280" },
- /* 281 */ { "unknown #281" },
- /* 282 */ { "unknown #282" },
- /* 283 */ { "unknown #283" },
- /* 284 */ { "unknown #284" },
- /* 285 */ { "unknown #285" },
- /* 286 */ { "unknown #286" },
- /* 287 */ { "unknown #287" },
- /* 288 */ { "unknown #288" },
- /* 289 */ { "unknown #289" },
- /* 290 */ { "unknown #290" },
- /* 291 */ { "unknown #291" },
- /* 292 */ { "unknown #292" },
- /* 293 */ { "unknown #293" },
- /* 294 */ { "unknown #294" },
- /* 295 */ { "unknown #295" },
- /* 296 */ { "unknown #296" },
- /* 297 */ { "unknown #297" },
- /* 298 */ { "unknown #298" },
- /* 299 */ { "unknown #299" },
-/*
- * Linux-specific system calls begin at 300
- */
- /* 300 */ { "bdflush" },
- /* 301 */ { "sethae" },
- /* 302 */ { "mount" },
- /* 303 */ { "old_adjtimex" },
- /* 304 */ { "swapoff" },
- /* 305 */ { "getdents" },
- /* 306 */ { "create_module" },
- /* 307 */ { "init_module" },
- /* 308 */ { "delete_module" },
- /* 309 */ { "get_kernel_syms" },
- /* 310 */ { "syslog" },
- /* 311 */ { "reboot" },
- /* 312 */ { "clone", cloneFunc<AlphaLinux> },
- /* 313 */ { "uselib" },
- /* 314 */ { "mlock" },
- /* 315 */ { "munlock" },
- /* 316 */ { "mlockall" },
- /* 317 */ { "munlockall" },
- /* 318 */ { "sysinfo", sysinfoFunc<AlphaLinux> },
- /* 319 */ { "_sysctl" },
- /* 320 */ { "was sys_idle" },
- /* 321 */ { "oldumount" },
- /* 322 */ { "swapon" },
- /* 323 */ { "times", ignoreFunc },
- /* 324 */ { "personality" },
- /* 325 */ { "setfsuid" },
- /* 326 */ { "setfsgid" },
- /* 327 */ { "ustat" },
- /* 328 */ { "statfs" },
- /* 329 */ { "fstatfs" },
- /* 330 */ { "sched_setparam" },
- /* 331 */ { "sched_getparam" },
- /* 332 */ { "sched_setscheduler" },
- /* 333 */ { "sched_getscheduler" },
- /* 334 */ { "sched_yield" },
- /* 335 */ { "sched_get_priority_max" },
- /* 336 */ { "sched_get_priority_min" },
- /* 337 */ { "sched_rr_get_interval" },
- /* 338 */ { "afs_syscall" },
- /* 339 */ { "uname", unameFunc },
- /* 340 */ { "nanosleep" },
- /* 341 */ { "mremap", mremapFunc<AlphaLinux> },
- /* 342 */ { "nfsservctl" },
- /* 343 */ { "setresuid" },
- /* 344 */ { "getresuid" },
- /* 345 */ { "pciconfig_read" },
- /* 346 */ { "pciconfig_write" },
- /* 347 */ { "query_module" },
- /* 348 */ { "prctl" },
- /* 349 */ { "pread" },
- /* 350 */ { "pwrite" },
- /* 351 */ { "rt_sigreturn" },
- /* 352 */ { "rt_sigaction", ignoreFunc },
- /* 353 */ { "rt_sigprocmask" },
- /* 354 */ { "rt_sigpending" },
- /* 355 */ { "rt_sigtimedwait" },
- /* 356 */ { "rt_sigqueueinfo" },
- /* 357 */ { "rt_sigsuspend" },
- /* 358 */ { "select" },
- /* 359 */ { "gettimeofday", gettimeofdayFunc<AlphaLinux> },
- /* 360 */ { "settimeofday" },
- /* 361 */ { "getitimer" },
- /* 362 */ { "setitimer" },
- /* 363 */ { "utimes", utimesFunc<AlphaLinux> },
- /* 364 */ { "getrusage", getrusageFunc<AlphaLinux> },
- /* 365 */ { "wait4" },
- /* 366 */ { "adjtimex" },
- /* 367 */ { "getcwd", getcwdFunc },
- /* 368 */ { "capget" },
- /* 369 */ { "capset" },
- /* 370 */ { "sendfile" },
- /* 371 */ { "setresgid" },
- /* 372 */ { "getresgid" },
- /* 373 */ { "dipc" },
- /* 374 */ { "pivot_root" },
- /* 375 */ { "mincore" },
- /* 376 */ { "pciconfig_iobase" },
- /* 377 */ { "getdents64" },
- /* 378 */ { "gettid" },
- /* 379 */ { "readahead" },
- /* 380 */ { "security" },
- /* 381 */ { "tkill" },
- /* 382 */ { "setxattr" },
- /* 383 */ { "lsetxattr" },
- /* 384 */ { "fsetxattr" },
- /* 385 */ { "getxattr" },
- /* 386 */ { "lgetxattr" },
- /* 387 */ { "fgetxattr" },
- /* 388 */ { "listxattr" },
- /* 389 */ { "llistxattr" },
- /* 390 */ { "flistxattr" },
- /* 391 */ { "removexattr" },
- /* 392 */ { "lremovexattr" },
- /* 393 */ { "fremovexattr" },
- /* 394 */ { "futex" },
- /* 395 */ { "sched_setaffinity" },
- /* 396 */ { "sched_getaffinity" },
- /* 397 */ { "tuxcall" },
- /* 398 */ { "io_setup" },
- /* 399 */ { "io_destroy" },
- /* 400 */ { "io_getevents" },
- /* 401 */ { "io_submit" },
- /* 402 */ { "io_cancel" },
- /* 403 */ { "unknown #403" },
- /* 404 */ { "unknown #404" },
- /* 405 */ { "exit_group", exitGroupFunc }, // exit all threads...
- /* 406 */ { "lookup_dcookie" },
- /* 407 */ { "sys_epoll_create" },
- /* 408 */ { "sys_epoll_ctl" },
- /* 409 */ { "sys_epoll_wait" },
- /* 410 */ { "remap_file_pages" },
- /* 411 */ { "set_tid_address" },
- /* 412 */ { "restart_syscall" },
- /* 413 */ { "fadvise64" },
- /* 414 */ { "timer_create" },
- /* 415 */ { "timer_settime" },
- /* 416 */ { "timer_gettime" },
- /* 417 */ { "timer_getoverrun" },
- /* 418 */ { "timer_delete" },
- /* 419 */ { "clock_settime" },
- /* 420 */ { "clock_gettime" },
- /* 421 */ { "clock_getres" },
- /* 422 */ { "clock_nanosleep" },
- /* 423 */ { "semtimedop" },
- /* 424 */ { "tgkill" },
- /* 425 */ { "stat64", stat64Func<AlphaLinux> },
- /* 426 */ { "lstat64", lstat64Func<AlphaLinux> },
- /* 427 */ { "fstat64", fstat64Func<AlphaLinux> },
- /* 428 */ { "vserver" },
- /* 429 */ { "mbind" },
- /* 430 */ { "get_mempolicy" },
- /* 431 */ { "set_mempolicy" },
- /* 432 */ { "mq_open" },
- /* 433 */ { "mq_unlink" },
- /* 434 */ { "mq_timedsend" },
- /* 435 */ { "mq_timedreceive" },
- /* 436 */ { "mq_notify" },
- /* 437 */ { "mq_getsetattr" },
- /* 438 */ { "waitid" },
- /* 439 */ { "add_key" },
- /* 440 */ { "request_key" },
- /* 441 */ { "keyctl" }
-};
-
-AlphaLinuxProcess::AlphaLinuxProcess(ProcessParams * params,
- ObjectFile *objFile)
- : AlphaProcess(params, objFile),
- Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc))
-{
- //init_regs->intRegFile[0] = 0;
-}
-
-
-
-SyscallDesc*
-AlphaLinuxProcess::getDesc(int callnum)
-{
- if (callnum < 0 || callnum >= Num_Syscall_Descs)
- return NULL;
- return &syscallDescs[callnum];
-}
-
-void
-AlphaLinuxProcess::syscall(ThreadContext *tc, Fault *fault)
-{
- doSyscall(tc->readIntReg(0), tc, fault);
-}
-
+++ /dev/null
-/*
- * Copyright (c) 2003-2004 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- */
-
-#ifndef __ALPHA_LINUX_PROCESS_HH__
-#define __ALPHA_LINUX_PROCESS_HH__
-
-#include "arch/alpha/process.hh"
-
-#include "sim/syscall_desc.hh"
-
-namespace AlphaISA {
-
-/// A process with emulated Alpha/Linux syscalls.
-class AlphaLinuxProcess : public AlphaProcess
-{
- public:
- /// Constructor.
- AlphaLinuxProcess(ProcessParams * params, ObjectFile *objFile);
-
- void syscall(ThreadContext *tc, Fault *fault) override;
-
- SyscallDesc *getDesc(int callnum) override;
-
- /// Array of syscall descriptors, indexed by call number.
- static SyscallDescABI<DefaultSyscallABI> syscallDescs[];
-
- const int Num_Syscall_Descs;
-};
-
-} // namespace AlphaISA
-
-#endif // __ALPHA_LINUX_PROCESS_HH__
+++ /dev/null
-/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
- * Lisa Hsu
- * Nathan Binkert
- * Steve Reinhardt
- */
-
-/**
- * @file
- * This code loads the linux kernel, console, pal and patches certain
- * functions. The symbol tables are loaded so that traces can show
- * the executing function and we can skip functions. Various delay
- * loops are skipped and their final values manually computed to speed
- * up boot time.
- */
-
-#include "arch/alpha/linux/system.hh"
-
-#include "arch/alpha/idle_event.hh"
-#include "arch/alpha/system.hh"
-#include "arch/generic/linux/threadinfo.hh"
-#include "arch/vtophys.hh"
-#include "base/loader/symtab.hh"
-#include "cpu/base.hh"
-#include "cpu/thread_context.hh"
-#include "debug/Thread.hh"
-#include "kern/linux/events.hh"
-#include "kern/linux/printk.hh"
-#include "mem/physical.hh"
-#include "mem/port.hh"
-#include "sim/arguments.hh"
-#include "sim/byteswap.hh"
-
-using namespace std;
-using namespace AlphaISA;
-using namespace Linux;
-
-LinuxAlphaSystem::LinuxAlphaSystem(Params *p)
- : AlphaSystem(p)
-{
-}
-
-void
-LinuxAlphaSystem::initState()
-{
- // Moved from the constructor to here since it relies on the
- // address map being resolved in the interconnect
-
- // Call the initialisation of the super class
- AlphaSystem::initState();
-
- Addr addr = 0;
-
- /**
- * The symbol swapper_pg_dir marks the beginning of the kernel and
- * the location of bootloader passed arguments
- */
- if (!kernelSymtab->findAddress("swapper_pg_dir", KernelStart)) {
- panic("Could not determine start location of kernel");
- }
-
- /**
- * Since we aren't using a bootloader, we have to copy the
- * kernel arguments directly into the kernel's memory.
- */
- virtProxy.writeBlob(CommandLine(),
- params()->boot_osflags.c_str(),
- params()->boot_osflags.length() + 1);
-
- /**
- * find the address of the est_cycle_freq variable and insert it
- * so we don't through the lengthly process of trying to
- * calculated it by using the PIT, RTC, etc.
- */
- if (kernelSymtab->findAddress("est_cycle_freq", addr))
- virtProxy.write(addr, (uint64_t)(SimClock::Frequency /
- params()->boot_cpu_frequency));
-
-
- /**
- * EV5 only supports 127 ASNs so we are going to tell the kernel that the
- * paritiuclar EV6 we have only supports 127 asns.
- * @todo At some point we should change ev5.hh and the palcode to support
- * 255 ASNs.
- */
- if (kernelSymtab->findAddress("dp264_mv", addr))
- virtProxy.write(addr + 0x18, htole((uint32_t)127));
- else
- panic("could not find dp264_mv\n");
-
-}
-
-void
-LinuxAlphaSystem::setupFuncEvents()
-{
- AlphaSystem::setupFuncEvents();
-#ifndef NDEBUG
- kernelPanicEvent = addKernelFuncEventOrPanic<BreakPCEvent>("panic");
-
-#endif
-
- /**
- * Any time ide_delay_50ms, calibarte_delay or
- * determine_cpu_caches is called just skip the
- * function. Currently determine_cpu_caches only is used put
- * information in proc, however if that changes in the future we
- * will have to fill in the cache size variables appropriately.
- */
-
- skipIdeDelay50msEvent =
- addKernelFuncEvent<SkipFuncEvent>("ide_delay_50ms");
- skipDelayLoopEvent =
- addKernelFuncEvent<SkipDelayLoopEvent>("calibrate_delay");
- skipCacheProbeEvent =
- addKernelFuncEvent<SkipFuncEvent>("determine_cpu_caches");
- debugPrintkEvent = addKernelFuncEvent<DebugPrintkEvent>("dprintk");
- idleStartEvent = addKernelFuncEvent<IdleStartEvent>("cpu_idle");
-
- // Disable for now as it runs into panic() calls in VPTr methods
- // (see sim/vptr.hh). Once those bugs are fixed, we can
- // re-enable, but we should find a better way to turn it on than
- // using DTRACE(Thread), since looking at a trace flag at tick 0
- // leads to non-intuitive behavior with --trace-start.
- Addr addr = 0;
- if (false && kernelSymtab->findAddress("alpha_switch_to", addr)) {
- printThreadEvent = new PrintThreadInfo(this, "threadinfo",
- addr + sizeof(MachInst) * 6);
- } else {
- printThreadEvent = NULL;
- }
-}
-
-LinuxAlphaSystem::~LinuxAlphaSystem()
-{
-#ifndef NDEBUG
- delete kernelPanicEvent;
-#endif
- delete skipIdeDelay50msEvent;
- delete skipDelayLoopEvent;
- delete skipCacheProbeEvent;
- delete debugPrintkEvent;
- delete idleStartEvent;
- delete printThreadEvent;
-}
-
-void
-LinuxAlphaSystem::setDelayLoop(ThreadContext *tc)
-{
- Addr addr = 0;
- if (kernelSymtab->findAddress("loops_per_jiffy", addr)) {
- Tick cpuFreq = tc->getCpuPtr()->frequency();
- assert(intrFreq);
- PortProxy &vp = tc->getVirtProxy();
- vp.write(addr, (uint32_t)((cpuFreq / intrFreq) * 0.9988),
- GuestByteOrder);
- }
-}
-
-void
-LinuxAlphaSystem::SkipDelayLoopEvent::process(ThreadContext *tc)
-{
- SkipFuncEvent::process(tc);
- // calculate and set loops_per_jiffy
- ((LinuxAlphaSystem *)tc->getSystemPtr())->setDelayLoop(tc);
-}
-
-void
-LinuxAlphaSystem::PrintThreadInfo::process(ThreadContext *tc)
-{
- Linux::ThreadInfo ti(tc);
-
- DPRINTF(Thread, "Currently Executing Thread %s, pid %d, started at: %d\n",
- ti.curTaskName(), ti.curTaskPID(), ti.curTaskStart());
-}
-
-LinuxAlphaSystem *
-LinuxAlphaSystemParams::create()
-{
- return new LinuxAlphaSystem(this);
-}
+++ /dev/null
-/*
- * Copyright (c) 2004-2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
- * Lisa Hsu
- * Nathan Binkert
- */
-
-#ifndef __ARCH_ALPHA_LINUX_SYSTEM_HH__
-#define __ARCH_ALPHA_LINUX_SYSTEM_HH__
-
-class ThreadContext;
-
-class BreakPCEvent;
-class IdleStartEvent;
-
-#include "arch/alpha/idle_event.hh"
-#include "arch/alpha/system.hh"
-#include "kern/linux/events.hh"
-#include "params/LinuxAlphaSystem.hh"
-
-/**
- * This class contains linux specific system code (Loading, Events).
- * It points to objects that are the system binaries to load and patches them
- * appropriately to work in simulator.
- */
-class LinuxAlphaSystem : public AlphaSystem
-{
- private:
- struct SkipDelayLoopEvent : public SkipFuncEvent
- {
- SkipDelayLoopEvent(PCEventScope *s, const std::string &desc, Addr addr)
- : SkipFuncEvent(s, desc, addr) {}
- virtual void process(ThreadContext *tc);
- };
-
- struct PrintThreadInfo : public PCEvent
- {
- PrintThreadInfo(PCEventScope *s, const std::string &desc, Addr addr)
- : PCEvent(s, desc, addr) {}
- virtual void process(ThreadContext *tc);
- };
-
- /**
- * Addresses defining where the kernel bootloader places various
- * elements. Details found in include/asm-alpha/system.h
- */
- Addr KernelStart; // Lookup the symbol swapper_pg_dir
-
- public:
- Addr InitStack() const { return KernelStart + 0x02000; }
- Addr EmptyPGT() const { return KernelStart + 0x04000; }
- Addr EmptyPGE() const { return KernelStart + 0x08000; }
- Addr ZeroPGE() const { return KernelStart + 0x0A000; }
- Addr StartAddr() const { return KernelStart + 0x10000; }
-
- Addr Param() const { return ZeroPGE() + 0x0; }
- Addr CommandLine() const { return Param() + 0x0; }
- Addr InitrdStart() const { return Param() + 0x100; }
- Addr InitrdSize() const { return Param() + 0x108; }
- static const int CommandLineSize = 256;
-
- private:
-#ifndef NDEBUG
- /** Event to halt the simulator if the kernel calls panic() */
- BreakPCEvent *kernelPanicEvent;
-
-#endif
-
- /**
- * Event to skip determine_cpu_caches() because we don't support
- * the IPRs that the code can access to figure out cache sizes
- */
- SkipFuncEvent *skipCacheProbeEvent;
-
- /** PC based event to skip the ide_delay_50ms() call */
- SkipFuncEvent *skipIdeDelay50msEvent;
-
- /**
- * PC based event to skip the dprink() call and emulate its
- * functionality
- */
- Linux::DebugPrintkEvent *debugPrintkEvent;
-
- /**
- * Skip calculate_delay_loop() rather than waiting for this to be
- * calculated
- */
- SkipDelayLoopEvent *skipDelayLoopEvent;
-
- /**
- * Event to print information about thread switches if the trace flag
- * Thread is set
- */
- PrintThreadInfo *printThreadEvent;
-
- /** Grab the PCBB of the idle process when it starts */
- IdleStartEvent *idleStartEvent;
-
- protected:
- /** Setup all the function events. Must be done after init() for Alpha since
- * fixFuncEvent() requires a function port
- */
- virtual void setupFuncEvents();
-
- public:
- typedef LinuxAlphaSystemParams Params;
- LinuxAlphaSystem(Params *p);
- ~LinuxAlphaSystem();
-
- /**
- * Initialise the system
- */
- virtual void initState();
-
- void setDelayLoop(ThreadContext *tc);
-
- const Params *params() const { return (const Params *)_params; }
-};
-
-#endif // __ARCH_ALPHA_LINUX_SYSTEM_HH__
+++ /dev/null
-/*
- * Copyright (c) 2012 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- */
-
-#ifndef __ARCH_ALPHA_LOCKED_MEM_HH__
-#define __ARCH_ALPHA_LOCKED_MEM_HH__
-
-/**
- * @file
- *
- * ISA-specific helper functions for locked memory accesses.
- *
- * Note that these functions are not embedded in the ISA description
- * because they operate on the *physical* address rather than the
- * virtual address. In the current M5 design, the physical address is
- * not accessible from the ISA description, only from the CPU model.
- * Thus the CPU is responsible for calling back to the ISA (here)
- * after the address translation has been performed to allow the ISA
- * to do these manipulations based on the physical address.
- */
-
-#include "arch/alpha/registers.hh"
-#include "base/logging.hh"
-#include "mem/packet.hh"
-#include "mem/request.hh"
-
-namespace AlphaISA {
-
-template <class XC>
-inline void
-handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
-{
- // If we see a snoop come into the CPU and we currently have an LLSC
- // operation pending we need to clear the lock flag if it is to the same
- // cache line.
-
- if (!xc->readMiscReg(MISCREG_LOCKFLAG))
- return;
-
- Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
- Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
-
- if (locked_addr == snoop_addr)
- xc->setMiscReg(MISCREG_LOCKFLAG, false);
-}
-
-
-template <class XC>
-inline void
-handleLockedRead(XC *xc, const RequestPtr &req)
-{
- xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf);
- xc->setMiscReg(MISCREG_LOCKFLAG, true);
-}
-
-template <class XC>
-inline void
-handleLockedSnoopHit(XC *xc)
-{
-}
-
-template <class XC>
-inline bool
-handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask)
-{
- if (req->isUncacheable()) {
- // Funky Turbolaser mailbox access...don't update
- // result register (see stq_c in decoder.isa)
- req->setExtraData(2);
- } else {
- // standard store conditional
- bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
- Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR);
- if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
- // Lock flag not set or addr mismatch in CPU;
- // don't even bother sending to memory system
- req->setExtraData(0);
- xc->setMiscReg(MISCREG_LOCKFLAG, false);
- // the rest of this code is not architectural;
- // it's just a debugging aid to help detect
- // livelock by warning on long sequences of failed
- // store conditionals
- int stCondFailures = xc->readStCondFailures();
- stCondFailures++;
- xc->setStCondFailures(stCondFailures);
- if (stCondFailures % 100000 == 0) {
- warn("context %d: %d consecutive "
- "store conditional failures\n",
- xc->contextId(), stCondFailures);
- }
-
- // store conditional failed already, so don't issue it to mem
- return false;
- }
- }
-
- return true;
-}
-
-template <class XC>
-inline void
-globalClearExclusive(XC *xc)
-{
- xc->getCpuPtr()->wakeup(xc->threadId());
-}
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_LOCKED_MEM_HH__
+++ /dev/null
-/*
- * Copyright (c) 2008 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#ifndef __ARCH_ALPHA_MICROCODE_ROM_HH__
-#define __ARCH_ALPHA_MICROCODE_ROM_HH__
-
-#include "sim/microcode_rom.hh"
-
-namespace AlphaISA
-{
- using ::MicrocodeRom;
-}
-
-#endif // __ARCH_ALPHA_MICROCODE_ROM_HH__
+++ /dev/null
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
- */
-
-#ifndef __ARCH_ALPHA_MMAPPED_IPR_HH__
-#define __ARCH_ALPHA_MMAPPED_IPR_HH__
-
-/**
- * @file
- *
- * ISA-specific helper functions for memory mapped IPR accesses.
- */
-
-#include "base/types.hh"
-
-class Packet;
-class ThreadContext;
-
-namespace AlphaISA
-{
-
-inline Cycles handleIprRead(ThreadContext *, Packet *) { return Cycles(1); }
-inline Cycles handleIprWrite(ThreadContext *, Packet *) { return Cycles(1); }
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_MMAPPED_IPR_HH__
+++ /dev/null
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- */
-
-#include "arch/alpha/osfpal.hh"
-
-const char *
-PAL::name(int index)
-{
- static const char *strings[PAL::NumCodes] = {
- // Priviledged PAL instructions
- "halt", // 0x00
- "cflush", // 0x01
- "draina", // 0x02
- 0, // 0x03
- 0, // 0x04
- 0, // 0x05
- 0, // 0x06
- 0, // 0x07
- 0, // 0x08
- "cserve", // 0x09
- "swppal", // 0x0a
- 0, // 0x0b
- 0, // 0x0c
- "wripir", // 0x0d
- 0, // 0x0e
- 0, // 0x0f
- "rdmces", // 0x10
- "wrmces", // 0x11
- 0, // 0x12
- 0, // 0x13
- 0, // 0x14
- 0, // 0x15
- 0, // 0x16
- 0, // 0x17
- 0, // 0x18
- 0, // 0x19
- 0, // 0x1a
- 0, // 0x1b
- 0, // 0x1c
- 0, // 0x1d
- 0, // 0x1e
- 0, // 0x1f
- 0, // 0x20
- 0, // 0x21
- 0, // 0x22
- 0, // 0x23
- 0, // 0x24
- 0, // 0x25
- 0, // 0x26
- 0, // 0x27
- 0, // 0x28
- 0, // 0x29
- 0, // 0x2a
- "wrfen", // 0x2b
- 0, // 0x2c
- "wrvptptr", // 0x2d
- 0, // 0x2e
- 0, // 0x2f
- "swpctx", // 0x30
- "wrval", // 0x31
- "rdval", // 0x32
- "tbi", // 0x33
- "wrent", // 0x34
- "swpipl", // 0x35
- "rdps", // 0x36
- "wrkgp", // 0x37
- "wrusp", // 0x38
- "wrperfmon", // 0x39
- "rdusp", // 0x3a
- 0, // 0x3b
- "whami", // 0x3c
- "retsys", // 0x3d
- "wtint", // 0x3e
- "rti", // 0x3f
- 0, // 0x40
- 0, // 0x41
- 0, // 0x42
- 0, // 0x43
- 0, // 0x44
- 0, // 0x45
- 0, // 0x46
- 0, // 0x47
- 0, // 0x48
- 0, // 0x49
- 0, // 0x4a
- 0, // 0x4b
- 0, // 0x4c
- 0, // 0x4d
- 0, // 0x4e
- 0, // 0x4f
- 0, // 0x50
- 0, // 0x51
- 0, // 0x52
- 0, // 0x53
- 0, // 0x54
- 0, // 0x55
- 0, // 0x56
- 0, // 0x57
- 0, // 0x58
- 0, // 0x59
- 0, // 0x5a
- 0, // 0x5b
- 0, // 0x5c
- 0, // 0x5d
- 0, // 0x5e
- 0, // 0x5f
- 0, // 0x60
- 0, // 0x61
- 0, // 0x62
- 0, // 0x63
- 0, // 0x64
- 0, // 0x65
- 0, // 0x66
- 0, // 0x67
- 0, // 0x68
- 0, // 0x69
- 0, // 0x6a
- 0, // 0x6b
- 0, // 0x6c
- 0, // 0x6d
- 0, // 0x6e
- 0, // 0x6f
- 0, // 0x70
- 0, // 0x71
- 0, // 0x72
- 0, // 0x73
- 0, // 0x74
- 0, // 0x75
- 0, // 0x76
- 0, // 0x77
- 0, // 0x78
- 0, // 0x79
- 0, // 0x7a
- 0, // 0x7b
- 0, // 0x7c
- 0, // 0x7d
- 0, // 0x7e
- 0, // 0x7f
-
- // Unpriviledged PAL instructions
- "bpt", // 0x80
- "bugchk", // 0x81
- 0, // 0x82
- "callsys", // 0x83
- 0, // 0x84
- 0, // 0x85
- "imb", // 0x86
- 0, // 0x87
- 0, // 0x88
- 0, // 0x89
- 0, // 0x8a
- 0, // 0x8b
- 0, // 0x8c
- 0, // 0x8d
- 0, // 0x8e
- 0, // 0x8f
- 0, // 0x90
- 0, // 0x91
- "urti", // 0x92
- 0, // 0x93
- 0, // 0x94
- 0, // 0x95
- 0, // 0x96
- 0, // 0x97
- 0, // 0x98
- 0, // 0x99
- 0, // 0x9a
- 0, // 0x9b
- 0, // 0x9c
- 0, // 0x9d
- "rdunique", // 0x9e
- "wrunique", // 0x9f
- 0, // 0xa0
- 0, // 0xa1
- 0, // 0xa2
- 0, // 0xa3
- 0, // 0xa4
- 0, // 0xa5
- 0, // 0xa6
- 0, // 0xa7
- 0, // 0xa8
- 0, // 0xa9
- "gentrap", // 0xaa
- 0, // 0xab
- 0, // 0xac
- 0, // 0xad
- "clrfen", // 0xae
- 0, // 0xaf
- 0, // 0xb0
- 0, // 0xb1
- 0, // 0xb2
- 0, // 0xb3
- 0, // 0xb4
- 0, // 0xb5
- 0, // 0xb6
- 0, // 0xb7
- 0, // 0xb8
- 0, // 0xb9
- 0, // 0xba
- 0, // 0xbb
- 0, // 0xbc
- 0, // 0xbd
- "nphalt", // 0xbe
- "copypal", // 0xbf
- };
-
- if (index > NumCodes || index < 0)
- return 0;
-
- return strings[index];
-}
+++ /dev/null
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- */
-
-#ifndef __ARCH_ALPHA_OSFPAL_HH__
-#define __ARCH_ALPHA_OSFPAL_HH__
-
-struct PAL
-{
- enum {
- // Privileged PAL functions
- halt = 0x00,
- cflush = 0x01,
- draina = 0x02,
- cserve = 0x09,
- swppal = 0x0a,
- wripir = 0x0d,
- rdmces = 0x10,
- wrmces = 0x11,
- wrfen = 0x2b,
- wrvptptr = 0x2d,
- swpctx = 0x30,
- wrval = 0x31,
- rdval = 0x32,
- tbi = 0x33,
- wrent = 0x34,
- swpipl = 0x35,
- rdps = 0x36,
- wrkgp = 0x37,
- wrusp = 0x38,
- wrperfmon = 0x39,
- rdusp = 0x3a,
- whami = 0x3c,
- retsys = 0x3d,
- wtint = 0x3e,
- rti = 0x3f,
-
- // unprivileged pal functions
- bpt = 0x80,
- bugchk = 0x81,
- callsys = 0x83,
- imb = 0x86,
- urti = 0x92,
- rdunique = 0x9e,
- wrunique = 0x9f,
- gentrap = 0xaa,
- clrfen = 0xae,
- nphalt = 0xbe,
- copypal = 0xbf,
- NumCodes
- };
-
- static const char *name(int index);
-};
-
-#endif // __ARCH_ALPHA_OSFPAL_HH__
+++ /dev/null
-/*
- * Copyright (c) 2006-2007 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#include "arch/alpha/pagetable.hh"
-
-#include "sim/serialize.hh"
-
-namespace AlphaISA {
-
-void
-TlbEntry::serialize(CheckpointOut &cp) const
-{
- SERIALIZE_SCALAR(tag);
- SERIALIZE_SCALAR(ppn);
- SERIALIZE_SCALAR(xre);
- SERIALIZE_SCALAR(xwe);
- SERIALIZE_SCALAR(asn);
- SERIALIZE_SCALAR(asma);
- SERIALIZE_SCALAR(fonr);
- SERIALIZE_SCALAR(fonw);
- SERIALIZE_SCALAR(valid);
-}
-
-void
-TlbEntry::unserialize(CheckpointIn &cp)
-{
- UNSERIALIZE_SCALAR(tag);
- UNSERIALIZE_SCALAR(ppn);
- UNSERIALIZE_SCALAR(xre);
- UNSERIALIZE_SCALAR(xwe);
- UNSERIALIZE_SCALAR(asn);
- UNSERIALIZE_SCALAR(asma);
- UNSERIALIZE_SCALAR(fonr);
- UNSERIALIZE_SCALAR(fonw);
- UNSERIALIZE_SCALAR(valid);
-}
-
-} // namespace AlphaISA
+++ /dev/null
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- * Steve Reinhardt
- */
-
-#ifndef __ARCH_ALPHA_PAGETABLE_H__
-#define __ARCH_ALPHA_PAGETABLE_H__
-
-#include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/utility.hh"
-
-namespace AlphaISA {
-
-struct VAddr
-{
- static const int ImplBits = 43;
- static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
- static const Addr UnImplMask = ~ImplMask;
-
- Addr addr;
-
- VAddr(const VAddr &) = default;
- VAddr(Addr a) : addr(a) {}
- operator Addr() const { return addr; }
- const VAddr &operator=(Addr a) { addr = a; return *this; }
-
- Addr vpn() const { return (addr & ImplMask) >> PageShift; }
- Addr page() const { return addr & PageMask; }
- Addr offset() const { return addr & PageOffset; }
-
- Addr level3() const
- { return PteAddr(addr >> PageShift); }
- Addr level2() const
- { return PteAddr(addr >> (NPtePageShift + PageShift)); }
- Addr level1() const
- { return PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
-};
-
-struct PageTableEntry
-{
- PageTableEntry(const PageTableEntry &) = default;
- PageTableEntry(uint64_t e) : entry(e) {}
- uint64_t entry;
- operator uint64_t() const { return entry; }
- const PageTableEntry &operator=(uint64_t e) { entry = e; return *this; }
- const PageTableEntry &operator=(const PageTableEntry &e)
- { entry = e.entry; return *this; }
-
- Addr _pfn() const { return (entry >> 32) & 0xffffffff; }
- Addr _sw() const { return (entry >> 16) & 0xffff; }
- int _rsv0() const { return (entry >> 14) & 0x3; }
- bool _uwe() const { return (entry >> 13) & 0x1; }
- bool _kwe() const { return (entry >> 12) & 0x1; }
- int _rsv1() const { return (entry >> 10) & 0x3; }
- bool _ure() const { return (entry >> 9) & 0x1; }
- bool _kre() const { return (entry >> 8) & 0x1; }
- bool _nomb() const { return (entry >> 7) & 0x1; }
- int _gh() const { return (entry >> 5) & 0x3; }
- bool _asm_() const { return (entry >> 4) & 0x1; }
- bool _foe() const { return (entry >> 3) & 0x1; }
- bool _fow() const { return (entry >> 2) & 0x1; }
- bool _for() const { return (entry >> 1) & 0x1; }
- bool valid() const { return (entry >> 0) & 0x1; }
-
- Addr paddr() const { return _pfn() << PageShift; }
-};
-
-// ITB/DTB table entry
-struct TlbEntry : public Serializable
-{
- Addr tag; // virtual page number tag
- Addr ppn; // physical page number
- uint8_t xre; // read permissions - VMEM_PERM_* mask
- uint8_t xwe; // write permissions - VMEM_PERM_* mask
- uint8_t asn; // address space number
- bool asma; // address space match
- bool fonr; // fault on read
- bool fonw; // fault on write
- bool valid; // valid page table entry
-
-
- TlbEntry(const TlbEntry &) = default;
-
- //Construct an entry that maps to physical address addr.
- TlbEntry(Addr _asn, Addr _vaddr, Addr _paddr,
- bool uncacheable, bool read_only)
- {
- VAddr vaddr(_vaddr);
- VAddr paddr(_paddr);
- tag = vaddr.vpn();
- ppn = paddr.vpn();
- xre = 15;
- xwe = 15;
- asn = _asn;
- asma = false;
- fonr = false;
- fonw = false;
- valid = true;
- if (uncacheable || read_only)
- warn("Alpha TlbEntry does not support uncacheable"
- " or read-only mappings\n");
- }
-
- TlbEntry()
- : tag(0), ppn(0), xre(0), xwe(0), asn(0),
- asma(false), fonr(0), fonw(0), valid(0)
- {
- }
-
- void
- updateVaddr(Addr new_vaddr)
- {
- VAddr vaddr(new_vaddr);
- tag = vaddr.vpn();
- }
-
- Addr
- pageStart()
- {
- return ppn << PageShift;
- }
-
- void serialize(CheckpointOut &cp) const override;
- void unserialize(CheckpointIn &cp) override;
-};
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_PAGETABLE_H__
-
+++ /dev/null
-/*
- * Copyright (c) 2003-2004 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- * Ali Saidi
- */
-
-#include "arch/alpha/process.hh"
-
-#include "arch/alpha/isa_traits.hh"
-#include "base/loader/elf_object.hh"
-#include "base/loader/object_file.hh"
-#include "base/logging.hh"
-#include "cpu/thread_context.hh"
-#include "debug/Loader.hh"
-#include "mem/page_table.hh"
-#include "params/Process.hh"
-#include "sim/aux_vector.hh"
-#include "sim/byteswap.hh"
-#include "sim/process_impl.hh"
-#include "sim/syscall_return.hh"
-#include "sim/system.hh"
-
-using namespace AlphaISA;
-using namespace std;
-
-AlphaProcess::AlphaProcess(ProcessParams *params, ObjectFile *objFile)
- : Process(params,
- new EmulationPageTable(params->name, params->pid, PageBytes),
- objFile)
-{
- fatal_if(params->useArchPT, "Arch page tables not implemented.");
- Addr brk_point = roundUp(image.maxAddr(), PageBytes);
-
- // Set up stack. On Alpha, stack goes below the image.
- Addr stack_base = image.minAddr() - (409600 + 4096);
-
- // Set up region for mmaps.
- Addr mmap_end = 0x10000;
-
- Addr max_stack_size = 8 * 1024 * 1024;
-
- // Set pointer for next thread stack. Reserve 8M for main stack.
- Addr next_thread_stack_base = stack_base - max_stack_size;
-
- memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
- next_thread_stack_base, mmap_end);
-}
-
-void
-AlphaProcess::argsInit(int intSize, int pageSize)
-{
- std::vector<AuxVector<uint64_t>> auxv;
-
- ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
- if (elfObject)
- {
- // modern glibc uses a bunch of auxiliary vectors to set up
- // TLS as well as do a bunch of other stuff
- // these vectors go on the bottom of the stack, below argc/argv/envp
- // pointers but above actual arg strings
- // I don't have all the ones glibc looks at here, but so far it doesn't
- // seem to be a problem.
- // check out _dl_aux_init() in glibc/elf/dl-support.c for details
- // --Lisa
- auxv.emplace_back(M5_AT_PAGESZ, AlphaISA::PageBytes);
- auxv.emplace_back(M5_AT_CLKTCK, 100);
- auxv.emplace_back(M5_AT_PHDR, elfObject->programHeaderTable());
- DPRINTF(Loader, "auxv at PHDR %08p\n",
- elfObject->programHeaderTable());
- auxv.emplace_back(M5_AT_PHNUM, elfObject->programHeaderCount());
- // This is the base address of the ELF interpreter; it should be
- // zero for static executables or contain the base address for
- // dynamic executables.
- auxv.emplace_back(M5_AT_BASE, getBias());
- auxv.emplace_back(M5_AT_ENTRY, objFile->entryPoint());
- auxv.emplace_back(M5_AT_UID, uid());
- auxv.emplace_back(M5_AT_EUID, euid());
- auxv.emplace_back(M5_AT_GID, gid());
- auxv.emplace_back(M5_AT_EGID, egid());
-
- }
-
- // Calculate how much space we need for arg & env & auxv arrays.
- int argv_array_size = intSize * (argv.size() + 1);
- int envp_array_size = intSize * (envp.size() + 1);
- int auxv_array_size = intSize * 2 * (auxv.size() + 1);
-
- int arg_data_size = 0;
- for (vector<string>::size_type i = 0; i < argv.size(); ++i) {
- arg_data_size += argv[i].size() + 1;
- }
- int env_data_size = 0;
- for (vector<string>::size_type i = 0; i < envp.size(); ++i) {
- env_data_size += envp[i].size() + 1;
- }
-
- int space_needed =
- argv_array_size +
- envp_array_size +
- auxv_array_size +
- arg_data_size +
- env_data_size;
-
- if (space_needed < 32*1024)
- space_needed = 32*1024;
-
- // set bottom of stack
- memState->setStackMin(memState->getStackBase() - space_needed);
- // align it
- memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
- memState->setStackSize(memState->getStackBase() - memState->getStackMin());
- // map memory
- allocateMem(memState->getStackMin(), roundUp(memState->getStackSize(),
- pageSize));
-
- // map out initial stack contents
- Addr argv_array_base = memState->getStackMin() + intSize; // room for argc
- Addr envp_array_base = argv_array_base + argv_array_size;
- Addr auxv_array_base = envp_array_base + envp_array_size;
- Addr arg_data_base = auxv_array_base + auxv_array_size;
- Addr env_data_base = arg_data_base + arg_data_size;
-
- // write contents to stack
- uint64_t argc = argv.size();
- if (intSize == 8)
- argc = htole((uint64_t)argc);
- else if (intSize == 4)
- argc = htole((uint32_t)argc);
- else
- panic("Unknown int size");
-
- initVirtMem.writeBlob(memState->getStackMin(), &argc, intSize);
-
- copyStringArray(argv, argv_array_base, arg_data_base,
- LittleEndianByteOrder, initVirtMem);
- copyStringArray(envp, envp_array_base, env_data_base,
- LittleEndianByteOrder, initVirtMem);
-
- //Copy the aux stuff
- Addr auxv_array_end = auxv_array_base;
- for (const auto &aux: auxv) {
- initVirtMem.write(auxv_array_end, aux, GuestByteOrder);
- auxv_array_end += sizeof(aux);
- }
-
- ThreadContext *tc = system->getThreadContext(contextIds[0]);
-
- tc->setIntReg(FirstArgumentReg, argc);
- tc->setIntReg(FirstArgumentReg + 1, argv_array_base);
- tc->setIntReg(StackPointerReg, memState->getStackMin());
-
- tc->pcState(getStartPC());
-}
-
-void
-AlphaProcess::setupASNReg()
-{
- ThreadContext *tc = system->getThreadContext(contextIds[0]);
- tc->setMiscRegNoEffect(IPR_DTB_ASN, _pid << 57);
-}
-
-
-void
-AlphaProcess::unserialize(CheckpointIn &cp)
-{
- Process::unserialize(cp);
- // need to set up ASN after unserialization since _pid value may
- // come from checkpoint
- setupASNReg();
-}
-
-
-void
-AlphaProcess::initState()
-{
- // need to set up ASN before further initialization since init
- // will involve writing to virtual memory addresses
- setupASNReg();
-
- Process::initState();
-
- argsInit(MachineBytes, PageBytes);
-
- ThreadContext *tc = system->getThreadContext(contextIds[0]);
- tc->setIntReg(GlobalPointerReg, 0);
- //Operate in user mode
- tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3);
- tc->setMiscRegNoEffect(IPR_DTB_CM, mode_user << 3);
- //No super page mapping
- tc->setMiscRegNoEffect(IPR_MCSR, 0);
-}
-
-RegVal
-AlphaProcess::getSyscallArg(ThreadContext *tc, int &i)
-{
- assert(i < 6);
- return tc->readIntReg(FirstArgumentReg + i++);
-}
-
-void
-AlphaProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
-{
- // check for error condition. Alpha syscall convention is to
- // indicate success/failure in reg a3 (r19) and put the
- // return value itself in the standard return value reg (v0).
- if (sysret.successful()) {
- // no error
- tc->setIntReg(SyscallSuccessReg, 0);
- tc->setIntReg(ReturnValueReg, sysret.returnValue());
- } else {
- // got an error, return details
- tc->setIntReg(SyscallSuccessReg, (RegVal)-1);
- tc->setIntReg(ReturnValueReg, sysret.errnoValue());
- }
-}
+++ /dev/null
-/*
- * Copyright (c) 2003-2004 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- * Ali Saidi
- */
-
-#ifndef __ARCH_ALPHA_PROCESS_HH__
-#define __ARCH_ALPHA_PROCESS_HH__
-
-#include "mem/page_table.hh"
-#include "sim/process.hh"
-
-class AlphaProcess : public Process
-{
- private:
- void setupASNReg();
-
- protected:
- AlphaProcess(ProcessParams *params, ObjectFile *objFile);
-
- void unserialize(CheckpointIn &cp) override;
- void initState() override;
-
- void argsInit(int intSize, int pageSize);
-
- public:
- RegVal getSyscallArg(ThreadContext *tc, int &i) override;
- /// Explicitly import the otherwise hidden getSyscallArg
- using Process::getSyscallArg;
- void setSyscallReturn(ThreadContext *tc,
- SyscallReturn return_value) override;
-
- // override default implementation in Process as the mmap
- // region for Alpha platforms grows upward
- virtual bool mmapGrowsDown() const override { return false; }
-};
-
-#endif // __ARCH_ALPHA_PROCESS_HH__
+++ /dev/null
-/*
- * Copyright (c) 2014 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Alexandru Dutu
- */
-
-#ifndef __ARCH_ALPHA_PSEUDO_INST_HH__
-#define __ARCH_ALPHA_PSEUDO_INST_HH__
-
-#include "arch/generic/pseudo_inst.hh"
-
-namespace AlphaISA
-{
-
-using GenericISA::m5PageFault;
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_PSEUDO_INST_HH__
-
+++ /dev/null
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#ifndef __ARCH_ALPHA_REGISTERS_HH__
-#define __ARCH_ALPHA_REGISTERS_HH__
-
-#include "arch/alpha/generated/max_inst_regs.hh"
-#include "arch/alpha/ipr.hh"
-#include "arch/generic/types.hh"
-#include "arch/generic/vec_pred_reg.hh"
-#include "arch/generic/vec_reg.hh"
-#include "base/types.hh"
-
-namespace AlphaISA {
-
-using AlphaISAInst::MaxInstSrcRegs;
-using AlphaISAInst::MaxInstDestRegs;
-
-// Locked read/write flags are can't be detected by the ISA parser
-const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1;
-
-// Not applicable to Alpha
-using VecElem = ::DummyVecElem;
-using VecReg = ::DummyVecReg;
-using ConstVecReg = ::DummyConstVecReg;
-using VecRegContainer = ::DummyVecRegContainer;
-constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
-constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;
-
-// Not applicable to Alpha
-using VecPredReg = ::DummyVecPredReg;
-using ConstVecPredReg = ::DummyConstVecPredReg;
-using VecPredRegContainer = ::DummyVecPredRegContainer;
-constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
-constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
-
-enum MiscRegIndex
-{
- MISCREG_FPCR = NumInternalProcRegs,
- MISCREG_UNIQ,
- MISCREG_LOCKFLAG,
- MISCREG_LOCKADDR,
- MISCREG_INTR,
- NUM_MISCREGS
-};
-
-// semantically meaningful register indices
-const RegIndex ZeroReg = 31; // architecturally meaningful
-// the rest of these depend on the ABI
-const RegIndex StackPointerReg = 30;
-const RegIndex GlobalPointerReg = 29;
-const RegIndex ProcedureValueReg = 27;
-const RegIndex ReturnAddressReg = 26;
-const RegIndex ReturnValueReg = 0;
-const RegIndex FramePointerReg = 15;
-
-const RegIndex SyscallNumReg = 0;
-const RegIndex FirstArgumentReg = 16;
-const RegIndex SyscallPseudoReturnReg = 20;
-const RegIndex SyscallSuccessReg = 19;
-
-const int NumIntArchRegs = 32;
-const int NumPALShadowRegs = 8;
-const int NumFloatArchRegs = 32;
-
-const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
-const int NumFloatRegs = NumFloatArchRegs;
-const int NumVecRegs = 1; // Not applicable to Alpha
- // (1 to prevent warnings)
-const int NumVecPredRegs = 1; // Not applicable to Alpha
- // (1 to prevent warnings)
-const int NumCCRegs = 0;
-const int NumMiscRegs = NUM_MISCREGS;
-
-const int TotalNumRegs =
- NumIntRegs + NumFloatRegs + NumMiscRegs;
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_REGFILE_HH__
+++ /dev/null
-/*
- * Copyright (c) 2003-2009 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- * Gabe Black
- * Kevin Lim
- */
-
-#include "arch/alpha/regredir.hh"
-
-namespace AlphaISA {
-
-const int reg_redir[NumIntRegs] = {
- /* 0 */ 0, 1, 2, 3, 4, 5, 6, 7,
- /* 8 */ 32, 33, 34, 35, 36, 37, 38, 15,
- /* 16 */ 16, 17, 18, 19, 20, 21, 22, 23,
- /* 24 */ 24, 39, 26, 27, 28, 29, 30, 31 };
-
-} // namespace AlphaISA
+++ /dev/null
-/*
- * Copyright (c) 2003-2009 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#ifndef __ARCH_ALPHA_REGREDIR_HH__
-#define __ARCH_ALPHA_REGREDIR_HH__
-
-#include "arch/alpha/registers.hh"
-
-namespace AlphaISA {
-
-// redirected register map, really only used for the full system case.
-extern const int reg_redir[NumIntRegs];
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_REGREDIR_HH__
+++ /dev/null
-/*
- * Copyright 2014 Google, Inc.
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- */
-
-/*
- * Copyright (c) 1990, 1993 The Regents of the University of California
- * All rights reserved.
- *
- * This software was developed by the Computer Systems Engineering group
- * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
- * contributed to Berkeley.
- *
- * All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by the University of
- * California, Lawrence Berkeley Laboratories.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by the University of
- * California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94
- */
-
-/*-
- * Copyright (c) 2001 The NetBSD Foundation, Inc.
- * All rights reserved.
- *
- * This code is derived from software contributed to The NetBSD Foundation
- * by Jason R. Thorpe.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by the NetBSD
- * Foundation, Inc. and its contributors.
- * 4. Neither the name of The NetBSD Foundation nor the names of its
- * contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $
- *
- * Taken from NetBSD
- *
- * "Stub" to allow remote cpu to debug over a serial line using gdb.
- */
-
-#include "arch/alpha/remote_gdb.hh"
-
-#include <sys/signal.h>
-#include <unistd.h>
-
-#include <string>
-
-#include "arch/alpha/decoder.hh"
-#include "arch/alpha/regredir.hh"
-#include "arch/alpha/utility.hh"
-#include "arch/alpha/vtophys.hh"
-#include "base/intmath.hh"
-#include "base/remote_gdb.hh"
-#include "base/socket.hh"
-#include "base/trace.hh"
-#include "cpu/static_inst.hh"
-#include "cpu/thread_context.hh"
-#include "debug/GDBAcc.hh"
-#include "debug/GDBMisc.hh"
-#include "mem/physical.hh"
-#include "mem/port.hh"
-#include "sim/full_system.hh"
-#include "sim/system.hh"
-
-using namespace std;
-using namespace AlphaISA;
-
-RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc, int _port)
- : BaseRemoteGDB(_system, tc, _port)
-{
- warn_once("Breakpoints do not work in Alpha PAL mode.\n"
- " See PCEventQueue::doService() in cpu/pc_event.cc.\n");
-}
-
-/*
- * Determine if the mapping at va..(va+len) is valid.
- */
-bool
-RemoteGDB::acc(Addr va, size_t len)
-{
- if (!FullSystem)
- panic("acc function needs to be rewritten for SE mode\n");
-
- Addr last_va;
-
- va = TruncPage(va);
- last_va = RoundPage(va + len);
-
- do {
- if (IsK0Seg(va)) {
- if (va < (K0SegBase + system()->memSize())) {
- DPRINTF(GDBAcc, "acc: Mapping is valid K0SEG <= "
- "%#x < K0SEG + size\n", va);
- return true;
- } else {
- DPRINTF(GDBAcc, "acc: Mapping invalid %#x "
- "> K0SEG + size\n", va);
- return false;
- }
- }
-
- /**
- * This code says that all accesses to palcode (instruction
- * and data) are valid since there isn't a va->pa mapping
- * because palcode is accessed physically. At some point this
- * should probably be cleaned up but there is no easy way to
- * do it.
- */
-
- if (PcPAL(va) || va < 0x10000)
- return true;
-
- Addr ptbr = context()->readMiscRegNoEffect(IPR_PALtemp20);
- PageTableEntry pte =
- kernel_pte_lookup(context()->getPhysProxy(), ptbr, va);
- if (!pte.valid()) {
- DPRINTF(GDBAcc, "acc: %#x pte is invalid\n", va);
- return false;
- }
- va += PageBytes;
- } while (va < last_va);
-
- DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va);
- return true;
-}
-
-void
-RemoteGDB::AlphaGdbRegCache::getRegs(ThreadContext *context)
-{
- DPRINTF(GDBAcc, "getRegs in remotegdb \n");
-
- r.pc = context->pcState().pc();
-
- if (PcPAL(r.pc)) {
- for (int i = 0; i < 32; ++i)
- r.gpr[i] = context->readIntReg(reg_redir[i]);
- } else {
- for (int i = 0; i < 32; ++i)
- r.gpr[i] = context->readIntReg(i);
- }
-
- for (int i = 0; i < 32; ++i)
-#ifdef KGDB_FP_REGS
- r.fpr[i] = context->readFloatReg(i);
-#else
- r.fpr[i] = 0;
-#endif
-}
-
-void
-RemoteGDB::AlphaGdbRegCache::setRegs(ThreadContext *context) const
-{
- DPRINTF(GDBAcc, "setRegs in remotegdb \n");
-
- if (PcPAL(r.pc)) {
- for (int i = 0; i < 32; ++i) {
- context->setIntReg(reg_redir[i], r.gpr[i]);
- }
- } else {
- for (int i = 0; i < 32; ++i) {
- context->setIntReg(i, r.gpr[i]);
- }
- }
-
-#ifdef KGDB_FP_REGS
- for (int i = 0; i < NumFloatArchRegs; ++i) {
- context->setFloatReg(i, gdbregs.regs64[i + KGDB_REG_F0]);
- }
-#endif
- context->pcState(r.pc);
-}
-
-
-BaseGdbRegCache*
-RemoteGDB::gdbRegs()
-{
- return new AlphaGdbRegCache(this);
-}
-
+++ /dev/null
-/*
- * Copyright (c) 2015 LabWare
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- * Boris Shingarov
- */
-
-#ifndef __ARCH_ALPHA_REMOTE_GDB_HH__
-#define __ARCH_ALPHA_REMOTE_GDB_HH__
-
-#include <map>
-
-#include "arch/alpha/types.hh"
-#include "base/pollevent.hh"
-#include "base/remote_gdb.hh"
-#include "base/socket.hh"
-#include "cpu/pc_event.hh"
-
-class System;
-class ThreadContext;
-
-namespace AlphaISA {
-
-class RemoteGDB : public BaseRemoteGDB
-{
- protected:
- // Machine memory
- bool acc(Addr addr, size_t len) override;
-
- class AlphaGdbRegCache : public BaseGdbRegCache
- {
- using BaseGdbRegCache::BaseGdbRegCache;
- private:
- struct {
- uint64_t gpr[32];
- uint64_t fpr[32];
- uint64_t pc;
- uint64_t vfp;
- } r;
- public:
- char *data() const { return (char *)&r; }
- size_t size() const { return sizeof(r); }
- void getRegs(ThreadContext*);
- void setRegs(ThreadContext*) const;
- const std::string
- name() const
- {
- return gdb->name() + ".AlphaGdbRegCache";
- }
- };
-
- public:
- RemoteGDB(System *system, ThreadContext *context, int _port);
- BaseGdbRegCache *gdbRegs() override;
-};
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_REMOTE_GDB_HH__
+++ /dev/null
-/*
- * Copyright (c) 2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- */
-
-#include "arch/alpha/stacktrace.hh"
-
-#include <string>
-
-#include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/vtophys.hh"
-#include "base/bitfield.hh"
-#include "base/trace.hh"
-#include "cpu/base.hh"
-#include "cpu/thread_context.hh"
-#include "mem/fs_translating_port_proxy.hh"
-#include "sim/system.hh"
-
-using namespace std;
-
-namespace AlphaISA {
-
-ProcessInfo::ProcessInfo(ThreadContext *_tc)
- : tc(_tc)
-{
- Addr addr = 0;
- PortProxy &vp = tc->getVirtProxy();
- SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;
-
- if (!symtab->findAddress("thread_info_size", addr))
- panic("thread info not compiled into kernel\n");
- thread_info_size = vp.read<int32_t>(addr, GuestByteOrder);
-
- if (!symtab->findAddress("task_struct_size", addr))
- panic("thread info not compiled into kernel\n");
- task_struct_size = vp.read<int32_t>(addr, GuestByteOrder);
-
- if (!symtab->findAddress("thread_info_task", addr))
- panic("thread info not compiled into kernel\n");
- task_off = vp.read<int32_t>(addr, GuestByteOrder);
-
- if (!symtab->findAddress("task_struct_pid", addr))
- panic("thread info not compiled into kernel\n");
- pid_off = vp.read<int32_t>(addr, GuestByteOrder);
-
- if (!symtab->findAddress("task_struct_comm", addr))
- panic("thread info not compiled into kernel\n");
- name_off = vp.read<int32_t>(addr, GuestByteOrder);
-}
-
-Addr
-ProcessInfo::task(Addr ksp) const
-{
- Addr base = ksp & ~0x3fff;
- if (base == ULL(0xfffffc0000000000))
- return 0;
-
- Addr tsk;
-
- PortProxy &vp = tc->getVirtProxy();
- tsk = vp.read<Addr>(base + task_off, GuestByteOrder);
-
- return tsk;
-}
-
-int
-ProcessInfo::pid(Addr ksp) const
-{
- Addr task = this->task(ksp);
- if (!task)
- return -1;
-
- uint16_t pd;
-
- PortProxy &vp = tc->getVirtProxy();
- pd = vp.read<uint16_t>(task + pid_off, GuestByteOrder);
-
- return pd;
-}
-
-string
-ProcessInfo::name(Addr ksp) const
-{
- Addr task = this->task(ksp);
- if (!task)
- return "console";
-
- char comm[256];
- tc->getVirtProxy().readString(comm, task + name_off, sizeof(comm));
- if (!comm[0])
- return "startup";
-
- return comm;
-}
-
-StackTrace::StackTrace()
- : tc(0), stack(64)
-{
-}
-
-StackTrace::StackTrace(ThreadContext *_tc, const StaticInstPtr &inst)
- : tc(0), stack(64)
-{
- trace(_tc, inst);
-}
-
-StackTrace::~StackTrace()
-{
-}
-
-void
-StackTrace::trace(ThreadContext *_tc, bool is_call)
-{
- tc = _tc;
-
- System *sys = tc->getSystemPtr();
-
- bool usermode =
- (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
-
- Addr pc = tc->pcState().npc();
- bool kernel = sys->kernelStart <= pc && pc <= sys->kernelEnd;
-
- if (usermode) {
- stack.push_back(user);
- return;
- }
-
- if (!kernel) {
- stack.push_back(console);
- return;
- }
-
- SymbolTable *symtab = sys->kernelSymtab;
- Addr ksp = tc->readIntReg(StackPointerReg);
- Addr bottom = ksp & ~0x3fff;
-
- if (is_call) {
- Addr addr;
- if (!symtab->findNearestAddr(pc, addr))
- panic("could not find address %#x", pc);
-
- stack.push_back(addr);
- pc = tc->pcState().pc();
- }
-
- while (ksp > bottom) {
- Addr addr;
- if (!symtab->findNearestAddr(pc, addr))
- panic("could not find symbol for pc=%#x", pc);
- assert(pc >= addr && "symbol botch: callpc < func");
-
- stack.push_back(addr);
-
- if (isEntry(addr))
- return;
-
- Addr ra;
- int size;
- if (decodePrologue(ksp, pc, addr, size, ra)) {
- if (!ra)
- return;
-
- if (size <= 0) {
- stack.push_back(unknown);
- return;
- }
-
- pc = ra;
- ksp += size;
- } else {
- stack.push_back(unknown);
- return;
- }
-
- kernel = sys->kernelStart <= pc && pc <= sys->kernelEnd;
- if (!kernel)
- return;
-
- if (stack.size() >= 1000)
- panic("unwinding too far");
- }
-
- panic("unwinding too far");
-}
-
-bool
-StackTrace::isEntry(Addr addr)
-{
- if (addr == tc->readMiscRegNoEffect(IPR_PALtemp12))
- return true;
-
- if (addr == tc->readMiscRegNoEffect(IPR_PALtemp7))
- return true;
-
- if (addr == tc->readMiscRegNoEffect(IPR_PALtemp11))
- return true;
-
- if (addr == tc->readMiscRegNoEffect(IPR_PALtemp21))
- return true;
-
- if (addr == tc->readMiscRegNoEffect(IPR_PALtemp9))
- return true;
-
- if (addr == tc->readMiscRegNoEffect(IPR_PALtemp2))
- return true;
-
- return false;
-}
-
-bool
-StackTrace::decodeStack(MachInst inst, int &disp)
-{
- // lda $sp, -disp($sp)
- //
- // Opcode<31:26> == 0x08
- // RA<25:21> == 30
- // RB<20:16> == 30
- // Disp<15:0>
- const MachInst mem_mask = 0xffff0000;
- const MachInst lda_pattern = 0x23de0000;
- const MachInst lda_disp_mask = 0x0000ffff;
-
- // subq $sp, disp, $sp
- // addq $sp, disp, $sp
- //
- // Opcode<31:26> == 0x10
- // RA<25:21> == 30
- // Lit<20:13>
- // One<12> = 1
- // Func<11:5> == 0x20 (addq)
- // Func<11:5> == 0x29 (subq)
- // RC<4:0> == 30
- const MachInst intop_mask = 0xffe01fff;
- const MachInst addq_pattern = 0x43c0141e;
- const MachInst subq_pattern = 0x43c0153e;
- const MachInst intop_disp_mask = 0x001fe000;
- const int intop_disp_shift = 13;
-
- if ((inst & mem_mask) == lda_pattern)
- disp = -sext<16>(inst & lda_disp_mask);
- else if ((inst & intop_mask) == addq_pattern)
- disp = -int((inst & intop_disp_mask) >> intop_disp_shift);
- else if ((inst & intop_mask) == subq_pattern)
- disp = int((inst & intop_disp_mask) >> intop_disp_shift);
- else
- return false;
-
- return true;
-}
-
-bool
-StackTrace::decodeSave(MachInst inst, int ®, int &disp)
-{
- // lda $stq, disp($sp)
- //
- // Opcode<31:26> == 0x08
- // RA<25:21> == ?
- // RB<20:16> == 30
- // Disp<15:0>
- const MachInst stq_mask = 0xfc1f0000;
- const MachInst stq_pattern = 0xb41e0000;
- const MachInst stq_disp_mask = 0x0000ffff;
- const MachInst reg_mask = 0x03e00000;
- const int reg_shift = 21;
-
- if ((inst & stq_mask) == stq_pattern) {
- reg = (inst & reg_mask) >> reg_shift;
- disp = sext<16>(inst & stq_disp_mask);
- } else {
- return false;
- }
-
- return true;
-}
-
-/*
- * Decode the function prologue for the function we're in, and note
- * which registers are stored where, and how large the stack frame is.
- */
-bool
-StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func, int &size,
- Addr &ra)
-{
- size = 0;
- ra = 0;
-
- for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) {
- MachInst inst = tc->getVirtProxy().read<MachInst>(pc);
-
- int reg, disp;
- if (decodeStack(inst, disp)) {
- if (size) {
- // panic("decoding frame size again");
- return true;
- }
- size += disp;
- } else if (decodeSave(inst, reg, disp)) {
- if (!ra && reg == ReturnAddressReg) {
- ra = tc->getVirtProxy().read<Addr>(sp + disp);
- if (!ra) {
- // panic("no return address value pc=%#x\n", pc);
- return false;
- }
- }
- }
- }
-
- return true;
-}
-
-#if TRACING_ON
-void
-StackTrace::dump()
-{
- StringWrap name(tc->getCpuPtr()->name());
- SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;
-
- DPRINTFN("------ Stack ------\n");
-
- string symbol;
- for (int i = 0, size = stack.size(); i < size; ++i) {
- Addr addr = stack[size - i - 1];
- if (addr == user)
- symbol = "user";
- else if (addr == console)
- symbol = "console";
- else if (addr == unknown)
- symbol = "unknown";
- else
- symtab->findSymbol(addr, symbol);
-
- DPRINTFN("%#x: %s\n", addr, symbol);
- }
-}
-#endif
-
-} // namespace AlphaISA
+++ /dev/null
-/*
- * Copyright (c) 2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- */
-
-#ifndef __ARCH_ALPHA_STACKTRACE_HH__
-#define __ARCH_ALPHA_STACKTRACE_HH__
-
-#include "base/trace.hh"
-#include "cpu/static_inst.hh"
-#include "debug/Stack.hh"
-
-class ThreadContext;
-
-namespace AlphaISA {
-
-class StackTrace;
-
-class ProcessInfo
-{
- private:
- ThreadContext *tc;
-
- int thread_info_size;
- int task_struct_size;
- int task_off;
- int pid_off;
- int name_off;
-
- public:
- ProcessInfo(ThreadContext *_tc);
-
- Addr task(Addr ksp) const;
- int pid(Addr ksp) const;
- std::string name(Addr ksp) const;
-};
-
-class StackTrace
-{
- private:
- ThreadContext *tc;
- std::vector<Addr> stack;
-
- private:
- bool isEntry(Addr addr);
- bool decodePrologue(Addr sp, Addr callpc, Addr func, int &size, Addr &ra);
- bool decodeSave(MachInst inst, int ®, int &disp);
- bool decodeStack(MachInst inst, int &disp);
-
- void trace(ThreadContext *tc, bool is_call);
-
- public:
- StackTrace();
- StackTrace(ThreadContext *tc, const StaticInstPtr &inst);
- ~StackTrace();
-
- void
- clear()
- {
- tc = 0;
- stack.clear();
- }
-
- bool valid() const { return tc != NULL; }
- bool trace(ThreadContext *tc, const StaticInstPtr &inst);
-
- public:
- const std::vector<Addr> &getstack() const { return stack; }
-
- enum {
- user = 1,
- console = 2,
- unknown = 3
- };
-
-#if TRACING_ON
- private:
- void dump();
-
- public:
- void dprintf() { if (DTRACE(Stack)) dump(); }
-#else
- public:
- void dprintf() {}
-#endif
-};
-
-inline bool
-StackTrace::trace(ThreadContext *tc, const StaticInstPtr &inst)
-{
- if (!inst->isCall() && !inst->isReturn())
- return false;
-
- if (valid())
- clear();
-
- trace(tc, !inst->isReturn());
- return true;
-}
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_STACKTRACE_HH__
+++ /dev/null
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
- * Nathan Binkert
- */
-
-#include "arch/alpha/system.hh"
-
-#include <sys/signal.h>
-
-#include "arch/alpha/ev5.hh"
-#include "arch/alpha/faults.hh"
-#include "arch/vtophys.hh"
-#include "base/loader/object_file.hh"
-#include "base/loader/symtab.hh"
-#include "base/trace.hh"
-#include "debug/Loader.hh"
-#include "mem/fs_translating_port_proxy.hh"
-#include "params/AlphaSystem.hh"
-#include "sim/byteswap.hh"
-
-using namespace AlphaISA;
-
-AlphaSystem::AlphaSystem(Params *p)
- : System(p), intrFreq(0), virtProxy(getSystemPort(), p->cache_line_size)
-{
- consoleSymtab = new SymbolTable;
- palSymtab = new SymbolTable;
-
-
- /**
- * Load the pal, and console code into memory
- */
- // Load Console Code
- console = createObjectFile(params()->console);
- if (console == NULL)
- fatal("Could not load console file %s", params()->console);
-
- // Load pal file
- pal = createObjectFile(params()->pal);
- if (pal == NULL)
- fatal("Could not load PALcode file %s", params()->pal);
-
- // load symbols
- if (!console->loadGlobalSymbols(consoleSymtab))
- panic("could not load console symbols\n");
-
- if (!pal->loadGlobalSymbols(palSymtab))
- panic("could not load pal symbols\n");
-
- if (!pal->loadLocalSymbols(palSymtab))
- panic("could not load pal symbols\n");
-
- if (!console->loadGlobalSymbols(debugSymbolTable))
- panic("could not load console symbols\n");
-
- if (!pal->loadGlobalSymbols(debugSymbolTable))
- panic("could not load pal symbols\n");
-
- if (!pal->loadLocalSymbols(debugSymbolTable))
- panic("could not load pal symbols\n");
-
-
-}
-
-AlphaSystem::~AlphaSystem()
-{
- delete consoleSymtab;
- delete console;
- delete pal;
-#ifdef DEBUG
- delete consolePanicEvent;
-#endif
-}
-
-void
-AlphaSystem::initState()
-{
- Addr addr = 0;
-
- // Moved from the constructor to here since it relies on the
- // address map being resolved in the interconnect
-
- // Call the initialisation of the super class
- System::initState();
-
- for (auto *tc: threadContexts) {
- int cpuId = tc->contextId();
- initIPRs(tc, cpuId);
-
- tc->setIntReg(16, cpuId);
- tc->setIntReg(0, cpuId);
-
- Addr base = tc->readMiscRegNoEffect(IPR_PAL_BASE);
- Addr offset = ResetFault().vect();
-
- tc->pcState(base + offset);
-
- tc->activate();
- }
-
- // Load program sections into memory
- pal->buildImage().mask(loadAddrMask).write(physProxy);
- console->buildImage().mask(loadAddrMask).write(physProxy);
-
- /**
- * Copy the osflags (kernel arguments) into the consoles
- * memory. (Presently Linux does not use the console service
- * routine to get these command line arguments, but Tru64 and
- * others do.)
- */
- if (consoleSymtab->findAddress("env_booted_osflags", addr)) {
- virtProxy.writeBlob(addr, params()->boot_osflags.c_str(),
- strlen(params()->boot_osflags.c_str()));
- }
-
- /**
- * Set the hardware reset parameter block system type and revision
- * information to Tsunami.
- */
- if (consoleSymtab->findAddress("m5_rpb", addr)) {
- uint64_t data;
- data = htole(params()->system_type);
- virtProxy.write(addr+0x50, data);
- data = htole(params()->system_rev);
- virtProxy.write(addr+0x58, data);
- } else
- panic("could not find hwrpb\n");
-}
-
-void
-AlphaSystem::startup()
-{
- // Setup all the function events now that we have a system and a symbol
- // table
- setupFuncEvents();
-}
-
-void
-AlphaSystem::setupFuncEvents()
-{
-#ifndef NDEBUG
- consolePanicEvent = addConsoleFuncEvent<BreakPCEvent>("panic");
-#endif
-}
-
-/**
- * This function fixes up addresses that are used to match PCs for
- * hooking simulator events on to target function executions.
- *
- * Alpha binaries may have multiple global offset table (GOT)
- * sections. A function that uses the GOT starts with a
- * two-instruction prolog which sets the global pointer (gp == r29) to
- * the appropriate GOT section. The proper gp value is calculated
- * based on the function address, which must be passed by the caller
- * in the procedure value register (pv aka t12 == r27). This sequence
- * looks like the following:
- *
- * opcode Ra Rb offset
- * ldah gp,X(pv) 09 29 27 X
- * lda gp,Y(gp) 08 29 29 Y
- *
- * for some constant offsets X and Y. The catch is that the linker
- * (or maybe even the compiler, I'm not sure) may recognize that the
- * caller and callee are using the same GOT section, making this
- * prolog redundant, and modify the call target to skip these
- * instructions. If we check for execution of the first instruction
- * of a function (the one the symbol points to) to detect when to skip
- * it, we'll miss all these modified calls. It might work to
- * unconditionally check for the third instruction, but not all
- * functions have this prolog, and there's some chance that those
- * first two instructions could have undesired consequences. So we do
- * the Right Thing and pattern-match the first two instructions of the
- * function to decide where to patch.
- *
- * Eventually this code should be moved into an ISA-specific file.
- */
-Addr
-AlphaSystem::fixFuncEventAddr(Addr addr)
-{
- // mask for just the opcode, Ra, and Rb fields (not the offset)
- const uint32_t inst_mask = 0xffff0000;
- // ldah gp,X(pv): opcode 9, Ra = 29, Rb = 27
- const uint32_t gp_ldah_pattern = (9 << 26) | (29 << 21) | (27 << 16);
- // lda gp,Y(gp): opcode 8, Ra = 29, rb = 29
- const uint32_t gp_lda_pattern = (8 << 26) | (29 << 21) | (29 << 16);
-
- uint32_t i1 = virtProxy.read<uint32_t>(addr);
- uint32_t i2 = virtProxy.read<uint32_t>(addr + sizeof(MachInst));
-
- if ((i1 & inst_mask) == gp_ldah_pattern &&
- (i2 & inst_mask) == gp_lda_pattern) {
- Addr new_addr = addr + 2 * sizeof(MachInst);
- DPRINTF(Loader, "fixFuncEventAddr: %p -> %p", addr, new_addr);
- return new_addr;
- } else {
- return addr;
- }
-}
-
-void
-AlphaSystem::setAlphaAccess(Addr access)
-{
- Addr addr = 0;
- if (consoleSymtab->findAddress("m5AlphaAccess", addr)) {
- virtProxy.write(addr, htole(Phys2K0Seg(access)));
- } else {
- panic("could not find m5AlphaAccess\n");
- }
-}
-
-void
-AlphaSystem::serializeSymtab(CheckpointOut &cp) const
-{
- consoleSymtab->serialize("console_symtab", cp);
- palSymtab->serialize("pal_symtab", cp);
-}
-
-void
-AlphaSystem::unserializeSymtab(CheckpointIn &cp)
-{
- consoleSymtab->unserialize("console_symtab", cp);
- palSymtab->unserialize("pal_symtab", cp);
-}
-
-AlphaSystem *
-AlphaSystemParams::create()
-{
- return new AlphaSystem(this);
-}
+++ /dev/null
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
- * Nathan Binkert
- */
-
-#ifndef __ARCH_ALPHA_SYSTEM_HH__
-#define __ARCH_ALPHA_SYSTEM_HH__
-
-#include <string>
-#include <vector>
-
-#include "base/loader/symtab.hh"
-#include "cpu/pc_event.hh"
-#include "kern/system_events.hh"
-#include "mem/fs_translating_port_proxy.hh"
-#include "params/AlphaSystem.hh"
-#include "sim/sim_object.hh"
-#include "sim/system.hh"
-
-class AlphaSystem : public System
-{
- public:
- typedef AlphaSystemParams Params;
- AlphaSystem(Params *p);
- ~AlphaSystem();
-
- public:
-
- /**
- * Initialise the state of the system.
- */
- void initState() override;
-
- /**
- * Serialization stuff
- */
- void serializeSymtab(CheckpointOut &cp) const override;
- void unserializeSymtab(CheckpointIn &cp) override;
-
- /** Override startup() to provide a path to call setupFuncEvents()
- */
- void startup() override;
-
- /**
- * Set the m5AlphaAccess pointer in the console
- */
- void setAlphaAccess(Addr access);
-
- /** console symbol table */
- SymbolTable *consoleSymtab;
-
- /** pal symbol table */
- SymbolTable *palSymtab;
-
- /** Object pointer for the console code */
- ObjectFile *console;
-
- /** Object pointer for the PAL code */
- ObjectFile *pal;
-
-#ifndef NDEBUG
- /** Event to halt the simulator if the console calls panic() */
- BreakPCEvent *consolePanicEvent;
-#endif
-
- protected:
- Tick intrFreq;
-
- /**
- * Proxy used to copy arguments directly into kernel memory.
- */
- FSTranslatingPortProxy virtProxy;
-
- const Params *params() const { return (const Params *)_params; }
-
-
- /** Setup all the function events. Must be done after init() for Alpha since
- * fixFuncEvent() requires a function port
- */
- virtual void setupFuncEvents();
-
- /** Add a function-based event to PALcode. */
- template <class T>
- T *
- addPalFuncEvent(const char *lbl)
- {
- return addFuncEvent<T>(palSymtab, lbl);
- }
-
- /** Add a function-based event to the console code. */
- template <class T>
- T *
- addConsoleFuncEvent(const char *lbl)
- {
- return addFuncEvent<T>(consoleSymtab, lbl);
- }
-
- Addr fixFuncEventAddr(Addr addr) override;
-
- public:
- void setIntrFreq(Tick freq) { intrFreq = freq; }
-};
-
-#endif // __ARCH_ALPHA_SYSTEM_HH__
-
+++ /dev/null
-/*
- * Copyright (c) 2001-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- * Steve Reinhardt
- * Andrew Schultz
- */
-
-#include "arch/alpha/tlb.hh"
-
-#include <algorithm>
-#include <memory>
-#include <string>
-#include <vector>
-
-#include "arch/alpha/faults.hh"
-#include "arch/alpha/pagetable.hh"
-#include "arch/generic/debugfaults.hh"
-#include "base/inifile.hh"
-#include "base/str.hh"
-#include "base/trace.hh"
-#include "cpu/thread_context.hh"
-#include "debug/TLB.hh"
-#include "sim/full_system.hh"
-
-using namespace std;
-
-namespace AlphaISA {
-
-///////////////////////////////////////////////////////////////////////
-//
-// Alpha TLB
-//
-
-#ifdef DEBUG
-bool uncacheBit39 = false;
-bool uncacheBit40 = false;
-#endif
-
-#define MODE2MASK(X) (1 << (X))
-
-TLB::TLB(const Params *p)
- : BaseTLB(p), table(p->size), nlu(0)
-{
- flushCache();
-}
-
-TLB::~TLB()
-{
-}
-
-void
-TLB::regStats()
-{
- BaseTLB::regStats();
-
- fetch_hits
- .name(name() + ".fetch_hits")
- .desc("ITB hits");
- fetch_misses
- .name(name() + ".fetch_misses")
- .desc("ITB misses");
- fetch_acv
- .name(name() + ".fetch_acv")
- .desc("ITB acv");
- fetch_accesses
- .name(name() + ".fetch_accesses")
- .desc("ITB accesses");
-
- fetch_accesses = fetch_hits + fetch_misses;
-
- read_hits
- .name(name() + ".read_hits")
- .desc("DTB read hits")
- ;
-
- read_misses
- .name(name() + ".read_misses")
- .desc("DTB read misses")
- ;
-
- read_acv
- .name(name() + ".read_acv")
- .desc("DTB read access violations")
- ;
-
- read_accesses
- .name(name() + ".read_accesses")
- .desc("DTB read accesses")
- ;
-
- write_hits
- .name(name() + ".write_hits")
- .desc("DTB write hits")
- ;
-
- write_misses
- .name(name() + ".write_misses")
- .desc("DTB write misses")
- ;
-
- write_acv
- .name(name() + ".write_acv")
- .desc("DTB write access violations")
- ;
-
- write_accesses
- .name(name() + ".write_accesses")
- .desc("DTB write accesses")
- ;
-
- data_hits
- .name(name() + ".data_hits")
- .desc("DTB hits")
- ;
-
- data_misses
- .name(name() + ".data_misses")
- .desc("DTB misses")
- ;
-
- data_acv
- .name(name() + ".data_acv")
- .desc("DTB access violations")
- ;
-
- data_accesses
- .name(name() + ".data_accesses")
- .desc("DTB accesses")
- ;
-
- data_hits = read_hits + write_hits;
- data_misses = read_misses + write_misses;
- data_acv = read_acv + write_acv;
- data_accesses = read_accesses + write_accesses;
-}
-
-// look up an entry in the TLB
-TlbEntry *
-TLB::lookup(Addr vpn, uint8_t asn)
-{
- // assume not found...
- TlbEntry *retval = NULL;
-
- if (EntryCache[0]) {
- if (vpn == EntryCache[0]->tag &&
- (EntryCache[0]->asma || EntryCache[0]->asn == asn))
- retval = EntryCache[0];
- else if (EntryCache[1]) {
- if (vpn == EntryCache[1]->tag &&
- (EntryCache[1]->asma || EntryCache[1]->asn == asn))
- retval = EntryCache[1];
- else if (EntryCache[2] && vpn == EntryCache[2]->tag &&
- (EntryCache[2]->asma || EntryCache[2]->asn == asn))
- retval = EntryCache[2];
- }
- }
-
- if (retval == NULL) {
- PageTable::const_iterator i = lookupTable.find(vpn);
- if (i != lookupTable.end()) {
- while (i->first == vpn) {
- int index = i->second;
- TlbEntry *entry = &table[index];
- assert(entry->valid);
- if (vpn == entry->tag && (entry->asma || entry->asn == asn)) {
- retval = updateCache(entry);
- break;
- }
-
- ++i;
- }
- }
- }
-
- DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
- retval ? "hit" : "miss", retval ? retval->ppn : 0);
- return retval;
-}
-
-Fault
-TLB::checkCacheability(const RequestPtr &req, bool itb)
-{
- // in Alpha, cacheability is controlled by upper-level bits of the
- // physical address
-
- /*
- * We support having the uncacheable bit in either bit 39 or bit
- * 40. The Turbolaser platform (and EV5) support having the bit
- * in 39, but Tsunami (which Linux assumes uses an EV6) generates
- * accesses with the bit in 40. So we must check for both, but we
- * have debug flags to catch a weird case where both are used,
- * which shouldn't happen.
- */
-
-
- if (req->getPaddr() & PAddrUncachedBit43) {
- // IPR memory space not implemented
- if (PAddrIprSpace(req->getPaddr())) {
- return std::make_shared<UnimpFault>(
- "IPR memory space not implemented!");
- } else {
- // mark request as uncacheable
- req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
-
- // Clear bits 42:35 of the physical address (10-2 in
- // Tsunami manual)
- req->setPaddr(req->getPaddr() & PAddrUncachedMask);
- }
- // We shouldn't be able to read from an uncachable address in Alpha as
- // we don't have a ROM and we don't want to try to fetch from a device
- // register as we destroy any data that is clear-on-read.
- if (req->isUncacheable() && itb)
- return std::make_shared<UnimpFault>(
- "CPU trying to fetch from uncached I/O");
-
- }
- return NoFault;
-}
-
-
-// insert a new TLB entry
-void
-TLB::insert(Addr addr, TlbEntry &entry)
-{
- flushCache();
- VAddr vaddr = addr;
- if (table[nlu].valid) {
- Addr oldvpn = table[nlu].tag;
- PageTable::iterator i = lookupTable.find(oldvpn);
-
- if (i == lookupTable.end())
- panic("TLB entry not found in lookupTable");
-
- int index;
- while ((index = i->second) != nlu) {
- if (table[index].tag != oldvpn)
- panic("TLB entry not found in lookupTable");
-
- ++i;
- }
-
- DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn);
-
- lookupTable.erase(i);
- }
-
- DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), entry.ppn);
-
- table[nlu] = entry;
- table[nlu].tag = vaddr.vpn();
- table[nlu].valid = true;
-
- lookupTable.insert(make_pair(vaddr.vpn(), nlu));
- nextnlu();
-}
-
-void
-TLB::flushAll()
-{
- DPRINTF(TLB, "flushAll\n");
- std::fill(table.begin(), table.end(), TlbEntry());
- flushCache();
- lookupTable.clear();
- nlu = 0;
-}
-
-void
-TLB::flushProcesses()
-{
- flushCache();
- PageTable::iterator i = lookupTable.begin();
- PageTable::iterator end = lookupTable.end();
- while (i != end) {
- int index = i->second;
- TlbEntry *entry = &table[index];
- assert(entry->valid);
-
- // we can't increment i after we erase it, so save a copy and
- // increment it to get the next entry now
- PageTable::iterator cur = i;
- ++i;
-
- if (!entry->asma) {
- DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index,
- entry->tag, entry->ppn);
- entry->valid = false;
- lookupTable.erase(cur);
- }
- }
-}
-
-void
-TLB::flushAddr(Addr addr, uint8_t asn)
-{
- flushCache();
- VAddr vaddr = addr;
-
- PageTable::iterator i = lookupTable.find(vaddr.vpn());
- if (i == lookupTable.end())
- return;
-
- while (i != lookupTable.end() && i->first == vaddr.vpn()) {
- int index = i->second;
- TlbEntry *entry = &table[index];
- assert(entry->valid);
-
- if (vaddr.vpn() == entry->tag && (entry->asma || entry->asn == asn)) {
- DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(),
- entry->ppn);
-
- // invalidate this entry
- entry->valid = false;
-
- lookupTable.erase(i++);
- } else {
- ++i;
- }
- }
-}
-
-
-void
-TLB::serialize(CheckpointOut &cp) const
-{
- const unsigned size(table.size());
- SERIALIZE_SCALAR(size);
- SERIALIZE_SCALAR(nlu);
-
- for (int i = 0; i < size; i++)
- table[i].serializeSection(cp, csprintf("Entry%d", i));
-}
-
-void
-TLB::unserialize(CheckpointIn &cp)
-{
- unsigned size(0);
- UNSERIALIZE_SCALAR(size);
- UNSERIALIZE_SCALAR(nlu);
-
- table.resize(size);
- for (int i = 0; i < size; i++) {
- table[i].unserializeSection(cp, csprintf("Entry%d", i));
- if (table[i].valid) {
- lookupTable.insert(make_pair(table[i].tag, i));
- }
- }
-}
-
-Fault
-TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
-{
- //If this is a pal pc, then set PHYSICAL
- if (FullSystem && PcPAL(req->getPC()))
- req->setFlags(Request::PHYSICAL);
-
- if (PcPAL(req->getPC())) {
- // strip off PAL PC marker (lsb is 1)
- req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
- fetch_hits++;
- return NoFault;
- }
-
- if (req->getFlags() & Request::PHYSICAL) {
- req->setPaddr(req->getVaddr());
- } else {
- // verify that this is a good virtual address
- if (!validVirtualAddress(req->getVaddr())) {
- fetch_acv++;
- return std::make_shared<ItbAcvFault>(req->getVaddr());
- }
-
-
- // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
- // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
- if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
- // only valid in kernel mode
- if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) !=
- mode_kernel) {
- fetch_acv++;
- return std::make_shared<ItbAcvFault>(req->getVaddr());
- }
-
- req->setPaddr(req->getVaddr() & PAddrImplMask);
-
- // sign extend the physical address properly
- if (req->getPaddr() & PAddrUncachedBit40)
- req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
- else
- req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
- } else {
- // not a physical address: need to look up pte
- int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
- TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(),
- asn);
-
- if (!entry) {
- fetch_misses++;
- return std::make_shared<ItbPageFault>(req->getVaddr());
- }
-
- req->setPaddr((entry->ppn << PageShift) +
- (VAddr(req->getVaddr()).offset()
- & ~3));
-
- // check permissions for this access
- if (!(entry->xre &
- (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) {
- // instruction access fault
- fetch_acv++;
- return std::make_shared<ItbAcvFault>(req->getVaddr());
- }
-
- fetch_hits++;
- }
- }
-
- // check that the physical address is ok (catch bad physical addresses)
- if (req->getPaddr() & ~PAddrImplMask) {
- return std::make_shared<MachineCheckFault>();
- }
-
- return checkCacheability(req, true);
-
-}
-
-Fault
-TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
-{
- mode_type mode =
- (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM));
-
- /**
- * Check for alignment faults
- */
- if (req->getVaddr() & (req->getSize() - 1)) {
- DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(),
- req->getSize());
- uint64_t flags = write ? MM_STAT_WR_MASK : 0;
- return std::make_shared<DtbAlignmentFault>(req->getVaddr(),
- req->getFlags(),
- flags);
- }
-
- if (PcPAL(req->getPC())) {
- mode = (req->getFlags() & AlphaRequestFlags::ALTMODE) ?
- (mode_type)ALT_MODE_AM(
- tc->readMiscRegNoEffect(IPR_ALT_MODE))
- : mode_kernel;
- }
-
- if (req->getFlags() & Request::PHYSICAL) {
- req->setPaddr(req->getVaddr());
- } else {
- // verify that this is a good virtual address
- if (!validVirtualAddress(req->getVaddr())) {
- if (write) { write_acv++; } else { read_acv++; }
- uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
- MM_STAT_BAD_VA_MASK |
- MM_STAT_ACV_MASK;
- return std::make_shared<DtbPageFault>(req->getVaddr(),
- req->getFlags(),
- flags);
- }
-
- // Check for "superpage" mapping
- if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
- // only valid in kernel mode
- if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) !=
- mode_kernel) {
- if (write) { write_acv++; } else { read_acv++; }
- uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
- MM_STAT_ACV_MASK);
-
- return std::make_shared<DtbAcvFault>(req->getVaddr(),
- req->getFlags(),
- flags);
- }
-
- req->setPaddr(req->getVaddr() & PAddrImplMask);
-
- // sign extend the physical address properly
- if (req->getPaddr() & PAddrUncachedBit40)
- req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
- else
- req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
- } else {
- if (write)
- write_accesses++;
- else
- read_accesses++;
-
- int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
-
- // not a physical address: need to look up pte
- TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), asn);
-
- if (!entry) {
- // page fault
- if (write) { write_misses++; } else { read_misses++; }
- uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
- MM_STAT_DTB_MISS_MASK;
- return (req->getFlags() & AlphaRequestFlags::VPTE) ?
- (Fault)(std::make_shared<PDtbMissFault>(req->getVaddr(),
- req->getFlags(),
- flags)) :
- (Fault)(std::make_shared<NDtbMissFault>(req->getVaddr(),
- req->getFlags(),
- flags));
- }
-
- req->setPaddr((entry->ppn << PageShift) +
- VAddr(req->getVaddr()).offset());
-
- if (write) {
- if (!(entry->xwe & MODE2MASK(mode))) {
- // declare the instruction access fault
- write_acv++;
- uint64_t flags = MM_STAT_WR_MASK |
- MM_STAT_ACV_MASK |
- (entry->fonw ? MM_STAT_FONW_MASK : 0);
- return std::make_shared<DtbPageFault>(req->getVaddr(),
- req->getFlags(),
- flags);
- }
- if (entry->fonw) {
- write_acv++;
- uint64_t flags = MM_STAT_WR_MASK | MM_STAT_FONW_MASK;
- return std::make_shared<DtbPageFault>(req->getVaddr(),
- req->getFlags(),
- flags);
- }
- } else {
- if (!(entry->xre & MODE2MASK(mode))) {
- read_acv++;
- uint64_t flags = MM_STAT_ACV_MASK |
- (entry->fonr ? MM_STAT_FONR_MASK : 0);
- return std::make_shared<DtbAcvFault>(req->getVaddr(),
- req->getFlags(),
- flags);
- }
- if (entry->fonr) {
- read_acv++;
- uint64_t flags = MM_STAT_FONR_MASK;
- return std::make_shared<DtbPageFault>(req->getVaddr(),
- req->getFlags(),
- flags);
- }
- }
- }
-
- if (write)
- write_hits++;
- else
- read_hits++;
- }
-
- // check that the physical address is ok (catch bad physical addresses)
- if (req->getPaddr() & ~PAddrImplMask) {
- return std::make_shared<MachineCheckFault>();
- }
-
- return checkCacheability(req);
-}
-
-TlbEntry &
-TLB::index(bool advance)
-{
- TlbEntry *entry = &table[nlu];
-
- if (advance)
- nextnlu();
-
- return *entry;
-}
-
-Fault
-TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
-{
- if (mode == Execute)
- return translateInst(req, tc);
- else
- return translateData(req, tc, mode == Write);
-}
-
-void
-TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
- Translation *translation, Mode mode)
-{
- assert(translation);
- translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
-}
-
-Fault
-TLB::finalizePhysical(const RequestPtr &req, ThreadContext *tc,
- Mode mode) const
-{
- return NoFault;
-}
-
-} // namespace AlphaISA
-
-AlphaISA::TLB *
-AlphaTLBParams::create()
-{
- return new AlphaISA::TLB(this);
-}
+++ /dev/null
-/*
- * Copyright (c) 2001-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- * Steve Reinhardt
- */
-
-#ifndef __ARCH_ALPHA_TLB_HH__
-#define __ARCH_ALPHA_TLB_HH__
-
-#include <map>
-
-#include "arch/alpha/ev5.hh"
-#include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/pagetable.hh"
-#include "arch/alpha/utility.hh"
-#include "arch/alpha/vtophys.hh"
-#include "arch/generic/tlb.hh"
-#include "base/statistics.hh"
-#include "mem/request.hh"
-#include "params/AlphaTLB.hh"
-
-class ThreadContext;
-
-namespace AlphaISA {
-
-struct TlbEntry;
-
-class TLB : public BaseTLB
-{
- protected:
- mutable Stats::Scalar fetch_hits;
- mutable Stats::Scalar fetch_misses;
- mutable Stats::Scalar fetch_acv;
- mutable Stats::Formula fetch_accesses;
- mutable Stats::Scalar read_hits;
- mutable Stats::Scalar read_misses;
- mutable Stats::Scalar read_acv;
- mutable Stats::Scalar read_accesses;
- mutable Stats::Scalar write_hits;
- mutable Stats::Scalar write_misses;
- mutable Stats::Scalar write_acv;
- mutable Stats::Scalar write_accesses;
- Stats::Formula data_hits;
- Stats::Formula data_misses;
- Stats::Formula data_acv;
- Stats::Formula data_accesses;
-
-
- typedef std::multimap<Addr, int> PageTable;
- PageTable lookupTable; // Quick lookup into page table
-
- std::vector<TlbEntry> table; // the Page Table
- int nlu; // not last used entry (for replacement)
-
- void nextnlu() { if (++nlu >= table.size()) nlu = 0; }
- TlbEntry *lookup(Addr vpn, uint8_t asn);
-
- public:
- typedef AlphaTLBParams Params;
- TLB(const Params *p);
- virtual ~TLB();
-
- void takeOverFrom(BaseTLB *otlb) override {}
-
- void regStats() override;
-
- int getsize() const { return table.size(); }
-
- TlbEntry &index(bool advance = true);
- void insert(Addr vaddr, TlbEntry &entry);
-
- void flushAll() override;
- void flushProcesses();
- void flushAddr(Addr addr, uint8_t asn);
-
- void
- demapPage(Addr vaddr, uint64_t asn) override
- {
- assert(asn < (1 << 8));
- flushAddr(vaddr, asn);
- }
-
- // static helper functions... really EV5 VM traits
- static bool
- validVirtualAddress(Addr vaddr)
- {
- // unimplemented bits must be all 0 or all 1
- Addr unimplBits = vaddr & VAddrUnImplMask;
- return unimplBits == 0 || unimplBits == VAddrUnImplMask;
- }
-
- static Fault checkCacheability(const RequestPtr &req, bool itb = false);
-
- // Checkpointing
- void serialize(CheckpointOut &cp) const override;
- void unserialize(CheckpointIn &cp) override;
-
- // Most recently used page table entries
- TlbEntry *EntryCache[3];
- inline void
- flushCache()
- {
- memset(EntryCache, 0, 3 * sizeof(TlbEntry*));
- }
-
- inline TlbEntry *
- updateCache(TlbEntry *entry) {
- EntryCache[2] = EntryCache[1];
- EntryCache[1] = EntryCache[0];
- EntryCache[0] = entry;
- return entry;
- }
-
- protected:
- Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
- Fault translateInst(const RequestPtr &req, ThreadContext *tc);
-
- public:
- Fault translateAtomic(
- const RequestPtr &req, ThreadContext *tc, Mode mode) override;
- void translateTiming(
- const RequestPtr &req, ThreadContext *tc,
- Translation *translation, Mode mode) override;
- Fault finalizePhysical(
- const RequestPtr &req, ThreadContext *tc,
- Mode mode) const override;
-};
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_TLB_HH__
+++ /dev/null
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- * Steve Reinhardt
- */
-
-#ifndef __ARCH_ALPHA_TYPES_HH__
-#define __ARCH_ALPHA_TYPES_HH__
-
-#include "arch/generic/types.hh"
-#include "base/types.hh"
-
-namespace AlphaISA {
-
-typedef uint32_t MachInst;
-typedef uint64_t ExtMachInst;
-
-typedef GenericISA::SimplePCState<MachInst> PCState;
-
-enum annotes
-{
- ANNOTE_NONE = 0,
- // An impossible number for instruction annotations
- ITOUCH_ANNOTE = 0xffffffff
-};
-
-/**
- * Alpha-specific memory request flags
- *
- * These flags map to the architecture-specific lower 8 bits of the
- * flags field in Request.
- */
-struct AlphaRequestFlags
-{
- typedef uint8_t ArchFlagsType;
-
- /** The request is an ALPHA VPTE pal access (hw_ld). */
- static const ArchFlagsType VPTE = 0x01;
- /** Use the alternate mode bits in ALPHA. */
- static const ArchFlagsType ALTMODE = 0x02;
-};
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_TYPES_HH__
+++ /dev/null
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- * Ali Saidi
- */
-
-#include "arch/alpha/utility.hh"
-
-#include "arch/alpha/vtophys.hh"
-#include "mem/fs_translating_port_proxy.hh"
-#include "sim/full_system.hh"
-
-namespace AlphaISA {
-
-uint64_t
-getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
-{
- if (!FullSystem) {
- panic("getArgument() is Full system only\n");
- M5_DUMMY_RETURN;
- }
-
- const int NumArgumentRegs = 6;
- if (number < NumArgumentRegs) {
- if (fp)
- return tc->readFloatReg(16 + number);
- else
- return tc->readIntReg(16 + number);
- } else {
- Addr sp = tc->readIntReg(StackPointerReg);
- PortProxy &vp = tc->getVirtProxy();
- uint64_t arg = vp.read<uint64_t>(sp +
- (number-NumArgumentRegs) *
- sizeof(uint64_t));
- return arg;
- }
-}
-
-void
-copyRegs(ThreadContext *src, ThreadContext *dest)
-{
- // First loop through the integer registers.
- for (int i = 0; i < NumIntRegs; ++i)
- dest->setIntReg(i, src->readIntReg(i));
-
- // Then loop through the floating point registers.
- for (int i = 0; i < NumFloatRegs; ++i)
- dest->setFloatReg(i, src->readFloatReg(i));
-
- // Would need to add condition-code regs if implemented
- assert(NumCCRegs == 0);
-
- // Copy misc. registers
- copyMiscRegs(src, dest);
-
- // Lastly copy PC/NPC
- dest->pcState(src->pcState());
-}
-
-void
-copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
- dest->setMiscRegNoEffect(MISCREG_FPCR,
- src->readMiscRegNoEffect(MISCREG_FPCR));
- dest->setMiscRegNoEffect(MISCREG_UNIQ,
- src->readMiscRegNoEffect(MISCREG_UNIQ));
- dest->setMiscRegNoEffect(MISCREG_LOCKFLAG,
- src->readMiscRegNoEffect(MISCREG_LOCKFLAG));
- dest->setMiscRegNoEffect(MISCREG_LOCKADDR,
- src->readMiscRegNoEffect(MISCREG_LOCKADDR));
-
- copyIprs(src, dest);
-}
-
-void
-skipFunction(ThreadContext *tc)
-{
- PCState newPC = tc->pcState();
- newPC.set(tc->readIntReg(ReturnAddressReg));
- tc->pcState(newPC);
-}
-
-
-} // namespace AlphaISA
-
+++ /dev/null
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- * Steve Reinhardt
- */
-
-#ifndef __ARCH_ALPHA_UTILITY_HH__
-#define __ARCH_ALPHA_UTILITY_HH__
-
-#include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/registers.hh"
-#include "arch/alpha/types.hh"
-#include "base/logging.hh"
-#include "cpu/static_inst.hh"
-#include "cpu/thread_context.hh"
-#include "arch/alpha/ev5.hh"
-
-namespace AlphaISA {
-
-inline PCState
-buildRetPC(const PCState &curPC, const PCState &callPC)
-{
- PCState retPC = callPC;
- retPC.advance();
- return retPC;
-}
-
-uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
-
-inline bool
-inUserMode(ThreadContext *tc)
-{
- return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
-}
-
-// Alpha IPR register accessors
-inline bool PcPAL(Addr addr) { return addr & 0x3; }
-
-////////////////////////////////////////////////////////////////////////
-//
-// Translation stuff
-//
-
-inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
-
-// User Virtual
-inline bool IsUSeg(Addr a) { assert(USegBase == 0); return a <= USegEnd; }
-
-// Kernel Direct Mapped
-inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; }
-inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; }
-
-// Kernel Virtual
-inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; }
-
-inline Addr
-TruncPage(Addr addr)
-{ return addr & ~(PageBytes - 1); }
-
-inline Addr
-RoundPage(Addr addr)
-{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
-
-void initIPRs(ThreadContext *tc, int cpuId);
-
-void copyRegs(ThreadContext *src, ThreadContext *dest);
-
-void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
-
-void skipFunction(ThreadContext *tc);
-
-inline void
-advancePC(PCState &pc, const StaticInstPtr &inst)
-{
- pc.advance();
-}
-
-inline uint64_t
-getExecutingAsid(ThreadContext *tc)
-{
- return DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN));
-}
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_UTILITY_HH__
+++ /dev/null
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- * Steve Reinhardt
- * Ali Saidi
- */
-
-#include "arch/alpha/vtophys.hh"
-
-#include <string>
-
-#include "arch/alpha/ev5.hh"
-#include "base/chunk_generator.hh"
-#include "base/trace.hh"
-#include "cpu/thread_context.hh"
-#include "debug/VtoPhys.hh"
-#include "mem/port_proxy.hh"
-
-using namespace std;
-
-namespace AlphaISA {
-
-PageTableEntry
-kernel_pte_lookup(PortProxy &mem, Addr ptbr, VAddr vaddr)
-{
- Addr level1_pte = ptbr + vaddr.level1();
- PageTableEntry level1 = mem.read<uint64_t>(level1_pte);
- if (!level1.valid()) {
- DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr);
- return 0;
- }
-
- Addr level2_pte = level1.paddr() + vaddr.level2();
- PageTableEntry level2 = mem.read<uint64_t>(level2_pte);
- if (!level2.valid()) {
- DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr);
- return 0;
- }
-
- Addr level3_pte = level2.paddr() + vaddr.level3();
- PageTableEntry level3 = mem.read<uint64_t>(level3_pte);
- if (!level3.valid()) {
- DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr);
- return 0;
- }
- return level3;
-}
-
-Addr
-vtophys(Addr vaddr)
-{
- Addr paddr = 0;
- if (IsUSeg(vaddr))
- DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
- else if (IsK0Seg(vaddr))
- paddr = K0Seg2Phys(vaddr);
- else
- panic("vtophys: ptbr is not set on virtual lookup");
-
- DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
-
- return paddr;
-}
-
-Addr
-vtophys(ThreadContext *tc, Addr addr)
-{
- VAddr vaddr = addr;
- Addr ptbr = tc->readMiscRegNoEffect(IPR_PALtemp20);
- Addr paddr = 0;
- //@todo Andrew couldn't remember why he commented some of this code
- //so I put it back in. Perhaps something to do with gdb debugging?
- if (PcPAL(vaddr) && (vaddr < PalMax)) {
- paddr = vaddr & ~ULL(1);
- } else {
- if (IsK0Seg(vaddr)) {
- paddr = K0Seg2Phys(vaddr);
- } else if (!ptbr) {
- paddr = vaddr;
- } else {
- PageTableEntry pte =
- kernel_pte_lookup(tc->getPhysProxy(), ptbr, vaddr);
- if (pte.valid())
- paddr = pte.paddr() | vaddr.offset();
- }
- }
-
-
- DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
-
- return paddr;
-}
-
-} // namespace AlphaISA
+++ /dev/null
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- * Steve Reinhardt
- */
-
-#ifndef __ARCH_ALPHA_VTOPHYS_H__
-#define __ARCH_ALPHA_VTOPHYS_H__
-
-#include "arch/alpha/isa_traits.hh"
-#include "arch/alpha/pagetable.hh"
-#include "arch/alpha/utility.hh"
-
-class ThreadContext;
-class PortProxy;
-
-namespace AlphaISA {
-
-PageTableEntry kernel_pte_lookup(PortProxy &mem, Addr ptbr,
- VAddr vaddr);
-
-Addr vtophys(Addr vaddr);
-Addr vtophys(ThreadContext *tc, Addr vaddr);
-
-} // namespace AlphaISA
-
-#endif // __ARCH_ALPHA_VTOPHYS_H__
-
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