sv: complete support for implied task/function port directions

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 678ce6c8759ae572dc5b7b0d5192b76aebc631b3..6c4b06d7feb823fd719167e8b106790f733d5882 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -884,7 +884,11 @@ task_func_args:
 
 task_func_port:
        attr wire_type range {
+               bool prev_was_input = true;
+               bool prev_was_output = false;
                if (albuf) {
+                       prev_was_input = astbuf1->is_input;
+                       prev_was_output = astbuf1->is_output;
                        delete astbuf1;
                        if (astbuf2 != NULL)
                                delete astbuf2;
@@ -893,6 +897,12 @@ task_func_port:
                albuf = $1;
                astbuf1 = $2;
                astbuf2 = checkRange(astbuf1, $3);
+               if (!astbuf1->is_input && !astbuf1->is_output) {
+                       if (!sv_mode)
+                               frontend_verilog_yyerror("task/function argument direction missing");
+                       astbuf1->is_input = prev_was_input;
+                       astbuf1->is_output = prev_was_output;
+               }
        } wire_name |
        {
                if (!astbuf1) {

diff --git a/tests/various/func_port_implied_dir.sv b/tests/various/func_port_implied_dir.sv
new file mode 100644 (file)
index 0000000..0424f1b
--- /dev/null
+++ b/tests/various/func_port_implied_dir.sv
@@ -0,0 +1,23 @@
+module gate(w, x, y, z);
+       function automatic integer bar(
+               integer a
+       );
+               bar = 2 ** a;
+       endfunction
+       output integer w = bar(4);
+
+       function automatic integer foo(
+               input integer a, /* implicitly input */ integer b,
+               output integer c, /* implicitly output */ integer d
+       );
+               c = 42;
+               d = 51;
+               foo = a + b + 1;
+       endfunction
+       output integer x, y, z;
+       initial x = foo(1, 2, y, z);
+endmodule
+
+module gold(w, x, y, z);
+       output integer w = 16, x = 4, y = 42, z = 51;
+endmodule

diff --git a/tests/various/func_port_implied_dir.ys b/tests/various/func_port_implied_dir.ys
new file mode 100644 (file)
index 0000000..b5c22a0
--- /dev/null
+++ b/tests/various/func_port_implied_dir.ys
@@ -0,0 +1,6 @@
+read_verilog -sv func_port_implied_dir.sv
+hierarchy
+proc
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert