tools: litex_gen: fix missing UART pins

diff --git a/litex/tools/litex_gen.py b/litex/tools/litex_gen.py
index 465be327f7f1cda55bdba53822c03fa4d4608760..39904ef642ad424967923a7a86bf88e7d4d221a4 100755 (executable)
--- a/litex/tools/litex_gen.py
+++ b/litex/tools/litex_gen.py
@@ -49,6 +49,15 @@ class LiteXCore(SoCMini):
 
         platform = Platform(_io)
 
+        # UART
+        if kwargs["with_uart"]:
+            platform.add_extension([
+                ("serial", 0,
+                    Subsignal("tx",  Pins(1)),
+                    Subsignal("rx", Pins(1)),
+                )
+            ])
+
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = CRG(platform.request("sys_clk"), rst=platform.request("sys_rst"))