# when predicate not set: 0=ignore/skip 1=zero
DZ = 3 # for destination
SZ = 4 # for source
+ ZZ = 3 # for both sz/dz, on all but CR-ops
# for branch-conditional
BC_SNZ = 3 # for branch-conditional mode
BC_VLI = 2 # for VL include/exclude on VLSET mode
sv_mode = 0b10
saturation = 0
# predicate zeroing
+ elif encmode == 'zz': # TODO, a lot more checking on legality
+ dst_zero = 1 # NOT on cr_ops, that's RM[6]
elif encmode == 'sz':
src_zero = 1
elif encmode == 'dz':
"""
| 0-1 | 2 | 3 4 | description |
| --- | --- |---------|--------------------------- |
- | 00 | 0 | dz els | normal mode |
- | 00 | 1 | dz shf | shift mode |
+ | 00 | 0 | zz els | normal mode |
+ | 00 | 1 | / / | reserved |
| 01 | inv | CR-bit | Rc=1: ffirst CR sel |
| 01 | inv | els RC1 | Rc=0: ffirst z/nonz |
- | 10 | N | dz els | sat mode: N=0/1 u/s |
+ | 10 | N | zz els | sat mode: N=0/1 u/s |
| 11 | inv | CR-bit | Rc=1: pred-result CR sel |
| 11 | inv | els RC1 | Rc=0: pred-result z/nonz |
"""