Flattening and syscallReturn fixes

src/cpu/o3/thread_context_impl.hh:
    Use flattened indices
src/cpu/simple_thread.hh:
    Use flattened indices, and pass a thread context to setSyscallReturn rather than a register file.
src/cpu/thread_context.hh:
    The SyscallReturn class is no longer in arch/syscallreturn.hh

--HG--
extra : convert_revision : ed84bb8ac5ef0774526ecd0d7270b0c60cd3708e

diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 0180756e38d3c152729f25c7f9a7b9a013e034c4..29c00a0c30ca9968d4e19e707a616240f9e12be2 100755 (executable)
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -29,6 +29,7 @@
  *          Korey Sewell
  */
 
+#include "arch/regfile.hh"
 #include "cpu/o3/thread_context.hh"
 #include "cpu/quiesce_event.hh"
 
@@ -303,6 +304,7 @@ template <class Impl>
 uint64_t
 O3ThreadContext<Impl>::readIntReg(int reg_idx)
 {
+    reg_idx = TheISA::flattenIntIndex(this, reg_idx);
     return cpu->readArchIntReg(reg_idx, thread->readTid());
 }
 
@@ -347,6 +349,7 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
 {
+    reg_idx = TheISA::flattenIntIndex(this, reg_idx);
     cpu->setArchIntReg(reg_idx, val, thread->readTid());
 
     // Squash if we're not already in a state update mode.

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index e8757c8c20b67e56de3f5f7953c83b7459f884cf..acbefeb67cdb242433dab1edf95325eb717bd5ac 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -33,6 +33,8 @@
 #define __CPU_SIMPLE_THREAD_HH__
 
 #include "arch/isa_traits.hh"
+#include "arch/regfile.hh"
+#include "arch/syscallreturn.hh"
 #include "config/full_system.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/thread_state.hh"
@@ -319,7 +321,7 @@ class SimpleThread : public ThreadState
     //
     uint64_t readIntReg(int reg_idx)
     {
-        return regs.readIntReg(reg_idx);
+        return regs.readIntReg(TheISA::flattenIntIndex(getTC(), reg_idx));
     }
 
     FloatReg readFloatReg(int reg_idx, int width)
@@ -344,7 +346,7 @@ class SimpleThread : public ThreadState
 
     void setIntReg(int reg_idx, uint64_t val)
     {
-        regs.setIntReg(reg_idx, val);
+        regs.setIntReg(TheISA::flattenIntIndex(getTC(), reg_idx), val);
     }
 
     void setFloatReg(int reg_idx, FloatReg val, int width)
@@ -445,18 +447,20 @@ class SimpleThread : public ThreadState
 #if !FULL_SYSTEM
     TheISA::IntReg getSyscallArg(int i)
     {
-        return regs.readIntReg(TheISA::ArgumentReg0 + i);
+        return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
+                    TheISA::ArgumentReg0 + i));
     }
 
     // used to shift args for indirect syscall
     void setSyscallArg(int i, TheISA::IntReg val)
     {
-        regs.setIntReg(TheISA::ArgumentReg0 + i, val);
+        regs.setIntReg(TheISA::flattenIntIndex(getTC(),
+                    TheISA::ArgumentReg0 + i), val);
     }
 
     void setSyscallReturn(SyscallReturn return_value)
     {
-        TheISA::setSyscallReturn(return_value, &regs);
+        TheISA::setSyscallReturn(return_value, getTC());
     }
 
     void syscall(int64_t callnum)

diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index baeb7a8bed24874753ef2e9c8aba7d44c7157c7b..2540df46b3ae4e1745784ce52f1984450a72a6c7 100644 (file)
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -32,13 +32,13 @@
 #define __CPU_THREAD_CONTEXT_HH__
 
 #include "arch/regfile.hh"
-#include "arch/syscallreturn.hh"
 #include "arch/types.hh"
 #include "config/full_system.hh"
 #include "mem/request.hh"
 #include "sim/faults.hh"
 #include "sim/host.hh"
 #include "sim/serialize.hh"
+#include "sim/syscallreturn.hh"
 #include "sim/byteswap.hh"
 
 // @todo: Figure out a more architecture independent way to obtain the ITB and