projects / gcc.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 9d2d283)
Fix PR target/93932
authorMichael Meissner <meissner@gcc.gnu.org>
Thu, 27 Feb 2020 19:41:39 +0000 (14:41 -0500)
committerMichael Meissner <meissner@gcc.gnu.org>
Thu, 27 Feb 2020 19:41:39 +0000 (14:41 -0500)
[gcc]
2020-02-27  Michael Meissner  <meissner@linux.ibm.com>

PR target/93932
* config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
Split the insn into two parts.  This insn only does variable
extract from a register.
(vsx_extract_<mode>_var_load, VSX_D iterator): New insn, do
variable extract from memory.
(vsx_extract_v4sf_var): Split the insn into two parts.  This insn
only does variable extract from a register.
(vsx_extract_v4sf_var_load): New insn, do variable extract from
memory.
(vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Split the insn
into two parts.  This insn only does variable extract from a
register.
(vsx_extract_<mode>_var_load, VSX_EXTRACT_I iterator): New insn,
do variable extract from memory.

[gcc/testsuite]
2020-02-27  Michael Meissner  <meissner@linux.ibm.com>

PR target/93932
* gcc.target/powerpc/fold-vec-extract-longlong.p8.c: Adjust
instruction counts.

gcc/ChangeLog patch | blob | history
gcc/config/rs6000/vsx.md patch | blob | history
gcc/testsuite/ChangeLog patch | blob | history
gcc/testsuite/gcc.target/powerpc/fold-vec-extract-longlong.p8.c patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 38064ccbdb83278e3eb1e5b92e65cf197c2611fa..f5d4e6dd582697565e0622079fb18f68b1b873b6 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,21 @@
+2020-02-27  Michael Meissner  <meissner@linux.ibm.com>
+
+       PR target/93932
+       * config/rs6000/vsx.md (vsx_extract_<mode>_var, VSX_D iterator):
+       Split the insn into two parts.  This insn only does variable
+       extract from a register.
+       (vsx_extract_<mode>_var_load, VSX_D iterator): New insn, do
+       variable extract from memory.
+       (vsx_extract_v4sf_var): Split the insn into two parts.  This insn
+       only does variable extract from a register.
+       (vsx_extract_v4sf_var_load): New insn, do variable extract from
+       memory.
+       (vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): Split the insn
+       into two parts.  This insn only does variable extract from a
+       register.
+       (vsx_extract_<mode>_var_load, VSX_EXTRACT_I iterator): New insn,
+       do variable extract from memory.
+
 2020-02-27  Martin Jambor  <mjambor@suse.cz>
            Feng Xue  <fxue@os.amperecomputing.com>
 
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 189c7d842ace19a3544b72fffa3e5d90cc85298f..b5d80f677dc79c40b1fe927ca6c11bb481482019 100644 (file)
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3245,14 +3245,14 @@
   "vslo %0,%1,%2"
   [(set_attr "type" "vecperm")])
 
-;; Variable V2DI/V2DF extract
+;; Variable V2DI/V2DF extract from a register
 (define_insn_and_split "vsx_extract_<mode>_var"
-  [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=v,wa,r")
-       (unspec:<VS_scalar> [(match_operand:VSX_D 1 "input_operand" "v,Q,Q")
-                            (match_operand:DI 2 "gpc_reg_operand" "r,r,r")]
+  [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=v")
+       (unspec:<VS_scalar> [(match_operand:VSX_D 1 "gpc_reg_operand" "v")
+                            (match_operand:DI 2 "gpc_reg_operand" "r")]
                            UNSPEC_VSX_EXTRACT))
-   (clobber (match_scratch:DI 3 "=r,&b,&b"))
-   (clobber (match_scratch:V2DI 4 "=&v,X,X"))]
+   (clobber (match_scratch:DI 3 "=r"))
+   (clobber (match_scratch:V2DI 4 "=&v"))]
   "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
   "#"
   "&& reload_completed"
@@ -3263,6 +3263,23 @@
   DONE;
 })
 
+;; Variable V2DI/V2DF extract from memory
+(define_insn_and_split "*vsx_extract_<mode>_var_load"
+  [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=wa,r")
+       (unspec:<VS_scalar> [(match_operand:VSX_D 1 "memory_operand" "Q,Q")
+                            (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+                           UNSPEC_VSX_EXTRACT))
+   (clobber (match_scratch:DI 3 "=&b,&b"))]
+  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 0) (match_dup 4))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+                                          operands[3], <VS_scalar>mode);
+}
+  [(set_attr "type" "fpload,load")])
+
 ;; Extract a SF element from V4SF
 (define_insn_and_split "vsx_extract_v4sf"
   [(set (match_operand:SF 0 "vsx_register_operand" "=wa")
@@ -3315,14 +3332,14 @@
    (set_attr "length" "8")
    (set_attr "isa" "*,p7v,p9v,*")])
 
-;; Variable V4SF extract
+;; Variable V4SF extract from a register
 (define_insn_and_split "vsx_extract_v4sf_var"
-  [(set (match_operand:SF 0 "gpc_reg_operand" "=wa,wa,?r")
-       (unspec:SF [(match_operand:V4SF 1 "input_operand" "v,Q,Q")
-                   (match_operand:DI 2 "gpc_reg_operand" "r,r,r")]
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
+       (unspec:SF [(match_operand:V4SF 1 "gpc_reg_operand" "v")
+                   (match_operand:DI 2 "gpc_reg_operand" "r")]
                   UNSPEC_VSX_EXTRACT))
-   (clobber (match_scratch:DI 3 "=r,&b,&b"))
-   (clobber (match_scratch:V2DI 4 "=&v,X,X"))]
+   (clobber (match_scratch:DI 3 "=r"))
+   (clobber (match_scratch:V2DI 4 "=&v"))]
   "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
   "#"
   "&& reload_completed"
@@ -3333,6 +3350,23 @@
   DONE;
 })
 
+;; Variable V4SF extract from memory
+(define_insn_and_split "*vsx_extract_v4sf_var_load"
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r")
+       (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q")
+                   (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+                  UNSPEC_VSX_EXTRACT))
+   (clobber (match_scratch:DI 3 "=&b,&b"))]
+  "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 0) (match_dup 4))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+                                          operands[3], SFmode);
+}
+  [(set_attr "type" "fpload,load")])
+
 ;; Expand the builtin form of xxpermdi to canonical rtl.
 (define_expand "vsx_xxpermdi_<mode>"
   [(match_operand:VSX_L 0 "vsx_register_operand")
@@ -3677,15 +3711,15 @@
   [(set_attr "type" "load")
    (set_attr "length" "8")])
 
-;; Variable V16QI/V8HI/V4SI extract
+;; Variable V16QI/V8HI/V4SI extract from a register
 (define_insn_and_split "vsx_extract_<mode>_var"
-  [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=r,r,r")
+  [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=r,r")
        (unspec:<VS_scalar>
-        [(match_operand:VSX_EXTRACT_I 1 "input_operand" "v,v,Q")
-         (match_operand:DI 2 "gpc_reg_operand" "r,r,r")]
+        [(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "v,v")
+         (match_operand:DI 2 "gpc_reg_operand" "r,r")]
         UNSPEC_VSX_EXTRACT))
-   (clobber (match_scratch:DI 3 "=r,r,&b"))
-   (clobber (match_scratch:V2DI 4 "=X,&v,X"))]
+   (clobber (match_scratch:DI 3 "=r,r"))
+   (clobber (match_scratch:V2DI 4 "=X,&v"))]
   "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
   "#"
   "&& reload_completed"
@@ -3695,7 +3729,25 @@
                                operands[3], operands[4]);
   DONE;
 }
-  [(set_attr "isa" "p9v,*,*")])
+  [(set_attr "isa" "p9v,*")])
+
+;; Variable V16QI/V8HI/V4SI extract from memory
+(define_insn_and_split "*vsx_extract_<mode>_var_load"
+  [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=r")
+       (unspec:<VS_scalar>
+        [(match_operand:VSX_EXTRACT_I 1 "memory_operand" "Q")
+         (match_operand:DI 2 "gpc_reg_operand" "r")]
+        UNSPEC_VSX_EXTRACT))
+   (clobber (match_scratch:DI 3 "=&b"))]
+  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 0) (match_dup 4))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+                                          operands[3], <VS_scalar>mode);
+}
+  [(set_attr "type" "load")])
 
 (define_insn_and_split "*vsx_extract_<mode>_<VS_scalar>mode_var"
   [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand" "=r,r,r")
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e606269cfa8a105f6ee5557a0f0df57a72bcbeda..35fd93a18fc7b5eb1ebd1f849ed4810ada5176e8 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2020-02-27  Michael Meissner  <meissner@linux.ibm.com>
+
+       PR target/93932
+       * gcc.target/powerpc/fold-vec-extract-longlong.p8.c: Adjust
+       instruction counts.
+
 2020-02-27  Martin Jambor  <mjambor@suse.cz>
            Feng Xue  <fxue@os.amperecomputing.com>
 
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-longlong.p8.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-longlong.p8.c
index 2784d80dabe0c83dc2828aa4a7123a0840cb2d53..56746989f7479c17de93e03ab1a1f547e22af7a1 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-longlong.p8.c
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-longlong.p8.c
@@ -7,24 +7,23 @@
 
 // Targeting P8LE and P8BE, six tests total.
 // P8 (LE) constants: mfvsrd
-// P8 (LE) variables: addi,xxpermdi,mr,stxvd2x|stxvd4x,rldicl,sldi,ldx,blr
-// P8 (BE) constants: mfvsrd
-// P8 (BE) Variables: addi,xxpermdi,rldicl,mr,stxvd2x|stxvd4x,sldi,ldx,blr
+// P8 (LE) variables: xori, rldic, mtvsrd, xxpermdi, vslo, mfvsrd
+// P8 (BE) constants: xxpermdi, mfvsrd
+// P8 (BE) Variables:       rldic, mtvsrd, xxpermdi, vslo, mfvsrd
 
-/* { dg-final { scan-assembler-times {\maddi\M} 6 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\maddi\M} 3 { target lp64 } } } */
+/* results. */
+/* { dg-final { scan-assembler-times {\mxori\M} 3 { target le } } } */
+/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvw4x\M} 4 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times {\madd\M} 3 { target ilp32 } } } */
 /* { dg-final { scan-assembler-times {\mlwz\M} 11 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\maddi\M} 6 { target ilp32 } } } */
+/* { dg-final { scan-assembler-times {\mmfvsrd\M} 6 { target lp64 } } } */
+/* { dg-final { scan-assembler-times {\mmtvsrd\M} 3 { target lp64 } } } */
 /* { dg-final { scan-assembler-times {\mxxpermdi\M} 3 { target le } } } */
+/* { dg-final { scan-assembler-times {\mxxpermdi\M} 6 { target { be && lp64 } } } } */
 /* { dg-final { scan-assembler-times {\mxxpermdi\M} 2 { target { be && ilp32 } } } } */
-/* { dg-final { scan-assembler-times {\mxxpermdi\M} 3 { target { be && lp64 } } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvw4x\M} 3 { target lp64 } } } */
-/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxvw4x\M} 4 { target ilp32 } } } */
-/* { dg-final { scan-assembler-times {\mrldicl\M|\mrldic\M|\mrlwinm\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mmfvsrd\M} 3 { target { lp64 } } } } */
-/* { dg-final { scan-assembler-times {\mmfvsrd\M} 0 { target { be && ilp32 } } } } */
-/* { dg-final { scan-assembler-times {\mmtvsrd\M} 0 { target { lp64 } } } } */
-/* { dg-final { scan-assembler-times {\mmtvsrd\M} 0 { target { be && ilp32 } } } } */
+/* { dg-final { scan-assembler-times {\mvslo\M} 3 { target lp64 } } } */
 
 #include <altivec.h>