Fix problems found by David Edelsohn I caused
authorDavid Edelsohn <edelsohn@mhpcc.edu>
Sun, 24 Jan 1999 17:20:07 +0000 (17:20 +0000)
committerMichael Meissner <meissner@gcc.gnu.org>
Sun, 24 Jan 1999 17:20:07 +0000 (17:20 +0000)
From-SVN: r24851

gcc/ChangeLog
gcc/config/rs6000/rs6000.md

index 155102046e8f860a924a168783e8f501161bc061..369fc8a266d603b5efaef3b859f67e54d1e96c9a 100644 (file)
@@ -1,7 +1,15 @@
+Sun Jan 24 20:13:45 1999  David Edelsohn  <edelsohn@mhpcc.edu>
+
+       * rs6000.md (left shift + set cr patterns): Add missing '#' to
+       split patterns.
+       (move register + set cr pattern): Ditto.
+       * rs6000.md (movdi, !TARGET_POWERPC64 splitters): Add back in
+       Jan. 15th patch, inadvertently deleted.
+
 Sun Jan 24 08:07:59 1999  Jeffrey A Law  (law@cygnus.com)
 
-        * stmt.c (stmt_loop_nest_empty): New function.
-        * tree.h (stmt_loop_nest_empty): Declare it.
+       * stmt.c (stmt_loop_nest_empty): New function.
+       * tree.h (stmt_loop_nest_empty): Declare it.
        * rtl.def (CALL_PLACEHOLDER): New rtx code.
 
 Sun Jan 24 21:24:43 1999  Michael Hayes  <m.hayes@elec.canterbury.ac.nz>
index fc8c8c9ccd4418bfa224788a5693a23239367cbc..03969a737145d0dd3729f9b88bff7d33556dbf2d 100644 (file)
         (const_int 0)))
    (clobber (match_scratch:SI 4 "=r,r"))]
   "includes_lshift_p (operands[2], operands[3])"
-  "{rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3"
+  "@
+  {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
+  #"
   [(set_attr "type" "delayed_compare")])
 
 (define_split
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
        (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
   "includes_lshift_p (operands[2], operands[3])"
-  "{rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3"
+  "@
+  {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
+  #"
   [(set_attr "type" "delayed_compare")])
 
 (define_split
                    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
   ""
-  "mr. %0,%1"
+  "@
+  mr. %0,%1
+  #"
   [(set_attr "type" "compare")])
 
 (define_split
 {
   operands[2] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN == 0);
   operands[3] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN != 0);
+#if HOST_BITS_PER_WIDE_INT == 32
   operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx;
+#else
+  operands[4] = (HOST_WIDE_INT) INTVAL (operands[1]) >> 32;
+  operands[1] = INTVAL (operands[1]) & 0xffffffff;
+#endif
 }")
 
 (define_split
   [(set (match_operand:DI 0 "gpc_reg_operand" "")
        (match_operand:DI 1 "const_double_operand" ""))]
-  "! TARGET_POWERPC64 && reload_completed"
+  "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed"
   [(set (match_dup 2) (match_dup 4))
    (set (match_dup 3) (match_dup 5))]
   "
                    (const_int 0)))
    (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
   "TARGET_POWERPC64"
-  "mr. %0,%1"
-  [(set_attr "type" "compare")])
-
-(define_insn ""
-  [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
-       (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r")
-                   (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
-  ""
-  "mr. %0,%1"
+  "@
+  mr. %0,%1
+  #"
   [(set_attr "type" "compare")])
 
 (define_split