Replace __riscv__ macros with __riscv.

The __riscv__ form is deprecated [1].

[1] - https://github.com/riscv/riscv-toolchain-conventions#cc-preprocessor-definitions

diff --git a/litex/soc/software/bios/main.c b/litex/soc/software/bios/main.c
index 64ca2e0bbf3b2ce1497b20be6209a457ccfb34f0..082aa62fb6ed09031b53287a69339ccc66af51b3 100644 (file)
--- a/litex/soc/software/bios/main.c
+++ b/litex/soc/software/bios/main.c
@@ -497,7 +497,7 @@ int main(int i, char **c)
        printf("\e[1mLM32\e[0m\n");
 #elif __or1k__
        printf("\e[1mOR1K\e[0m\n");
-#elif __riscv__
+#elif __riscv
        printf("\e[1mRISC-V\n");
 #else
        printf("\e[1mUnknown\e[0m\n");

diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index 5b1ebd70125ff496cf7a56c551dc1e16552f710e..7550282adce076d99ec1be4789eee444d6e4e6f4 100644 (file)
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -18,7 +18,7 @@ static void cdelay(int i)
                __asm__ volatile("nop");
 #elif defined (__or1k__)
                __asm__ volatile("l.nop");
-#elif defined (__riscv__)
+#elif defined (__riscv)
                __asm__ volatile("nop");
 #else
 #error Unsupported architecture

diff --git a/litex/soc/software/common.mak b/litex/soc/software/common.mak
index 11e8fc3855e2cf853bc622ea2946edfd4308fd53..82cb37c0c3c7f4a9bd498b908afccbd3351c456a 100644 (file)
--- a/litex/soc/software/common.mak
+++ b/litex/soc/software/common.mak
@@ -1,7 +1,7 @@
 TARGET_PREFIX=$(TRIPLE)-
 
 RM ?= rm -f
-PYTHON ?= python3
+PYTHON ?= python
 
 ifeq ($(CLANG),1)
 CC_normal      := clang -target $(TRIPLE) -integrated-as

diff --git a/litex/soc/software/libbase/system.c b/litex/soc/software/libbase/system.c
index 4306b93200d7b53fc61bbdfa04444f4f963acb89..f23dced81b0bd33127b0a812909e61a0156b9ffe 100644 (file)
--- a/litex/soc/software/libbase/system.c
+++ b/litex/soc/software/libbase/system.c
@@ -34,7 +34,7 @@ void flush_cpu_icache(void)
 
        for (i = 0; i < cache_size; i += cache_block_size)
                mtspr(SPR_ICBIR, i);
-#elif defined (__riscv__)
+#elif defined (__riscv)
        /* no instruction cache */
        asm volatile("nop");
 #else
@@ -65,7 +65,7 @@ void flush_cpu_dcache(void)
 
        for (i = 0; i < cache_size; i += cache_block_size)
                mtspr(SPR_DCBIR, i);
-#elif defined (__riscv__)
+#elif defined (__riscv)
        /* no data cache */
        asm volatile("nop");
 #else
@@ -86,7 +86,7 @@ void flush_l2_cache(void)
                __asm__ volatile("lw %0, (%1+0)\n":"=r"(dummy):"r"(addr));
 #elif defined (__or1k__)
                __asm__ volatile("l.lwz %0, 0(%1)\n":"=r"(dummy):"r"(addr));
-#elif defined (__riscv__)
+#elif defined (__riscv)
        /* FIXME */
        asm volatile("nop");
 #else