arch-arm, dev-arm: Remove Python 2 compatibility code
authorAndreas Sandberg <andreas.sandberg@arm.com>
Thu, 21 Jan 2021 16:44:16 +0000 (16:44 +0000)
committerAndreas Sandberg <andreas.sandberg@arm.com>
Fri, 22 Jan 2021 11:05:01 +0000 (11:05 +0000)
Remove uses of six and imports from __future__ and use native Python 3
functionality instead.

Change-Id: Ifeb925c0b802f8186dd148e382aefe1c32fc8176
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39580
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/arm/ArmSystem.py
src/dev/Device.py
src/dev/arm/RealView.py
src/dev/arm/SMMUv3.py
src/dev/arm/css/MHU.py

index 7ab4b6ec43a7d191d4bd616f4050bae3d64fca24..f7d9cd546d94d26ad26c4bb6bd1396ad4f2680d0 100644 (file)
@@ -108,7 +108,7 @@ class ArmSystem(System):
         # root instead of appended.
 
         def generateMemNode(mem_range):
-            node = FdtNode("memory@%x" % long(mem_range.start))
+            node = FdtNode("memory@%x" % int(mem_range.start))
             node.append(FdtPropertyStrings("device_type", ["memory"]))
             node.append(FdtPropertyWords("reg",
                 state.addrCells(mem_range.start) +
index af495042f36b4dddb5231af2e0d6011caecefd08..46e992c3cef4ad60b579941253b372a2cfe4d482 100644 (file)
@@ -51,7 +51,7 @@ class PioDevice(ClockedObject):
 
     def generateBasicPioDeviceNode(self, state, name, pio_addr,
                                    size, interrupts = None):
-        node = FdtNode("%s@%x" % (name, long(pio_addr)))
+        node = FdtNode("%s@%x" % (name, int(pio_addr)))
         node.append(FdtPropertyWords("reg",
             state.addrCells(pio_addr) +
             state.sizeCells(size) ))
index 8fa0edde11a5765c33a5d981a599785f11c19ada..81d1f0755db4044feb05dfc542e2dfd395625533 100644 (file)
@@ -211,7 +211,7 @@ class RealViewCtrl(BasicPioDevice):
     idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
 
     def generateDeviceTree(self, state):
-        node = FdtNode("sysreg@%x" % long(self.pio_addr))
+        node = FdtNode("sysreg@%x" % int(self.pio_addr))
         node.appendCompatible("arm,vexpress-sysreg")
         node.append(FdtPropertyWords("reg",
             state.addrCells(self.pio_addr) +
@@ -250,7 +250,7 @@ class RealViewOsc(ClockDomain):
 
     def generateDeviceTree(self, state):
         phandle = state.phandle(self)
-        node = FdtNode("osc@" + format(long(phandle), 'x'))
+        node = FdtNode("osc@" + format(int(phandle), 'x'))
         node.appendCompatible("arm,vexpress-osc")
         node.append(FdtPropertyWords("arm,vexpress-sysreg,func",
                                      [0x1, int(self.device)]))
@@ -595,7 +595,7 @@ class MmioSRAM(ParentMem):
         super(MmioSRAM, self).__init__(**kwargs)
 
     def generateDeviceTree(self, state):
-        node = FdtNode("sram@%x" % long(self.range.start))
+        node = FdtNode("sram@%x" % int(self.range.start))
         node.appendCompatible(["mmio-sram"])
         node.append(FdtPropertyWords("reg",
             state.addrCells(self.range.start) +
index f444d644cbe8530622a9fda7b548fa6d8ab9c285..85c10ad39b12d68a07fb1d4aa25ca8a9669aae0f 100644 (file)
@@ -187,7 +187,7 @@ class SMMUv3(ClockedObject):
     def generateDeviceTree(self, state):
         reg_addr = self.reg_map.start
         reg_size = self.reg_map.size()
-        node = FdtNode("smmuv3@%x" % long(reg_addr))
+        node = FdtNode("smmuv3@%x" % int(reg_addr))
         node.appendCompatible("arm,smmu-v3")
         node.append(FdtPropertyWords("reg",
             state.addrCells(reg_addr) +
index 878ca221c38d3114736120244f6fffe8d59a3810..f5bb7e5bb924a71c702306e1c20c10ea1802a054 100644 (file)
@@ -89,7 +89,7 @@ class MHU(BasicPioDevice):
     scp = Param.Scp(Parent.any, "System Control Processor")
 
     def generateDeviceTree(self, state):
-        node = FdtNode("mailbox@%x" % long(self.pio_addr))
+        node = FdtNode("mailbox@%x" % int(self.pio_addr))
         node.appendCompatible(["arm,mhu", "arm,primecell"])
         node.append(FdtPropertyWords("reg",
             state.addrCells(self.pio_addr) +