sdram/phy/simphy: OK with DDR3

diff --git a/misoclib/mem/sdram/phy/simphy.py b/misoclib/mem/sdram/phy/simphy.py
index 1dc818e26316c058a7eb205dada07f9e51fbc5a2..6ec3962615af629d625231aef0ebcbcee50cf790 100644 (file)
--- a/misoclib/mem/sdram/phy/simphy.py
+++ b/misoclib/mem/sdram/phy/simphy.py
@@ -2,10 +2,8 @@
 # License: BSD
 
 # SDRAM simulation PHY at DFI level
-# Status:
-# - tested against software memtest with SDR/DDR/LPDDR/DDR2 with Verilator.
+# tested with SDR/DDR/DDR2/LPDDR/DDR3
 # TODO:
-# - test with DDR3
 # - add $display support to Migen and manage timing violations?
 
 from migen.fhdl.std import *