Add SIGRIE instruction for MIPS R6

opcodes/

	* mips-opc.c (mips_builtin_opcodes): Add "sigrie".

gas/testsuite/

	* gas/mips/r6.s: Add tests for "sigrie".
	* gas/mips/r6.d: Check for "sigrie".
	* gas/mips/r6-n32.d: Likewise.
	* gas/mips/r6-n64.d: Likewise.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 68d176134c68ef92697b38f71e628b87d8370a40..e2e3fd49ded9d334d7db13d6eb4ba7024f1bced3 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
+
+       * gas/mips/r6.s: Add tests for "sigrie".
+       * gas/mips/r6.d: Check for "sigrie".
+       * gas/mips/r6-n32.d: Likewise.
+       * gas/mips/r6-n64.d: Likewise.
+
 2015-07-30  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR binutils/13571

diff --git a/gas/testsuite/gas/mips/r6-n32.d b/gas/testsuite/gas/mips/r6-n32.d
index acca6c4929b95cdd9a814c3e2d2a9d1b17af87df..fb55086e91cf3990507c45e2efaecad2d65a92b7 100644 (file)
--- a/gas/testsuite/gas/mips/r6-n32.d
+++ b/gas/testsuite/gas/mips/r6-n32.d
@@ -497,4 +497,6 @@ Disassembly of section .text:
 0+0598 <[^>]*> 41600024        dvp
 0+059c <[^>]*> 41620004        evp     v0
 0+05a0 <[^>]*> 41620024        dvp     v0
+0+05a4 <[^>]*> 41700000        sigrie  0x0
+0+05a8 <[^>]*> 4170ffff        sigrie  0xffff
        \.\.\.

diff --git a/gas/testsuite/gas/mips/r6-n64.d b/gas/testsuite/gas/mips/r6-n64.d
index 10deeae5d910b183d546490e2001489e143842b8..fd4da21f31cc996f1768484fe27d89dbba7c7712 100644 (file)
--- a/gas/testsuite/gas/mips/r6-n64.d
+++ b/gas/testsuite/gas/mips/r6-n64.d
@@ -753,4 +753,6 @@ Disassembly of section .text:
 0+0598 <[^>]*> 41600024        dvp
 0+059c <[^>]*> 41620004        evp     v0
 0+05a0 <[^>]*> 41620024        dvp     v0
+0+05a4 <[^>]*> 41700000        sigrie  0x0
+0+05a8 <[^>]*> 4170ffff        sigrie  0xffff
        \.\.\.

diff --git a/gas/testsuite/gas/mips/r6.d b/gas/testsuite/gas/mips/r6.d
index cca10a7988bb0a1eba9e7e41a30efad579dd6416..8588e92efcffd4e1aa22293f118dd4c318e119e2 100644 (file)
--- a/gas/testsuite/gas/mips/r6.d
+++ b/gas/testsuite/gas/mips/r6.d
@@ -496,4 +496,6 @@ Disassembly of section .text:
 0+0598 <[^>]*> 41600024        dvp
 0+059c <[^>]*> 41620004        evp     v0
 0+05a0 <[^>]*> 41620024        dvp     v0
+0+05a4 <[^>]*> 41700000        sigrie  0x0
+0+05a8 <[^>]*> 4170ffff        sigrie  0xffff
        \.\.\.

diff --git a/gas/testsuite/gas/mips/r6.s b/gas/testsuite/gas/mips/r6.s
index 0635066d10579a13ea5031730a5299d3dbdc71f3..9fc5fcd82827756624a30f7dad9ced6977e588af 100644 (file)
--- a/gas/testsuite/gas/mips/r6.s
+++ b/gas/testsuite/gas/mips/r6.s
@@ -266,6 +266,9 @@ new:        maddf.s $f0,$f1,$f2
        evp     $2
        dvp     $2
 
+       sigrie  0
+       sigrie  0xffff
+
 # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
        .align  2
        .space  8

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 995deae73d39ab840e4409751daa558268863657..4638e150c1e319226df865db95b64ff8f50057a9 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2015-08-10  Robert Suchanek  <robert.suchanek@imgtec.com>
+
+       * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
+
 2015-08-07  Amit Pawar <Amit.Pawar@amd.com>
 
        * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index a0b0e26988ff1dd3a5fa4284863b03e1b0599224..7349ade30f9c4979996d16890a431d4a8d0f2f2e 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -1858,6 +1858,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"shfl.repa.qh",       "X,Y,Z",        0x7b20001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
 {"shfl.repb.qh",       "X,Y,Z",        0x7ba0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
 {"shfl.upsl.ob",       "X,Y,Z",        0x78c0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
+{"sigrie",             "u",            0x41700000, 0xffff0000, TRAP,                   0,              I37,            0,      0 },
 {"sle",                        "d,v,t",        0,    (int) M_SLE,      INSN_MACRO,             0,              I1,             0,      0 },
 {"sle",                        "d,v,I",        0,    (int) M_SLE_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"sle",                        "S,T",          0x46a0003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },