struct input_osc
{
- signed64 on_time;
- signed64 off_time;
- signed64 repeat;
+ int64_t on_time;
+ int64_t off_time;
+ int64_t repeat;
struct hw_event *event;
const char *name;
- uint8 mask;
- uint8 value;
- uint16 addr;
+ uint8_t mask;
+ uint8_t value;
+ uint16_t addr;
};
#define NR_PORT_A_OSC (4)
static hw_port_event_method m68hc11cpu_port_event;
static void make_oscillator (struct m68hc11cpu *controller,
- const char *id, uint16 addr, uint8 mask);
+ const char *id, uint16_t addr, uint8_t mask);
static struct input_osc *find_oscillator (struct m68hc11cpu *controller,
const char *id);
static void reset_oscillators (struct hw *me);
static void
make_oscillator (struct m68hc11cpu *controller, const char *name,
- uint16 addr, uint8 mask)
+ uint16_t addr, uint8_t mask)
{
struct input_osc *osc;
struct input_osc *osc = (struct input_osc*) data;
SIM_DESC sd;
sim_cpu *cpu;
- signed64 dt;
- uint8 val;
+ int64_t dt;
+ uint8_t val;
sd = hw_system (me);
cpu = STATE_CPU (sd, 0);
m68hc11_info (struct hw *me)
{
SIM_DESC sd;
- uint16 base = 0;
+ uint16_t base = 0;
sim_cpu *cpu;
struct m68hc11sio *controller;
- uint8 val;
+ uint8_t val;
sd = hw_system (me);
cpu = STATE_CPU (sd, 0);
val = cpu->ios[M6811_INIT];
print_io_byte (sd, "INIT ", 0, val, base + M6811_INIT);
sim_io_printf (sd, "Ram = 0x%04x IO = 0x%04x\n",
- (((uint16) (val & 0xF0)) << 8),
- (((uint16) (val & 0x0F)) << 12));
+ (((uint16_t) (val & 0xF0)) << 8),
+ (((uint16_t) (val & 0x0F)) << 12));
cpu_info (sd, cpu);
stops. */
int
m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
- double ton, double toff, signed64 repeat)
+ double ton, double toff, int64_t repeat)
{
sim_cpu *cpu;
struct input_osc *osc;
/* Compute the ON time in cpu cycles. */
f = (double) (cpu->cpu_frequency) * ton;
- osc->on_time = (signed64) (f / 4.0);
+ osc->on_time = (int64_t) (f / 4.0);
if (osc->on_time < 1)
osc->on_time = 1;
/* Compute the OFF time in cpu cycles. */
f = (double) (cpu->cpu_frequency) * toff;
- osc->off_time = (signed64) (f / 4.0);
+ osc->off_time = (int64_t) (f / 4.0);
if (osc->off_time < 1)
osc->off_time = 1;
case OPTION_OSC_INFO:
for (i = 0; i < controller->last_oscillator; i++)
{
- signed64 t;
+ int64_t t;
struct input_osc *osc;
osc = &controller->oscillators[i];
void
m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
- unsigned addr, uint8 val)
+ unsigned addr, uint8_t val)
{
- uint8 mask;
- uint8 delta;
+ uint8_t mask;
+ uint8_t delta;
int check_interrupts = 0;
int i;
/* Scan IC3, IC2 and IC1. Bit number is 3 - i. */
for (i = 0; i < 3; i++)
{
- uint8 mask = (1 << i);
+ uint8_t mask = (1 << i);
if (delta & mask)
{
- uint8 edge;
+ uint8_t edge;
int captured;
edge = cpu->ios[M6811_TCTL2];
static void
m68hc11cpu_io_write (struct hw *me, sim_cpu *cpu,
- unsigned_word addr, uint8 val)
+ unsigned_word addr, uint8_t val)
{
switch (addr)
{
/* Change the RAM and I/O mapping. */
case M6811_INIT:
{
- uint8 old_bank = cpu->ios[M6811_INIT];
+ uint8_t old_bank = cpu->ios[M6811_INIT];
cpu->ios[M6811_INIT] = val;
byte = 0;
while (nr_bytes)
{
- uint8 val;
+ uint8_t val;
if (base >= controller->attach_size)
break;
- val = *((uint8*) source);
+ val = *((uint8_t*) source);
m68hc11cpu_io_write (me, cpu, base, val);
source = (char*) source + 1;
base++;
located at the end of the EEPROM (eeprom size + 1). It is not mapped
in memory but it's saved in the EEPROM file. */
unsigned long eeprom_wcycle;
- uint16 eeprom_waddr;
- uint8 eeprom_wbyte;
- uint8 eeprom_wmode;
+ uint16_t eeprom_waddr;
+ uint8_t eeprom_wbyte;
+ uint8_t eeprom_wmode;
- uint8* eeprom;
+ uint8_t* eeprom;
/* Minimum time in CPU cycles for programming the EEPROM. */
unsigned long eeprom_min_cycles;
m68hc11eepr_info (struct hw *me)
{
SIM_DESC sd;
- uint16 base = 0;
+ uint16_t base = 0;
sim_cpu *cpu;
struct m68hc11eepr *controller;
- uint8 val;
+ uint8_t val;
sd = hw_system (me);
cpu = STATE_CPU (sd, 0);
{
case M6811_PPROG:
case M6811_CONFIG:
- *((uint8*) dest) = cpu->ios[base];
+ *((uint8_t*) dest) = cpu->ios[base];
break;
default:
hw_abort (me, "reading wrong register 0x%04x", base);
}
- dest = (uint8*) (dest) + 1;
+ dest = (uint8_t*) (dest) + 1;
base++;
nr_bytes--;
cnt++;
SIM_DESC sd;
struct m68hc11eepr *controller;
sim_cpu *cpu;
- uint8 val;
+ uint8_t val;
HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
if (nr_bytes != 1)
hw_abort (me, "Cannot write more than 1 byte to EEPROM device at a time");
- val = *((const uint8*) source);
+ val = *((const uint8_t*) source);
/* Write to the EEPROM control register. */
if (space == io_map && base == M6811_PPROG)
{
- uint8 wrong_bits;
- uint16 addr;
+ uint8_t wrong_bits;
+ uint16_t addr;
addr = base + cpu_get_io_base (cpu);
SIM_DESC sd;
struct m68hc11sio *controller;
sim_cpu *cpu;
- unsigned8 val;
+ uint8_t val;
controller = hw_data (me);
sd = hw_system (me);
m68hc11sio_info (struct hw *me)
{
SIM_DESC sd;
- uint16 base = 0;
+ uint16_t base = 0;
sim_cpu *cpu;
struct m68hc11sio *controller;
- uint8 val;
+ uint8_t val;
long clock_cycle;
sd = hw_system (me);
if (controller->tx_poll_event)
{
- signed64 t;
+ int64_t t;
int n;
t = hw_event_remain_time (me, controller->tx_poll_event);
}
if (controller->rx_poll_event)
{
- signed64 t;
+ int64_t t;
t = hw_event_remain_time (me, controller->rx_poll_event);
sim_io_printf (sd, " Receive finished in %s\n",
SIM_DESC sd;
struct m68hc11sio *controller;
sim_cpu *cpu;
- unsigned8 val;
+ uint8_t val;
HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
default:
return 0;
}
- *((unsigned8*) dest) = val;
+ *((uint8_t*) dest) = val;
return 1;
}
SIM_DESC sd;
struct m68hc11sio *controller;
sim_cpu *cpu;
- unsigned8 val;
+ uint8_t val;
HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
cpu = STATE_CPU (sd, 0);
controller = hw_data (me);
- val = *((const unsigned8*) source);
+ val = *((const uint8_t*) source);
switch (base)
{
case M6811_BAUD:
SIM_DESC sd;
struct m68hc11spi *controller;
sim_cpu *cpu;
- unsigned8 val;
+ uint8_t val;
controller = hw_data (me);
sd = hw_system (me);
static void
set_bit_port (struct hw *me, sim_cpu *cpu, int port, int mask, int value)
{
- uint8 val;
+ uint8_t val;
if (value)
val = cpu->ios[port] | mask;
m68hc11spi_info (struct hw *me)
{
SIM_DESC sd;
- uint16 base = 0;
+ uint16_t base = 0;
sim_cpu *cpu;
struct m68hc11spi *controller;
- uint8 val;
+ uint8_t val;
sd = hw_system (me);
cpu = STATE_CPU (sd, 0);
if (controller->spi_event)
{
- signed64 t;
+ int64_t t;
sim_io_printf (sd, " SPI has %d bits to send\n",
controller->tx_bit + 1);
SIM_DESC sd;
struct m68hc11spi *controller;
sim_cpu *cpu;
- unsigned8 val;
+ uint8_t val;
HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
default:
return 0;
}
- *((unsigned8*) dest) = val;
+ *((uint8_t*) dest) = val;
return 1;
}
SIM_DESC sd;
struct m68hc11spi *controller;
sim_cpu *cpu;
- unsigned8 val;
+ uint8_t val;
HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
cpu = STATE_CPU (sd, 0);
controller = hw_data (me);
- val = *((const unsigned8*) source);
+ val = *((const uint8_t*) source);
switch (base)
{
case M6811_SPCR:
unsigned long cop_delay;
unsigned long rti_delay;
unsigned long ovf_delay;
- signed64 clock_prescaler;
- signed64 tcnt_adjust;
- signed64 cop_prev_interrupt;
- signed64 rti_prev_interrupt;
+ int64_t clock_prescaler;
+ int64_t tcnt_adjust;
+ int64_t cop_prev_interrupt;
+ int64_t rti_prev_interrupt;
/* Periodic timers. */
struct hw_event *rti_timer_event;
SIM_DESC sd;
struct m68hc11tim *controller;
sim_cpu *cpu;
- unsigned8 val;
- unsigned16 tcnt;
+ uint8_t val;
+ uint16_t tcnt;
controller = hw_data (me);
sd = hw_system (me);
}
case CAPTURE:
- tcnt = (uint16) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
+ tcnt = (uint16_t) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
/ controller->clock_prescaler);
switch (level)
{
unsigned flags;
unsigned long tcnt_internal;
unsigned long tcnt, tcnt_prev;
- signed64 tcnt_insn_end;
- signed64 tcnt_insn_start;
+ int64_t tcnt_insn_end;
+ int64_t tcnt_insn_start;
int i;
sim_events *events;
};
static double
-to_realtime (sim_cpu *cpu, signed64 t)
+to_realtime (sim_cpu *cpu, int64_t t)
{
return (double) (t) / (double) (cpu->cpu_frequency / 4);
}
const char*
-cycle_to_string (sim_cpu *cpu, signed64 t, int flags)
+cycle_to_string (sim_cpu *cpu, int64_t t, int flags)
{
char time_buf[32];
char cycle_buf[32];
}
else
{
- signed64 t;
+ int64_t t;
sim_cpu *cpu;
cpu = STATE_CPU (sd, 0);
m68hc11tim_info (struct hw *me)
{
SIM_DESC sd;
- uint16 base = 0;
+ uint16_t base = 0;
sim_cpu *cpu;
struct m68hc11tim *controller;
- uint8 val;
- uint16 val16;
+ uint8_t val;
+ uint16_t val16;
sd = hw_system (me);
cpu = STATE_CPU (sd, 0);
SIM_DESC sd;
struct m68hc11tim *controller;
sim_cpu *cpu;
- unsigned8 val;
+ uint8_t val;
unsigned cnt = 0;
HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
Reading in a 16-bit register will be split in two accesses
but this will be atomic within the simulator. */
case M6811_TCTN_H:
- val = (uint8) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
+ val = (uint8_t) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
/ (controller->clock_prescaler * 256));
break;
case M6811_TCTN_L:
- val = (uint8) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
+ val = (uint8_t) ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
/ controller->clock_prescaler);
break;
val = cpu->ios[base];
break;
}
- *((unsigned8*) dest) = val;
+ *((uint8_t*) dest) = val;
dest = (char*) dest + 1;
base++;
nr_bytes--;
SIM_DESC sd;
struct m68hc11tim *controller;
sim_cpu *cpu;
- unsigned8 val, n;
- signed64 adj;
+ uint8_t val, n;
+ int64_t adj;
int reset_compare = 0;
int reset_overflow = 0;
int cnt = 0;
while (nr_bytes)
{
- val = *((const unsigned8*) source);
+ val = *((const uint8_t*) source);
switch (base)
{
/* Set the timer counter low part, trying to preserve the low part.
in 64-bit to avoid overflow problems. */
case M6811_TCTN_L:
adj = ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
- / (controller->clock_prescaler * (signed64) 256)) & 0x0FF;
+ / (controller->clock_prescaler * (int64_t) 256)) & 0x0FF;
adj = cpu->cpu_absolute_cycle
- - (adj * controller->clock_prescaler * (signed64) 256)
- - ((signed64) adj * controller->clock_prescaler);
+ - (adj * controller->clock_prescaler * (int64_t) 256)
+ - ((int64_t) adj * controller->clock_prescaler);
controller->tcnt_adjust = adj;
reset_compare = 1;
reset_overflow = 1;
adj = ((cpu->cpu_absolute_cycle - controller->tcnt_adjust)
/ controller->clock_prescaler) & 0x0ff;
adj = cpu->cpu_absolute_cycle
- - ((signed64) val * controller->clock_prescaler * (signed64) 256)
+ - ((int64_t) val * controller->clock_prescaler * (int64_t) 256)
- (adj * controller->clock_prescaler);
controller->tcnt_adjust = adj;
reset_compare = 1;
{
address_word base_address; /* Base address of ram. */
unsigned size; /* Size of ram. */
- unsigned8 *data; /* Pointer to ram memory. */
+ uint8_t *data; /* Pointer to ram memory. */
const char *file_name; /* Path of ram file. */
int fd; /* File description of opened ram file. */
enum nvram_mode mode; /* How load/save ram file. */
cpu->cpu_running = 0;
while (size)
{
- uint8 val = memory_read8 (cpu, addr);
+ uint8_t val = memory_read8 (cpu, addr);
if (write (0, &val, 1) != 1)
printf ("write failed: %s\n", strerror (errno));
{ "rts11", "addr = cpu_m68hc11_pop_uint16 (cpu); cpu_set_pc (cpu, addr); cpu_return (cpu)" },
{ "rts12", "addr = cpu_m68hc12_pop_uint16 (cpu); cpu_set_pc (cpu, addr); cpu_return (cpu)" },
- { "mul16", "dst16 = ((uint16) src8 & 0x0FF) * ((uint16) dst8 & 0x0FF)",
+ { "mul16", "dst16 = ((uint16_t) src8 & 0x0FF) * ((uint16_t) dst8 & 0x0FF)",
"cpu_set_ccr_C (cpu, src8 & 0x80)" },
{ "neg8", "dst8 = - src8",
"cpu_set_ccr_C (cpu, src8 == 0); cpu_ccr_update_tst8 (cpu, dst8)" },
{ "txys16", "dst16 = src16 - 1;"},
/* Add b to X or Y with an unsigned extension 8->16. Flags not changed. */
- { "abxy16","dst16 = dst16 + (uint16) src8"},
+ { "abxy16","dst16 = dst16 + (uint16_t) src8"},
/* After 'daa', the Z flag is undefined. Mark it as changed. */
{ "daa8", "cpu_special (cpu, M6811_DAA)" },
cpu_set_ccr_C (cpu, dst16 == 0);\n\
}\nelse\n{\n\
unsigned long l = (unsigned long) (dst16) << 16;\n\
-cpu_set_d (cpu, (uint16) (l % (unsigned long) (src16)));\n\
-dst16 = (uint16) (l / (unsigned long) (src16));\n\
+cpu_set_d (cpu, (uint16_t) (l % (unsigned long) (src16)));\n\
+dst16 = (uint16_t) (l / (unsigned long) (src16));\n\
cpu_set_ccr_V (cpu, 0);\n\
cpu_set_ccr_C (cpu, 0);\n\
cpu_set_ccr_Z (cpu, dst16 == 0);\n\
{ "call_ind", "cpu_special (cpu, M6812_CALL_INDIRECT)" },
{ "dbcc8", "cpu_dbcc (cpu)" },
{ "ediv", "cpu_special (cpu, M6812_EDIV)" },
- { "emul", "{ uint32 src1 = (uint32) cpu_get_d (cpu);\
- uint32 src2 = (uint32) cpu_get_y (cpu);\
+ { "emul", "{ uint32_t src1 = (uint32_t) cpu_get_d (cpu);\
+ uint32_t src2 = (uint32_t) cpu_get_y (cpu);\
src1 *= src2;\
cpu_set_d (cpu, src1);\
cpu_set_y (cpu, src1 >> 16);\
- End of input operands.
Example:
- (x),a->a addr = x + (uint16) (fetch8 (cpu));
+ (x),a->a addr = x + (uint16_t) (fetch8 (cpu));
src8 = a
- *,#,r addr = (uint16) (fetch8 (cpu)) <- Temporary 'addr'
+ *,#,r addr = (uint16_t) (fetch8 (cpu)) <- Temporary 'addr'
src8 = read_mem8 (cpu, addr)
dst8 = fetch8 (cpu)
addr = fetch_relbranch (cpu) <- Final 'addr'
addr_set = 1;
current_insn_size += 1;
- print (fp, col, "addr = (uint16) cpu_fetch8 (cpu);");
+ print (fp, col, "addr = (uint16_t) cpu_fetch8 (cpu);");
print (fp, col, "%s%s = memory_read%s (cpu, addr);",
vars[cur_var], operand_size, operand_size);
break;
if (strncmp (operands, "(x)", 3) == 0)
{
current_insn_size += 1;
- print (fp, col, "addr = cpu_get_x (cpu) + (uint16) cpu_fetch8 (cpu);");
+ print (fp, col, "addr = cpu_get_x (cpu) + (uint16_t) cpu_fetch8 (cpu);");
operands += 3;
}
else if (strncmp (operands, "(y)", 3) == 0)
{
current_insn_size += 1;
- print (fp, col, "addr = cpu_get_y (cpu) + (uint16) cpu_fetch8 (cpu);");
+ print (fp, col, "addr = cpu_get_y (cpu) + (uint16_t) cpu_fetch8 (cpu);");
operands += 3;
}
else if (strncmp (operands, "()", 2) == 0)
{
addr_set = 1;
current_insn_size += 1;
- print (fp, col, "addr = cpu_get_x (cpu) + (uint16) cpu_fetch8 (cpu);");
+ print (fp, col, "addr = cpu_get_x (cpu) + (uint16_t) cpu_fetch8 (cpu);");
print (fp, col, "%s%s = memory_read%s (cpu, addr);",
vars[cur_var], operand_size, operand_size);
operands += 2;
{
addr_set = 1;
current_insn_size += 1;
- print (fp, col, "addr = cpu_get_y (cpu) + (uint16) cpu_fetch8 (cpu);");
+ print (fp, col, "addr = cpu_get_y (cpu) + (uint16_t) cpu_fetch8 (cpu);");
print (fp, col, "%s%s = memory_read%s (cpu, addr);",
vars[cur_var], operand_size, operand_size);
operands += 2;
if (addr_set == 0)
{
current_insn_size += 1;
- print (fp, col, "addr = (uint16) cpu_fetch8 (cpu);");
+ print (fp, col, "addr = (uint16_t) cpu_fetch8 (cpu);");
}
result_size = operand_size;
print (fp, col, "memory_write%s (cpu, addr, dst%s);",
/* Interpretor local variables. */
print (fp, indent_level, "unsigned char op;");
- print (fp, indent_level, "uint16 addr, src16, dst16;");
+ print (fp, indent_level, "uint16_t addr, src16, dst16;");
if (locals & USE_SRC8)
- print (fp, indent_level, "uint8 src8;\n");
+ print (fp, indent_level, "uint8_t src8;\n");
if (locals & USE_DST8)
- print (fp, indent_level, "uint8 dst8;\n");
+ print (fp, indent_level, "uint8_t dst8;\n");
}
void
static int
m68hc11_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
- uint16 val;
+ uint16_t val;
int size = 2;
switch (rn)
static int
m68hc11_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
- uint16 val;
+ uint16_t val;
val = *memory++;
if (length == 2)
#endif
};
-#define CYCLES_MAX ((((signed64) 1) << 62) - 1)
+#define CYCLES_MAX ((((int64_t) 1) << 62) - 1)
enum
{
if (interrupts->cpu->cpu_mode == M6811_SMOD)
{
bfd_vma addr = interrupts->vectors_addr;
- uint16 vector = 0x0100 - 3 * (M6811_INT_NUMBER - 1);
+ uint16_t vector = 0x0100 - 3 * (M6811_INT_NUMBER - 1);
for (i = 0; i < M6811_INT_NUMBER; i++)
{
memory_write16 (interrupts->cpu, addr, vector);
interrupts_update_pending (struct interrupts *interrupts)
{
int i;
- uint8 *ioregs;
+ uint8_t *ioregs;
unsigned long clear_mask;
unsigned long set_mask;
for (i = 0; i < ARRAY_SIZE (idefs); i++)
{
struct interrupt_def *idef = &idefs[i];
- uint8 data;
+ uint8_t data;
/* Look if the interrupt is enabled. */
if (idef->enable_paddr)
Also implements the breakpoint-on-interrupt. */
if (set_mask)
{
- signed64 cycle = cpu_current_cycle (interrupts->cpu);
+ int64_t cycle = cpu_current_cycle (interrupts->cpu);
int must_stop = 0;
for (i = 0; i < M6811_INT_NUMBER; i++)
interrupts_process (struct interrupts *interrupts)
{
int id;
- uint8 ccr;
+ uint8_t ccr;
/* See if interrupts are enabled/disabled and keep track of the
number of cycles the interrupts are masked. Such information is
else if (interrupts->start_mask_cycle >= 0
&& (ccr & M6811_I_BIT) == 0)
{
- signed64 t = cpu_current_cycle (interrupts->cpu);
+ int64_t t = cpu_current_cycle (interrupts->cpu);
t -= interrupts->start_mask_cycle;
if (t < interrupts->min_mask_cycles)
else if (interrupts->xirq_start_mask_cycle >= 0
&& (ccr & M6811_X_BIT) == 0)
{
- signed64 t = cpu_current_cycle (interrupts->cpu);
+ int64_t t = cpu_current_cycle (interrupts->cpu);
t -= interrupts->xirq_start_mask_cycle;
if (t < interrupts->xirq_min_mask_cycles)
id = interrupts_get_current (interrupts);
if (id >= 0)
{
- uint16 addr;
+ uint16_t addr;
struct interrupt_history *h;
/* Implement the breakpoint-on-interrupt. */
void
interrupts_info (SIM_DESC sd, struct interrupts *interrupts)
{
- signed64 t, prev_interrupt;
+ int64_t t, prev_interrupt;
int i;
sim_io_printf (sd, "Interrupts Info:\n");
{
int which;
struct interrupt_history *h;
- signed64 dt;
+ int64_t dt;
which = interrupts->history_index - i - 1;
if (which < 0)
enum M6811_INT type;
/* CPU cycle when interrupt handler is called. */
- signed64 taken_cycle;
+ int64_t taken_cycle;
/* CPU cycle when the interrupt is first raised by the device. */
- signed64 raised_cycle;
+ int64_t raised_cycle;
};
#define SIM_STOP_WHEN_RAISED 1
struct interrupt
{
/* CPU cycle when the interrupt is raised by the device. */
- signed64 cpu_cycle;
+ int64_t cpu_cycle;
/* Number of times the interrupt was raised. */
unsigned long raised_count;
/* Address of vector table. This is set depending on the
68hc11 init mode. */
- uint16 vectors_addr;
+ uint16_t vectors_addr;
/* Priority order of interrupts. This is controlled by setting the HPRIO
IO register. */
/* Simulator statistics to report useful debug information to users. */
/* - Max/Min number of CPU cycles executed with interrupts masked. */
- signed64 start_mask_cycle;
- signed64 min_mask_cycles;
- signed64 max_mask_cycles;
- signed64 last_mask_cycles;
+ int64_t start_mask_cycle;
+ int64_t min_mask_cycles;
+ int64_t max_mask_cycles;
+ int64_t last_mask_cycles;
/* - Same for XIRQ. */
- signed64 xirq_start_mask_cycle;
- signed64 xirq_min_mask_cycles;
- signed64 xirq_max_mask_cycles;
- signed64 xirq_last_mask_cycles;
+ int64_t xirq_start_mask_cycle;
+ int64_t xirq_min_mask_cycles;
+ int64_t xirq_max_mask_cycles;
+ int64_t xirq_last_mask_cycles;
/* - Total number of interrupts raised. */
unsigned long nb_interrupts_raised;
void
-cpu_call (sim_cpu *cpu, uint16 addr)
+cpu_call (sim_cpu *cpu, uint16_t addr)
{
cpu_set_pc (cpu, addr);
/* Set the stack pointer and re-compute the current frame. */
void
-cpu_set_sp (sim_cpu *cpu, uint16 val)
+cpu_set_sp (sim_cpu *cpu, uint16_t val)
{
cpu->cpu_regs.sp = val;
}
-static uint16
-cpu_get_reg (sim_cpu *cpu, uint8 reg)
+static uint16_t
+cpu_get_reg (sim_cpu *cpu, uint8_t reg)
{
switch (reg)
{
}
}
-static uint16
-cpu_get_src_reg (sim_cpu *cpu, uint8 reg)
+static uint16_t
+cpu_get_src_reg (sim_cpu *cpu, uint8_t reg)
{
switch (reg)
{
}
static void
-cpu_set_dst_reg (sim_cpu *cpu, uint8 reg, uint16 val)
+cpu_set_dst_reg (sim_cpu *cpu, uint8_t reg, uint16_t val)
{
switch (reg)
{
}
static void
-cpu_set_reg (sim_cpu *cpu, uint8 reg, uint16 val)
+cpu_set_reg (sim_cpu *cpu, uint8_t reg, uint16_t val)
{
switch (reg)
{
/* Returns the address of a 68HC12 indexed operand.
Pre and post modifications are handled on the source register. */
-uint16
+uint16_t
cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted)
{
- uint8 reg;
- uint16 sval;
- uint16 addr;
- uint8 code;
+ uint8_t reg;
+ uint16_t sval;
+ uint16_t addr;
+ uint8_t code;
code = cpu_fetch8 (cpu);
return addr;
}
-static uint8
+static uint8_t
cpu_get_indexed_operand8 (sim_cpu *cpu, int restricted)
{
- uint16 addr;
+ uint16_t addr;
addr = cpu_get_indexed_operand_addr (cpu, restricted);
return memory_read8 (cpu, addr);
}
-static uint16
+static uint16_t
cpu_get_indexed_operand16 (sim_cpu *cpu, int restricted)
{
- uint16 addr;
+ uint16_t addr;
addr = cpu_get_indexed_operand_addr (cpu, restricted);
return memory_read16 (cpu, addr);
}
void
-cpu_move8 (sim_cpu *cpu, uint8 code)
+cpu_move8 (sim_cpu *cpu, uint8_t code)
{
- uint8 src;
- uint16 addr;
+ uint8_t src;
+ uint16_t addr;
switch (code)
{
}
void
-cpu_move16 (sim_cpu *cpu, uint8 code)
+cpu_move16 (sim_cpu *cpu, uint8_t code)
{
- uint16 src;
- uint16 addr;
+ uint16_t src;
+ uint16_t addr;
switch (code)
{
int
cpu_restart (sim_cpu *cpu)
{
- uint16 addr;
+ uint16_t addr;
/* Get CPU starting address depending on the CPU mode. */
if (cpu->cpu_use_elf_start == 0)
void
print_io_byte (SIM_DESC sd, const char *name, io_reg_desc *desc,
- uint8 val, uint16 addr)
+ uint8_t val, uint16_t addr)
{
sim_io_printf (sd, " %-9.9s @ 0x%04x 0x%02x ", name, addr, val);
if (desc)
void
print_io_word (SIM_DESC sd, const char *name, io_reg_desc *desc,
- uint16 val, uint16 addr)
+ uint16_t val, uint16_t addr)
{
sim_io_printf (sd, " %-9.9s @ 0x%04x 0x%04x ", name, addr, val);
if (desc)
}
void
-cpu_ccr_update_tst8 (sim_cpu *cpu, uint8 val)
+cpu_ccr_update_tst8 (sim_cpu *cpu, uint8_t val)
{
cpu_set_ccr_V (cpu, 0);
cpu_set_ccr_N (cpu, val & 0x80 ? 1 : 0);
}
-uint16
+uint16_t
cpu_fetch_relbranch (sim_cpu *cpu)
{
- uint16 addr = (uint16) cpu_fetch8 (cpu);
+ uint16_t addr = (uint16_t) cpu_fetch8 (cpu);
if (addr & 0x0080)
{
return addr;
}
-uint16
+uint16_t
cpu_fetch_relbranch16 (sim_cpu *cpu)
{
- uint16 addr = cpu_fetch16 (cpu);
+ uint16_t addr = cpu_fetch16 (cpu);
addr += cpu->cpu_regs.pc;
return addr;
void
cpu_dbcc (sim_cpu *cpu)
{
- uint8 code;
- uint16 addr;
- uint16 inc;
- uint16 reg;
+ uint8_t code;
+ uint16_t addr;
+ uint16_t inc;
+ uint16_t reg;
code = cpu_fetch8 (cpu);
switch (code & 0xc0)
}
void
-cpu_exg (sim_cpu *cpu, uint8 code)
+cpu_exg (sim_cpu *cpu, uint8_t code)
{
- uint8 r1, r2;
- uint16 src1;
- uint16 src2;
+ uint8_t r1, r2;
+ uint16_t src1;
+ uint16_t src2;
r1 = (code >> 4) & 0x07;
r2 = code & 0x07;
{
case M6811_RTI:
{
- uint8 ccr;
+ uint8_t ccr;
ccr = cpu_m68hc11_pop_uint8 (cpu);
cpu_set_ccr (cpu, ccr);
case M6812_RTI:
{
- uint8 ccr;
+ uint8_t ccr;
ccr = cpu_m68hc12_pop_uint8 (cpu);
cpu_set_ccr (cpu, ccr);
case M6811_ILLEGAL:
if (cpu->cpu_emul_syscall)
{
- uint8 op = memory_read8 (cpu,
+ uint8_t op = memory_read8 (cpu,
cpu_get_pc (cpu) - 1);
if (op == 0x41)
{
case M6812_IDIVS:
{
- int32 src1 = (int16) cpu_get_d (cpu);
- int32 src2 = (int16) cpu_get_x (cpu);
+ int32_t src1 = (int16_t) cpu_get_d (cpu);
+ int32_t src2 = (int16_t) cpu_get_x (cpu);
if (src2 == 0)
{
case M6812_EDIV:
{
- uint32 src1 = (uint32) cpu_get_x (cpu);
- uint32 src2 = (uint32) (cpu_get_y (cpu) << 16)
- | (uint32) (cpu_get_d (cpu));
+ uint32_t src1 = (uint32_t) cpu_get_x (cpu);
+ uint32_t src2 = (uint32_t) (cpu_get_y (cpu) << 16)
+ | (uint32_t) (cpu_get_d (cpu));
if (src1 == 0)
{
case M6812_EDIVS:
{
- int32 src1 = (int16) cpu_get_x (cpu);
- int32 src2 = (uint32) (cpu_get_y (cpu) << 16)
- | (uint32) (cpu_get_d (cpu));
+ int32_t src1 = (int16_t) cpu_get_x (cpu);
+ int32_t src2 = (uint32_t) (cpu_get_y (cpu) << 16)
+ | (uint32_t) (cpu_get_d (cpu));
if (src1 == 0)
{
case M6812_EMULS:
{
- int32 src1, src2;
+ int32_t src1, src2;
- src1 = (int16) cpu_get_d (cpu);
- src2 = (int16) cpu_get_y (cpu);
+ src1 = (int16_t) cpu_get_d (cpu);
+ src2 = (int16_t) cpu_get_y (cpu);
src1 = src1 * src2;
cpu_set_d (cpu, src1 & 0x0ffff);
cpu_set_y (cpu, src1 >> 16);
case M6812_EMACS:
{
- int32 src1, src2;
- uint16 addr;
+ int32_t src1, src2;
+ uint16_t addr;
addr = cpu_fetch16 (cpu);
- src1 = (int16) memory_read16 (cpu, cpu_get_x (cpu));
- src2 = (int16) memory_read16 (cpu, cpu_get_y (cpu));
+ src1 = (int16_t) memory_read16 (cpu, cpu_get_x (cpu));
+ src2 = (int16_t) memory_read16 (cpu, cpu_get_y (cpu));
src1 = src1 * src2;
- src2 = (((uint32) memory_read16 (cpu, addr)) << 16)
- | (uint32) memory_read16 (cpu, addr + 2);
+ src2 = (((uint32_t) memory_read16 (cpu, addr)) << 16)
+ | (uint32_t) memory_read16 (cpu, addr + 2);
memory_write16 (cpu, addr, (src1 + src2) >> 16);
memory_write16 (cpu, addr + 2, (src1 + src2));
case M6812_CALL:
{
- uint8 page;
- uint16 addr;
+ uint8_t page;
+ uint16_t addr;
addr = cpu_fetch16 (cpu);
page = cpu_fetch8 (cpu);
case M6812_CALL_INDIRECT:
{
- uint8 code;
- uint16 addr;
- uint8 page;
+ uint8_t code;
+ uint16_t addr;
+ uint8_t page;
code = memory_read8 (cpu, cpu_get_pc (cpu));
/* Indirect addressing call has the page specified in the
case M6812_RTC:
{
- uint8 page = cpu_m68hc12_pop_uint8 (cpu);
- uint16 addr = cpu_m68hc12_pop_uint16 (cpu);
+ uint8_t page = cpu_m68hc12_pop_uint8 (cpu);
+ uint16_t addr = cpu_m68hc12_pop_uint16 (cpu);
cpu_set_page (cpu, page);
cpu_set_pc (cpu, addr);
/* VARARGS */
void
sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
- uint16 addr, const char *message, ...)
+ uint16_t addr, const char *message, ...)
{
char buf[1024];
va_list args;
void
cpu_memory_exception (sim_cpu *cpu, SIM_SIGNAL excep,
- uint16 addr, const char *message)
+ uint16_t addr, const char *message)
{
if (cpu->cpu_running == 0)
return;
#include "sim-signal.h"
#include "sim-types.h"
-typedef unsigned8 uint8;
-typedef unsigned16 uint16;
-typedef signed16 int16;
-typedef unsigned32 uint32;
-typedef signed32 int32;
-typedef unsigned64 uint64;
-typedef signed64 int64;
-
struct _sim_cpu;
#include "interrupts.h"
extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
int mode);
extern void print_io_byte (SIM_DESC sd, const char *name,
- io_reg_desc *desc, uint8 val, uint16 addr);
+ io_reg_desc *desc, uint8_t val, uint16_t addr);
extern void print_io_word (SIM_DESC sd, const char *name,
- io_reg_desc *desc, uint16 val, uint16 addr);
+ io_reg_desc *desc, uint16_t val, uint16_t addr);
/* List of special 68HC11&68HC12 instructions that are not handled by the
/* CPU absolute cycle time. The cycle time is updated after
each instruction, by the number of cycles taken by the instruction.
It is cleared only when reset occurs. */
- signed64 cpu_absolute_cycle;
+ int64_t cpu_absolute_cycle;
/* Number of cycles to increment after the current instruction.
This is also the number of ticks for the generic event scheduler. */
- uint8 cpu_current_cycle;
+ uint8_t cpu_current_cycle;
int cpu_emul_syscall;
int cpu_is_initialized;
int cpu_running;
/* The starting address specified in ELF header. */
int cpu_elf_start;
- uint16 cpu_insn_pc;
+ uint16_t cpu_insn_pc;
/* CPU frequency. This is the quartz frequency. It is divided by 4 to
get the cycle time. This is used for the timer rate and for the baud
enum cpu_type cpu_type;
/* Initial value of the CONFIG register. */
- uint8 cpu_config;
- uint8 cpu_use_local_config;
+ uint8_t cpu_config;
+ uint8_t cpu_use_local_config;
- uint8 ios[MAX_PORTS];
+ uint8_t ios[MAX_PORTS];
/* Memory bank parameters which describe how the memory bank window
is mapped in memory and how to convert it in virtual address. */
- uint16 bank_start;
- uint16 bank_end;
+ uint16_t bank_start;
+ uint16_t bank_end;
address_word bank_virtual;
unsigned bank_shift;
/* Returns the cpu absolute cycle time (A virtual counter incremented
at each 68HC11 E clock). */
#define cpu_current_cycle(cpu) ((cpu)->cpu_absolute_cycle)
-#define cpu_add_cycles(cpu, T) ((cpu)->cpu_current_cycle += (signed64) (T))
+#define cpu_add_cycles(cpu, T) ((cpu)->cpu_current_cycle += (int64_t) (T))
#define cpu_is_running(cpu) ((cpu)->cpu_running)
/* Get the IO/RAM base addresses depending on the M6811_INIT register. */
#define cpu_get_io_base(cpu) \
- (((uint16)(((cpu)->ios[M6811_INIT]) & 0x0F)) << 12)
+ (((uint16_t)(((cpu)->ios[M6811_INIT]) & 0x0F)) << 12)
#define cpu_get_reg_base(cpu) \
- (((uint16)(((cpu)->ios[M6811_INIT]) & 0xF0)) << 8)
+ (((uint16_t)(((cpu)->ios[M6811_INIT]) & 0xF0)) << 8)
/* Returns the different CPU registers. */
#define cpu_get_ccr(cpu) ((cpu)->cpu_regs.ccr)
extern void cpu_memory_exception (sim_cpu *cpu,
SIM_SIGNAL excep,
- uint16 addr,
+ uint16_t addr,
const char *message);
STATIC_INLINE UNUSED address_word
return (address_word) (addr);
}
-STATIC_INLINE UNUSED uint8
-memory_read8 (sim_cpu *cpu, uint16 addr)
+STATIC_INLINE UNUSED uint8_t
+memory_read8 (sim_cpu *cpu, uint16_t addr)
{
- uint8 val;
+ uint8_t val;
if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
{
}
STATIC_INLINE UNUSED void
-memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
+memory_write8 (sim_cpu *cpu, uint16_t addr, uint8_t val)
{
if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
{
}
}
-STATIC_INLINE UNUSED uint16
-memory_read16 (sim_cpu *cpu, uint16 addr)
+STATIC_INLINE UNUSED uint16_t
+memory_read16 (sim_cpu *cpu, uint16_t addr)
{
- uint8 b[2];
+ uint8_t b[2];
if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
{
cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
"Read error");
}
- return (((uint16) (b[0])) << 8) | ((uint16) b[1]);
+ return (((uint16_t) (b[0])) << 8) | ((uint16_t) b[1]);
}
STATIC_INLINE UNUSED void
-memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
+memory_write16 (sim_cpu *cpu, uint16_t addr, uint16_t val)
{
- uint8 b[2];
+ uint8_t b[2];
b[0] = val >> 8;
b[1] = val;
}
}
extern void
-cpu_ccr_update_tst8 (sim_cpu *cpu, uint8 val);
+cpu_ccr_update_tst8 (sim_cpu *cpu, uint8_t val);
STATIC_INLINE UNUSED void
-cpu_ccr_update_tst16 (sim_cpu *cpu, uint16 val)
+cpu_ccr_update_tst16 (sim_cpu *cpu, uint16_t val)
{
cpu_set_ccr_V (cpu, 0);
cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0);
}
STATIC_INLINE UNUSED void
-cpu_ccr_update_shift8 (sim_cpu *cpu, uint8 val)
+cpu_ccr_update_shift8 (sim_cpu *cpu, uint8_t val)
{
cpu_set_ccr_N (cpu, val & 0x80 ? 1 : 0);
cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
}
STATIC_INLINE UNUSED void
-cpu_ccr_update_shift16 (sim_cpu *cpu, uint16 val)
+cpu_ccr_update_shift16 (sim_cpu *cpu, uint16_t val)
{
cpu_set_ccr_N (cpu, val & 0x8000 ? 1 : 0);
cpu_set_ccr_Z (cpu, val == 0 ? 1 : 0);
}
STATIC_INLINE UNUSED void
-cpu_ccr_update_add8 (sim_cpu *cpu, uint8 r, uint8 a, uint8 b)
+cpu_ccr_update_add8 (sim_cpu *cpu, uint8_t r, uint8_t a, uint8_t b)
{
cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
STATIC_INLINE UNUSED void
-cpu_ccr_update_sub8 (sim_cpu *cpu, uint8 r, uint8 a, uint8 b)
+cpu_ccr_update_sub8 (sim_cpu *cpu, uint8_t r, uint8_t a, uint8_t b)
{
cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
}
STATIC_INLINE UNUSED void
-cpu_ccr_update_add16 (sim_cpu *cpu, uint16 r, uint16 a, uint16 b)
+cpu_ccr_update_add16 (sim_cpu *cpu, uint16_t r, uint16_t a, uint16_t b)
{
cpu_set_ccr_C (cpu, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
cpu_set_ccr_V (cpu, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
}
STATIC_INLINE UNUSED void
-cpu_ccr_update_sub16 (sim_cpu *cpu, uint16 r, uint16 a, uint16 b)
+cpu_ccr_update_sub16 (sim_cpu *cpu, uint16_t r, uint16_t a, uint16_t b)
{
cpu_set_ccr_C (cpu, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
cpu_set_ccr_V (cpu, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
/* Push and pop instructions for 68HC11 (next-available stack mode). */
STATIC_INLINE UNUSED void
-cpu_m68hc11_push_uint8 (sim_cpu *cpu, uint8 val)
+cpu_m68hc11_push_uint8 (sim_cpu *cpu, uint8_t val)
{
- uint16 addr = cpu->cpu_regs.sp;
+ uint16_t addr = cpu->cpu_regs.sp;
memory_write8 (cpu, addr, val);
cpu->cpu_regs.sp = addr - 1;
}
STATIC_INLINE UNUSED void
-cpu_m68hc11_push_uint16 (sim_cpu *cpu, uint16 val)
+cpu_m68hc11_push_uint16 (sim_cpu *cpu, uint16_t val)
{
- uint16 addr = cpu->cpu_regs.sp - 1;
+ uint16_t addr = cpu->cpu_regs.sp - 1;
memory_write16 (cpu, addr, val);
cpu->cpu_regs.sp = addr - 1;
}
-STATIC_INLINE UNUSED uint8
+STATIC_INLINE UNUSED uint8_t
cpu_m68hc11_pop_uint8 (sim_cpu *cpu)
{
- uint16 addr = cpu->cpu_regs.sp;
- uint8 val;
+ uint16_t addr = cpu->cpu_regs.sp;
+ uint8_t val;
val = memory_read8 (cpu, addr + 1);
cpu->cpu_regs.sp = addr + 1;
return val;
}
-STATIC_INLINE UNUSED uint16
+STATIC_INLINE UNUSED uint16_t
cpu_m68hc11_pop_uint16 (sim_cpu *cpu)
{
- uint16 addr = cpu->cpu_regs.sp;
- uint16 val;
+ uint16_t addr = cpu->cpu_regs.sp;
+ uint16_t val;
val = memory_read16 (cpu, addr + 1);
cpu->cpu_regs.sp = addr + 2;
/* Push and pop instructions for 68HC12 (last-used stack mode). */
STATIC_INLINE UNUSED void
-cpu_m68hc12_push_uint8 (sim_cpu *cpu, uint8 val)
+cpu_m68hc12_push_uint8 (sim_cpu *cpu, uint8_t val)
{
- uint16 addr = cpu->cpu_regs.sp;
+ uint16_t addr = cpu->cpu_regs.sp;
addr --;
memory_write8 (cpu, addr, val);
}
STATIC_INLINE UNUSED void
-cpu_m68hc12_push_uint16 (sim_cpu *cpu, uint16 val)
+cpu_m68hc12_push_uint16 (sim_cpu *cpu, uint16_t val)
{
- uint16 addr = cpu->cpu_regs.sp;
+ uint16_t addr = cpu->cpu_regs.sp;
addr -= 2;
memory_write16 (cpu, addr, val);
cpu->cpu_regs.sp = addr;
}
-STATIC_INLINE UNUSED uint8
+STATIC_INLINE UNUSED uint8_t
cpu_m68hc12_pop_uint8 (sim_cpu *cpu)
{
- uint16 addr = cpu->cpu_regs.sp;
- uint8 val;
+ uint16_t addr = cpu->cpu_regs.sp;
+ uint8_t val;
val = memory_read8 (cpu, addr);
cpu->cpu_regs.sp = addr + 1;
return val;
}
-STATIC_INLINE UNUSED uint16
+STATIC_INLINE UNUSED uint16_t
cpu_m68hc12_pop_uint16 (sim_cpu *cpu)
{
- uint16 addr = cpu->cpu_regs.sp;
- uint16 val;
+ uint16_t addr = cpu->cpu_regs.sp;
+ uint16_t val;
val = memory_read16 (cpu, addr);
cpu->cpu_regs.sp = addr + 2;
}
/* Fetch a 8/16 bit value and update the PC. */
-STATIC_INLINE UNUSED uint8
+STATIC_INLINE UNUSED uint8_t
cpu_fetch8 (sim_cpu *cpu)
{
- uint16 addr = cpu->cpu_regs.pc;
- uint8 val;
+ uint16_t addr = cpu->cpu_regs.pc;
+ uint8_t val;
val = memory_read8 (cpu, addr);
cpu->cpu_regs.pc = addr + 1;
return val;
}
-STATIC_INLINE UNUSED uint16
+STATIC_INLINE UNUSED uint16_t
cpu_fetch16 (sim_cpu *cpu)
{
- uint16 addr = cpu->cpu_regs.pc;
- uint16 val;
+ uint16_t addr = cpu->cpu_regs.pc;
+ uint16_t val;
val = memory_read16 (cpu, addr);
cpu->cpu_regs.pc = addr + 2;
return val;
}
-extern void cpu_call (sim_cpu *cpu, uint16 addr);
-extern void cpu_exg (sim_cpu *cpu, uint8 code);
+extern void cpu_call (sim_cpu *cpu, uint16_t addr);
+extern void cpu_exg (sim_cpu *cpu, uint8_t code);
extern void cpu_dbcc (sim_cpu *cpu);
extern void cpu_special (sim_cpu *cpu, enum M6811_Special special);
-extern void cpu_move8 (sim_cpu *cpu, uint8 op);
-extern void cpu_move16 (sim_cpu *cpu, uint8 op);
+extern void cpu_move8 (sim_cpu *cpu, uint8_t op);
+extern void cpu_move16 (sim_cpu *cpu, uint8_t op);
-extern uint16 cpu_fetch_relbranch (sim_cpu *cpu);
-extern uint16 cpu_fetch_relbranch16 (sim_cpu *cpu);
+extern uint16_t cpu_fetch_relbranch (sim_cpu *cpu);
+extern uint16_t cpu_fetch_relbranch16 (sim_cpu *cpu);
extern void cpu_push_all (sim_cpu *cpu);
extern void cpu_single_step (sim_cpu *cpu);
/* Returns the address of a 68HC12 indexed operand.
Pre and post modifications are handled on the source register. */
-extern uint16 cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted);
+extern uint16_t cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted);
extern void cpu_return (sim_cpu *cpu);
-extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
+extern void cpu_set_sp (sim_cpu *cpu, uint16_t val);
extern int cpu_reset (sim_cpu *cpu);
extern int cpu_restart (sim_cpu *cpu);
extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
- uint16 addr, const char *message, ...);
+ uint16_t addr, const char *message, ...);
extern void emul_os (int op, sim_cpu *cpu);
extern void cpu_interp_m6811 (sim_cpu *cpu);
extern void cpu_interp_m6812 (sim_cpu *cpu);
extern int m68hc11cpu_set_oscillator (SIM_DESC sd, const char *port,
double ton, double toff,
- signed64 repeat);
+ int64_t repeat);
extern int m68hc11cpu_clear_oscillator (SIM_DESC sd, const char *port);
extern void m68hc11cpu_set_port (struct hw *me, sim_cpu *cpu,
- unsigned addr, uint8 val);
+ unsigned addr, uint8_t val);
extern void sim_board_reset (SIM_DESC sd);
#define PRINT_TIME 0x01
#define PRINT_CYCLE 0x02
-extern const char *cycle_to_string (sim_cpu *cpu, signed64 t, int flags);
+extern const char *cycle_to_string (sim_cpu *cpu, int64_t t, int flags);
#endif
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