synth_xilinx -arch -> -family, consistent with older synth_intel

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index dfe4c647b7ae381b735232260b8bbfe3ef802fe5..7dc9915e9f630872ee2852241b289fd6ed6b956d 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -42,8 +42,9 @@ struct SynthXilinxPass : public ScriptPass
                log("    -top <module>\n");
                log("        use the specified module as top module\n");
                log("\n");
-               log("    -arch {xcup|xcu|xc7|xc6s}\n");
+               log("    -family {xcup|xcu|xc7|xc6s}\n");
                log("        run synthesis for the specified Xilinx architecture\n");
+               log("        generate the synthesis netlist for the specified family.\n");
                log("        default: xc7\n");
                log("\n");
                log("    -edif <file>\n");
@@ -90,7 +91,7 @@ struct SynthXilinxPass : public ScriptPass
                log("\n");
        }
 
-       std::string top_opt, edif_file, blif_file, arch;
+       std::string top_opt, edif_file, blif_file, family;
        bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut;
 
        void clear_flags() YS_OVERRIDE
@@ -106,7 +107,7 @@ struct SynthXilinxPass : public ScriptPass
                nosrl = false;
                nocarry = false;
                nowidelut = false;
-               arch = "xc7";
+               family = "xc7";
        }
 
        void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -121,8 +122,8 @@ struct SynthXilinxPass : public ScriptPass
                                top_opt = "-top " + args[++argidx];
                                continue;
                        }
-                       if (args[argidx] == "-arch" && argidx+1 < args.size()) {
-                               arch = args[++argidx];
+                       if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
+                               family = args[++argidx];
                                continue;
                        }
                        if (args[argidx] == "-edif" && argidx+1 < args.size()) {
@@ -177,8 +178,8 @@ struct SynthXilinxPass : public ScriptPass
                }
                extra_args(args, argidx, design);
 
-               if (arch != "xcup" && arch != "xcu" && arch != "xc7" && arch != "xc6s")
-                       log_cmd_error("Invalid Xilinx -arch setting: %s\n", arch.c_str());
+               if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6s")
+                       log_cmd_error("Invalid Xilinx -family setting: %s\n", family.c_str());
 
                if (!design->full_selection())
                        log_cmd_error("This command only operates on fully selected designs!\n");