I also removed the unnecessary shadowing of `width_hint` and `sign_hint`
in the corresponding case in `simplify()`.
* SystemVerilog
- Support parameters using struct as a wiretype
+ - Fixed regression preventing the use array querying functions in case
+ expressions and case item expressions
* New commands and options
- Added "-genlib" option to "abc" pass
}
break;
}
+ if (str == "\\$size" || str == "\\$bits" || str == "\\$high" || str == "\\$low" || str == "\\$left" || str == "\\$right") {
+ width_hint = 32;
+ sign_hint = true;
+ break;
+ }
if (current_scope.count(str))
{
// This width detection is needed for function calls which are
if (const_fold && type == AST_CASE)
{
- int width_hint;
- bool sign_hint;
detectSignWidth(width_hint, sign_hint);
while (children[0]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) { }
if (children[0]->type == AST_CONSTANT && children[0]->bits_only_01()) {
--- /dev/null
+module top(
+ output logic [5:0] out
+);
+always_comb begin
+ out = '0;
+ case (1'b1 << 1)
+ 2'b10: out = '1;
+ default: out = '0;
+ endcase
+end
+endmodule
--- /dev/null
+module top(
+ output logic [5:0] out
+);
+always_comb begin
+ out = '0;
+ case ($bits (out)) 6:
+ case ($size (out)) 6:
+ case ($high (out)) 5:
+ case ($low (out)) 0:
+ case ($left (out)) 5:
+ case ($right(out)) 0:
+ case (6) $bits (out):
+ case (6) $size (out):
+ case (5) $high (out):
+ case (0) $low (out):
+ case (5) $left (out):
+ case (0) $right(out):
+ out = '1;
+ endcase
+ endcase
+ endcase
+ endcase
+ endcase
+ endcase
+ endcase
+ endcase
+ endcase
+ endcase
+ endcase
+ endcase
+end
+endmodule