soc_core: use new way to add wisbone slave (now prefered)

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 8f703ec8387e6167e0c6f203c4eb0136bceb407f..a6592044843c67f060b9c1c41d1c623680903e96 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -422,13 +422,12 @@ class SoCCore(Module):
 
         self._memory_regions.append((name, origin, length))
 
-    def register_mem(self, name, address, interface, size=None):
-        self.add_wb_slave(mem_decoder(address), interface)
-        if size is not None:
-            self.add_memory_region(name, address, size)
+    def register_mem(self, name, address, interface, size=0x10000000):
+        self.add_wb_slave(address, interface, size)
+        self.add_memory_region(name, address, size)
 
     def register_rom(self, interface, rom_size=0xa000):
-        self.add_wb_slave(mem_decoder(self.soc_mem_map["rom"]), interface)
+        self.add_wb_slave(self.soc_mem_map["rom"], interface, rom_size)
         self.add_memory_region("rom", self.cpu_reset_address, rom_size)
 
     def get_memory_regions(self):