system-arm: Add aarch64 bootloader support for GICv3

Change-Id: If75262709868cc59d320f60273a32397339f1dd5
Signed-off-by: Jairo Balart <jairo.balart@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13435
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

diff --git a/.gitignore b/.gitignore
index 6075ffe0b1805cb672be6346e25ba9d54dcd9ceb..9a276b266a34446e8cffa18986325a560fb1c098 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -24,3 +24,4 @@ m5out
 /system/arm/simple_bootloader/boot.arm
 /system/arm/simple_bootloader/boot_emm.arm
 /system/arm/aarch64_bootloader/boot_emm.arm64
+/system/arm/aarch64_bootloader/boot_emm_v2.arm64

diff --git a/system/arm/aarch64_bootloader/boot.S b/system/arm/aarch64_bootloader/boot.S
index 71c683017f1bb84b5dee9f440d9513abf5be81fa..589f38a4bec3928e575fbb9aadabcde960b5f193 100644 (file)
--- a/system/arm/aarch64_bootloader/boot.S
+++ b/system/arm/aarch64_bootloader/boot.S
@@ -67,6 +67,34 @@ _start:
         // Test the the MPIDR_EL1 register against 0xff00ffffff to
         // extract the primary CPU.
         ldr x1, =0xff00ffffff
+#ifdef GICV3
+        and    x2, x0, #0xff // use Aff0 as cpuid for now...
+        tst    x0, x1 // check for cpuid==zero
+        b.ne   1f // secondary CPU
+
+        ldr    x1, =GIC_DIST_BASE // GICD_CTLR
+        mov    w0, #7 // EnableGrp0 | EnableGrp1NS | EnableGrp1S
+        str    w0, [x1]
+
+
+1:      ldr    x1, =GIC_REDIST_BASE + 0x10000 + 0x80 // GICR_IGROUPR0
+        // 128K for each redistributor, 256K strided...
+        mov    x3, #1 << 18 // GICv4
+        mul    x3, x3, x2
+        add    x1, x1, x3
+        mov    w0, #~0 // Grp1 interrupts
+        str    w0, [x1], #4
+        b.ne   2f // Only local interrupts for secondary CPUs
+        ldr    x1, =GIC_DIST_BASE + 0x84 // GICD_IGROUPR
+        str    w0, [x1], #4
+        str    w0, [x1], #4
+        str    w0, [x1], #4
+
+
+2:      mov    x0, #1
+        msr    S3_0_c12_c12_6, x0 // ICC_IGRPEN0_EL1 Enable
+        msr    S3_0_C12_C12_7, x0 // ICC_IGRPEN1_EL1 Enable
+#else
         tst x0, x1                    // check for cpuid==zero
         b.ne   1f                                    // secondary CPU
 
@@ -88,6 +116,7 @@ _start:
 
         mov    w0, #1 << 7                     // allow NS access to GICC_PMR
         str    w0, [x1, #4]                    // GICC_PMR
+#endif
 
         msr    sctlr_el2, xzr
 

diff --git a/system/arm/aarch64_bootloader/makefile b/system/arm/aarch64_bootloader/makefile
index 4428d2620ed44f2dea4764db8f36014dd7f11f8d..9ffff76c7b2078ecb21be8adf7267f14788d6794 100644 (file)
--- a/system/arm/aarch64_bootloader/makefile
+++ b/system/arm/aarch64_bootloader/makefile
@@ -1,4 +1,7 @@
 build:
        aarch64-linux-gnu-gcc -c  -DPHYS_OFFSET=0x80000000 -DCNTFRQ=0x01800000 -DUART_BASE=0x1c090000 -DSYSREGS_BASE=0x1c010000 -DGIC_DIST_BASE=0x2c001000 -DGIC_CPU_BASE=0x2c002000 -Dkernel=0x80080000 -Dmbox=0x8000fff8 -Ddtb=0x80000100 -o boot_emm.o -march=armv8-a boot.S
        aarch64-linux-gnu-ld -o boot_emm.arm64 -N -Ttext 0x00000010 boot_emm.o -non_shared -static
-       rm boot_emm.o
\ No newline at end of file
+       rm boot_emm.o
+       aarch64-linux-gnu-gcc -c  -DGICV3 -DPHYS_OFFSET=0x80000000 -DCNTFRQ=0x01800000 -DUART_BASE=0x1c090000 -DSYSREGS_BASE=0x1c010000 -DGIC_DIST_BASE=0x2c000000 -DGIC_REDIST_BASE=0x2c010000 -Dkernel=0x80080000 -Dmbox=0x8000fff8 -Ddtb=0x80000100 -o boot_emm_v2.o -march=armv8-a boot.S
+       aarch64-linux-gnu-ld -o boot_emm_v2.arm64 -N -Ttext 0x00000010 boot_emm_v2.o -non_shared -static
+       rm boot_emm_v2.o