soc/interconnect/stream/gearbox: inverse bit order

diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py
index 3676a1f6358a62835d925294d1897edcd3eca6a8..b10155b1d934b72faff91387d4b022f64dc32c27 100644 (file)
--- a/litex/soc/interconnect/stream.py
+++ b/litex/soc/interconnect/stream.py
@@ -404,12 +404,12 @@ class Gearbox(Module):
 
         i_cases = {}
         for i in range(io_lcm//i_dw):
-            i_cases[i] = shift_register[i_dw*i:i_dw*(i+1)].eq(sink.data)
+            i_cases[i] = shift_register[i_dw*i:i_dw*(i+1)].eq(sink.data[::-1])
         self.sync += If(sink.valid & sink.ready, Case(i_count, i_cases))
 
         o_cases = {}
         for i in range(io_lcm//o_dw):
-            o_cases[i] = source.data.eq(shift_register[o_dw*i:o_dw*(i+1)])
+            o_cases[i] = source.data.eq(shift_register[o_dw*i:o_dw*(i+1)][::-1])
         self.comb += Case(o_count, o_cases)
 
 # TODO: clean up code below