i965: get inputs read from nir info

This is a step towards dropping the GLSL IR version of
do_set_program_inouts() in i965 and moving towards native nir support.

This is important because we want to eventually convert to nir and
use its optimisations passes before we can call this GLSL IR pass.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index 9100a8f59e3f96f9b9c06d3a4f2d09622aab431d..7f9594ce342db683c11a1e69ead4b1b34816d911 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -50,6 +50,7 @@
  */
 
 
+#include "compiler/nir/nir.h"
 #include "main/context.h"
 #include "main/macros.h"
 #include "main/enums.h"
@@ -324,7 +325,8 @@ emit:
     * BRW_NEW_FRAGMENT_PROGRAM
     */
    if (brw->gen == 4 && !brw->is_g4x &&
-       (brw->fragment_program->Base.InputsRead & (1 << VARYING_SLOT_POS))) {
+       (brw->fragment_program->Base.nir->info.inputs_read &
+        (1 << VARYING_SLOT_POS))) {
       BEGIN_BATCH(2);
       OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2));
       OUT_BATCH(0);

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 0eaa0f22025e5eeb71d14d48646e34f186a7f113..af98464bb615a8c003993052163ae86cd4f7e204 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -302,7 +302,7 @@ brw_merge_inputs(struct brw_context *brw,
    }
 
    if (brw->gen < 8 && !brw->is_haswell) {
-      GLbitfield64 mask = ctx->VertexProgram._Current->Base.InputsRead;
+      uint64_t mask = ctx->VertexProgram._Current->Base.nir->info.inputs_read;
       /* Prior to Haswell, the hardware can't natively support GL_FIXED or
        * 2_10_10_10_REV vertex formats.  Set appropriate workaround flags.
        */

diff --git a/src/mesa/drivers/dri/i965/brw_interpolation_map.c b/src/mesa/drivers/dri/i965/brw_interpolation_map.c
index 6d0a813eee7b1faf6788f7cb58939106672a8b38..7ca3c05e1a285bd88838a8ebb9f0f6d51d8acad2 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_interpolation_map.c
+++ b/src/mesa/drivers/dri/i965/brw_interpolation_map.c
@@ -22,6 +22,7 @@
  */
 
 #include "brw_state.h"
+#include "compiler/nir/nir.h"
 
 static char const *get_qual_name(int mode)
 {
@@ -72,7 +73,7 @@ brw_setup_vue_interpolation(struct brw_context *brw)
       if (varying == VARYING_SLOT_BFC0 || varying == VARYING_SLOT_BFC1)
          frag_attrib = varying - VARYING_SLOT_BFC0 + VARYING_SLOT_COL0;
 
-      if (!(fprog->Base.InputsRead & BITFIELD64_BIT(frag_attrib)))
+      if (!(fprog->Base.nir->info.inputs_read & BITFIELD64_BIT(frag_attrib)))
          continue;
 
       enum glsl_interp_mode mode = fprog->InterpQualifier[frag_attrib];

diff --git a/src/mesa/drivers/dri/i965/brw_sf.c b/src/mesa/drivers/dri/i965/brw_sf.c
index 6d8cd74bdf02c93b45f417f50687a5d55675c5c5..2090737fd05447027930d8e3cb7baae81b7dc4d1 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_sf.c
+++ b/src/mesa/drivers/dri/i965/brw_sf.c
@@ -29,7 +29,7 @@
   *   Keith Whitwell <keithw@vmware.com>
   */
 
-
+#include "compiler/nir/nir.h"
 #include "main/macros.h"
 #include "main/mtypes.h"
 #include "main/enums.h"
@@ -192,8 +192,11 @@ brw_upload_sf_prog(struct brw_context *brw)
    if (key.do_point_sprite) {
       key.point_sprite_coord_replace = ctx->Point.CoordReplace & 0xff;
    }
-   if (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(VARYING_SLOT_PNTC))
+   if (brw->fragment_program->Base.nir->info.inputs_read &
+       BITFIELD64_BIT(VARYING_SLOT_PNTC)) {
       key.do_point_coord = 1;
+   }
+
    /*
     * Window coordinates in a FBO are inverted, which means point
     * sprite origin must be inverted, too.

diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c b/src/mesa/drivers/dri/i965/brw_tcs.c
index 0b691397a2db7da95caf63daba9783830bf5c5bc..f566e779249cdb600ffd7fa385ad2188ac4658a4 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_tcs.c
+++ b/src/mesa/drivers/dri/i965/brw_tcs.c
@@ -316,8 +316,10 @@ void
 brw_tcs_populate_key(struct brw_context *brw,
                      struct brw_tcs_prog_key *key)
 {
-   uint64_t per_vertex_slots = brw->tess_eval_program->Base.InputsRead;
-   uint32_t per_patch_slots = brw->tess_eval_program->Base.PatchInputsRead;
+   uint64_t per_vertex_slots =
+      brw->tess_eval_program->Base.nir->info.inputs_read;
+   uint32_t per_patch_slots =
+      brw->tess_eval_program->Base.nir->info.patch_inputs_read;
 
    struct brw_tess_ctrl_program *tcp =
       (struct brw_tess_ctrl_program *) brw->tess_ctrl_program;
@@ -353,7 +355,7 @@ brw_tcs_populate_key(struct brw_context *brw,
       /* _NEW_TEXTURE */
       brw_populate_sampler_prog_key_data(&brw->ctx, prog, &key->tex);
    } else {
-      key->outputs_written = tep->program.Base.InputsRead;
+      key->outputs_written = tep->program.Base.nir->info.inputs_read;
    }
 }
 

diff --git a/src/mesa/drivers/dri/i965/brw_tes.c b/src/mesa/drivers/dri/i965/brw_tes.c
index d1f56bde6061e67f9b1d99b1e25b8c15e9a8d73c..5612c46d678e08b41f08f0c951e69ca80840d8de 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_tes.c
+++ b/src/mesa/drivers/dri/i965/brw_tes.c
@@ -234,8 +234,10 @@ brw_tes_populate_key(struct brw_context *brw,
                      struct brw_tes_prog_key *key)
 {
 
-   uint64_t per_vertex_slots = brw->tess_eval_program->Base.InputsRead;
-   uint32_t per_patch_slots = brw->tess_eval_program->Base.PatchInputsRead;
+   uint64_t per_vertex_slots =
+      brw->tess_eval_program->Base.nir->info.inputs_read;
+   uint32_t per_patch_slots =
+      brw->tess_eval_program->Base.nir->info.patch_inputs_read;
 
    struct brw_tess_eval_program *tep =
       (struct brw_tess_eval_program *) brw->tess_eval_program;
@@ -314,8 +316,8 @@ brw_tes_precompile(struct gl_context *ctx,
    memset(&key, 0, sizeof(key));
 
    key.program_string_id = btep->id;
-   key.inputs_read = prog->InputsRead;
-   key.patch_inputs_read = prog->PatchInputsRead;
+   key.inputs_read = prog->nir->info.inputs_read;
+   key.patch_inputs_read = prog->nir->info.patch_inputs_read;
 
    if (shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL]) {
       struct gl_program *tcp =

diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
index aa1ae2851610bd86fc6b7069656fbec1cc9de76a..25484ddcfbe25885c21322176fb8f5855b6981e6 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -152,7 +152,7 @@ brw_codegen_vs_prog(struct brw_context *brw,
    uint64_t outputs_written =
       brw_vs_outputs_written(brw, key,
                              vp->program.Base.nir->info.outputs_written);
-   prog_data.inputs_read = vp->program.Base.InputsRead;
+   prog_data.inputs_read = vp->program.Base.nir->info.inputs_read;
 
    if (key->copy_edgeflag) {
       prog_data.inputs_read |= VERT_BIT_EDGEFLAG;

diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index d5f3b22ff74b98e88495c11d7f945aa2a7b68450..f782da15792814ade5a8f26ca669f3768c3dd2f2 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -543,9 +543,11 @@ brw_wm_populate_key(struct brw_context *brw, struct brw_wm_prog_key *key)
    }
 
    /* BRW_NEW_VUE_MAP_GEOM_OUT */
-   if (brw->gen < 6 || _mesa_bitcount_64(fp->program.Base.InputsRead &
-                                         BRW_FS_VARYING_INPUT_MASK) > 16)
+   if (brw->gen < 6 ||
+       _mesa_bitcount_64(fp->program.Base.nir->info.inputs_read &
+                         BRW_FS_VARYING_INPUT_MASK) > 16) {
       key->input_slots_valid = brw->vue_map_geom_out.slots_valid;
+   }
 
 
    /* _NEW_COLOR | _NEW_BUFFERS */
@@ -618,9 +620,11 @@ brw_fs_precompile(struct gl_context *ctx,
       key.iz_lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
    }
 
-   if (brw->gen < 6 || _mesa_bitcount_64(fp->Base.InputsRead &
-                                         BRW_FS_VARYING_INPUT_MASK) > 16)
-      key.input_slots_valid = fp->Base.InputsRead | VARYING_BIT_POS;
+   if (brw->gen < 6 || _mesa_bitcount_64(fp->Base.nir->info.inputs_read &
+                                         BRW_FS_VARYING_INPUT_MASK) > 16) {
+      key.input_slots_valid =
+         fp->Base.nir->info.inputs_read | VARYING_BIT_POS;
+   }
 
    brw_setup_tex_for_precompile(brw, &key.tex, &fp->Base);
 

diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 0afc97d4993b0c85c51d83b56f28f1bba58ff635..0149308bb80efc4c4697cdd7ebe7c0c424eb83f6 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -29,6 +29,7 @@
 #include "brw_state.h"
 #include "brw_defines.h"
 #include "brw_util.h"
+#include "compiler/nir/nir.h"
 #include "main/macros.h"
 #include "main/fbobject.h"
 #include "main/framebuffer.h"
@@ -176,7 +177,8 @@ calculate_attr_overrides(const struct brw_context *brw,
     * - VARYING_SLOT_{PSIZ,LAYER} and VARYING_SLOT_POS on gen6+
     */
 
-   bool fs_needs_vue_header = brw->fragment_program->Base.InputsRead &
+   bool fs_needs_vue_header =
+      brw->fragment_program->Base.nir->info.inputs_read &
       (VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT);
 
    *urb_entry_read_offset = fs_needs_vue_header ? 0 : 1;

diff --git a/src/mesa/drivers/dri/i965/gen8_sf_state.c b/src/mesa/drivers/dri/i965/gen8_sf_state.c
index d8eec23978d73ad26f6ca543620e4a159e79fd27..4c13f45f136fde58c60705c0f32320ae8ac0e4d0 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_sf_state.c
@@ -21,6 +21,7 @@
  * IN THE SOFTWARE.
  */
 
+#include "compiler/nir/nir.h"
 #include "brw_context.h"
 #include "brw_state.h"
 #include "brw_defines.h"
@@ -94,8 +95,10 @@ upload_sbe(struct brw_context *brw)
       /* prepare the active component dwords */
       int input_index = 0;
       for (int attr = 0; attr < VARYING_SLOT_MAX; attr++) {
-         if (!(brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(attr)))
+         if (!(brw->fragment_program->Base.nir->info.inputs_read &
+               BITFIELD64_BIT(attr))) {
             continue;
+         }
 
          assert(input_index < 32);