case 0x1: cond = COND_VS; break;
case 0x2: cond = COND_GE; break;
case 0x3: cond = COND_GT; break;
+ default: panic("unreachable");
}
if (size == 3) {
return new VselD(machInst, vd, vn, vm, cond);
#define __ARCH_GENERIC_TYPES_HH__
#include <iostream>
+#include <limits>
#include "base/trace.hh"
#include "base/types.hh"
/** Logical vector register elem index type. */
using ElemIndex = uint16_t;
+/** ElemIndex value that indicates that the register is not a vector. */
+#define ILLEGAL_ELEM_INDEX std::numeric_limits<ElemIndex>::max()
+
namespace GenericISA
{
/*
- * Copyright (c) 2016-2018 ARM Limited
+ * Copyright (c) 2016-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
friend struct std::hash<RegId>;
public:
- RegId() : regClass(IntRegClass), regIdx(0), elemIdx(-1) {}
+ RegId() : RegId(IntRegClass, 0) {}
+
RegId(RegClass reg_class, RegIndex reg_idx)
- : regClass(reg_class), regIdx(reg_idx), elemIdx(-1),
- numPinnedWrites(0)
- {
- panic_if(regClass == VecElemClass,
- "Creating vector physical index w/o element index");
- }
+ : RegId(reg_class, reg_idx, ILLEGAL_ELEM_INDEX) {}
explicit RegId(RegClass reg_class, RegIndex reg_idx, ElemIndex elem_idx)
: regClass(reg_class), regIdx(reg_idx), elemIdx(elem_idx),
- numPinnedWrites(0)
- {
- panic_if(regClass != VecElemClass,
- "Creating non-vector physical index w/ element index");
+ numPinnedWrites(0) {
+ if (elemIdx == ILLEGAL_ELEM_INDEX) {
+ panic_if(regClass == VecElemClass,
+ "Creating vector physical index w/o element index");
+ } else {
+ panic_if(regClass != VecElemClass,
+ "Creating non-vector physical index w/ element index");
+ }
}
bool operator==(const RegId& that) const {