add extra suppression of verilator warnings

diff --git a/Makefile b/Makefile
index a3a32b84c4e9fab7f39399a6114951de63dc5bd7..5bd396d660043c60b1300fdb7f9c2bcf55d00a5b 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -139,20 +139,20 @@ $(soc_dram_tbs): %: $(soc_dram_files) $(soc_dram_sim_files) $(soc_dram_sim_obj_f
 endif
 
 # Hello world
-MEMORY_SIZE=8192
-RAM_INIT_FILE=hello_world/hello_world.hex
-SIM_MAIN_BRAM=true
+#MEMORY_SIZE=8192
+#RAM_INIT_FILE=hello_world/hello_world.hex
+#SIM_MAIN_BRAM=false
 
 # Micropython
 #MEMORY_SIZE=393216
 #RAM_INIT_FILE=micropython/firmware.hex
 
 # Linux
-#MEMORY_SIZE=536870912
-#RAM_INIT_FILE=dtbImage.microwatt.hex
-#SIM_MAIN_BRAM=false
+MEMORY_SIZE=536870912
+RAM_INIT_FILE=dtbImage.microwatt.hex
+SIM_MAIN_BRAM=false
 #SIM_BRAM_CHAINBOOT=5242880 # 0x500000
-#SIM_BRAM_CHAINBOOT=6291456 # 0x600000
+SIM_BRAM_CHAINBOOT=6291456 # 0x600000
 
 FPGA_TARGET ?= ORANGE-CRAB
 
@@ -226,7 +226,17 @@ microwatt.v: $(synth_files) $(RAM_INIT_FILE)
 # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
 # --top-module toplevel
 microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
-       verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Iuart16550 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT # --trace
+       verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY)" --assert --cc microwatt.v --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c -o $@ -Iuart16550 \
+       -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT \
+           -Wno-BLKANDNBLK \
+           -Wno-COMBDLY  \
+           -Wno-CASEINCOMPLETE \
+           -Wno-WIDTH \
+       # --trace
+       #    --unroll-count 256 \
+       #    --output-split 5000 \
+       #    --output-split-cfuncs 500 \
+       #    --output-split-ctrace 500 \
        make -C obj_dir -f Vmicrowatt.mk
        @cp -f obj_dir/microwatt-verilator microwatt-verilator