(no commit message)

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index bf82f88cd383ffc3bae88fd4ac36f7c3c113f497..38b917b1e6705f6334182734fff46a1785852921 100644 (file)
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -21,6 +21,7 @@ Links:
  (instruction form SVL-Form, field designations, pseudocode, SPR allocation)
 * <https://bugs.libre-soc.org/show_bug.cgi?id=615> agree sv assembly syntax
 * <https://bugs.libre-soc.org/show_bug.cgi?id=617> TestIssuer add single/twin Predication
+* <https://bugs.libre-soc.org/show_bug.cgi?id=617> ISACaller add single/twin Predication
 
 # Code to convert
 
@@ -187,7 +188,12 @@ At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP sca
 
 ## Single and Twin Predication
 
-* <https://bugs.libre-soc.org/show_bug.cgi?id=617> TestIssuer 
+both CR and INT predication is needed
+
+* TestIssuer <https://bugs.libre-soc.org/show_bug.cgi?id=617> 
+* ISACaller <https://bugs.libre-soc.org/show_bug.cgi?id=617>
+* power-gem5: TODO
+* Microwatt: TODO
 
 ## Element width overrides