mem: Fix for 100% write threshold in DRAM controller

This patch fixes the controller when a write threshold of 100% is
used.  Earlier for 100% write threshold no data is written to memory
as writes never get triggered since this corner case is not
considered.

diff --git a/src/mem/simple_dram.cc b/src/mem/simple_dram.cc
index 9cbca6a1ce8a7717a668f32cb0e45cc8b1cc76cd..9669c7a03921e533801f23e3118f9b3ff49ca753 100644 (file)
--- a/src/mem/simple_dram.cc
+++ b/src/mem/simple_dram.cc
@@ -563,7 +563,7 @@ SimpleDRAM::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
     accessAndRespond(pkt, frontendLatency);
 
     // If your write buffer is starting to fill up, drain it!
-    if (writeQueue.size() > writeThreshold && !stopReads){
+    if (writeQueue.size() >= writeThreshold && !stopReads){
         triggerWrites();
     }
 }