test/support: fix default ncycles

diff --git a/migen/test/support.py b/migen/test/support.py
index 394cc424d7820b98944877346b95b08051e51f3a..51a897079b6f777a930f6848eb716dd43d1e1dda 100644 (file)
--- a/migen/test/support.py
+++ b/migen/test/support.py
@@ -17,6 +17,6 @@ class SimCase:
        def test_to_verilog(self):
                verilog.convert(self.tb)
 
-       def run_with(self, cb, ncycles=-1):
+       def run_with(self, cb, ncycles=None):
                self.tb.callback = cb
                run_simulation(self.tb, ncycles=ncycles)